On Wed, May 28, 2025 at 12:02:49PM +0100, Jiaxun Yang wrote: > After adding AHCI controller reset functionality there are multiple > reports on AHCI booting regression. > > As per my experiments on various machines, to reset controller > properly it is necessary to poll HOST_CTL_RESET bit until it's > clear. It is also required to read back HOST_CTL after changing > HOST_CTL_AHCI_EN bits to ensure the controller has accepted write. > > Tested on ASMedia ASM1061, Intel H61 native SATA and AMD Phoenix > native SATA. > > Link: > https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/RDNRKWBN4N5XQX2TQMM5P4WZ2OOPPNAM/ > Link: https://github.com/FlyGoat/csmwrap/issues/14 > Fixes: 8863cbbd15a7 ("ahci: add controller reset") > Signed-off-by: Jiaxun Yang <jiaxun.y...@flygoat.com> > Acked-by: Paul Menzel <pmen...@molgen.mpg.de>
Applied & pushed. take care, Gerd _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-le...@seabios.org
