RE: [PATCH v4 0/6] VCN and JPEG RAS poison detection
[AMD Official Use Only] Dear Paul, Thank for review. Added comment inline. Regards, Mohammad >-Original Message- >From: Paul Menzel >Sent: Monday, March 28, 2022 12:09 PM >To: Ziya, Mohammad zafar >Cc: amd-gfx@lists.freedesktop.org; Zhou1, Tao ; >Lazar, Lijo ; Zhang, Hawking > >Subject: Re: [PATCH v4 0/6] VCN and JPEG RAS poison detection > >Dear Mahommad, > > >Am 28.03.22 um 08:24 schrieb Mohammad Zafar Ziya: >> VCN and JPEG RAS poison detection > >It’d be great if you extended this a little bit. Especially, how it can be >tested. [Mohammad]: This is the first series of the RAS poison consumption detection support, where this series only detects the poison consumption. The Interrupt from VCN/JPEG block will be intercepted and check the poison consumed by VCN/JPEG and cross check it is indeed the vcn/jpeg poison consumption interrupt. > >> Mohammad Zafar Ziya (6): >>drm/amdgpu: Add vcn and jpeg ras support flag >>drm/amdgpu/vcn: Add vcn ras support >>drm/amdgpu/jpeg: Add jpeg block ras support >>drm/amdgpu/vcn: vcn and jpeg ver 2.6 ras register definition >>drm/amdgpu/vcn: VCN ras error query support >>drm/amdgpu/jpeg: jpeg ras error query support > >It’d be great if you made the last three commit message summaries also >statements (by adding a verb in imperative mood). [Mohammad]: The 2nd last and last commit only facilitate the functionality of the poison consumption detection of the vcn/jpeg block. This will be called under IH/BH to check indeed interrupt from VCN/JPEG poison consumption. The 3rd last commits only add the register definition needed to facilitate the functionality. > > >Kind regards, > >Paul
Re: [PATCH 1/2] drm/amd/display: detach fpu operations from dcn10_validate_bandwidth in calcs
Am 26.03.22 um 21:24 schrieb Melissa Wen:
dcn10_validate_bandwidth is only used on dcn10 files, but is declared in
dcn_calcs files. Rename dcn10_* to dcn_* in calcs, remove DC_FP_* wrapper
inside DML folder and create an specific dcn10_validate_bandwidth in
dcn10_resources that calls dcn_validate_bandwidth and properly wraps that
FPU function with DC_FP_* macro.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 14 ++
.../gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 5 +
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 4048908dd265..1587a060b55a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1141,6 +1141,20 @@ static void dcn10_destroy_resource_pool(struct
resource_pool **pool)
*pool = NULL;
}
+static bool dcn10_validate_bandwidth(
+ struct dc *dc,
+ struct dc_state *context,
+ bool fast_validate)
+{
+ bool voltage_supported;
+
+ DC_FP_START();
+ voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate);
+ DC_FP_END();
+
+ return voltage_supported;
+}
+
static enum dc_status dcn10_validate_plane(const struct dc_plane_state
*plane_state, struct dc_caps *caps)
{
if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index e447c74be713..c25023f7d604 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -764,7 +764,7 @@ static unsigned int
get_highest_allowed_voltage_level(uint32_t chip_family,
return 4;
}
-bool dcn10_validate_bandwidth(
+bool dcn_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -790,7 +790,6 @@ bool dcn10_validate_bandwidth(
dcn_bw_sync_calcs_and_dml(dc);
memset(v, 0, sizeof(*v));
- DC_FP_START();
v->sr_exit_time = dc->dcn_soc->sr_exit_time;
v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
@@ -1323,8 +1322,6 @@ bool dcn10_validate_bandwidth(
bw_limit = dc->dcn_soc->percent_disp_bw_limit *
v->fabric_and_dram_bandwidth_vmax0p9;
bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
- DC_FP_END();
-
PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH();
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
index 337c0161e72d..806f3041db14 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -619,7 +619,7 @@ struct dcn_ip_params {
};
extern const struct dcn_ip_params dcn10_ip_defaults;
-bool dcn10_validate_bandwidth(
+bool dcn_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate);
Just for the record: That's not really usual kernel coding style, but
that's not topic of this patch set.
The series is Acked-by: Christian König
And it would be really nice if we could make the DC_FP_* macros somehow
fail in the dml folder.
Thanks,
Christian.
Re: [PATCH v4 2/6] drm/amdgpu/vcn: Add vcn ras support
Dear Mohammad,
Thank you for your patch.
Am 28.03.22 um 08:24 schrieb Mohammad Zafar Ziya:
VCN block ras feature support addition
V2: default ras callback removed
Signed-off-by: Mohammad Zafar Ziya
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index e2fde88aaf5e..ea07974ef6f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -24,6 +24,8 @@
#ifndef __AMDGPU_VCN_H__
#define __AMDGPU_VCN_H__
+#include "amdgpu_ras.h"
+
#define AMDGPU_VCN_STACK_SIZE (128*1024)
#define AMDGPU_VCN_CONTEXT_SIZE (512*1024)
@@ -232,6 +234,10 @@ struct amdgpu_vcn_inst {
struct amdgpu_vcn_fw_shared fw_shared;
};
+struct amdgpu_vcn_ras {
+ struct amdgpu_ras_block_object ras_block;
+};
+
struct amdgpu_vcn {
unsignedfw_version;
struct delayed_work idle_work;
@@ -251,6 +257,9 @@ struct amdgpu_vcn {
unsignedharvest_config;
int (*pause_dpg_mode)(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
+
+ struct ras_common_if*ras_if;
+ struct amdgpu_vcn_ras *ras;
};
struct amdgpu_fw_shared_rb_ptrs_struct {
@@ -339,4 +348,5 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);
void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
uint8_t i, struct amdgpu_vcn_inst *vcn);
+
#endif
This hunk looks unrelated. Maybe remove it?
Kind regards,
Paul
Re: [PATCH v4 0/6] VCN and JPEG RAS poison detection
Dear Mahommad, Am 28.03.22 um 08:24 schrieb Mohammad Zafar Ziya: VCN and JPEG RAS poison detection It’d be great if you extended this a little bit. Especially, how it can be tested. Mohammad Zafar Ziya (6): drm/amdgpu: Add vcn and jpeg ras support flag drm/amdgpu/vcn: Add vcn ras support drm/amdgpu/jpeg: Add jpeg block ras support drm/amdgpu/vcn: vcn and jpeg ver 2.6 ras register definition drm/amdgpu/vcn: VCN ras error query support drm/amdgpu/jpeg: jpeg ras error query support It’d be great if you made the last three commit message summaries also statements (by adding a verb in imperative mood). Kind regards, Paul
[PATCH v4 6/6] drm/amdgpu/jpeg: jpeg ras error query support
RAS error query support addition for JPEG 2.6
V2: removed unused options and corrected comment format.
Moved register definition to header file.
V3: poison query status check added.
Removed the error query support
V4: Return statement refactored.
Signed-off-by: Mohammad Zafar Ziya
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 74 ++
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h | 7 +++
2 files changed, 81 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index a29c86617fb5..4f2de9c31d6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -26,6 +26,7 @@
#include "soc15.h"
#include "soc15d.h"
#include "jpeg_v2_0.h"
+#include "jpeg_v2_5.h"
#include "vcn/vcn_2_5_offset.h"
#include "vcn/vcn_2_5_sh_mask.h"
@@ -39,6 +40,7 @@ static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device
*adev);
static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
static int jpeg_v2_5_set_powergating_state(void *handle,
enum amd_powergating_state state);
+static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
static int amdgpu_ih_clientid_jpeg[] = {
SOC15_IH_CLIENTID_VCN,
@@ -70,6 +72,7 @@ static int jpeg_v2_5_early_init(void *handle)
jpeg_v2_5_set_dec_ring_funcs(adev);
jpeg_v2_5_set_irq_funcs(adev);
+ jpeg_v2_5_set_ras_funcs(adev);
return 0;
}
@@ -730,3 +733,74 @@ const struct amdgpu_ip_block_version jpeg_v2_6_ip_block =
.rev = 0,
.funcs = &jpeg_v2_6_ip_funcs,
};
+
+static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
+ uint32_t instance, uint32_t sub_block)
+{
+ uint32_t poison_stat = 0, reg_value = 0;
+
+ switch (sub_block) {
+ case AMDGPU_JPEG_V2_6_JPEG0:
+ reg_value = RREG32_SOC15(JPEG, instance,
mmUVD_RAS_JPEG0_STATUS);
+ poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS,
POISONED_PF);
+ break;
+ case AMDGPU_JPEG_V2_6_JPEG1:
+ reg_value = RREG32_SOC15(JPEG, instance,
mmUVD_RAS_JPEG1_STATUS);
+ poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS,
POISONED_PF);
+ break;
+ default:
+ break;
+ }
+
+ if (poison_stat)
+ dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",
+ instance, sub_block);
+
+ return poison_stat;
+}
+
+static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev)
+{
+ uint32_t inst = 0, sub = 0, poison_stat = 0;
+
+ for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
+ for (sub = 0; sub < AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK; sub++)
+ poison_stat +=
+ jpeg_v2_6_query_poison_by_instance(adev, inst, sub);
+
+ return poison_stat ? true : false;
+}
+
+const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = {
+ .query_poison_status = jpeg_v2_6_query_ras_poison_status,
+};
+
+static struct amdgpu_jpeg_ras jpeg_v2_6_ras = {
+ .ras_block = {
+ .hw_ops = &jpeg_v2_6_ras_hw_ops,
+ },
+};
+
+static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[JPEG_HWIP][0]) {
+ case IP_VERSION(2, 6, 0):
+ adev->jpeg.ras = &jpeg_v2_6_ras;
+ break;
+ default:
+ break;
+ }
+
+ if (adev->jpeg.ras) {
+ amdgpu_ras_register_ras_block(adev, &adev->jpeg.ras->ras_block);
+
+ strcpy(adev->jpeg.ras->ras_block.ras_comm.name, "jpeg");
+ adev->jpeg.ras->ras_block.ras_comm.block =
AMDGPU_RAS_BLOCK__JPEG;
+ adev->jpeg.ras->ras_block.ras_comm.type =
AMDGPU_RAS_ERROR__POISON;
+ adev->jpeg.ras_if = &adev->jpeg.ras->ras_block.ras_comm;
+
+ /* If don't define special ras_late_init function, use default
ras_late_init */
+ if (!adev->jpeg.ras->ras_block.ras_late_init)
+ adev->jpeg.ras->ras_block.ras_late_init =
amdgpu_ras_block_late_init;
+ }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
index 3b0aa29b9879..1e858c6cdf13 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
@@ -24,6 +24,13 @@
#ifndef __JPEG_V2_5_H__
#define __JPEG_V2_5_H__
+enum amdgpu_jpeg_v2_6_sub_block {
+ AMDGPU_JPEG_V2_6_JPEG0 = 0,
+ AMDGPU_JPEG_V2_6_JPEG1,
+
+ AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK,
+};
+
extern const struct amdgpu_ip_block_version jpeg_v2_5_ip_block;
extern const struct amdgpu_ip_block_version jpeg_v2_6_ip_block;
--
2.25.1
[PATCH v4 4/6] drm/amdgpu/vcn: vcn and jpeg ver 2.6 ras register definition
Adding vcn and jpeg ver 2.6 ras register definition Signed-off-by: Mohammad Zafar Ziya Reviewed-by: Hawking Zhang --- .../amd/include/asic_reg/vcn/vcn_2_5_offset.h | 13 ++ .../include/asic_reg/vcn/vcn_2_5_sh_mask.h| 24 +++ 2 files changed, 37 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h index 90350f46a0c4..363d2139cea2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h @@ -988,4 +988,17 @@ #define mmMDM_WIG_PIPE_BUSY_BASE_IDX 1 +/* VCN 2_6_0 regs */ +#define mmUVD_RAS_VCPU_VCODEC_STATUS 0x0057 +#define mmUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1 +#define mmUVD_RAS_MMSCH_FATAL_ERROR0x0058 +#define mmUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1 + + +/* JPEG 2_6_0 regs */ +#define mmUVD_RAS_JPEG0_STATUS 0x0059 +#define mmUVD_RAS_JPEG0_STATUS_BASE_IDX1 +#define mmUVD_RAS_JPEG1_STATUS 0x005a +#define mmUVD_RAS_JPEG1_STATUS_BASE_IDX1 + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h index c41c59c30006..8de883b76d90 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h @@ -3606,4 +3606,28 @@ #define UVD_LMI_CRC3__CRC32_MASK 0xL +/* VCN 2_6_0 UVD_RAS_VCPU_VCODEC_STATUS */ +#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0 +#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f +#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK0x7FFFL +#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK0x8000L + +/* VCN 2_6_0 UVD_RAS_MMSCH_FATAL_ERROR */ +#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0 +#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f +#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFL +#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x8000L + +/* JPEG 2_6_0 UVD_RAS_JPEG0_STATUS */ +#define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT0x0 +#define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT0x1f +#define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFL +#define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x8000L + +/* JPEG 2_6_0 UVD_RAS_JPEG1_STATUS */ +#define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT0x0 +#define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT0x1f +#define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFL +#define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x8000L + #endif -- 2.25.1
[PATCH v4 5/6] drm/amdgpu/vcn: VCN ras error query support
RAS error query support addition for VCN 2.6
V2: removed unused option and corrected comment format
Moved the register definition under header file
V3: poison query status check added.
Removed error query interface
V4: MMSCH poison check option removed, return true/false refactored.
Signed-off-by: Mohammad Zafar Ziya
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 71 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h | 6 +++
3 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 1e1a3b736859..606df8869b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -508,6 +508,7 @@ struct amdgpu_ras_block_hw_ops {
void (*query_ras_error_address)(struct amdgpu_device *adev, void
*ras_error_status);
void (*reset_ras_error_count)(struct amdgpu_device *adev);
void (*reset_ras_error_status)(struct amdgpu_device *adev);
+ bool (*query_poison_status)(struct amdgpu_device *adev);
};
/* work flow
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 1869bae4104b..3988fc647741 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -31,6 +31,7 @@
#include "soc15d.h"
#include "vcn_v2_0.h"
#include "mmsch_v1_0.h"
+#include "vcn_v2_5.h"
#include "vcn/vcn_2_5_offset.h"
#include "vcn/vcn_2_5_sh_mask.h"
@@ -59,6 +60,7 @@ static int vcn_v2_5_set_powergating_state(void *handle,
static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state
*new_state);
static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
+static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);
static int amdgpu_ih_clientid_vcns[] = {
SOC15_IH_CLIENTID_VCN,
@@ -100,6 +102,7 @@ static int vcn_v2_5_early_init(void *handle)
vcn_v2_5_set_dec_ring_funcs(adev);
vcn_v2_5_set_enc_ring_funcs(adev);
vcn_v2_5_set_irq_funcs(adev);
+ vcn_v2_5_set_ras_funcs(adev);
return 0;
}
@@ -1930,3 +1933,71 @@ const struct amdgpu_ip_block_version vcn_v2_6_ip_block =
.rev = 0,
.funcs = &vcn_v2_6_ip_funcs,
};
+
+static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
+ uint32_t instance, uint32_t sub_block)
+{
+ uint32_t poison_stat = 0, reg_value = 0;
+
+ switch (sub_block) {
+ case AMDGPU_VCN_V2_6_VCPU_VCODEC:
+ reg_value = RREG32_SOC15(VCN, instance,
mmUVD_RAS_VCPU_VCODEC_STATUS);
+ poison_stat = REG_GET_FIELD(reg_value,
UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
+ break;
+ default:
+ break;
+ };
+
+ if (poison_stat)
+ dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
+ instance, sub_block);
+
+ return poison_stat;
+}
+
+static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev)
+{
+ uint32_t inst, sub;
+ uint32_t poison_stat = 0;
+
+ for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
+ for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++)
+ poison_stat +=
+ vcn_v2_6_query_poison_by_instance(adev, inst, sub);
+
+ return poison_stat ? true : false;
+}
+
+const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = {
+ .query_poison_status = vcn_v2_6_query_poison_status,
+};
+
+static struct amdgpu_vcn_ras vcn_v2_6_ras = {
+ .ras_block = {
+ .hw_ops = &vcn_v2_6_ras_hw_ops,
+ },
+};
+
+static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[VCN_HWIP][0]) {
+ case IP_VERSION(2, 6, 0):
+ adev->vcn.ras = &vcn_v2_6_ras;
+ break;
+ default:
+ break;
+ }
+
+ if (adev->vcn.ras) {
+ amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block);
+
+ strcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn");
+ adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
+ adev->vcn.ras->ras_block.ras_comm.type =
AMDGPU_RAS_ERROR__POISON;
+ adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm;
+
+ /* If don't define special ras_late_init function, use default
ras_late_init */
+ if (!adev->vcn.ras->ras_block.ras_late_init)
+ adev->vcn.ras->ras_block.ras_late_init =
amdgpu_ras_block_late_init;
+ }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h
index e72f799ed0fd..1c19af74e4fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h
@@ -24,6 +24,12 @@
[PATCH v4 3/6] drm/amdgpu/jpeg: Add jpeg block ras support
Ras support addition for JPEG block
V2: removed default callback
Signed-off-by: Mohammad Zafar Ziya
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
index 55fbff2be761..b6c7fb00e05a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
@@ -24,6 +24,8 @@
#ifndef __AMDGPU_JPEG_H__
#define __AMDGPU_JPEG_H__
+#include "amdgpu_ras.h"
+
#define AMDGPU_MAX_JPEG_INSTANCES 2
#define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
@@ -39,6 +41,10 @@ struct amdgpu_jpeg_inst {
struct amdgpu_jpeg_reg external;
};
+struct amdgpu_jpeg_ras {
+ struct amdgpu_ras_block_object ras_block;
+};
+
struct amdgpu_jpeg {
uint8_t num_jpeg_inst;
struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
@@ -48,6 +54,8 @@ struct amdgpu_jpeg {
enum amd_powergating_state cur_state;
struct mutex jpeg_pg_lock;
atomic_t total_submission_cnt;
+ struct ras_common_if*ras_if;
+ struct amdgpu_jpeg_ras *ras;
};
int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
--
2.25.1
[PATCH v4 2/6] drm/amdgpu/vcn: Add vcn ras support
VCN block ras feature support addition
V2: default ras callback removed
Signed-off-by: Mohammad Zafar Ziya
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index e2fde88aaf5e..ea07974ef6f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -24,6 +24,8 @@
#ifndef __AMDGPU_VCN_H__
#define __AMDGPU_VCN_H__
+#include "amdgpu_ras.h"
+
#define AMDGPU_VCN_STACK_SIZE (128*1024)
#define AMDGPU_VCN_CONTEXT_SIZE(512*1024)
@@ -232,6 +234,10 @@ struct amdgpu_vcn_inst {
struct amdgpu_vcn_fw_shared fw_shared;
};
+struct amdgpu_vcn_ras {
+ struct amdgpu_ras_block_object ras_block;
+};
+
struct amdgpu_vcn {
unsignedfw_version;
struct delayed_work idle_work;
@@ -251,6 +257,9 @@ struct amdgpu_vcn {
unsignedharvest_config;
int (*pause_dpg_mode)(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
+
+ struct ras_common_if*ras_if;
+ struct amdgpu_vcn_ras *ras;
};
struct amdgpu_fw_shared_rb_ptrs_struct {
@@ -339,4 +348,5 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);
void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
uint8_t i, struct amdgpu_vcn_inst *vcn);
+
#endif
--
2.25.1
[PATCH v4 1/6] drm/amdgpu: Add vcn and jpeg ras support flag
Add vcn and jpeg ras support options
V2: vcn and jpeg ras flag enabled for aldebaran asic only
V3: vcn and jpeg ras flag disabled for error counter query
Generic poison query interface added
VCN and JPEG ras enabled based on IP version check
V4: vcn and jpeg ras flag moved under ecc flag for dGPU
Signed-off-by: Mohammad Zafar Ziya
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index f9104f99eb9c..4bbed76b79c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -66,6 +66,8 @@ const char *ras_block_string[] = {
"mp1",
"fuse",
"mca",
+ "vcn",
+ "jpeg",
};
const char *ras_mca_block_string[] = {
@@ -2205,6 +2207,13 @@ static void amdgpu_ras_check_supported(struct
amdgpu_device *adev)
dev_info(adev->dev, "SRAM ECC is active.\n");
adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
1 << AMDGPU_RAS_BLOCK__DF);
+
+ if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6,
0))
+ adev->ras_hw_enabled |= (1 <<
AMDGPU_RAS_BLOCK__VCN |
+ 1 << AMDGPU_RAS_BLOCK__JPEG);
+ else
+ adev->ras_hw_enabled &= ~(1 <<
AMDGPU_RAS_BLOCK__VCN |
+ 1 << AMDGPU_RAS_BLOCK__JPEG);
} else {
dev_info(adev->dev, "SRAM ECC is not presented.\n");
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 9314fde81e68..1e1a3b736859 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -49,6 +49,8 @@ enum amdgpu_ras_block {
AMDGPU_RAS_BLOCK__MP1,
AMDGPU_RAS_BLOCK__FUSE,
AMDGPU_RAS_BLOCK__MCA,
+ AMDGPU_RAS_BLOCK__VCN,
+ AMDGPU_RAS_BLOCK__JPEG,
AMDGPU_RAS_BLOCK__LAST
};
--
2.25.1
[PATCH v4 0/6] VCN and JPEG RAS poison detection
VCN and JPEG RAS poison detection Mohammad Zafar Ziya (6): drm/amdgpu: Add vcn and jpeg ras support flag drm/amdgpu/vcn: Add vcn ras support drm/amdgpu/jpeg: Add jpeg block ras support drm/amdgpu/vcn: vcn and jpeg ver 2.6 ras register definition drm/amdgpu/vcn: VCN ras error query support drm/amdgpu/jpeg: jpeg ras error query support drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 8 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 10 +++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 74 +++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 7 ++ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 71 ++ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h | 6 ++ .../amd/include/asic_reg/vcn/vcn_2_5_offset.h | 13 .../include/asic_reg/vcn/vcn_2_5_sh_mask.h| 24 ++ 10 files changed, 225 insertions(+) -- 2.25.1
Re: [PATCH 01/13] drm/amd/display: HDCP SEND AKI INIT error
Dear Alex, Am 25.03.22 um 21:43 schrieb Hung, Alex: Thanks for your feedback. Thank you for your reply. For the future, it’d be great if you could use interleaved style [1], when replying, or when it’s a new topic, do not cite the previous message. I fixed many errors and typos you highlighted in this series. In cases where modification requires re-testing we or anyone can have follow-up patches in the future. Thank you. Did you resubmit them in *[PATCH 00/16] DC Patches March 25, 2022*? Unfortunately, they are not tagged as v2 and the emails do not contain an information what was changed between v1 and v2. Can you please send them again with the correct tags, and information included? Kind regards, Paul [1]: https://en.wikipedia.org/wiki/Posting_style
RE: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
Reviewed-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Ji, Ruili
> Sent: Monday, March 28, 2022 12:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Yifan ; Liu, Aaron
> ; Liang, Prike ; Huang, Ray
> ; Deucher, Alexander
> ; Ji, Ruili
> Subject: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
>
> From: Ruili Ji
>
> gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for
> GCR_GENERAL_CNTL
>
> Signed-off-by: Ruili Ji
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 99df18ae7316..e4c9d92ac381 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden
> golden_settings_gc_10_3_3[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0242),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff,
> 0x00e4),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210), @@ -3436,7 +3436,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_6[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0042),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff,
> 0x0044),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210), @@ -3461,7 +3461,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_7[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0041),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff,
> 0x00e4),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210),
> --
> 2.25.1
[PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
From: Ruili Ji
gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for GCR_GENERAL_CNTL
Signed-off-by: Ruili Ji
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 99df18ae7316..e4c9d92ac381 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden
golden_settings_gc_10_3_3[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0242),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1,
0x0500),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x,
0x32103210),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x,
0x32103210),
@@ -3436,7 +3436,7 @@ static const struct soc15_reg_golden
golden_settings_gc_10_3_6[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0042),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1,
0x0500),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x0044),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x,
0x32103210),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x,
0x32103210),
@@ -3461,7 +3461,7 @@ static const struct soc15_reg_golden
golden_settings_gc_10_3_7[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0041),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1,
0x0500),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x,
0x32103210),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x,
0x32103210),
--
2.25.1
RE: [PATCH] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
[AMD Official Use Only]
Thanks Ruili. Please remove Change-Id.
With this fixed, Reviewed-by: Aaron Liu
> -Original Message-
> From: Ji, Ruili
> Sent: Monday, March 28, 2022 11:47 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Liu, Aaron ; Zhang, Yifan
> ; Liang, Prike ; Ji, Ruili
>
> Subject: [PATCH] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
>
> From: Ruili Ji
>
> RMB shall use 0x1580 address for GCR_GENERAL_CNTL
>
> Signed-off-by: Ruili Ji
> Change-Id: I10a85891986f31411f85fa3db46970aaa8a5bd03
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 99df18ae7316..e4c9d92ac381 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden
> golden_settings_gc_10_3_3[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0242),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER,
> 0x00ff, 0x00e4),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210), @@ -3436,7 +3436,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_6[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0042),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER,
> 0x00ff, 0x0044),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210), @@ -3461,7 +3461,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_7[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x,
> 0x0280),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x,
> 0x0080),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x0041),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1, 0x0500),
> + SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
> +0x0500),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER,
> 0x00ff, 0x00e4),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x, 0x32103210),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x, 0x32103210),
> --
> 2.25.1
[PATCH] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
From: Ruili Ji
RMB shall use 0x1580 address for GCR_GENERAL_CNTL
Signed-off-by: Ruili Ji
Change-Id: I10a85891986f31411f85fa3db46970aaa8a5bd03
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 99df18ae7316..e4c9d92ac381 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden
golden_settings_gc_10_3_3[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0242),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1,
0x0500),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x,
0x32103210),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x,
0x32103210),
@@ -3436,7 +3436,7 @@ static const struct soc15_reg_golden
golden_settings_gc_10_3_6[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0042),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1,
0x0500),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x0044),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x,
0x32103210),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x,
0x32103210),
@@ -3461,7 +3461,7 @@ static const struct soc15_reg_golden
golden_settings_gc_10_3_7[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0041),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1,
0x0500),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1,
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x,
0x32103210),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x,
0x32103210),
--
2.25.1
Re: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
[AMD Official Use Only]
Thank you very much for your suggestion, but I have already submitted.
Regards,
Rico
From: Chen, Guchun
Sent: Monday, March 28, 2022 10:17
To: Chen, Guchun ; Yin, Tianci (Rico)
; amd-gfx@lists.freedesktop.org
Cc: Wang, Yu (Charlie) ; Zhu, James ; Yin,
Tianci (Rico)
Subject: RE: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
Hi Tianci,
I think we shall improve the subject a bit like "drm/amdgpu: fix incorrect
instance id passing when stopping dpg mode". How do you think?
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Monday, March 28, 2022 9:26 AM
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Wang, Yu (Charlie) ; Zhu, James ; Yin,
Tianci (Rico)
Subject: RE: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Tianci Yin
Sent: Sunday, March 27, 2022 7:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhu, James ; Wang,
Yu (Charlie) ; Yin, Tianci (Rico)
Subject: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
From: tiancyin
Some video card has more than one vcn instance, passing 0 to
vcn_v3_0_pause_dpg_mode is incorrect.
Error msg:
Register(1) [mmUVD_POWER_STATUS] failed to reach value
0x0001 != 0x0002
Signed-off-by: tiancyin
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e1cca0a10653..cb5f0a12333f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1488,7 +1488,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device
*adev, int inst_idx)
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
uint32_t tmp;
- vcn_v3_0_pause_dpg_mode(adev, 0, &state);
+ vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);
/* Wait for power status to be 1 */
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
--
2.25.1
RE: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
Hi Tianci,
I think we shall improve the subject a bit like "drm/amdgpu: fix incorrect
instance id passing when stopping dpg mode". How do you think?
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Monday, March 28, 2022 9:26 AM
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Wang, Yu (Charlie) ; Zhu, James ; Yin,
Tianci (Rico)
Subject: RE: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Tianci Yin
Sent: Sunday, March 27, 2022 7:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhu, James ; Wang,
Yu (Charlie) ; Yin, Tianci (Rico)
Subject: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
From: tiancyin
Some video card has more than one vcn instance, passing 0 to
vcn_v3_0_pause_dpg_mode is incorrect.
Error msg:
Register(1) [mmUVD_POWER_STATUS] failed to reach value
0x0001 != 0x0002
Signed-off-by: tiancyin
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e1cca0a10653..cb5f0a12333f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1488,7 +1488,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device
*adev, int inst_idx)
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
uint32_t tmp;
- vcn_v3_0_pause_dpg_mode(adev, 0, &state);
+ vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);
/* Wait for power status to be 1 */
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
--
2.25.1
RE: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode
[AMD Official Use Only]
Hi Harry,
I have been reminded to do some modifications to the patch format. So the 3/25
it's the date I resent the mail v2.
If the mail title usage is not correct, please let me know.
And about the questions:
" This file lives in DC, which is shared code between Windows and Linux. We
cannot directly use adev here. Any information needs to go through DC structs."
- I use the adev here because I just reference the code I found in the
same function.
+ if (strcmp(entry->device_class, "battery") == 0) {
< I added.
+ adev->pm.ac_power = power_supply_is_system_supplied() > 0;
+ }
+
if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
< I found.
if (power_supply_is_system_supplied() > 0)
DRM_DEBUG_DRIVER("pm: AC\n");
-And the reason why I need to add another comparison is that the string
of the device_class I got is always "battery" when I plug/unplug the ac cable.
It never reports "ac_adapter" to me. So I add the "battery" line to do
that.
"I seem to remember someone saying that ABM gets disabled on Windows when we're
in AC mode. Have you checked with our Windows guys about this? I feel we're
re-inventing the wheel here for no good reason."
-Yes, I have asked the Windows guys and they told me the ABM should be
disabled in AC mode. But seems we don’t have this function on Linux, so I
implemented this to disable ABM in AC mode.
Thanks,
Ryan Lin.
-Original Message-
From: Wentland, Harry
Sent: Friday, March 25, 2022 10:46 PM
To: Lin, Tsung-hua (Ryan) ; Li, Sun peng (Leo)
; Deucher, Alexander ; Koenig,
Christian ; david1.z...@amd.com; airl...@linux.ie;
dan...@ffwll.ch; seanp...@chromium.org; b...@basnieuwenhuizen.nl; Kazlauskas,
Nicholas ; sas...@kernel.org;
markyac...@google.com; victorchengchi...@amd.com;
ching-shih...@amd.corp-partner.google.com; Siqueira, Rodrigo
; ddavenp...@chromium.org;
amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
linux-ker...@vger.kernel.org; Li, Leon
Subject: Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode
On 2022-03-25 00:05, Ryan Lin wrote:
> Disable ABM feature when the system is running on AC mode to get the
> more perfect contrast of the display.
It says patch 3 out of 25. Are there other patches? If so, I can't find them in
my mailbox and neither can patchwork
https://patchwork.freedesktop.org/series/101767/
> Signed-off-by: Ryan Lin
>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 1 +
> drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 58 ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 +
> 4 files changed, 42 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index c560c1ab62ecb..bc8bb9aad2e36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -822,6 +822,10 @@ static int amdgpu_acpi_event(struct notifier_block *nb,
> struct amdgpu_device *adev = container_of(nb, struct amdgpu_device,
> acpi_nb);
> struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
>
> + if (strcmp(entry->device_class, "battery") == 0) {
> + adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> + }
> +
> if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
> if (power_supply_is_system_supplied() > 0)
> DRM_DEBUG_DRIVER("pm: AC\n");
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index abfcc1304ba0c..3a0afe7602727 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3454,6 +3454,7 @@ int amdgpu_device_init(struct amdgpu_device
> *adev,
>
> adev->gfx.gfx_off_req_count = 1;
> adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> + adev->pm.old_ac_power = true;
>
> atomic_set(&adev->throttling_logging_enabled, 1);
> /*
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> index 54a1408c8015c..478a734b66926 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> @@ -23,6 +23,8 @@
> *
> */
>
> +#include
> +#include "amdgpu.h"
> #include "dmub_abm.h"
> #include "dce_abm.h"
> #include "dc.h"
> @@ -51,6 +53,7 @@
> #define DISABLE_ABM_IMMEDIATELY 255
>
>
> +extern uint amdgpu_dm_abm_level;
>
> static void dmub_abm_enable_fractional_pwm(struct dc_context *dc) {
> @@ -117,28 +120,6 @@ static void dmub_abm_init(struct abm *abm, uint32_t
> backlight)
> dmub_abm_enable_fractional_pwm(abm->ctx);
> }
>
> -static unsigned int
RE: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Tianci Yin
Sent: Sunday, March 27, 2022 7:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhu, James ; Wang,
Yu (Charlie) ; Yin, Tianci (Rico)
Subject: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
From: tiancyin
Some video card has more than one vcn instance, passing 0 to
vcn_v3_0_pause_dpg_mode is incorrect.
Error msg:
Register(1) [mmUVD_POWER_STATUS] failed to reach value
0x0001 != 0x0002
Signed-off-by: tiancyin
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e1cca0a10653..cb5f0a12333f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1488,7 +1488,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device
*adev, int inst_idx)
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
uint32_t tmp;
- vcn_v3_0_pause_dpg_mode(adev, 0, &state);
+ vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);
/* Wait for power status to be 1 */
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
--
2.25.1
Re: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
[AMD Official Use Only]
Thank you James!
Rico
From: Zhu, James
Sent: Sunday, March 27, 2022 21:47
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Wang, Yu (Charlie)
Subject: Re: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
[AMD Official Use Only]
This patch is Reviewed-by: James Zhu
From: Tianci Yin
Sent: Sunday, March 27, 2022 7:18 AM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhu, James ; Wang,
Yu (Charlie) ; Yin, Tianci (Rico)
Subject: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
From: tiancyin
Some video card has more than one vcn instance, passing 0 to
vcn_v3_0_pause_dpg_mode is incorrect.
Error msg:
Register(1) [mmUVD_POWER_STATUS] failed to reach value
0x0001 != 0x0002
Signed-off-by: tiancyin
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e1cca0a10653..cb5f0a12333f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1488,7 +1488,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device
*adev, int inst_idx)
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
uint32_t tmp;
- vcn_v3_0_pause_dpg_mode(adev, 0, &state);
+ vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);
/* Wait for power status to be 1 */
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
--
2.25.1
Re: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
[AMD Official Use Only]
This patch is Reviewed-by: James Zhu
From: Tianci Yin
Sent: Sunday, March 27, 2022 7:18 AM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhu, James ; Wang,
Yu (Charlie) ; Yin, Tianci (Rico)
Subject: [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
From: tiancyin
Some video card has more than one vcn instance, passing 0 to
vcn_v3_0_pause_dpg_mode is incorrect.
Error msg:
Register(1) [mmUVD_POWER_STATUS] failed to reach value
0x0001 != 0x0002
Signed-off-by: tiancyin
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e1cca0a10653..cb5f0a12333f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1488,7 +1488,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device
*adev, int inst_idx)
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
uint32_t tmp;
- vcn_v3_0_pause_dpg_mode(adev, 0, &state);
+ vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);
/* Wait for power status to be 1 */
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
--
2.25.1
[PATCH] drm/amd/vcn: fix an error msg on vcn 3.0
From: tiancyin
Some video card has more than one vcn instance, passing 0 to
vcn_v3_0_pause_dpg_mode is incorrect.
Error msg:
Register(1) [mmUVD_POWER_STATUS] failed to reach value
0x0001 != 0x0002
Signed-off-by: tiancyin
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e1cca0a10653..cb5f0a12333f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1488,7 +1488,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device
*adev, int inst_idx)
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
uint32_t tmp;
- vcn_v3_0_pause_dpg_mode(adev, 0, &state);
+ vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);
/* Wait for power status to be 1 */
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
--
2.25.1
[PATCH 3/5] umr: Add command line support for "--gpu-metrics"
Add command line support for --gpu-metrics, to fall in line with the rest
of the command line arguments' format.
Cc: Tom StDenis
Cc: Jinzhou.Su
Signed-off-by: Luben Tuikov
---
src/app/main.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/app/main.c b/src/app/main.c
index 62ea2f42145f60..6cfbe09bea7b4d 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -861,7 +861,9 @@ int main(int argc, char **argv)
if (umr_print_pp_table(asic, NULL) != 0)
fprintf(stderr, "[ERROR]: can not print
pp table info.\n");
}
- } else if (!strcmp(argv[i], "--gpu_metrics") ||
!strcmp(argv[i], "-gm")) {
+ } else if (!strcmp(argv[i], "--gpu-metrics") ||
+ !strcmp(argv[i], "--gpu_metrics") ||
+ !strcmp(argv[i], "-gm")) {
if (!asic)
asic = get_asic();
if (umr_print_gpu_metrics(asic) != 0)
--
2.35.1.607.gf01e51a7cf
[PATCH 1/5] umr: Add support for "--ppt-read"
Add support for "--ppt-read" to fall in line with the way rest of the
command line options are formatted. The old "--ppt_read" is still
supported.
Cc: Tom StDenis
Cc: Jinzhou.Su
Signed-off-by: Luben Tuikov
---
src/app/main.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/app/main.c b/src/app/main.c
index 2f9d6aadd7ff46..62ea2f42145f60 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -848,7 +848,9 @@ int main(int argc, char **argv)
umr_set_clock_performance(asic, "auto");
if (umr_check_clock_performance(asic, clockperformance,
sizeof(clockperformance)) != 0)
printf("power_dpm_force_performance_level: %s",
clockperformance);
- } else if (!strcmp(argv[i], "--ppt_read") || !strcmp(argv[i],
"-pptr")) {
+ } else if (!strcmp(argv[i], "--ppt-read") ||
+ !strcmp(argv[i], "--ppt_read") ||
+ !strcmp(argv[i], "-pptr")) {
if (!asic)
asic = get_asic();
if (i + 1 < argc) {
base-commit: decd91d8eae42d63eda4f6b7c97159b9cc343c26
--
2.35.1.607.gf01e51a7cf
[PATCH 4/5] umr: Document new format command line options
Document new format command line options in the manual page: "--ppt-read" and "--gpu-metrics". The old format using underscores is still supported in the main app, in case it is used in scripts, and so on. Cc: Tom StDenis Cc: Jinzhou.Su Signed-off-by: Luben Tuikov --- doc/umr.1 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/umr.1 b/doc/umr.1 index 62eea7db320b88..ad518e0fa7451d 100644 --- a/doc/umr.1 +++ b/doc/umr.1 @@ -288,11 +288,11 @@ Set power_dpm_force_performance_level to low. .IP "--clock-auto, -ca" Set power_dpm_force_performance_level to auto. -.IP "--ppt_read, -pptr [ppt_field_name]" +.IP "--ppt-read, -pptr [ppt_field_name]" Read powerplay table value and print it to stdout. This command will print all the powerplay table information or the corresponding string in powerplay table. -.IP "--gpu_metrics, -gm" +.IP "--gpu-metrics, -gm" Print the GPU metrics table for the device. .SH "Notes" -- 2.35.1.607.gf01e51a7cf
[PATCH 5/5] umr: Completion: update new format options
Update completion for "--ppt-read" and "--gpu-metrics".
Cc: Tom StDenis
Cc: Jinzhou.Su
Signed-off-by: Luben Tuikov
---
scripts/umr-completion.bash | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/umr-completion.bash b/scripts/umr-completion.bash
index 0e1444357c82a9..bd0b61b2d38831 100644
--- a/scripts/umr-completion.bash
+++ b/scripts/umr-completion.bash
@@ -333,7 +333,7 @@ _umr_comp_ring_stream()
_umr_completion()
{
-local ALL_LONG_ARGS=(--database-path --option --gpu --instance --force
--pci --gfxoff --vm_partition --bank --sbank --cbank --config --enumerate
--list-blocks --list-regs --dump-discovery-table --lookup --write --writebit
--read --scan --logscan --top --waves --profiler --vm-decode --vm-read
--vm-write --vm-write-word --vm-disasm --ring-stream --dump-ib --dump-ib-file
--header-dump --power --clock-scan --clock-manual --clock-high --clock-low
--clock-auto --ppt_read --gpu_metrics --power --vbios_info --test-log
--test-harness --server --gui)
+local ALL_LONG_ARGS=(--database-path --option --gpu --instance --force
--pci --gfxoff --vm_partition --bank --sbank --cbank --config --enumerate
--list-blocks --list-regs --dump-discovery-table --lookup --write --writebit
--read --scan --logscan --top --waves --profiler --vm-decode --vm-read
--vm-write --vm-write-word --vm-disasm --ring-stream --dump-ib --dump-ib-file
--header-dump --power --clock-scan --clock-manual --clock-high --clock-low
--clock-auto --ppt-read --gpu-metrics --power --vbios_info --test-log
--test-harness --server --gui)
local cur prev
--
2.35.1.607.gf01e51a7cf
[PATCH 2/5] umr: Reorg and print the message on ppt-read
Reorganize the logic and actually print the error message when the ASIC
doesn't support the power-play table feature.
Cc: Tom StDenis
Cc: Jinzhou.Su
Signed-off-by: Luben Tuikov
---
src/app/pp_table.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/src/app/pp_table.c b/src/app/pp_table.c
index 9ab42a9ae2296c..33c2d01e897ef3 100644
--- a/src/app/pp_table.c
+++ b/src/app/pp_table.c
@@ -20,27 +20,32 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
+
+#include
#include "umrapp.h"
#include "smu_pptable_navi10.h"
-int umr_print_pp_table(struct umr_asic *asic, const char* param)
+int umr_print_pp_table(struct umr_asic *asic, const char *param)
{
- FILE* fp;
- int ret = -1;
+ FILE *fp;
+ int res;
char name[256];
snprintf(name, sizeof(name)-1, \
- "/sys/class/drm/card%d/device/pp_table", asic->instance);
+"/sys/class/drm/card%d/device/pp_table", asic->instance);
fp = fopen(name, "r");
- if (fp) {
- if (strcmp(asic->asicname, "navi10") == 0 ||
strcmp(asic->asicname, "navi14") == 0) {
- ret = umr_navi10_pptable_print(param, fp);
- }
- fclose(fp);
+ if (!fp) {
+ asic->err_msg("fopen: %s: %d\n", strerror(errno), errno);
+ return -errno;
+ }
+ if (strcmp(asic->asicname, "navi10") == 0 ||
+ strcmp(asic->asicname, "navi14") == 0) {
+ res = umr_navi10_pptable_print(param, fp);
} else {
- printf("Powerplay table feature only support on Navi10/Navi14
now.");
- return -1;
+ asic->err_msg("The powerplay table feature is currently
supported only on Navi10/Navi14.\n");
+ res = -1;
}
+ fclose(fp);
- return ret;
+ return res;
}
--
2.35.1.607.gf01e51a7cf
