Reminder: Only 2 days left to nominate candidates for the 2023 X.Org Board of Directors Elections
Further reminder that the nomination period for the X.Org Board of Director elections finishes in only 2 days, on March 19th. Please send your nominations or self-nominations as soon as possible following the instructions below. Thanks again for your attention. On Mon, 2023-03-13 at 16:27 +0100, Ricardo Garcia wrote: > This is a reminder that the nomination period for the X.Org Board of > Director elections finishes in a week, on March 19th. > > If you would like to nominate yourself please send email to the election > committee electi...@x.org, giving your > > name > current professional affiliation > a statement of contribution to X.Org or related technologies > a personal statement. > > To vote or to be elected to the Board you needed to be a Member of the > X.Org Foundation. To be a Member of the X.Org Foundation you need to > apply or renew your membership until the end of the nomination period. > > Original email follows below. Thanks for your attention. > > On Wed, 2023-02-15 at 21:53 +0100, Ricardo Garcia wrote: > > We are seeking nominations for candidates for election to the X.Org > > Foundation Board of Directors. All X.Org Foundation members are eligible > > for election to the board. > > > > Nominations for the 2023 election are now open and will remain open > > until 23:59 UTC on 19 March 2023. > > > > The Board consists of directors elected from the membership. Each year, > > an election is held to bring the total number of directors to eight. The > > four members receiving the highest vote totals will serve as directors > > for two year terms. > > > > The directors who received two year terms starting in 2022 were Emma > > Anholt, Mark Filion, Alyssa Rosenzweig and Ricardo Garcia. They will > > continue to serve until their term ends in 2024. Current directors whose > > term expires in 2023 are Samuel Iglesias Gonsálvez, Manasi D Navare, > > Lyude Paul and Daniel Vetter. > > > > A director is expected to participate in the fortnightly IRC meeting to > > discuss current business and to attend the annual meeting of the X.Org > > Foundation, which will be held at a location determined in advance by > > the Board of Directors. > > > > A member may nominate themselves or any other member they feel is > > qualified. Nominations should be sent to the Election Committee at > > elections at x.org. > > > > Nominees shall be required to be current members of the X.Org > > Foundation, and submit a personal statement of up to 200 words that will > > be provided to prospective voters. The collected statements, along with > > the statement of contribution to the X.Org Foundation in the member's > > account page on http://members.x.org, will be made available to all > > voters to help them make their voting decisions. > > > > Nominations, membership applications or renewals and completed personal > > statements must be received no later than 23:59 UTC on 19 March 2023. > > > > The slate of candidates will be published 26 March 2023 and candidate > > Q will begin then. The deadline for Xorg membership applications and > > renewals is 26 March 2023. > > > > Cheers, > > Ricardo Garcia, on behalf of the X.Org BoD > > >
[PATCH 19/19] drm/amdgpu/smu11: enable TEMP_DEPENDENT_VMIN for navi1x
From: Alex Deucher May help stability with some navi1x boards. Hopefully this helps with stability with multiple monitors and would allow us to re-enable MPC_SPLIT_DYNAMIC in the DC code for better power savings. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2196 Reviewed-by: Rodrigo Siqueira Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 95da6dd1cc65..c4000518dc56 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -304,7 +304,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_GFX_SS_BIT) | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) | FEATURE_MASK(FEATURE_FW_CTF_BIT) - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); + | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT) + | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); -- 2.34.1
[PATCH 18/19] drm/amd/display: 3.2.228
From: Aric Cyr This DC version brings along: - Power down eDP if eDP not present - Set MPC_SPLIT_DYNAMIC for DCN10 and DCN301 - Initialize link_srv in virtual env - Code cleanup and alignment Acked-by: Qingqing Zhuo Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1e6fa2d387f7..475128db02bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.227" +#define DC_VER "3.2.228" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH 17/19] drm/amd/display: Set dcn32 caps.seamless_odm
From: Hersen Wu
[Why & How]
seamless_odm set was not picked up while
merging 2d017189e2b3 ("drm/amd/display:
Blank eDP on enable drv if odm enabled")
Fixes: 2d017189e2b3 ("drm/amd/display: Blank eDP on enable drv if odm enabled")
Reviewed-by: Qingqing Zhuo
Acked-by: Qingqing Zhuo
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 633491331722..1715909b1225 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2185,6 +2185,7 @@ static bool dcn32_resource_construct(
dc->caps.edp_dsc_support = true;
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
+ dc->caps.seamless_odm = true;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
--
2.34.1
[PATCH 16/19] drm/amd/display: fix wrong index used in dccg32_set_dpstreamclk
From: Hersen Wu
[Why & How]
When merging commit 8f6de23e03f1
("drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming"),
index change was not picked up.
Cc: sta...@vger.kernel.org
Cc: Mario Limonciello
Fixes: 8f6de23e03f1 ("drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming")
Reviewed-by: Qingqing Zhuo
Acked-by: Qingqing Zhuo
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 5dbef498580b..ffbb739d85b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -293,8 +293,7 @@ static void dccg32_set_dpstreamclk(
dccg32_set_dtbclk_p_src(dccg, src, otg_inst);
/* enabled to select one of the DTBCLKs for pipe */
- switch (otg_inst)
- {
+ switch (dp_hpo_inst) {
case 0:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK0_EN,
--
2.34.1
[PATCH 15/19] drm/amd/display: align commit_planes_for_stream to latest dc code
From: Hersen Wu
[Why & How]
Due to historic issues, commit_planes_for_stream() has grown differently
compared to latest dc code. Apply missed changes to make it aligned.
Acked-by: Qingqing Zhuo
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +++-
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dc67256f565d..40f2e174c524 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3493,22 +3493,6 @@ static void commit_planes_for_stream(struct dc *dc,
dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates,
context);
- if (update_type != UPDATE_TYPE_FAST) {
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *new_pipe =
>res_ctx.pipe_ctx[i];
-
- if ((new_pipe->stream &&
new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) ||
- subvp_prev_use) {
- // If old context or new context has phantom
pipes, apply
- // the phantom timings now. We can't change the
phantom
- // pipe configuration safely without driver
acquiring
- // the DMCUB lock first.
- dc->hwss.apply_ctx_to_hw(dc, context);
- break;
- }
- }
- }
-
// Stream updates
if (stream_update)
commit_planes_do_stream_update(dc, stream, stream_update,
update_type, context);
@@ -3724,6 +3708,9 @@ static void commit_planes_for_stream(struct dc *dc,
}
}
+ if (update_type != UPDATE_TYPE_FAST)
+ dc->hwss.post_unlock_program_front_end(dc, context);
+
if (subvp_prev_use && !subvp_curr_use) {
/* If disabling subvp, disable phantom streams after front end
* programming has completed (we turn on phantom OTG in order
@@ -3732,16 +3719,9 @@ static void commit_planes_for_stream(struct dc *dc,
dc->hwss.apply_ctx_to_hw(dc, context);
}
- if (update_type != UPDATE_TYPE_FAST)
- dc->hwss.post_unlock_program_front_end(dc, context);
if (update_type != UPDATE_TYPE_FAST)
if (dc->hwss.commit_subvp_config)
dc->hwss.commit_subvp_config(dc, context);
-
- if (update_type != UPDATE_TYPE_FAST)
- if (dc->hwss.commit_subvp_config)
- dc->hwss.commit_subvp_config(dc, context);
-
/* Since phantom pipe programming is moved to
post_unlock_program_front_end,
* move the SubVP lock to after the phantom pipes have been setup
*/
--
2.34.1
[PATCH 14/19] Revert "drm/amdgpu/display: change pipe policy for DCN 2.0"
From: Alex Deucher
This reverts commit bcfab8e35ce81e2fd3230c1575024bfde0d28c8b.
Hopefully this is fixed by the previous patch to enable
TEMP_DEPENDENT_VMIN for navi1x or otherwise and we can re-enable
MPC_SPLIT_DYNAMIC for DCN 2.0 for better power savings.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 77ef474ced07..1d8c5805ef20 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -712,7 +712,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
--
2.34.1
[PATCH 13/19] drm/amd/display: Set MPC_SPLIT_DYNAMIC for DCN301
From: Rodrigo Siqueira
Since DC version 3.2.226, DC started to use a new internal commit
sequence that better deals with hardware limitations. Usually, DC adopts
split pipe dynamics to improve the display bandwidth and, in some cases,
to save power. This commit sets MPC_SPLIT_DYNAMIC for DCN301, improving
the bandwidth and fixing the cursor bug on KDE when it tries hardware
rotation.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2247
Cc: Melissa Wen
Cc: Xaver Hugl
Reviewed-by: Melissa Wen
Acked-by: Qingqing Zhuo
Acked-by: Hamza Mahfooz
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index b93b4498dba4..5ac2a272c380 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -687,7 +687,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_clock_gate = true,
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = true,
- .pipe_split_policy = MPC_SPLIT_AVOID,
+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
--
2.34.1
[PATCH 12/19] drm/amd/display: Set MPC_SPLIT_DYNAMIC for DCN10
From: Rodrigo Siqueira
Since DC version 3.2.226, DC started to use a new internal commit
sequence that better deals with multiple hardware constraints. One of
the improvements is a more reliable sequence for pipe split. Due to the
transition made in version 3.2.226, it should be more reliable to use
the pipe policy as MPC_SPLIT_DYNAMIC, and this commit makes this change.
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 2bb8e11f26e0..21ec1ba5ed75 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -542,8 +542,8 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_pplib_clock_request = false,
.disable_pplib_wm_range = false,
.pplib_wm_report_mode = WM_REPORT_DEFAULT,
- .pipe_split_policy = MPC_SPLIT_AVOID,
- .force_single_disp_pipe_split = false,
+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+ .force_single_disp_pipe_split = true,
.disable_dcc = DCC_ENABLE,
.voltage_align_fclk = true,
.disable_stereo_support = true,
--
2.34.1
[PATCH 11/19] drm/amd/display: add missing code change init pix_per_cycle
From: Charlene Liu
[why]
missing change when port to these two dcn version.
Reviewed-by: Chris Park
Reviewed-by: Leo Ma
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
index 89de64f18040..d05e7655f603 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
@@ -294,6 +294,7 @@ static void enc32_stream_encoder_dp_unblank(
|| is_dp_dig_pixel_rate_div_policy(dc, >timing))
{
/*this logic should be the same in
get_pixel_clock_parameters() */
n_multiply = 1;
+ pix_per_cycle = 1;
}
/* M / N = Fstream / Flink
* m_vid / n_vid = pixel rate / link rate
--
2.34.1
[PATCH 10/19] drm/amd/display: Add CRC and DMUB test support
From: Charlene Liu
[Why & How]
- Add CRC for test support
- Add params to allow control into to DMUB.
Reviewed-by: Chris Park
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 29 +++
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 ++
.../gpu/drm/amd/display/include/dal_asic_id.h | 1 +
3 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 0b37bb0e184b..db766689af58 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -161,10 +161,20 @@ struct dcn_optc_registers {
uint32_t OTG_CRC_CNTL2;
uint32_t OTG_CRC0_DATA_RG;
uint32_t OTG_CRC0_DATA_B;
+ uint32_t OTG_CRC1_DATA_B;
+ uint32_t OTG_CRC2_DATA_B;
+ uint32_t OTG_CRC3_DATA_B;
+ uint32_t OTG_CRC1_DATA_RG;
+ uint32_t OTG_CRC2_DATA_RG;
+ uint32_t OTG_CRC3_DATA_RG;
uint32_t OTG_CRC0_WINDOWA_X_CONTROL;
uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
+ uint32_t OTG_CRC1_WINDOWA_X_CONTROL;
+ uint32_t OTG_CRC1_WINDOWA_Y_CONTROL;
+ uint32_t OTG_CRC1_WINDOWB_X_CONTROL;
+ uint32_t OTG_CRC1_WINDOWB_Y_CONTROL;
uint32_t GSL_SOURCE_SELECT;
uint32_t DWB_SOURCE_SELECT;
uint32_t OTG_DSC_START_POSITION;
@@ -464,6 +474,15 @@ struct dcn_optc_registers {
type CRC0_R_CR;\
type CRC0_G_Y;\
type CRC0_B_CB;\
+ type CRC1_R_CR;\
+ type CRC1_G_Y;\
+ type CRC1_B_CB;\
+ type CRC2_R_CR;\
+ type CRC2_G_Y;\
+ type CRC2_B_CB;\
+ type CRC3_R_CR;\
+ type CRC3_G_Y;\
+ type CRC3_B_CB;\
type OTG_CRC0_WINDOWA_X_START;\
type OTG_CRC0_WINDOWA_X_END;\
type OTG_CRC0_WINDOWA_Y_START;\
@@ -472,6 +491,15 @@ struct dcn_optc_registers {
type OTG_CRC0_WINDOWB_X_END;\
type OTG_CRC0_WINDOWB_Y_START;\
type OTG_CRC0_WINDOWB_Y_END;\
+ type OTG_CRC_WINDOW_DB_EN;\
+ type OTG_CRC1_WINDOWA_X_START;\
+ type OTG_CRC1_WINDOWA_X_END;\
+ type OTG_CRC1_WINDOWA_Y_START;\
+ type OTG_CRC1_WINDOWA_Y_END;\
+ type OTG_CRC1_WINDOWB_X_START;\
+ type OTG_CRC1_WINDOWB_X_END;\
+ type OTG_CRC1_WINDOWB_Y_START;\
+ type OTG_CRC1_WINDOWB_Y_END;\
type GSL0_READY_SOURCE_SEL;\
type GSL1_READY_SOURCE_SEL;\
type GSL2_READY_SOURCE_SEL;\
@@ -525,6 +553,7 @@ struct dcn_optc_registers {
#define TG_REG_FIELD_LIST_DCN3_2(type) \
type OTG_H_TIMING_DIV_MODE_MANUAL;
+
struct dcn_optc_shift {
TG_REG_FIELD_LIST(uint8_t)
TG_REG_FIELD_LIST_DCN3_2(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index a391b939d709..ba1715e2d25a 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -261,6 +261,8 @@ struct dmub_srv_hw_params {
bool usb4_cm_version;
bool fw_in_system_memory;
bool dpia_hpd_int_enable_supported;
+ bool disable_clock_gate;
+ bool disallow_dispclk_dppclk_ds;
};
/**
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index c3089c673975..e317089cf6ee 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -246,6 +246,7 @@ enum {
#define AMDGPU_FAMILY_GC_11_0_0 145
#define AMDGPU_FAMILY_GC_11_0_1 148
+#define AMDGPU_FAMILY_GC_11_5_0 150
#define GC_11_0_0_A0 0x1
#define GC_11_0_2_A0 0x10
#define GC_11_0_3_A0 0x20
--
2.34.1
[PATCH 09/19] drm/amd/display: Add function pointer for validate bw usb4
From: Mustapha Ghaddar
[WHY]
In order to follow the new protocol of calling link functions
[HOW]
Add the function pointer to the link_srv
Reviewed-by: Kshitij Bhardwaj
Acked-by: Qingqing Zhuo
Signed-off-by: Mustapha Ghaddar
---
.../drm/amd/display/dc/core/dc_link_exports.c | 5 +
drivers/gpu/drm/amd/display/dc/dc.h| 13 +
drivers/gpu/drm/amd/display/dc/inc/link.h | 3 +++
.../gpu/drm/amd/display/dc/link/link_factory.c | 1 +
.../drm/amd/display/dc/link/link_validation.c | 18 ++
.../drm/amd/display/dc/link/link_validation.h | 4
.../dc/link/protocols/link_dp_dpia_bw.c| 9 ++---
.../dc/link/protocols/link_dp_dpia_bw.h| 7 ++-
8 files changed, 52 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index d24bc0a0b1d4..18e098568cb4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -473,3 +473,8 @@ void dc_link_enable_hpd_filter(struct dc_link *link, bool
enable)
{
link->dc->link_srv->enable_hpd_filter(link, enable);
}
+
+bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams,
const unsigned int count)
+{
+ return dc->link_srv->validate_dpia_bandwidth(streams, count);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 624acd402eae..1e6fa2d387f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2028,6 +2028,19 @@ void dc_link_handle_usb4_bw_alloc_response(struct
dc_link *link,
int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
struct dc_link *link, int peak_bw);
+/*
+ * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
+ * available BW for each host router
+ *
+ * @dc: pointer to dc struct
+ * @stream: pointer to all possible streams
+ * @num_streams: number of valid DPIA streams
+ *
+ * return: TRUE if bw used by DPIAs doesn't exceed available BW else return
FALSE
+ */
+bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams,
+ const unsigned int count);
+
/* Sink Interfaces - A sink corresponds to a display output device */
struct dc_container_id {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h
b/drivers/gpu/drm/amd/display/dc/inc/link.h
index 11aaa7a9518a..f839494d59d8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link.h
@@ -144,6 +144,9 @@ struct link_service {
uint32_t (*dp_link_bandwidth_kbps)(
const struct dc_link *link,
const struct dc_link_settings *link_settings);
+ bool (*validate_dpia_bandwidth)(
+ const struct dc_stream_state *stream,
+ const unsigned int num_streams);
/*** DPMS */
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 3951d48118c4..1515c817f03b 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -99,6 +99,7 @@ static void construct_link_service_validation(struct
link_service *link_srv)
{
link_srv->validate_mode_timing = link_validate_mode_timing;
link_srv->dp_link_bandwidth_kbps = dp_link_bandwidth_kbps;
+ link_srv->validate_dpia_bandwidth = link_validate_dpia_bandwidth;
}
/* link dpms owns the programming sequence of stream's dpms state associated
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index 9a5010f86003..139012ab20e3 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -30,6 +30,7 @@
*/
#include "link_validation.h"
#include "protocols/link_dp_capability.h"
+#include "protocols/link_dp_dpia_bw.h"
#include "resource.h"
#define DC_LOGGER_INIT(logger)
@@ -394,3 +395,20 @@ enum dc_status link_validate_mode_timing(
return DC_OK;
}
+
+bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const
unsigned int num_streams)
+{
+ bool ret = true;
+ int bw_needed[MAX_DPIA_NUM];
+ struct dc_link *link[MAX_DPIA_NUM];
+
+ if (!num_streams || num_streams > MAX_DPIA_NUM)
+ return ret;
+
+ for (uint8_t i = 0; i < num_streams; ++i) {
+
+ link[i] = stream[i].link;
+ bw_needed[i] =
dc_bandwidth_in_kbps_from_timing([i].timing);
+ }
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.h
b/drivers/gpu/drm/amd/display/dc/link/link_validation.h
index 2191d3a4950c..4a954317d0da 100644
---
[PATCH 08/19] drm/amd/display: initialize link_srv in virtual env
From: Martin Leung [why] when refactoring to link_srv, we did not include the virtual environment case where dc_construct_ctx gets called instead of dc_construct [how] add initialize link_srv to dc_construct_ctx as well Reviewed-by: Leo Ma Acked-by: Qingqing Zhuo Signed-off-by: Martin Leung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ae5f1b7b4fef..dc67256f565d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -887,6 +887,7 @@ static bool dc_construct_ctx(struct dc *dc, } dc->ctx = dc_ctx; + dc->link_srv = link_create_link_service(); return true; } -- 2.34.1
[PATCH 07/19] drm/amd/display: power down eDP if eDP not present
From: Paul Hsieh
[Why]
When init, driver will power up eDP to check eDP
present or not. If eDP not present, driver doesn't
power off eDP VDD cause power consumption.
[How]
If eDP is not present when detection, power off eDP
VDD.
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/link/link_detection.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index fee71ebdfc73..57cf6fa0de7a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -1225,6 +1225,11 @@ bool link_detect_connection_type(struct dc_link *link,
enum dc_connection_type *
/* TODO: need to do the actual detection */
} else {
*type = dc_connection_none;
+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
+ /* eDP is not connected, power down it */
+ if (!link->dc->config.edp_no_power_sequencing)
+ link->dc->hwss.edp_power_control(link, false);
+ }
}
return true;
--
2.34.1
[PATCH 06/19] drm/amd/display: update dio for two pixel per container case
From: Charlene Liu [why] Processing rate of the DP encoder, must be programmed to be the same as DIG_FIFO_OUTPUT_ PROCESSING_MODE in DP mode 0: 1 pixel per cycle 1: 2 pixel per cycle Reviewed-by: Alvin Lee Acked-by: Qingqing Zhuo Signed-off-by: Charlene Liu --- .../gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c index c72448125976..89de64f18040 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -286,6 +286,7 @@ static void enc32_stream_encoder_dp_unblank( uint32_t n_vid = 0x8000; uint32_t m_vid; uint32_t n_multiply = 0; + uint32_t pix_per_cycle = 0; uint64_t m_vid_l = n_vid; /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ @@ -320,6 +321,10 @@ static void enc32_stream_encoder_dp_unblank( REG_UPDATE_2(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1, DP_VID_N_MUL, n_multiply); + + REG_UPDATE(DP_PIXEL_FORMAT, + DP_PIXEL_PER_CYCLE_PROCESSING_MODE, + pix_per_cycle); } /* make sure stream is disabled before resetting steer fifo */ -- 2.34.1
[PATCH 05/19] drm/amd/display: skip wait vblank
From: Zhikai Zhai
[WHY]
There is no need to wait vblank in the vupdate locked
region at a full type update
[HOW]
skip wait vblank when global sync change
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Zhikai Zhai
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 53669f832ba5..69ea1f4ea749 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1720,10 +1720,8 @@ static void dcn20_program_pipe(
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width);
- if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM)
{
-
pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
CRTC_STATE_VBLANK);
+ if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM)
pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
CRTC_STATE_VACTIVE);
- }
pipe_ctx->stream_res.tg->funcs->set_vtg_params(
pipe_ctx->stream_res.tg,
_ctx->stream->timing, true);
--
2.34.1
[PATCH 03/19] drm/amd/display: Make DCN32 3dlut function available to future DCNs
From: Wesley Chalmers
[Why & How]
Make DCN32 3dlut function non-static and thus
available for future DCNs.
Reviewed-by: Chris Park
Acked-by: Qingqing Zhuo
Signed-off-by: Wesley Chalmers
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 5016b1313f3d..42255c22605d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -414,7 +414,7 @@ void dcn32_subvp_pipe_control_lock(struct dc *dc,
}
-static bool dcn32_set_mpc_shaper_3dlut(
+bool dcn32_set_mpc_shaper_3dlut(
struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
{
struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
index 84c1f36c3fa6..2a5376eb9d66 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
@@ -54,6 +54,9 @@ bool dcn32_set_input_transfer_func(struct dc *dc,
struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
+bool dcn32_set_mpc_shaper_3dlut(
+ struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream);
+
bool dcn32_set_output_transfer_func(struct dc *dc,
struct pipe_ctx *pipe_ctx,
const struct dc_stream_state *stream);
--
2.34.1
[PATCH 04/19] drm/amd/display: Add const to a function
From: Rodrigo Siqueira
When calling the dc_link_bw_kbps_from_raw_frl_link_rate_data from
amdgpu_dm, GCC highlighted the following issue:
In function ‘get_conv_frl_bw’:
error: passing argument 1 of
‘dc_link_bw_kbps_from_raw_frl_link_rate_data’ discards ‘const’ qualifier
from pointer target type [-Werror=discarded-qualifiers]
997 | aconnector->dc_link->dc,
This commit fix this issue by making DC a constant variable since we
only use it to invoke the function
bw_kbps_from_raw_frl_link_rate_data().
Reviewed-by: Chris Park
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c | 3 +--
drivers/gpu/drm/amd/display/dc/dc.h | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index 58fa911b1417..d24bc0a0b1d4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -285,8 +285,7 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
ddc, payload, operation_result);
}
-uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(
- struct dc *dc, uint8_t bw)
+uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc,
uint8_t bw)
{
return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2818483964dd..624acd402eae 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1768,8 +1768,7 @@ void dc_restore_link_res_map(const struct dc *dc,
uint32_t *map);
bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
/* translate a raw link rate data to bandwidth in kbps */
-uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(
- struct dc *dc, uint8_t bw);
+uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc,
uint8_t bw);
/* determine the optimal bandwidth given link and required bw.
* @link - current detected link
--
2.34.1
[PATCH 02/19] drm/amd/display: remove outdated 8bpc comments
From: Alex Hung
[Why]
The commit ad9adba9d1cf ("drm/amd/display: Don't restrict bpc to 8 bpc")
removes the historical 8bpc dependency and sets max_bpc to 16.
[How]
The comment that states "8bpc for non-edp" needs to be removed as well.
Reviewed-by: Harry Wentland
Acked-by: Qingqing Zhuo
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ae0a223b90a1..724c565ae688 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7283,7 +7283,6 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
if (!aconnector->mst_root)
drm_connector_attach_max_bpc_property(>base, 8, 16);
- /* This defaults to the max in the range, but we want 8bpc for non-edp.
*/
aconnector->base.state->max_bpc = 16;
aconnector->base.state->max_requested_bpc =
aconnector->base.state->max_bpc;
--
2.34.1
[PATCH 01/19] drm/amd/display: Implement workaround for writing to OTG_PIXEL_RATE_DIV register
From: Saaem Rizvi
[Why and How]
Current implementation requires FPGA builds to take a different
code path from DCN32 to write to OTG_PIXEL_RATE_DIV. Now that
we have a workaround to write to OTG_PIXEL_RATE_DIV register without
blanking display on hotplug on DCN32, we can allow the code paths for
FPGA to be exactly the same allowing for more consistent
testing.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Saaem Rizvi
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 3 ++-
.../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 22 +++
.../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h | 3 ++-
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 2 +-
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 3 ++-
5 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 915a20461c77..893c0809cd4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -230,7 +230,8 @@
type DTBCLK_P2_SRC_SEL;\
type DTBCLK_P2_EN;\
type DTBCLK_P3_SRC_SEL;\
- type DTBCLK_P3_EN;
+ type DTBCLK_P3_EN;\
+ type DENTIST_DISPCLK_CHG_DONE;
struct dccg_shift {
DCCG_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index e4472c6be6c3..5dbef498580b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -42,6 +42,20 @@
#define DC_LOGGER \
dccg->ctx->logger
+/* This function is a workaround for writing to OTG_PIXEL_RATE_DIV
+ * without the probability of causing a DIG FIFO error.
+ */
+static void dccg32_wait_for_dentist_change_done(
+ struct dccg *dccg)
+{
+ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+ uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);
+
+ REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);
+ REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
+}
+
static void dccg32_get_pixel_rate_div(
struct dccg *dccg,
uint32_t otg_inst,
@@ -110,21 +124,29 @@ static void dccg32_set_pixel_rate_div(
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
OTG0_PIXEL_RATE_DIVK1, k1,
OTG0_PIXEL_RATE_DIVK2, k2);
+
+ dccg32_wait_for_dentist_change_done(dccg);
break;
case 1:
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
OTG1_PIXEL_RATE_DIVK1, k1,
OTG1_PIXEL_RATE_DIVK2, k2);
+
+ dccg32_wait_for_dentist_change_done(dccg);
break;
case 2:
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
OTG2_PIXEL_RATE_DIVK1, k1,
OTG2_PIXEL_RATE_DIVK2, k2);
+
+ dccg32_wait_for_dentist_change_done(dccg);
break;
case 3:
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
OTG3_PIXEL_RATE_DIVK1, k1,
OTG3_PIXEL_RATE_DIVK2, k2);
+
+ dccg32_wait_for_dentist_change_done(dccg);
break;
default:
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
index 271c163e4844..8071ab98d708 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
@@ -111,7 +111,8 @@
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
- DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh)
+ DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
+ DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
struct dccg *dccg32_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index f9073b722b36..5016b1313f3d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -,7 +,7 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct
pipe_ctx *pipe_ctx, unsign
*k2_div = PIXEL_RATE_DIV_BY_2;
else
*k2_div = PIXEL_RATE_DIV_BY_4;
- } else if (dc_is_dp_signal(stream->signal)) {
+ } else if (dc_is_dp_signal(stream->signal) ||
dc_is_virtual_signal(stream->signal)) {
if (two_pix_per_container) {
*k1_div = PIXEL_RATE_DIV_BY_1;
*k2_div = PIXEL_RATE_DIV_BY_2;
diff --git
[PATCH 00/19] DC Patches Mar 20th, 2023
This DC patchset brings improvements in multiple areas. In summary, we highlight: - Power down eDP if eDP not present - Set MPC_SPLIT_DYNAMIC for DCN10 and DCN301 - Initialize link_srv in virtual env - Code cleanup and alignment Cc: Daniel Wheeler --- Alex Deucher (2): Revert "drm/amdgpu/display: change pipe policy for DCN 2.0" drm/amdgpu/smu11: enable TEMP_DEPENDENT_VMIN for navi1x Alex Hung (1): drm/amd/display: remove outdated 8bpc comments Aric Cyr (1): drm/amd/display: 3.2.228 Charlene Liu (3): drm/amd/display: update dio for two pixel per container case drm/amd/display: Add CRC and DMUB test support drm/amd/display: add missing code change init pix_per_cycle Hersen Wu (3): drm/amd/display: align commit_planes_for_stream to latest dc code drm/amd/display: fix wrong index used in dccg32_set_dpstreamclk drm/amd/display: Set dcn32 caps.seamless_odm Martin Leung (1): drm/amd/display: initialize link_srv in virtual env Mustapha Ghaddar (1): drm/amd/display: Add function pointer for validate bw usb4 Paul Hsieh (1): drm/amd/display: power down eDP if eDP not present Rodrigo Siqueira (3): drm/amd/display: Add const to a function drm/amd/display: Set MPC_SPLIT_DYNAMIC for DCN10 drm/amd/display: Set MPC_SPLIT_DYNAMIC for DCN301 Saaem Rizvi (1): drm/amd/display: Implement workaround for writing to OTG_PIXEL_RATE_DIV register Wesley Chalmers (1): drm/amd/display: Make DCN32 3dlut function available to future DCNs Zhikai Zhai (1): drm/amd/display: skip wait vblank .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - drivers/gpu/drm/amd/display/dc/core/dc.c | 27 +++-- .../drm/amd/display/dc/core/dc_link_exports.c | 8 +++-- drivers/gpu/drm/amd/display/dc/dc.h | 18 ++-- .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 29 +++ .../drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +-- .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 3 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 +-- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- .../amd/display/dc/dcn301/dcn301_resource.c | 2 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 25 ++-- .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h | 3 +- .../dc/dcn32/dcn32_dio_stream_encoder.c | 6 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 4 +-- .../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 3 ++ .../drm/amd/display/dc/dcn32/dcn32_resource.c | 1 + .../drm/amd/display/dc/dcn32/dcn32_resource.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/link.h | 3 ++ .../drm/amd/display/dc/link/link_detection.c | 5 .../drm/amd/display/dc/link/link_factory.c| 1 + .../drm/amd/display/dc/link/link_validation.c | 18 .../drm/amd/display/dc/link/link_validation.h | 4 +++ .../dc/link/protocols/link_dp_dpia_bw.c | 9 ++ .../dc/link/protocols/link_dp_dpia_bw.h | 7 - drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 ++ .../gpu/drm/amd/display/include/dal_asic_id.h | 1 + .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +- 27 files changed, 144 insertions(+), 52 deletions(-) -- 2.34.1
