[PATCH 1/2] drm/amdgpu: update SMC firmware image for polaris10 variants
Some new variants require different firmwares.
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index ceadeeadfa56..387f1cf1dc20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -381,7 +381,8 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device
*cgs_device,
(adev->pdev->revision == 0xe7) ||
(adev->pdev->revision == 0xef)))
||
((adev->pdev->device == 0x6fdf) &&
-(adev->pdev->revision == 0xef))) {
+((adev->pdev->revision == 0xef) ||
+ (adev->pdev->revision == 0xff
{
info->is_kicker = true;
strcpy(fw_name,
"amdgpu/polaris10_k_smc.bin");
} else if ((adev->pdev->device ==
0x67df) &&
--
2.17.1
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[PATCH 2/2] drm/amdgpu: update MC firmware image for polaris10 variants
Some new variants require different firmwares. Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 1ad7e6b8ed1d..0edb8622f666 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -244,7 +244,10 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_POLARIS10: if ((adev->pdev->device == 0x67df) && ((adev->pdev->revision == 0xe1) || -(adev->pdev->revision == 0xf7))) +(adev->pdev->revision == 0xf7)) || + ((adev->pdev->device == 0x6fdf) && +((adev->pdev->revision == 0xef) || + (adev->pdev->revision == 0xff chip_name = "polaris10_k"; else chip_name = "polaris10"; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: disable UVD/VCE for some polaris10 variants
Some variants don't support UVD and VCE.
Signed-off-by: Junwei Zhang
Reviewed-by: Flora Cui
---
drivers/gpu/drm/amd/amdgpu/vi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index f3a4cf1f013a..16a28d20be82 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1660,8 +1660,13 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _v11_2_ip_block);
amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
amdgpu_device_ip_block_add(adev, _v3_1_ip_block);
- amdgpu_device_ip_block_add(adev, _v6_3_ip_block);
- amdgpu_device_ip_block_add(adev, _v3_4_ip_block);
+ if ((adev->pdev->device == 0x67df) &&
+ (adev->pdev->revision == 0xf7)) {
+ /* Some polaris10 variants don't support UVD/VCE */
+ } else {
+ amdgpu_device_ip_block_add(adev, _v6_3_ip_block);
+ amdgpu_device_ip_block_add(adev, _v3_4_ip_block);
+ }
break;
case CHIP_CARRIZO:
amdgpu_device_ip_block_add(adev, _common_ip_block);
--
2.17.1
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[PATCH] drm/amdgpu: disable UVD/VCE for some polaris 12 variants
Some variants don't support UVD and VCE. Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/vi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index f3a4cf1f013a..3338b013ded4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1660,6 +1660,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _v11_2_ip_block); amdgpu_device_ip_block_add(adev, _v8_0_ip_block); amdgpu_device_ip_block_add(adev, _v3_1_ip_block); + /* Some polaris12 variants don't support UVD/VCE */ + if ((adev->pdev->device == 0x67df) && + (adev->pdev->revision == 0xf7)) + break; amdgpu_device_ip_block_add(adev, _v6_3_ip_block); amdgpu_device_ip_block_add(adev, _v3_4_ip_block); break; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: disable UVD/VCE for some polaris 12 variants
Some variants don't support UVD and VCE. Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/vi.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index f3a4cf1f013a..46a92eca831b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1660,6 +1660,11 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _v11_2_ip_block); amdgpu_device_ip_block_add(adev, _v8_0_ip_block); amdgpu_device_ip_block_add(adev, _v3_1_ip_block); + /* Some polaris12 variants don't support UVD/VCE */ + if (((adev->pdev->device == 0x67df) && +((adev->pdev->revision == 0xe1) || + (adev->pdev->revision == 0xf7 + break; amdgpu_device_ip_block_add(adev, _v6_3_ip_block); amdgpu_device_ip_block_add(adev, _v3_4_ip_block); break; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix gfx wptr for sdma v4
The wptr value will be shitfed when function returns.
Remove the redundant shift and clean up.
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 2b944db86950..da3b6d9cf4a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -372,16 +372,11 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct
amdgpu_ring *ring)
wptr = READ_ONCE(*((u64 *)>wb.wb[ring->wptr_offs]));
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
- u32 lowbit, highbit;
-
- lowbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR) >> 2;
- highbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI) >> 2;
-
- DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
- ring->me, highbit, lowbit);
- wptr = highbit;
+ wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
wptr = wptr << 32;
- wptr |= lowbit;
+ wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
+ DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
+ ring->me, wptr);
}
return wptr >> 2;
--
2.17.1
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[PATCH libdrm] amdgpu: add error return value for finding bo by cpu mapping (v2)
If nothing is found, error should be returned.
v2: udpate the error value different from parameter check
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
Reviewed-by: Michel Dänzer
---
amdgpu/amdgpu_bo.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 2f4f90f..a2fc525 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -549,8 +549,9 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
amdgpu_bo_handle *buf_handle,
uint64_t *offset_in_bo)
{
- uint32_t i;
struct amdgpu_bo *bo;
+ uint32_t i;
+ int r = 0;
if (cpu == NULL || size == 0)
return -EINVAL;
@@ -577,10 +578,11 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle
dev,
} else {
*buf_handle = NULL;
*offset_in_bo = 0;
+ r = -ENXIO;
}
pthread_mutex_unlock(>bo_table_mutex);
- return 0;
+ return r;
}
int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
--
1.9.1
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[PATCH libdrm] amdgpu: add error return value for finding bo by cpu mapping
If nothing is found, error should be returned.
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 2f4f90f..3812c5e 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -550,6 +550,7 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
uint64_t *offset_in_bo)
{
uint32_t i;
+ int r = 0;
struct amdgpu_bo *bo;
if (cpu == NULL || size == 0)
@@ -577,10 +578,11 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle
dev,
} else {
*buf_handle = NULL;
*offset_in_bo = 0;
+ r = -EINVAL;
}
pthread_mutex_unlock(>bo_table_mutex);
- return 0;
+ return r;
}
int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
--
1.9.1
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[PATCH libdrm 2/2] amdgpu: add a function to create amdgpu bo internally (v4)
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
v4: update error handling and rebase
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
amdgpu/amdgpu_bo.c | 211 +++--
1 file changed, 106 insertions(+), 105 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d9556ec..757a0d3 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -48,11 +48,31 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle
dev,
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
}
+static int amdgpu_bo_create(amdgpu_device_handle dev,
+ uint64_t size,
+ uint32_t handle,
+ amdgpu_bo_handle *buf_handle)
+{
+ struct amdgpu_bo *bo;
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+
+ atomic_set(>refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = handle;
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+
+ *buf_handle = bo;
+ return 0;
+}
+
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
- struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
@@ -61,14 +81,6 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = alloc_buffer->alloc_size;
-
memset(, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
@@ -80,24 +92,23 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
, sizeof(args));
+ if (r)
+ goto out;
+
+ r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
+buf_handle);
if (r) {
- free(bo);
- return r;
+ amdgpu_close_kms_handle(dev, args.out.handle);
+ goto out;
}
- bo->handle = args.out.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
-
+ pthread_mutex_lock(>bo_table_mutex);
+ r = handle_table_insert(>bo_handles, (*buf_handle)->handle,
+ *buf_handle);
+ pthread_mutex_unlock(>bo_table_mutex);
if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
-
+ amdgpu_bo_free(*buf_handle);
+out:
return r;
}
@@ -257,7 +268,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
struct drm_gem_open open_arg = {};
struct drm_gem_close close_arg = {};
struct amdgpu_bo *bo = NULL;
- int r;
+ uint32_t handle = 0, flink_name = 0;
+ uint64_t alloc_size = 0;
+ int r = 0;
int dma_fd;
uint64_t dma_buf_size = 0;
@@ -267,22 +280,18 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, );
- if (r) {
- pthread_mutex_unlock(>bo_table_mutex);
- return r;
- }
+ if (r)
+ goto unlock;
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
- pthread_mutex_unlock(>bo_table_mutex);
- amdgpu_close_kms_handle(dev, handle);
- return -errno;
+ r = -errno;
+ goto free_bo_handle;
}
lseek(shared_handle, 0, SEEK_SET);
@@ -303,12 +312,12 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
case amdgpu_bo_handle_type_kms:
case amdgpu_bo_handle_type_kms_noimport:
/* Importing a KMS handle in not allowed. */
-
[PATCH libdrm 1/2] amdgpu: free flink bo in bo import
Fix potential memory leak when handle flink bo in bo import.
Free the flink bo after bo import and in error handling.
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..d9556ec 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -255,6 +255,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
struct amdgpu_bo_import_result *output)
{
struct drm_gem_open open_arg = {};
+ struct drm_gem_close close_arg = {};
struct amdgpu_bo *bo = NULL;
int r;
int dma_fd;
@@ -342,15 +343,19 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
bo->handle = open_arg.handle;
if (dev->flink_fd != dev->fd) {
+ close_arg.handle = open_arg.handle;
r = drmPrimeHandleToFD(dev->flink_fd, bo->handle,
DRM_CLOEXEC, _fd);
if (r) {
free(bo);
+ drmIoctl(dev->flink_fd, DRM_IOCTL_GEM_CLOSE,
+_arg);
pthread_mutex_unlock(>bo_table_mutex);
return r;
}
r = drmPrimeFDToHandle(dev->fd, dma_fd, >handle );
close(dma_fd);
+ drmIoctl(dev->flink_fd, DRM_IOCTL_GEM_CLOSE,
_arg);
if (r) {
free(bo);
--
1.9.1
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[PATCH libdrm] amdgpu: add a function to create amdgpu bo internally (v4)
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
v4: update error handling and free flink bo in bo import
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 208 +++--
1 file changed, 107 insertions(+), 101 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..ad72f09 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -48,11 +48,31 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle
dev,
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
}
+static int amdgpu_bo_create(amdgpu_device_handle dev,
+ uint64_t size,
+ uint32_t handle,
+ amdgpu_bo_handle *buf_handle)
+{
+ struct amdgpu_bo *bo;
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+
+ atomic_set(>refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = handle;
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+
+ *buf_handle = bo;
+ return 0;
+}
+
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
- struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
@@ -61,14 +81,6 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = alloc_buffer->alloc_size;
-
memset(, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
@@ -80,24 +92,23 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
, sizeof(args));
+ if (r)
+ goto out;
+
+ r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
+buf_handle);
if (r) {
- free(bo);
- return r;
+ amdgpu_close_kms_handle(dev, args.out.handle);
+ goto out;
}
- bo->handle = args.out.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
-
+ pthread_mutex_lock(>bo_table_mutex);
+ r = handle_table_insert(>bo_handles, (*buf_handle)->handle,
+ *buf_handle);
+ pthread_mutex_unlock(>bo_table_mutex);
if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
-
+ amdgpu_bo_free(*buf_handle);
+out:
return r;
}
@@ -255,8 +266,11 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
struct amdgpu_bo_import_result *output)
{
struct drm_gem_open open_arg = {};
+ struct drm_gem_close close_args = {};
struct amdgpu_bo *bo = NULL;
- int r;
+ uint32_t handle = 0, flink_name = 0;
+ uint64_t alloc_size = 0;
+ int r = 0;
int dma_fd;
uint64_t dma_buf_size = 0;
@@ -266,22 +280,18 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, );
- if (r) {
- pthread_mutex_unlock(>bo_table_mutex);
- return r;
- }
+ if (r)
+ goto unlock;
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
- pthread_mutex_unlock(>bo_table_mutex);
- amdgpu_close_kms_handle(dev, handle);
- return -errno;
+ r = -errno;
+ goto free_bo_handle;
}
lseek(shared_handle, 0, SEEK_SET);
@@ -302,12 +312,12 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
case amdgpu_bo_handle_type_kms:
case amdgpu_bo_handle_type_kms_noimport:
[PATCH libdrm] amdgpu: add a function to create amdgpu bo internally (v3)
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 196 ++---
1 file changed, 95 insertions(+), 101 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..6f0baf1 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -48,11 +48,31 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle
dev,
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
}
+static int amdgpu_bo_create(amdgpu_device_handle dev,
+ uint64_t size,
+ uint32_t handle,
+ amdgpu_bo_handle *buf_handle)
+{
+ struct amdgpu_bo *bo;
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+
+ atomic_set(>refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = handle;
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+
+ *buf_handle = bo;
+ return 0;
+}
+
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
- struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
@@ -61,14 +81,6 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = alloc_buffer->alloc_size;
-
memset(, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
@@ -80,24 +92,23 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
, sizeof(args));
+ if (r)
+ goto out;
+
+ r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
+buf_handle);
if (r) {
- free(bo);
- return r;
+ amdgpu_close_kms_handle(dev, args.out.handle);
+ goto out;
}
- bo->handle = args.out.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
-
+ pthread_mutex_lock(>bo_table_mutex);
+ r = handle_table_insert(>bo_handles, (*buf_handle)->handle,
+ *buf_handle);
+ pthread_mutex_unlock(>bo_table_mutex);
if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
-
+ amdgpu_bo_free(*buf_handle);
+out:
return r;
}
@@ -256,7 +267,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
{
struct drm_gem_open open_arg = {};
struct amdgpu_bo *bo = NULL;
- int r;
+ uint32_t handle = 0, flink_name = 0;
+ uint64_t alloc_size = 0;
+ int r = 0;
int dma_fd;
uint64_t dma_buf_size = 0;
@@ -266,22 +279,18 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, );
- if (r) {
- pthread_mutex_unlock(>bo_table_mutex);
- return r;
- }
+ if (r)
+ goto unlock;
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
- pthread_mutex_unlock(>bo_table_mutex);
- amdgpu_close_kms_handle(dev, handle);
- return -errno;
+ r = -errno;
+ goto close_handle;
}
lseek(shared_handle, 0, SEEK_SET);
@@ -302,12 +311,12 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
case amdgpu_bo_handle_type_kms:
case amdgpu_bo_handle_type_kms_noimport:
/* Importing a KMS handle in not allowed. */
- pthread_mutex_unlock(>bo_table_mutex);
- return -EPERM;
+ r = -EPERM;
[PATCH] drm/amdgpu: move amdgpu ttm structures to amdgpu_ttm.h
code cleanup for amdgpu ttm structures
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 17 +
2 files changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c6611cf..87f4e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -776,26 +776,6 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct
ttm_buffer_object *bo,
(offset >> PAGE_SHIFT);
}
-/*
- * TTM backend functions.
- */
-struct amdgpu_ttm_gup_task_list {
- struct list_headlist;
- struct task_struct *task;
-};
-
-struct amdgpu_ttm_tt {
- struct ttm_dma_tt ttm;
- u64 offset;
- uint64_tuserptr;
- struct task_struct *usertask;
- uint32_tuserflags;
- spinlock_t guptasklock;
- struct list_headguptasks;
- atomic_tmmu_invalidations;
- uint32_tlast_set_pages;
-};
-
/**
* amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR
* pointer to memory
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 8b3cc66..b8c391a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -66,6 +66,23 @@ struct amdgpu_copy_mem {
unsigned long offset;
};
+struct amdgpu_ttm_gup_task_list {
+ struct list_headlist;
+ struct task_struct *task;
+};
+
+struct amdgpu_ttm_tt {
+ struct ttm_dma_tt ttm;
+ u64 offset;
+ uint64_tuserptr;
+ struct task_struct *usertask;
+ uint32_tuserflags;
+ spinlock_t guptasklock;
+ struct list_headguptasks;
+ atomic_tmmu_invalidations;
+ uint32_tlast_set_pages;
+};
+
extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm 2/2] [RFC] amdgpu: do not free flink bo for flink_fd
the flink bo is used to export
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 6f0baf1..5b91cfc 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -219,12 +219,6 @@ static int amdgpu_bo_export_flink(amdgpu_bo_handle bo)
bo->flink_name = flink.name;
- if (bo->dev->flink_fd != bo->dev->fd) {
- struct drm_gem_close args = {};
- args.handle = handle;
- drmIoctl(bo->dev->flink_fd, DRM_IOCTL_GEM_CLOSE, );
- }
-
pthread_mutex_lock(>dev->bo_table_mutex);
r = handle_table_insert(>dev->bo_flink_names, bo->flink_name, bo);
pthread_mutex_unlock(>dev->bo_table_mutex);
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm 1/2] amdgpu: add a function to create amdgpu bo internally (v3)
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 196 ++---
1 file changed, 95 insertions(+), 101 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..6f0baf1 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -48,11 +48,31 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle
dev,
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
}
+static int amdgpu_bo_create(amdgpu_device_handle dev,
+ uint64_t size,
+ uint32_t handle,
+ amdgpu_bo_handle *buf_handle)
+{
+ struct amdgpu_bo *bo;
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+
+ atomic_set(>refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = handle;
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+
+ *buf_handle = bo;
+ return 0;
+}
+
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
- struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
@@ -61,14 +81,6 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = alloc_buffer->alloc_size;
-
memset(, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
@@ -80,24 +92,23 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
, sizeof(args));
+ if (r)
+ goto out;
+
+ r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
+buf_handle);
if (r) {
- free(bo);
- return r;
+ amdgpu_close_kms_handle(dev, args.out.handle);
+ goto out;
}
- bo->handle = args.out.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
-
+ pthread_mutex_lock(>bo_table_mutex);
+ r = handle_table_insert(>bo_handles, (*buf_handle)->handle,
+ *buf_handle);
+ pthread_mutex_unlock(>bo_table_mutex);
if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
-
+ amdgpu_bo_free(*buf_handle);
+out:
return r;
}
@@ -256,7 +267,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
{
struct drm_gem_open open_arg = {};
struct amdgpu_bo *bo = NULL;
- int r;
+ uint32_t handle = 0, flink_name = 0;
+ uint64_t alloc_size = 0;
+ int r = 0;
int dma_fd;
uint64_t dma_buf_size = 0;
@@ -266,22 +279,18 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, );
- if (r) {
- pthread_mutex_unlock(>bo_table_mutex);
- return r;
- }
+ if (r)
+ goto unlock;
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
- pthread_mutex_unlock(>bo_table_mutex);
- amdgpu_close_kms_handle(dev, handle);
- return -errno;
+ r = -errno;
+ goto close_handle;
}
lseek(shared_handle, 0, SEEK_SET);
@@ -302,12 +311,12 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
case amdgpu_bo_handle_type_kms:
case amdgpu_bo_handle_type_kms_noimport:
/* Importing a KMS handle in not allowed. */
- pthread_mutex_unlock(>bo_table_mutex);
- return -EPERM;
+ r = -EPERM;
[PATCH libdrm 1/2] amdgpu: add a function to create amdgpu bo internally (v3)
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 195 ++---
1 file changed, 94 insertions(+), 101 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..2947715 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -48,11 +48,31 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle
dev,
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
}
+static int amdgpu_bo_create(amdgpu_device_handle dev,
+ uint64_t size,
+ uint32_t handle,
+ amdgpu_bo_handle *buf_handle)
+{
+ struct amdgpu_bo *bo;
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+
+ atomic_set(>refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = handle;
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+
+ *buf_handle = bo;
+ return 0;
+}
+
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
- struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
@@ -61,14 +81,6 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = alloc_buffer->alloc_size;
-
memset(, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
@@ -80,24 +92,23 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
, sizeof(args));
+ if (r)
+ goto out;
+
+ r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
+buf_handle);
if (r) {
- free(bo);
- return r;
+ amdgpu_close_kms_handle(dev, args.out.handle);
+ goto out;
}
- bo->handle = args.out.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
-
+ pthread_mutex_lock(>bo_table_mutex);
+ r = handle_table_insert(>bo_handles, (*buf_handle)->handle,
+ *buf_handle);
+ pthread_mutex_unlock(>bo_table_mutex);
if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
-
+ amdgpu_bo_free(*buf_handle);
+out:
return r;
}
@@ -256,7 +267,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
{
struct drm_gem_open open_arg = {};
struct amdgpu_bo *bo = NULL;
- int r;
+ uint32_t handle = 0, flink_name = 0;
+ uint64_t alloc_size = 0;
+ int r = 0;
int dma_fd;
uint64_t dma_buf_size = 0;
@@ -266,22 +279,18 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, );
- if (r) {
- pthread_mutex_unlock(>bo_table_mutex);
- return r;
- }
+ if (r)
+ goto unlock;
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
- pthread_mutex_unlock(>bo_table_mutex);
- amdgpu_close_kms_handle(dev, handle);
- return -errno;
+ r = -errno;
+ goto close_handle;
}
lseek(shared_handle, 0, SEEK_SET);
@@ -302,12 +311,12 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
case amdgpu_bo_handle_type_kms:
case amdgpu_bo_handle_type_kms_noimport:
/* Importing a KMS handle in not allowed. */
- pthread_mutex_unlock(>bo_table_mutex);
- return -EPERM;
+ r = -EPERM;
[PATCH libdrm 2/2] [RFC] amdgpu: do not free flink bo for flink_fd
the flink bo is used to export
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 2947715..0d0c73b 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -219,12 +219,6 @@ static int amdgpu_bo_export_flink(amdgpu_bo_handle bo)
bo->flink_name = flink.name;
- if (bo->dev->flink_fd != bo->dev->fd) {
- struct drm_gem_close args = {};
- args.handle = handle;
- drmIoctl(bo->dev->flink_fd, DRM_IOCTL_GEM_CLOSE, );
- }
-
pthread_mutex_lock(>dev->bo_table_mutex);
r = handle_table_insert(>dev->bo_flink_names, bo->flink_name, bo);
pthread_mutex_unlock(>dev->bo_table_mutex);
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm] amdgpu: add a function to create amdgpu bo internally (v2)
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 186 +
1 file changed, 89 insertions(+), 97 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..a608820 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -48,11 +48,32 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle
dev,
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
}
+static int amdgpu_bo_create(amdgpu_device_handle dev,
+ uint64_t size,
+ uint32_t handle,
+ amdgpu_bo_handle *buf_handle)
+{
+ struct amdgpu_bo *bo;
+ int r = 0;
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+
+ atomic_set(>refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = handle;
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+
+ *buf_handle = bo;
+ return 0;
+}
+
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
- struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
@@ -61,14 +82,6 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = alloc_buffer->alloc_size;
-
memset(, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
@@ -80,24 +93,23 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
, sizeof(args));
+ if (r)
+ goto out;
+
+ r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
+buf_handle);
if (r) {
- free(bo);
- return r;
+ amdgpu_close_kms_handle(dev, args.out.handle);
+ goto out;
}
- bo->handle = args.out.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
-
+ pthread_mutex_lock(>bo_table_mutex);
+ r = handle_table_insert(>bo_handles, (*buf_handle)->handle,
+ *buf_handle);
+ pthread_mutex_unlock(>bo_table_mutex);
if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
-
+ amdgpu_bo_free(*buf_handle);
+out:
return r;
}
@@ -256,7 +268,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
{
struct drm_gem_open open_arg = {};
struct amdgpu_bo *bo = NULL;
- int r;
+ uint32_t handle = 0, flink_name = 0;
+ uint64_t alloc_size = 0;
+ int r = 0;
int dma_fd;
uint64_t dma_buf_size = 0;
@@ -266,22 +280,18 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, );
- if (r) {
- pthread_mutex_unlock(>bo_table_mutex);
- return r;
- }
+ if (r)
+ goto unlock;
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
- pthread_mutex_unlock(>bo_table_mutex);
- amdgpu_close_kms_handle(dev, handle);
- return -errno;
+ r = -errno;
+ goto unlock;
}
lseek(shared_handle, 0, SEEK_SET);
@@ -320,58 +330,32 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
return 0;
}
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo) {
- pthread_mutex_unlock(>bo_table_mutex);
- if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- amdgpu_close_kms_handle(dev, shared_handle);
- }
-
[PATCH libdrm] amdgpu: add a function to create amdgpu bo internally
a helper function to create and initialize amdgpu bo
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 184 -
1 file changed, 84 insertions(+), 100 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..2cca40d 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -48,11 +48,32 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle
dev,
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
}
+static int amdgpu_bo_create(amdgpu_device_handle dev,
+ uint64_t size,
+ uint32_t handle,
+ amdgpu_bo_handle *buf_handle)
+{
+ struct amdgpu_bo *bo;
+ int r = 0;
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+
+ atomic_set(>refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = handle;
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+
+ *buf_handle = bo;
+ return 0;
+}
+
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
- struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
@@ -61,14 +82,6 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = alloc_buffer->alloc_size;
-
memset(, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
@@ -80,24 +93,21 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
, sizeof(args));
- if (r) {
- free(bo);
- return r;
- }
-
- bo->handle = args.out.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
+ if (r)
+ goto out;
+ r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
+buf_handle);
if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
+ goto out;
+ pthread_mutex_lock(>bo_table_mutex);
+ r = handle_table_insert(>bo_handles, (*buf_handle)->handle,
+ *buf_handle);
+ pthread_mutex_unlock(>bo_table_mutex);
+ if (r)
+ amdgpu_bo_free(*buf_handle);
+out:
return r;
}
@@ -256,7 +266,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
{
struct drm_gem_open open_arg = {};
struct amdgpu_bo *bo = NULL;
- int r;
+ uint32_t handle = 0, flink_name = 0;
+ uint64_t alloc_size = 0;
+ int r = 0;
int dma_fd;
uint64_t dma_buf_size = 0;
@@ -266,22 +278,18 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, );
- if (r) {
- pthread_mutex_unlock(>bo_table_mutex);
- return r;
- }
+ if (r)
+ goto unlock;
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
- pthread_mutex_unlock(>bo_table_mutex);
- amdgpu_close_kms_handle(dev, handle);
- return -errno;
+ r = -errno;
+ goto unlock;
}
lseek(shared_handle, 0, SEEK_SET);
@@ -320,58 +328,32 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
return 0;
}
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo) {
- pthread_mutex_unlock(>bo_table_mutex);
- if (type == amdgpu_bo_handle_type_dma_buf_fd) {
- amdgpu_close_kms_handle(dev, shared_handle);
- }
- return -ENOMEM;
- }
-
/* Open the handle. */
switch (type) {
case am
[PATCH libdrm 1/3] amdgpu: add bo from user memory to handle table
When create bo from user memory, add it to handle table for future query. Signed-off-by: Junwei Zhang Reviewed-by: Christian König --- amdgpu/amdgpu_bo.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 422c7c9..b24e698 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -556,7 +556,16 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, bo->alloc_size = size; bo->handle = args.handle; - *buf_handle = bo; + pthread_mutex_lock(>dev->bo_table_mutex); + r = handle_table_insert(>dev->bo_handles, bo->handle, bo); + pthread_mutex_unlock(>dev->bo_table_mutex); + + pthread_mutex_init(>cpu_access_mutex, NULL); + + if (r) + amdgpu_bo_free(bo); + else + *buf_handle = bo; return r; } -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm 3/3] tests/amdgpu: add test for finding bo by CPU mapping
Add a test for API to query bo by CPU mapping
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
tests/amdgpu/bo_tests.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 9d4da4a..dc2de9b 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -27,6 +27,7 @@
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
#define BUFFER_SIZE (4*1024)
#define BUFFER_ALIGN (4*1024)
@@ -44,6 +45,7 @@ static void amdgpu_bo_metadata(void);
static void amdgpu_bo_map_unmap(void);
static void amdgpu_memory_alloc(void);
static void amdgpu_mem_fail_alloc(void);
+static void amdgpu_bo_find_by_cpu_mapping(void);
CU_TestInfo bo_tests[] = {
{ "Export/Import", amdgpu_bo_export_import },
@@ -51,6 +53,7 @@ CU_TestInfo bo_tests[] = {
{ "CPU map/unmap", amdgpu_bo_map_unmap },
{ "Memory alloc Test", amdgpu_memory_alloc },
{ "Memory fail alloc Test", amdgpu_mem_fail_alloc },
+ { "Find bo by CPU mapping", amdgpu_bo_find_by_cpu_mapping },
CU_TEST_INFO_NULL,
};
@@ -262,3 +265,33 @@ static void amdgpu_mem_fail_alloc(void)
CU_ASSERT_EQUAL(r, 0);
}
}
+
+static void amdgpu_bo_find_by_cpu_mapping(void)
+{
+ amdgpu_bo_handle bo_handle, find_bo_handle;
+ amdgpu_va_handle va_handle;
+ void *bo_cpu;
+ uint64_t bo_mc_address;
+ uint64_t offset;
+ int r;
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ _handle, _cpu,
+ _mc_address, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_find_bo_by_cpu_mapping(device_handle,
+ bo_cpu,
+ 4096,
+ _bo_handle,
+ );
+ CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(offset, 0);
+ CU_ASSERT_EQUAL(bo_handle->handle, find_bo_handle->handle);
+
+ atomic_dec(_bo_handle->refcount, 1);
+ r = amdgpu_bo_unmap_and_free(bo_handle, va_handle,
+bo_mc_address, 4096);
+ CU_ASSERT_EQUAL(r, 0);
+}
--
1.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm 2/3] amdgpu: add a function to find bo by cpu mapping (v2)
Userspace needs to know if the user memory is from BO or malloc.
v2: update mutex range and rebase
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
amdgpu/amdgpu.h| 23 +++
amdgpu/amdgpu_bo.c | 39 +++
2 files changed, 62 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index be83b45..a8c353c 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -678,6 +678,29 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle
dev,
amdgpu_bo_handle *buf_handle);
/**
+ * Validate if the user memory comes from BO
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param cpu - [in] CPU address of user allocated memory which we
+ * want to map to GPU address space (make GPU accessible)
+ * (This address must be correctly aligned).
+ * \param size - [in] Size of allocation (must be correctly aligned)
+ * \param buf_handle - [out] Buffer handle for the userptr memory
+ * if the user memory is not from BO, the buf_handle will be NULL.
+ * \param offset_in_bo - [out] offset in this BO for this user memory
+ *
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo);
+
+/**
* Free previosuly allocated memory
*
* \param dev - \c [in] Device handle. See
#amdgpu_device_initialize()
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b24e698..b790e9b 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -529,6 +529,45 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
}
}
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo)
+{
+ int i;
+ struct amdgpu_bo *bo;
+
+ if (cpu == NULL || size == 0)
+ return -EINVAL;
+
+ /*
+* Workaround for a buggy application which tries to import previously
+* exposed CPU pointers. If we find a real world use case we should
+* improve that by asking the kernel for the right handle.
+*/
+ pthread_mutex_lock(>bo_table_mutex);
+ for (i = 0; i < dev->bo_handles.max_key; i++) {
+ bo = handle_table_lookup(>bo_handles, i);
+ if (!bo || !bo->cpu_ptr || size > bo->alloc_size)
+ continue;
+ if (cpu >= bo->cpu_ptr && cpu < (bo->cpu_ptr + bo->alloc_size))
+ break;
+ }
+
+ if (i < dev->bo_handles.max_key) {
+ atomic_inc(>refcount);
+ *buf_handle = bo;
+ *offset_in_bo = cpu - bo->cpu_ptr;
+ } else {
+ *buf_handle = NULL;
+ *offset_in_bo = 0;
+ }
+ pthread_mutex_unlock(>bo_table_mutex);
+
+ return 0;
+}
+
int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm 3/4] tests/amdgpu: add test for finding bo by CPU mapping
Add a test for API to query bo by CPU mapping
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
tests/amdgpu/bo_tests.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 9d4da4a..dc2de9b 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -27,6 +27,7 @@
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
#define BUFFER_SIZE (4*1024)
#define BUFFER_ALIGN (4*1024)
@@ -44,6 +45,7 @@ static void amdgpu_bo_metadata(void);
static void amdgpu_bo_map_unmap(void);
static void amdgpu_memory_alloc(void);
static void amdgpu_mem_fail_alloc(void);
+static void amdgpu_bo_find_by_cpu_mapping(void);
CU_TestInfo bo_tests[] = {
{ "Export/Import", amdgpu_bo_export_import },
@@ -51,6 +53,7 @@ CU_TestInfo bo_tests[] = {
{ "CPU map/unmap", amdgpu_bo_map_unmap },
{ "Memory alloc Test", amdgpu_memory_alloc },
{ "Memory fail alloc Test", amdgpu_mem_fail_alloc },
+ { "Find bo by CPU mapping", amdgpu_bo_find_by_cpu_mapping },
CU_TEST_INFO_NULL,
};
@@ -262,3 +265,33 @@ static void amdgpu_mem_fail_alloc(void)
CU_ASSERT_EQUAL(r, 0);
}
}
+
+static void amdgpu_bo_find_by_cpu_mapping(void)
+{
+ amdgpu_bo_handle bo_handle, find_bo_handle;
+ amdgpu_va_handle va_handle;
+ void *bo_cpu;
+ uint64_t bo_mc_address;
+ uint64_t offset;
+ int r;
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ _handle, _cpu,
+ _mc_address, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_find_bo_by_cpu_mapping(device_handle,
+ bo_cpu,
+ 4096,
+ _bo_handle,
+ );
+ CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(offset, 0);
+ CU_ASSERT_EQUAL(bo_handle->handle, find_bo_handle->handle);
+
+ atomic_dec(_bo_handle->refcount, 1);
+ r = amdgpu_bo_unmap_and_free(bo_handle, va_handle,
+bo_mc_address, 4096);
+ CU_ASSERT_EQUAL(r, 0);
+}
--
1.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm 4/4] amdgpu: add a function to create amdgpu bo internally
a helper function to create and initialize amdgpu bo
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 81 ++
1 file changed, 33 insertions(+), 48 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index a7f0662..59cba69 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -48,11 +48,39 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle
dev,
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
}
+static int amdgpu_bo_create(amdgpu_device_handle dev,
+ uint64_t size,
+ uint32_t handle,
+ amdgpu_bo_handle *buf_handle)
+{
+ struct amdgpu_bo *bo;
+ int r = 0;
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
+
+ atomic_set(>refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = handle;
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+
+ pthread_mutex_lock(>dev->bo_table_mutex);
+ r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
+ pthread_mutex_unlock(>dev->bo_table_mutex);
+ if (r)
+ amdgpu_bo_free(bo);
+ else
+ *buf_handle = bo;
+
+ return r;
+}
+
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
- struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
@@ -61,14 +89,6 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = alloc_buffer->alloc_size;
-
memset(, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
@@ -80,25 +100,11 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
, sizeof(args));
- if (r) {
- free(bo);
- return r;
- }
-
- bo->handle = args.out.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
-
if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
+ return r;
- return r;
+ return amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
+ buf_handle);
}
int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
@@ -569,7 +575,6 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
amdgpu_bo_handle *buf_handle)
{
int r;
- struct amdgpu_bo *bo;
struct drm_amdgpu_gem_userptr args;
args.addr = (uintptr_t)cpu;
@@ -581,27 +586,7 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle
dev,
if (r)
return r;
- bo = calloc(1, sizeof(struct amdgpu_bo));
- if (!bo)
- return -ENOMEM;
-
- atomic_set(>refcount, 1);
- bo->dev = dev;
- bo->alloc_size = size;
- bo->handle = args.handle;
-
- pthread_mutex_lock(>dev->bo_table_mutex);
- r = handle_table_insert(>dev->bo_handles, bo->handle, bo);
- pthread_mutex_unlock(>dev->bo_table_mutex);
-
- pthread_mutex_init(>cpu_access_mutex, NULL);
-
- if (r)
- amdgpu_bo_free(bo);
- else
- *buf_handle = bo;
-
- return r;
+ return amdgpu_bo_create(dev, size, args.handle, buf_handle);
}
int amdgpu_bo_list_create(amdgpu_device_handle dev,
--
1.9.1
___
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[PATCH libdrm 2/4] amdgpu: add a function to find bo by cpu mapping (v2)
Userspace needs to know if the user memory is from BO or malloc.
v2: update mutex range and rebase
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu.h| 23 +++
amdgpu/amdgpu_bo.c | 34 ++
2 files changed, 57 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index be83b45..a8c353c 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -678,6 +678,29 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle
dev,
amdgpu_bo_handle *buf_handle);
/**
+ * Validate if the user memory comes from BO
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param cpu - [in] CPU address of user allocated memory which we
+ * want to map to GPU address space (make GPU accessible)
+ * (This address must be correctly aligned).
+ * \param size - [in] Size of allocation (must be correctly aligned)
+ * \param buf_handle - [out] Buffer handle for the userptr memory
+ * if the user memory is not from BO, the buf_handle will be NULL.
+ * \param offset_in_bo - [out] offset in this BO for this user memory
+ *
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo);
+
+/**
* Free previosuly allocated memory
*
* \param dev - \c [in] Device handle. See
#amdgpu_device_initialize()
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b24e698..a7f0662 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -529,6 +529,40 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
}
}
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo)
+{
+ int i;
+ struct amdgpu_bo *bo;
+
+ if (cpu == NULL || size == 0)
+ return -EINVAL;
+
+ pthread_mutex_lock(>bo_table_mutex);
+ for (i = 0; i < dev->bo_handles.max_key; i++) {
+ bo = handle_table_lookup(>bo_handles, i);
+ if (!bo || !bo->cpu_ptr || size > bo->alloc_size)
+ continue;
+ if (cpu >= bo->cpu_ptr && cpu < (bo->cpu_ptr + bo->alloc_size))
+ break;
+ }
+
+ if (i < dev->bo_handles.max_key) {
+ atomic_inc(>refcount);
+ *buf_handle = bo;
+ *offset_in_bo = cpu - bo->cpu_ptr;
+ } else {
+ *buf_handle = NULL;
+ *offset_in_bo = 0;
+ }
+ pthread_mutex_unlock(>bo_table_mutex);
+
+ return 0;
+}
+
int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
--
1.9.1
___
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[PATCH libdrm 1/4] amdgpu: add bo from user memory to handle table
When create bo from user memory, add it to handle table for future query. Signed-off-by: Junwei Zhang Reviewed-by: Christian König --- amdgpu/amdgpu_bo.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 422c7c9..b24e698 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -556,7 +556,16 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, bo->alloc_size = size; bo->handle = args.handle; - *buf_handle = bo; + pthread_mutex_lock(>dev->bo_table_mutex); + r = handle_table_insert(>dev->bo_handles, bo->handle, bo); + pthread_mutex_unlock(>dev->bo_table_mutex); + + pthread_mutex_init(>cpu_access_mutex, NULL); + + if (r) + amdgpu_bo_free(bo); + else + *buf_handle = bo; return r; } -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm 2/4] amdgpu: add count for handle table
count indicats the total number of key in handle table
max_key becomes the max value of key
Signed-off-by: Junwei Zhang
---
amdgpu/handle_table.c | 18 +++---
amdgpu/handle_table.h | 1 +
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/amdgpu/handle_table.c b/amdgpu/handle_table.c
index 15cd476..34e8027 100644
--- a/amdgpu/handle_table.c
+++ b/amdgpu/handle_table.c
@@ -31,34 +31,37 @@
drm_private int handle_table_insert(struct handle_table *table, uint32_t key,
void *value)
{
- if (key >= table->max_key) {
+ if (key >= table->count) {
uint32_t alignment = sysconf(_SC_PAGESIZE) / sizeof(void*);
- uint32_t max_key = ALIGN(key, alignment);
+ uint32_t count = ALIGN(key, alignment);
void **values;
- values = realloc(table->values, max_key * sizeof(void *));
+ values = realloc(table->values, count * sizeof(void *));
if (!values)
return -ENOMEM;
- memset(values + table->max_key, 0, (max_key - table->max_key) *
+ memset(values + table->count, 0, (count - table->count) *
sizeof(void *));
- table->max_key = max_key;
+ table->count = count;
table->values = values;
}
+ if (key > table->max_key)
+ table->max_key = key;
+
table->values[key] = value;
return 0;
}
drm_private void handle_table_remove(struct handle_table *table, uint32_t key)
{
- if (key < table->max_key)
+ if (key <= table->max_key)
table->values[key] = NULL;
}
drm_private void *handle_table_lookup(struct handle_table *table, uint32_t key)
{
- if (key < table->max_key)
+ if (key <= table->max_key)
return table->values[key];
else
return NULL;
@@ -68,5 +71,6 @@ drm_private void handle_table_fini(struct handle_table *table)
{
free(table->values);
table->max_key = 0;
+ table->count = 0;
table->values = NULL;
}
diff --git a/amdgpu/handle_table.h b/amdgpu/handle_table.h
index 461193f..007bb58 100644
--- a/amdgpu/handle_table.h
+++ b/amdgpu/handle_table.h
@@ -29,6 +29,7 @@
struct handle_table {
uint32_tmax_key;
+ uint32_tcount;
void**values;
};
--
1.9.1
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[PATCH libdrm 3/4] amdgpu: add a function to find bo by cpu mapping
Userspace needs to know if the user memory is from BO or malloc.
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu.h| 23 +++
amdgpu/amdgpu_bo.c | 34 ++
2 files changed, 57 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index be83b45..a8c353c 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -678,6 +678,29 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle
dev,
amdgpu_bo_handle *buf_handle);
/**
+ * Validate if the user memory comes from BO
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param cpu - [in] CPU address of user allocated memory which we
+ * want to map to GPU address space (make GPU accessible)
+ * (This address must be correctly aligned).
+ * \param size - [in] Size of allocation (must be correctly aligned)
+ * \param buf_handle - [out] Buffer handle for the userptr memory
+ * if the user memory is not from BO, the buf_handle will be NULL.
+ * \param offset_in_bo - [out] offset in this BO for this user memory
+ *
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo);
+
+/**
* Free previosuly allocated memory
*
* \param dev - \c [in] Device handle. See
#amdgpu_device_initialize()
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b24e698..a631050 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -529,6 +529,40 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
}
}
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo)
+{
+ int i;
+ struct amdgpu_bo *bo;
+
+ if (cpu == NULL || size == 0)
+ return -EINVAL;
+
+ pthread_mutex_lock(>bo_table_mutex);
+ for (i = 0; i <= dev->bo_handles.max_key; i++) {
+ bo = handle_table_lookup(>bo_handles, i);
+ if (!bo || !bo->cpu_ptr || size > bo->alloc_size)
+ continue;
+ if (cpu >= bo->cpu_ptr && cpu < (bo->cpu_ptr + bo->alloc_size))
+ break;
+ }
+ pthread_mutex_unlock(>bo_table_mutex);
+
+ if (i <= dev->bo_handles.max_key) {
+ atomic_inc(>refcount);
+ *buf_handle = bo;
+ *offset_in_bo = cpu - bo->cpu_ptr;
+ } else {
+ *buf_handle = NULL;
+ *offset_in_bo = 0;
+ }
+
+ return 0;
+}
+
int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
--
1.9.1
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[PATCH libdrm 4/4] tests/amdgpu: add test for finding bo by CPU mapping
Add a test for API to query bo by CPU mapping
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
tests/amdgpu/bo_tests.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 9d4da4a..dc2de9b 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -27,6 +27,7 @@
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
#define BUFFER_SIZE (4*1024)
#define BUFFER_ALIGN (4*1024)
@@ -44,6 +45,7 @@ static void amdgpu_bo_metadata(void);
static void amdgpu_bo_map_unmap(void);
static void amdgpu_memory_alloc(void);
static void amdgpu_mem_fail_alloc(void);
+static void amdgpu_bo_find_by_cpu_mapping(void);
CU_TestInfo bo_tests[] = {
{ "Export/Import", amdgpu_bo_export_import },
@@ -51,6 +53,7 @@ CU_TestInfo bo_tests[] = {
{ "CPU map/unmap", amdgpu_bo_map_unmap },
{ "Memory alloc Test", amdgpu_memory_alloc },
{ "Memory fail alloc Test", amdgpu_mem_fail_alloc },
+ { "Find bo by CPU mapping", amdgpu_bo_find_by_cpu_mapping },
CU_TEST_INFO_NULL,
};
@@ -262,3 +265,33 @@ static void amdgpu_mem_fail_alloc(void)
CU_ASSERT_EQUAL(r, 0);
}
}
+
+static void amdgpu_bo_find_by_cpu_mapping(void)
+{
+ amdgpu_bo_handle bo_handle, find_bo_handle;
+ amdgpu_va_handle va_handle;
+ void *bo_cpu;
+ uint64_t bo_mc_address;
+ uint64_t offset;
+ int r;
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ _handle, _cpu,
+ _mc_address, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_find_bo_by_cpu_mapping(device_handle,
+ bo_cpu,
+ 4096,
+ _bo_handle,
+ );
+ CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(offset, 0);
+ CU_ASSERT_EQUAL(bo_handle->handle, find_bo_handle->handle);
+
+ atomic_dec(_bo_handle->refcount, 1);
+ r = amdgpu_bo_unmap_and_free(bo_handle, va_handle,
+bo_mc_address, 4096);
+ CU_ASSERT_EQUAL(r, 0);
+}
--
1.9.1
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[PATCH libdrm 1/4] amdgpu: add bo from user memory to handle table
When create bo from user memory, add it to handle table for future query. Signed-off-by: Junwei Zhang --- amdgpu/amdgpu_bo.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 422c7c9..b24e698 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -556,7 +556,16 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, bo->alloc_size = size; bo->handle = args.handle; - *buf_handle = bo; + pthread_mutex_lock(>dev->bo_table_mutex); + r = handle_table_insert(>dev->bo_handles, bo->handle, bo); + pthread_mutex_unlock(>dev->bo_table_mutex); + + pthread_mutex_init(>cpu_access_mutex, NULL); + + if (r) + amdgpu_bo_free(bo); + else + *buf_handle = bo; return r; } -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm] amdgpu: add valid function for handle table
When insert or lookup a handle in table,
it needs to check if the handle is vaild or not.
Sometimes it may find a non-existing bo in table
Signed-off-by: Junwei Zhang
---
amdgpu/handle_table.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/amdgpu/handle_table.c b/amdgpu/handle_table.c
index 9acc44d..d089472 100644
--- a/amdgpu/handle_table.c
+++ b/amdgpu/handle_table.c
@@ -26,6 +26,12 @@
#include
#include "handle_table.h"
#include "util_math.h"
+#include
+
+drm_private static bool handle_table_valid(struct handle_table *table,
uint32_t key)
+{
+ return key < table->max_key;
+}
drm_private int handle_table_insert(struct handle_table *table, uint32_t key,
void *value)
@@ -50,10 +56,14 @@ drm_private int handle_table_insert(struct handle_table
*table, uint32_t key,
drm_private void handle_table_remove(struct handle_table *table, uint32_t key)
{
- table->values[key] = NULL;
+ if (handle_table_valid(table, key))
+ table->values[key] = NULL;
}
drm_private void *handle_table_lockup(struct handle_table *table, uint32_t key)
{
- return table->values[key];
+ if (handle_table_valid(table, key))
+ return table->values[key];
+ else
+ return NULL;
}
--
1.9.1
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[PATCH libdrm] tests/amdgpu: add test for finding bo by CPU mapping
Signed-off-by: Junwei Zhang
---
tests/amdgpu/bo_tests.c | 32
1 file changed, 32 insertions(+)
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 9d4da4a..4d05027 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -27,6 +27,7 @@
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
#define BUFFER_SIZE (4*1024)
#define BUFFER_ALIGN (4*1024)
@@ -44,6 +45,7 @@ static void amdgpu_bo_metadata(void);
static void amdgpu_bo_map_unmap(void);
static void amdgpu_memory_alloc(void);
static void amdgpu_mem_fail_alloc(void);
+static void amdgpu_bo_find_by_cpu_mapping(void);
CU_TestInfo bo_tests[] = {
{ "Export/Import", amdgpu_bo_export_import },
@@ -51,6 +53,7 @@ CU_TestInfo bo_tests[] = {
{ "CPU map/unmap", amdgpu_bo_map_unmap },
{ "Memory alloc Test", amdgpu_memory_alloc },
{ "Memory fail alloc Test", amdgpu_mem_fail_alloc },
+ { "Find bo by CPU mapping", amdgpu_bo_find_by_cpu_mapping },
CU_TEST_INFO_NULL,
};
@@ -262,3 +265,32 @@ static void amdgpu_mem_fail_alloc(void)
CU_ASSERT_EQUAL(r, 0);
}
}
+
+static void amdgpu_bo_find_by_cpu_mapping(void)
+{
+ amdgpu_bo_handle bo_handle, find_bo_handle;
+ amdgpu_va_handle va_handle;
+ void *bo_cpu;
+ uint64_t bo_mc_address;
+ uint64_t offset;
+ int r;
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ _handle, _cpu,
+ _mc_address, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_find_bo_by_cpu_mapping(device_handle,
+ bo_cpu,
+ 4096,
+ _bo_handle,
+ );
+ CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(offset, 0);
+ CU_ASSERT_EQUAL(bo_handle->handle, find_bo_handle->handle);
+
+ r = amdgpu_bo_unmap_and_free(bo_handle, va_handle,
+bo_mc_address, 4096);
+ CU_ASSERT_EQUAL(r, 0);
+}
--
1.9.1
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[PATCH libdrm] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface (v2)
From: Chunming Zhou
(amdgpu_drm.h will be synced from kernel header as general approach, here
provided for review only)
userspace needs to know if the user memory is from BO or malloc.
v2: modify IOCTL data as union(in, out)
update bo table management(get, set)
simplify code logic
Signed-off-by: Chunming Zhou
Signed-off-by: Junwei Zhang (v2)
Reviewed-by: Jammy Zhou
Reviewed-by: Christian König
---
amdgpu/amdgpu.h | 24
amdgpu/amdgpu_bo.c | 49
include/drm/amdgpu_drm.h | 21 +
3 files changed, 94 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index be83b45..e7a6642 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -678,6 +678,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle
dev,
amdgpu_bo_handle *buf_handle);
/**
+ * Validate if the user memory comes from BO
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param cpu - [in] CPU address of user allocated memory which we
+ * want to map to GPU address space (make GPU accessible)
+ * (This address must be correctly aligned).
+ * \param size - [in] Size of allocation (must be correctly aligned)
+ * \param buf_handle - [out] Buffer handle for the userptr memory
+ * if the user memory is not from BO, the buf_handle will be NULL.
+ * \param offset_in_bo - [out] offset in this BO for this user memory
+ *
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo);
+
+
+/**
* Free previosuly allocated memory
*
* \param dev - \c [in] Device handle. See
#amdgpu_device_initialize()
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d29be24..6c4b8f5 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -534,6 +534,55 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
}
}
+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo)
+{
+ int r;
+ struct amdgpu_bo *bo;
+ union drm_amdgpu_gem_find_bo args;
+
+ args.in.addr = (uintptr_t)cpu;
+ args.in.size = size;
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_FIND_BO,
+ , sizeof(args));
+ if (r)
+ return r;
+ if (args.out.handle == 0)
+ return -EINVAL;
+
+ pthread_mutex_lock(>bo_table_mutex);
+ bo = util_hash_table_get(dev->bo_handles,
+(void*)(uintptr_t)args.out.handle);
+ if (bo) {
+ pthread_mutex_unlock(>bo_table_mutex);
+ atomic_inc(>refcount);
+ goto out;
+ }
+
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo) {
+ pthread_mutex_unlock(>bo_table_mutex);
+ return -ENOMEM;
+ }
+
+ atomic_set(>refcount, 1);
+ pthread_mutex_init(>cpu_access_mutex, NULL);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = args.out.handle;
+ util_hash_table_set(dev->bo_handles, (void*)(uintptr_t)bo->handle, bo);
+ pthread_mutex_unlock(>bo_table_mutex);
+
+out:
+ *buf_handle = bo;
+ *offset_in_bo = args.out.offset;
+ return r;
+}
+
+
int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index c363b67..6305cb6 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -54,6 +54,7 @@ extern "C" {
#define DRM_AMDGPU_VM 0x13
#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
#define DRM_AMDGPU_SCHED 0x15
+#define DRM_AMDGPU_GEM_FIND_BO 0x16
#define DRM_IOCTL_AMDGPU_GEM_CREATEDRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -71,6 +72,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_VMDRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_VM, union drm_amdgpu_vm)
#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE +
DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
[PATCH 1/2] drm/amdgpu: return bo itself if userptr is cpu addr of bo (v3)
From: Chunming Zhou
v2: get original gem handle from gobj
v3: update find bo data structure as union(in, out)
simply some code logic
Signed-off-by: Chunming Zhou
Signed-off-by: Junwei Zhang (v3)
Reviewed-by: Christian König
Reviewed-by: Jammy Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 63 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +-
include/uapi/drm/amdgpu_drm.h | 21 +++
4 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4cd20e7..46c370b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1213,6 +1213,8 @@ int amdgpu_gem_info_ioctl(struct drm_device *dev, void
*data,
struct drm_file *filp);
int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
+int amdgpu_gem_find_bo_by_cpu_mapping_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 71792d8..bae8417 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -288,6 +288,69 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
return 0;
}
+static int amdgpu_gem_get_handle_from_object(struct drm_file *filp,
+struct drm_gem_object *obj)
+{
+ int i;
+ struct drm_gem_object *tmp;
+
+ spin_lock(>table_lock);
+ idr_for_each_entry(>object_idr, tmp, i) {
+ if (obj == tmp) {
+ drm_gem_object_reference(obj);
+ spin_unlock(>table_lock);
+ return i;
+ }
+ }
+ spin_unlock(>table_lock);
+
+ return 0;
+}
+
+int amdgpu_gem_find_bo_by_cpu_mapping_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ union drm_amdgpu_gem_find_bo *args = data;
+ struct drm_gem_object *gobj;
+ struct amdgpu_bo *bo;
+ struct ttm_buffer_object *tbo;
+ struct vm_area_struct *vma;
+ uint32_t handle;
+ int r;
+
+ if (offset_in_page(args->in.addr | args->in.size))
+ return -EINVAL;
+
+ down_read(>mm->mmap_sem);
+ vma = find_vma(current->mm, args->in.addr);
+ if (!vma || vma->vm_file != filp->filp ||
+ (args->in.size > (vma->vm_end - args->in.addr))) {
+ args->out.handle = 0;
+ up_read(>mm->mmap_sem);
+ return -EINVAL;
+ }
+ args->out.offset = args->in.addr - vma->vm_start;
+
+ tbo = vma->vm_private_data;
+ bo = container_of(tbo, struct amdgpu_bo, tbo);
+ amdgpu_bo_ref(bo);
+ gobj = >gem_base;
+
+ handle = amdgpu_gem_get_handle_from_object(filp, gobj);
+ if (!handle) {
+ r = drm_gem_handle_create(filp, gobj, );
+ if (r) {
+ DRM_ERROR("create gem handle failed\n");
+ up_read(>mm->mmap_sem);
+ return r;
+ }
+ }
+ args->out.handle = handle;
+ up_read(>mm->mmap_sem);
+
+ return 0;
+}
+
int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 7956848..1bd2cc1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1100,7 +1100,8 @@ void amdgpu_disable_vblank_kms(struct drm_device *dev,
unsigned int pipe)
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
- DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_display_freesync_ioctl,
DRM_MASTER)
+ DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_display_freesync_ioctl,
DRM_MASTER),
+ DRM_IOCTL_DEF_DRV(AMDGPU_GEM_FIND_BO,
amdgpu_gem_find_bo_by_cpu_mapping_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
};
const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 9ee..000c415 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@
[PATCH 2/2] drm/amdgpu: bump version for API to find bo by cpu mapping
bump version for new API involved. Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 8843a06..6b52551 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -70,9 +70,10 @@ * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. + * - 3.28.0 - Add API to find bo by cpu mapping for UMD bo validation. */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 27 +#define KMS_DRIVER_MINOR 28 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: correct evict flag for bo move
pass the evict flag instead of hard code
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 8c4358e..c1ae528 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -580,7 +580,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object
*bo, bool evict,
}
/* blit VRAM to GTT */
- r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, _mem, old_mem);
+ r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, _mem, old_mem);
if (unlikely(r)) {
goto out_cleanup;
}
@@ -632,7 +632,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object
*bo, bool evict,
}
/* copy to VRAM */
- r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem);
+ r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
if (unlikely(r)) {
goto out_cleanup;
}
--
1.9.1
___
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[PATCH] drm/scheduler: add NULL pointer check for run queue (v2)
To check rq pointer before adding entity into it.
That avoids NULL pointer access in some case.
v2: move the check to caller
Suggested-by: Christian König
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/scheduler/gpu_scheduler.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c
b/drivers/gpu/drm/scheduler/gpu_scheduler.c
index 16bf446..dac71e3 100644
--- a/drivers/gpu/drm/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c
@@ -547,6 +547,11 @@ void drm_sched_entity_push_job(struct drm_sched_job
*sched_job,
if (first) {
/* Add the entity to the run queue */
spin_lock(>rq_lock);
+ if (!entity->rq) {
+ DRM_ERROR("Trying to push to a killed entity\n");
+ spin_unlock(>rq_lock);
+ return;
+ }
drm_sched_rq_add_entity(entity->rq, entity);
spin_unlock(>rq_lock);
drm_sched_wakeup(sched);
--
1.9.1
___
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[PATCH] drm/scheduler: add NULL pointer check for run queue
To check rq pointer before adding entity into it.
That avoids NULL pointer access in some case.
Suggested-by: Christian König
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/scheduler/gpu_scheduler.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c
b/drivers/gpu/drm/scheduler/gpu_scheduler.c
index 16bf446..5e5268d 100644
--- a/drivers/gpu/drm/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c
@@ -91,6 +91,10 @@ static void drm_sched_rq_add_entity(struct drm_sched_rq *rq,
{
if (!list_empty(>list))
return;
+ if (!rq) {
+ DRM_ERROR("rq is NULL!\n");
+ return;
+ }
spin_lock(>lock);
list_add_tail(>list, >entities);
spin_unlock(>lock);
--
1.9.1
___
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[PATCH] drm/amdgpu: Reserve fence slots for command submission
From: Michel Dänzer Without this, there could not be enough slots, which could trigger the BUG_ON in reservation_object_add_shared_fence. v2: * Jump to the error label instead of returning directly (Jerry Zhang) v3: * Reserve slots for command submission after VM updates (Christian König) Cc: sta...@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/106418 Reported-by: mikhail.v.gavri...@gmail.com Signed-off-by: Michel Dänzer Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 7a625f3..1bc0281 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -928,6 +928,10 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, r = amdgpu_bo_vm_update_pte(p); if (r) return r; + + r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); + if (r) + return r; } return amdgpu_cs_sync_rings(p); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: allocate gart memory when it's required (v3)
Instead of calling gart memory on every bo pin,
allocates it on demand
v2: fix error handling
v3: drop the change for kfd gtt bo mapping, not needed.
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 14 --
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 8
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 15 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 5 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++--
7 files changed, 57 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 98e3bf8..e3ed08d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -280,6 +280,12 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
goto allocate_mem_pin_bo_failed;
}
+ r = amdgpu_ttm_alloc_gart(>tbo);
+ if (r) {
+ dev_err(adev->dev, "%p bind failed\n", bo);
+ goto allocate_mem_kmap_bo_failed;
+ }
+
r = amdgpu_bo_kmap(bo, _ptr_tmp);
if (r) {
dev_err(adev->dev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index cb88d7e..3079ea8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -96,11 +96,16 @@ static void amdgpu_benchmark_move(struct amdgpu_device
*adev, unsigned size,
if (unlikely(r != 0))
goto out_cleanup;
r = amdgpu_bo_pin(sobj, sdomain);
- saddr = amdgpu_bo_gpu_offset(sobj);
+ if (r) {
+ amdgpu_bo_unreserve(sobj);
+ goto out_cleanup;
+ }
+ r = amdgpu_ttm_alloc_gart(>tbo);
amdgpu_bo_unreserve(sobj);
if (r) {
goto out_cleanup;
}
+ saddr = amdgpu_bo_gpu_offset(sobj);
bp.domain = ddomain;
r = amdgpu_bo_create(adev, , );
if (r) {
@@ -110,11 +115,16 @@ static void amdgpu_benchmark_move(struct amdgpu_device
*adev, unsigned size,
if (unlikely(r != 0))
goto out_cleanup;
r = amdgpu_bo_pin(dobj, ddomain);
- daddr = amdgpu_bo_gpu_offset(dobj);
+ if (r) {
+ amdgpu_bo_unreserve(sobj);
+ goto out_cleanup;
+ }
+ r = amdgpu_ttm_alloc_gart(>tbo);
amdgpu_bo_unreserve(dobj);
if (r) {
goto out_cleanup;
}
+ daddr = amdgpu_bo_gpu_offset(dobj);
if (adev->mman.buffer_funcs) {
time = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 036b6f7..7d6a36b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -194,6 +194,12 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc
*crtc,
goto unreserve;
}
+ r = amdgpu_ttm_alloc_gart(_abo->tbo);
+ if (unlikely(r != 0)) {
+ DRM_ERROR("%p bind failed\n", new_abo);
+ goto unpin;
+ }
+
r = reservation_object_get_fences_rcu(new_abo->tbo.resv, >excl,
>shared_count,
>shared);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 462b7a1..cd68a2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -173,6 +173,14 @@ static int amdgpufb_create_pinned_object(struct
amdgpu_fbdev *rfbdev,
amdgpu_bo_unreserve(abo);
goto out_unref;
}
+
+ ret = amdgpu_ttm_alloc_gart(>tbo);
+ if (ret) {
+ amdgpu_bo_unreserve(abo);
+ dev_err(adev->dev, "%p bind failed\n", abo);
+ goto out_unref;
+ }
+
ret = amdgpu_bo_kmap(abo, NULL);
amdgpu_bo_unreserve(abo);
if (ret) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 79cdbf1..7f7c221 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -257,6 +257,13 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
goto error_unreserve;
}
+
+ r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
+ if (r) {
+ dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
+ goto error_unpin;
+ }
+
[PATCH 3/3] drm/amdgpu: fix kmap error handling for bo creations
kmap happens after bo pin, so unpin is required on error
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 7f7c221..9ee678d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -271,7 +271,7 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
if (r) {
dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
- goto error_unreserve;
+ goto error_unpin;
}
}
--
1.9.1
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[PATCH 1/3] drm/amdgpu: separate gpu address from bo pin
It could be got by amdgpu_bo_gpu_offset() if need
Signed-off-by: Junwei Zhang
Reviewed-by: Michel Dänzer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 17 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 10 +-
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 10 +-
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
17 files changed, 50 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 305143f..98e3bf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -251,7 +251,6 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
struct amdgpu_bo *bo = NULL;
struct amdgpu_bo_param bp;
int r;
- uint64_t gpu_addr_tmp = 0;
void *cpu_ptr_tmp = NULL;
memset(, 0, sizeof(bp));
@@ -275,8 +274,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
goto allocate_mem_reserve_bo_failed;
}
- r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT,
- _addr_tmp);
+ r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
if (r) {
dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
goto allocate_mem_pin_bo_failed;
@@ -290,7 +288,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
}
*mem_obj = bo;
- *gpu_addr = gpu_addr_tmp;
+ *gpu_addr = amdgpu_bo_gpu_offset(bo);
*cpu_ptr = cpu_ptr_tmp;
amdgpu_bo_unreserve(bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index ff8fd75..079af8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1587,7 +1587,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct
kgd_dev *kgd,
goto bo_reserve_failed;
}
- ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
+ ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
if (ret) {
pr_err("Failed to pin bo. ret %d\n", ret);
goto pin_failed;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 19cfff3..cb88d7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -95,7 +95,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev,
unsigned size,
r = amdgpu_bo_reserve(sobj, false);
if (unlikely(r != 0))
goto out_cleanup;
- r = amdgpu_bo_pin(sobj, sdomain, );
+ r = amdgpu_bo_pin(sobj, sdomain);
+ saddr = amdgpu_bo_gpu_offset(sobj);
amdgpu_bo_unreserve(sobj);
if (r) {
goto out_cleanup;
@@ -108,7 +109,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device
*adev, unsigned size,
r = amdgpu_bo_reserve(dobj, false);
if (unlikely(r != 0))
goto out_cleanup;
- r = amdgpu_bo_pin(dobj, ddomain, );
+ r = amdgpu_bo_pin(dobj, ddomain);
+ daddr = amdgpu_bo_gpu_offset(dobj);
amdgpu_bo_unreserve(dobj);
if (r) {
goto out_cleanup;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 995dc02..d2745de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2736,11 +2736,10 @@ int amdgpu_device_resume(struct drm_device *dev, bool
resume, bool fbcon)
struct amdgpu_bo *aobj =
gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
r = amdgpu_bo_reserve(aobj, true);
if (r == 0) {
- r = amdgpu_bo_pin(aobj,
- AMDGPU_GEM_DOMAIN_VRAM,
- _crtc->cursor_addr);
+ r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
[PATCH 2/3] drm/amdgpu: allocate gart memory when it's required (v2)
Instead of calling gart memory on every bo pin,
allocates it on demand
v2: fix error handling
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 14 --
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 8
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 15 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 5 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++--
8 files changed, 63 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 98e3bf8..e3ed08d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -280,6 +280,12 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
goto allocate_mem_pin_bo_failed;
}
+ r = amdgpu_ttm_alloc_gart(>tbo);
+ if (r) {
+ dev_err(adev->dev, "%p bind failed\n", bo);
+ goto allocate_mem_kmap_bo_failed;
+ }
+
r = amdgpu_bo_kmap(bo, _ptr_tmp);
if (r) {
dev_err(adev->dev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 079af8a..2c0bc7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1593,6 +1593,12 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct
kgd_dev *kgd,
goto pin_failed;
}
+ ret = amdgpu_ttm_alloc_gart(>tbo);
+ if (ret) {
+ pr_err("%p bind failed\n", bo);
+ goto kmap_failed;
+ }
+
ret = amdgpu_bo_kmap(bo, kptr);
if (ret) {
pr_err("Failed to map bo to kernel. ret %d\n", ret);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index cb88d7e..3079ea8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -96,11 +96,16 @@ static void amdgpu_benchmark_move(struct amdgpu_device
*adev, unsigned size,
if (unlikely(r != 0))
goto out_cleanup;
r = amdgpu_bo_pin(sobj, sdomain);
- saddr = amdgpu_bo_gpu_offset(sobj);
+ if (r) {
+ amdgpu_bo_unreserve(sobj);
+ goto out_cleanup;
+ }
+ r = amdgpu_ttm_alloc_gart(>tbo);
amdgpu_bo_unreserve(sobj);
if (r) {
goto out_cleanup;
}
+ saddr = amdgpu_bo_gpu_offset(sobj);
bp.domain = ddomain;
r = amdgpu_bo_create(adev, , );
if (r) {
@@ -110,11 +115,16 @@ static void amdgpu_benchmark_move(struct amdgpu_device
*adev, unsigned size,
if (unlikely(r != 0))
goto out_cleanup;
r = amdgpu_bo_pin(dobj, ddomain);
- daddr = amdgpu_bo_gpu_offset(dobj);
+ if (r) {
+ amdgpu_bo_unreserve(sobj);
+ goto out_cleanup;
+ }
+ r = amdgpu_ttm_alloc_gart(>tbo);
amdgpu_bo_unreserve(dobj);
if (r) {
goto out_cleanup;
}
+ daddr = amdgpu_bo_gpu_offset(dobj);
if (adev->mman.buffer_funcs) {
time = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 036b6f7..7d6a36b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -194,6 +194,12 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc
*crtc,
goto unreserve;
}
+ r = amdgpu_ttm_alloc_gart(_abo->tbo);
+ if (unlikely(r != 0)) {
+ DRM_ERROR("%p bind failed\n", new_abo);
+ goto unpin;
+ }
+
r = reservation_object_get_fences_rcu(new_abo->tbo.resv, >excl,
>shared_count,
>shared);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 462b7a1..cd68a2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -173,6 +173,14 @@ static int amdgpufb_create_pinned_object(struct
amdgpu_fbdev *rfbdev,
amdgpu_bo_unreserve(abo);
goto out_unref;
}
+
+ ret = amdgpu_ttm_alloc_gart(>tbo);
+ if (ret) {
+ amdgpu_bo_unreserve(abo);
+ dev_err(adev->dev, "%p bind failed\n", abo);
+ goto out_unref;
+ }
+
ret = amdgpu_bo_kmap(abo, NULL);
[PATCH 2/2] drm/amdgpu: allocate gart memory when it's required
Instead of calling gart memory on every bo pin,
allocates it on demand
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 10 --
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 8
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 13 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 5 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +--
8 files changed, 55 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 98e3bf8..982cfa5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -280,6 +280,12 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
goto allocate_mem_pin_bo_failed;
}
+ r = amdgpu_ttm_alloc_gart(>tbo);
+ if (r) {
+ dev_err(adev->dev, "%p bind failed\n", bo);
+ goto allocate_mem_pin_bo_failed;
+ }
+
r = amdgpu_bo_kmap(bo, _ptr_tmp);
if (r) {
dev_err(adev->dev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 079af8a..d498b3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1593,6 +1593,12 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct
kgd_dev *kgd,
goto pin_failed;
}
+ ret = amdgpu_ttm_alloc_gart(>tbo);
+ if (ret) {
+ pr_err("%p bind failed\n", bo);
+ goto pin_failed;
+ }
+
ret = amdgpu_bo_kmap(bo, kptr);
if (ret) {
pr_err("Failed to map bo to kernel. ret %d\n", ret);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index cb88d7e..1d92a88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -96,11 +96,14 @@ static void amdgpu_benchmark_move(struct amdgpu_device
*adev, unsigned size,
if (unlikely(r != 0))
goto out_cleanup;
r = amdgpu_bo_pin(sobj, sdomain);
- saddr = amdgpu_bo_gpu_offset(sobj);
+ if (r)
+ goto out_cleanup;
+ r = amdgpu_ttm_alloc_gart(>tbo);
amdgpu_bo_unreserve(sobj);
if (r) {
goto out_cleanup;
}
+ saddr = amdgpu_bo_gpu_offset(sobj);
bp.domain = ddomain;
r = amdgpu_bo_create(adev, , );
if (r) {
@@ -110,11 +113,14 @@ static void amdgpu_benchmark_move(struct amdgpu_device
*adev, unsigned size,
if (unlikely(r != 0))
goto out_cleanup;
r = amdgpu_bo_pin(dobj, ddomain);
- daddr = amdgpu_bo_gpu_offset(dobj);
+ if (r)
+ goto out_cleanup;
+ r = amdgpu_ttm_alloc_gart(>tbo);
amdgpu_bo_unreserve(dobj);
if (r) {
goto out_cleanup;
}
+ daddr = amdgpu_bo_gpu_offset(dobj);
if (adev->mman.buffer_funcs) {
time = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 036b6f7..0d1c4be 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -194,6 +194,12 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc
*crtc,
goto unreserve;
}
+ r = amdgpu_ttm_alloc_gart(_abo->tbo);
+ if (unlikely(r != 0)) {
+ DRM_ERROR("%p bind failed\n", new_abo);
+ goto unreserve;
+ }
+
r = reservation_object_get_fences_rcu(new_abo->tbo.resv, >excl,
>shared_count,
>shared);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 462b7a1..cd68a2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -173,6 +173,14 @@ static int amdgpufb_create_pinned_object(struct
amdgpu_fbdev *rfbdev,
amdgpu_bo_unreserve(abo);
goto out_unref;
}
+
+ ret = amdgpu_ttm_alloc_gart(>tbo);
+ if (ret) {
+ amdgpu_bo_unreserve(abo);
+ dev_err(adev->dev, "%p bind failed\n", abo);
+ goto out_unref;
+ }
+
ret = amdgpu_bo_kmap(abo, NULL);
amdgpu_bo_unreserve(abo);
if (ret) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/d
[PATCH 1/2] drm/amdgpu: separate gpu address from bo pin
It could be got by amdgpu_bo_gpu_offset() if need
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 16 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 10 +-
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 10 +-
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
17 files changed, 50 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 305143f..98e3bf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -251,7 +251,6 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
struct amdgpu_bo *bo = NULL;
struct amdgpu_bo_param bp;
int r;
- uint64_t gpu_addr_tmp = 0;
void *cpu_ptr_tmp = NULL;
memset(, 0, sizeof(bp));
@@ -275,8 +274,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
goto allocate_mem_reserve_bo_failed;
}
- r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT,
- _addr_tmp);
+ r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
if (r) {
dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
goto allocate_mem_pin_bo_failed;
@@ -290,7 +288,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
}
*mem_obj = bo;
- *gpu_addr = gpu_addr_tmp;
+ *gpu_addr = amdgpu_bo_gpu_offset(bo);
*cpu_ptr = cpu_ptr_tmp;
amdgpu_bo_unreserve(bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index ff8fd75..079af8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1587,7 +1587,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct
kgd_dev *kgd,
goto bo_reserve_failed;
}
- ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
+ ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
if (ret) {
pr_err("Failed to pin bo. ret %d\n", ret);
goto pin_failed;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 19cfff3..cb88d7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -95,7 +95,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev,
unsigned size,
r = amdgpu_bo_reserve(sobj, false);
if (unlikely(r != 0))
goto out_cleanup;
- r = amdgpu_bo_pin(sobj, sdomain, );
+ r = amdgpu_bo_pin(sobj, sdomain);
+ saddr = amdgpu_bo_gpu_offset(sobj);
amdgpu_bo_unreserve(sobj);
if (r) {
goto out_cleanup;
@@ -108,7 +109,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device
*adev, unsigned size,
r = amdgpu_bo_reserve(dobj, false);
if (unlikely(r != 0))
goto out_cleanup;
- r = amdgpu_bo_pin(dobj, ddomain, );
+ r = amdgpu_bo_pin(dobj, ddomain);
+ daddr = amdgpu_bo_gpu_offset(dobj);
amdgpu_bo_unreserve(dobj);
if (r) {
goto out_cleanup;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 995dc02..d2745de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2736,11 +2736,10 @@ int amdgpu_device_resume(struct drm_device *dev, bool
resume, bool fbcon)
struct amdgpu_bo *aobj =
gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
r = amdgpu_bo_reserve(aobj, true);
if (r == 0) {
- r = amdgpu_bo_pin(aobj,
- AMDGPU_GEM_DOMAIN_VRAM,
- _crtc->cursor_addr);
+ r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
if (r != 0)
[PATCH] drm/amdgpu: correct GART location info
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f77b07b..f9fe8d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -676,17 +676,17 @@ void amdgpu_device_vram_location(struct amdgpu_device
*adev,
}
/**
- * amdgpu_device_gart_location - try to find GTT location
+ * amdgpu_device_gart_location - try to find GART location
*
* @adev: amdgpu device structure holding all necessary informations
* @mc: memory controller structure holding memory informations
*
- * Function will place try to place GTT before or after VRAM.
+ * Function will place try to place GART before or after VRAM.
*
- * If GTT size is bigger than space left then we ajust GTT size.
+ * If GART size is bigger than space left then we ajust GART size.
* Thus function will never fails.
*
- * FIXME: when reducing GTT size align new size on power of 2.
+ * FIXME: when reducing GART size align new size on power of 2.
*/
void amdgpu_device_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
@@ -699,13 +699,13 @@ void amdgpu_device_gart_location(struct amdgpu_device
*adev,
size_bf = mc->vram_start;
if (size_bf > size_af) {
if (mc->gart_size > size_bf) {
- dev_warn(adev->dev, "limiting GTT\n");
+ dev_warn(adev->dev, "limiting GART\n");
mc->gart_size = size_bf;
}
mc->gart_start = 0;
} else {
if (mc->gart_size > size_af) {
- dev_warn(adev->dev, "limiting GTT\n");
+ dev_warn(adev->dev, "limiting GART\n");
mc->gart_size = size_af;
}
/* VCE doesn't like it when BOs cross a 4GB segment, so align
@@ -714,7 +714,7 @@ void amdgpu_device_gart_location(struct amdgpu_device *adev,
mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL);
}
mc->gart_end = mc->gart_start + mc->gart_size - 1;
- dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
+ dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
mc->gart_size >> 20, mc->gart_start, mc->gart_end);
}
--
1.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: remove unused parameter for va update
Don't need validation list any more
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 5fb156a..eff716d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -510,7 +510,6 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void
*data,
* @adev: amdgpu_device pointer
* @vm: vm to update
* @bo_va: bo_va to update
- * @list: validation list
* @operation: map, unmap or clear
*
* Update the bo_va directly after setting its address. Errors are not
@@ -519,7 +518,6 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void
*data,
static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
struct amdgpu_bo_va *bo_va,
- struct list_head *list,
uint32_t operation)
{
int r;
@@ -673,7 +671,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
break;
}
if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
- amdgpu_gem_va_update_vm(adev, >vm, bo_va, ,
+ amdgpu_gem_va_update_vm(adev, >vm, bo_va,
args->operation);
error_backoff:
--
1.9.1
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[PATCH] drm/amdgpu: fix clear_all and replace handling in the VM (v2)
From: Christian König (comments: I cannot receive amdgfx mail recently and reply the mail directly, so send it out with my update v2, tested with Unigine Heaven, glmark2, gputest, some cases from vulkan PRT test) v2: store bo_va as well We need to put the lose ends on the invalid list because it is possible that we need to split up huge pages for them. Signed-off-by: Christian König Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 850cd66..cc9d486 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2172,7 +2172,8 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, before->last = saddr - 1; before->offset = tmp->offset; before->flags = tmp->flags; - list_add(>list, >list); + before->bo_va = tmp->bo_va; + list_add(>list, >bo_va->invalids); } /* Remember mapping split at the end */ @@ -2182,7 +2183,8 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, after->offset = tmp->offset; after->offset += after->start - tmp->start; after->flags = tmp->flags; - list_add(>list, >list); + after->bo_va = tmp->bo_va; + list_add(>list, >bo_va->invalids); } list_del(>list); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: skip huge page for PRT mapping
PRT mapping doesn't support huge page, since it's per PTE basis.
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 850cd66..4ce8bb0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -,7 +,8 @@ static void amdgpu_vm_handle_huge_pages(struct
amdgpu_pte_update_params *p,
/* In the case of a mixed PT the PDE must point to it*/
if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
- nptes == AMDGPU_VM_PTE_COUNT(p->adev)) {
+ nptes == AMDGPU_VM_PTE_COUNT(p->adev) &&
+ !(flags & AMDGPU_PTE_PRT)) {
/* Set the huge page flag to stop scanning at this PDE */
flags |= AMDGPU_PDE_PTE;
}
--
1.9.1
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[PATCH] drm/amdgpu: fix NULL pointer dereference when run App with DRI_PRIME=1
[ 632.679861] BUG: unable to handle kernel NULL pointer dereference at (null)
[ 632.679892] IP: drm_prime_sg_to_page_addr_arrays+0x52/0xb0 [drm]
[ 632.680011] Call Trace:
[ 632.680082] amdgpu_ttm_tt_populate+0x3e/0xa0 [amdgpu]
[ 632.680092] ttm_tt_populate.part.7+0x22/0x60 [amdttm]
[ 632.680098] amdttm_tt_bind+0x52/0x60 [amdttm]
[ 632.680106] ttm_bo_handle_move_mem+0x54b/0x5c0 [amdttm]
[ 632.680112] ? find_next_bit+0xb/0x10
[ 632.680119] amdttm_bo_validate+0x11d/0x130 [amdttm]
[ 632.680176] amdgpu_cs_bo_validate+0x9d/0x150 [amdgpu]
[ 632.680232] amdgpu_cs_validate+0x41/0x270 [amdgpu]
[ 632.680288] amdgpu_cs_list_validate+0xc7/0x1a0 [amdgpu]
[ 632.680343] amdgpu_cs_ioctl+0x1634/0x1c00 [amdgpu]
[ 632.680401] ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[ 632.680416] drm_ioctl_kernel+0x6b/0xb0 [drm]
[ 632.680431] drm_ioctl+0x3e4/0x450 [drm]
[ 632.680485] ? amdgpu_cs_find_mapping+0x120/0x120 [amdgpu]
[ 632.680537] amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
[ 632.680542] do_vfs_ioctl+0xa4/0x600
[ 632.680546] ? SyS_futex+0x7f/0x180
[ 632.680549] SyS_ioctl+0x79/0x90
[ 632.680554] entry_SYSCALL_64_fastpath+0x24/0xab
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 57d4da6..b293809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1212,7 +1212,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct
ttm_buffer_object *bo,
gtt->ttm.ttm.func = _backend_func;
/* allocate space for the uninitialized page entries */
- if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+ if (ttm_dma_tt_init(>ttm, bo, page_flags)) {
kfree(gtt);
return NULL;
}
--
1.9.1
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[PATCH] drm/amdgpu: fix null pointer for bo unmap trace function
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 532263a..e96e26d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -275,7 +275,7 @@ ), TP_fast_assign( - __entry->bo = bo_va->base.bo; + __entry->bo = bo_va ? bo_va->base.bo : NULL; __entry->start = mapping->start; __entry->last = mapping->last; __entry->offset = mapping->offset; -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdgpu: set ttm bo priority before initialization
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e62153a..6a9e46a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -419,6 +419,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
bo->tbo.bdev = >mman.bdev;
amdgpu_ttm_placement_from_domain(bo, bp->domain);
+ if (bp->type == ttm_bo_type_kernel)
+ bo->tbo.priority = 1;
r = ttm_bo_init_reserved(>mman.bdev, >tbo, size, bp->type,
>placement, page_align, , acc_size,
@@ -434,9 +436,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
else
amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
- if (bp->type == ttm_bo_type_kernel)
- bo->tbo.priority = 1;
-
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
struct dma_fence *fence;
--
1.9.1
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[PATCH 1/2] drm/ttm: remove priority hard code when initializing ttm bo
Then priority could be set before initialization. By default, it requires to kzalloc ttm bo. In fact, we always do so. Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/ttm/ttm_bo.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 98e06f8..cba5015 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1175,7 +1175,6 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, reservation_object_init(>ttm_resv); atomic_inc(>bdev->glob->bo_count); drm_vma_node_reset(>vma_node); - bo->priority = 0; /* * For ttm_bo_type_device buffers, allocate -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/ttm: specify bo priority when initializing ttm bo
Expect to add an evitable bo who has reservation object
to the correct lru[bo->priority] list
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 11 ++-
drivers/gpu/drm/ast/ast_ttm.c | 2 +-
drivers/gpu/drm/bochs/bochs_mm.c| 2 +-
drivers/gpu/drm/cirrus/cirrus_ttm.c | 2 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c | 2 +-
drivers/gpu/drm/mgag200/mgag200_ttm.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_bo.c| 2 +-
drivers/gpu/drm/qxl/qxl_object.c| 2 +-
drivers/gpu/drm/radeon/radeon_object.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo.c| 8 +---
drivers/gpu/drm/virtio/virtgpu_object.c | 2 +-
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c| 2 +-
drivers/staging/vboxvideo/vbox_ttm.c| 2 +-
include/drm/ttm/ttm_bo_api.h| 5 -
14 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e62153a..9a25ecb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -360,6 +360,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
};
struct amdgpu_bo *bo;
unsigned long page_align, size = bp->size;
+ uint32_t prio = 0;
size_t acc_size;
int r;
@@ -419,10 +420,13 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
bo->tbo.bdev = >mman.bdev;
amdgpu_ttm_placement_from_domain(bo, bp->domain);
+ if (bp->type == ttm_bo_type_kernel)
+ prio = 1;
r = ttm_bo_init_reserved(>mman.bdev, >tbo, size, bp->type,
->placement, page_align, , acc_size,
-NULL, bp->resv, _ttm_bo_destroy);
+prio, >placement, page_align, ,
+acc_size, NULL, bp->resv,
+_ttm_bo_destroy);
if (unlikely(r != 0))
return r;
@@ -434,9 +438,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
else
amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
- if (bp->type == ttm_bo_type_kernel)
- bo->tbo.priority = 1;
-
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
struct dma_fence *fence;
diff --git a/drivers/gpu/drm/ast/ast_ttm.c b/drivers/gpu/drm/ast/ast_ttm.c
index fe354eb..aabb96a 100644
--- a/drivers/gpu/drm/ast/ast_ttm.c
+++ b/drivers/gpu/drm/ast/ast_ttm.c
@@ -320,7 +320,7 @@ int ast_bo_create(struct drm_device *dev, int size, int
align,
sizeof(struct ast_bo));
ret = ttm_bo_init(>ttm.bdev, >bo, size,
- ttm_bo_type_device, >placement,
+ ttm_bo_type_device, 0, >placement,
align >> PAGE_SHIFT, false, acc_size,
NULL, NULL, ast_bo_ttm_destroy);
if (ret)
diff --git a/drivers/gpu/drm/bochs/bochs_mm.c b/drivers/gpu/drm/bochs/bochs_mm.c
index 39cd084..9693109 100644
--- a/drivers/gpu/drm/bochs/bochs_mm.c
+++ b/drivers/gpu/drm/bochs/bochs_mm.c
@@ -366,7 +366,7 @@ static int bochs_bo_create(struct drm_device *dev, int
size, int align,
sizeof(struct bochs_bo));
ret = ttm_bo_init(>ttm.bdev, >bo, size,
- ttm_bo_type_device, >placement,
+ ttm_bo_type_device, 0, >placement,
align >> PAGE_SHIFT, false, acc_size,
NULL, NULL, bochs_bo_ttm_destroy);
if (ret)
diff --git a/drivers/gpu/drm/cirrus/cirrus_ttm.c
b/drivers/gpu/drm/cirrus/cirrus_ttm.c
index f219532..c1d85f8 100644
--- a/drivers/gpu/drm/cirrus/cirrus_ttm.c
+++ b/drivers/gpu/drm/cirrus/cirrus_ttm.c
@@ -327,7 +327,7 @@ int cirrus_bo_create(struct drm_device *dev, int size, int
align,
sizeof(struct cirrus_bo));
ret = ttm_bo_init(>ttm.bdev, >bo, size,
- ttm_bo_type_device, >placement,
+ ttm_bo_type_device, 0, >placement,
align >> PAGE_SHIFT, false, acc_size,
NULL, NULL, cirrus_bo_ttm_destroy);
if (ret)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c
b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c
index 4871025..8c24731 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c
@@ -315,7 +315,7 @@ int hibmc_bo_create(struct drm_device *dev, int size, int
align,
s
[PATCH] drm/amd/powerplay: add PME smu message for raven
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h index 5d07b6e..a2991fa 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h @@ -82,7 +82,8 @@ #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x33 #define PPSMC_MSG_SetSoftMaxVcn 0x34 #define PPSMC_MSG_PowerGateMmHub0x35 -#define PPSMC_Message_Count 0x36 +#define PPSMC_MSG_SetRccPfcPmeRestoreRegister 0x36 +#define PPSMC_Message_Count 0x37 typedef uint16_t PPSMC_Result; -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: bo could be null when access in vm bo update
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6a372ca..1c00f1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1509,7 +1509,6 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
- uint32_t mem_type;
int r;
if (clear || !bo_va->base.bo) {
@@ -1568,9 +1567,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
* the evicted list so that it gets validated again on the
* next command submission.
*/
- mem_type = bo->tbo.mem.mem_type;
if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
- !(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
+ !(bo->preferred_domains &
+ amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)))
list_add_tail(_va->base.vm_status, >evicted);
spin_unlock(>status_lock);
--
1.9.1
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[PATCH v2] drm/amdgpu: simplify bo_va list when vm bo update (v2)
v2: fix compiling warning
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8c34060..e3e0375 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1509,6 +1509,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+ uint32_t mem_type;
int r;
if (clear || !bo_va->base.bo) {
@@ -1561,19 +1562,16 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
}
spin_lock(>status_lock);
- if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
- unsigned mem_type = bo->tbo.mem.mem_type;
+ list_del_init(_va->base.vm_status);
- /* If the BO is not in its preferred location add it back to
-* the evicted list so that it gets validated again on the
-* next command submission.
-*/
- list_del_init(_va->base.vm_status);
- if (!(bo->preferred_domains &
amdgpu_mem_type_to_domain(mem_type)))
- list_add_tail(_va->base.vm_status, >evicted);
- } else {
- list_del_init(_va->base.vm_status);
- }
+ /* If the BO is not in its preferred location add it back to
+* the evicted list so that it gets validated again on the
+* next command submission.
+*/
+ mem_type = bo->tbo.mem.mem_type;
+ if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
+ !(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
+ list_add_tail(_va->base.vm_status, >evicted);
spin_unlock(>status_lock);
list_splice_init(_va->invalids, _va->valids);
--
1.9.1
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[PATCH] drm/amdgpu: disable ECC check for Raven to avoid error message annoyance
It should be enabled until ECC is supported for Raven.
Change-Id: If847663d503c26d2a08274ca721b4ce1bc637111
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index c12ee75..a333442 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -533,6 +533,10 @@ static int gmc_v9_0_ecc_available(struct amdgpu_device
*adev)
DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
+ /* Temporally skip ECC for Raven to avoid error message annoyance */
+ if (adev->asic_type == CHIP_RAVEN)
+ return 0;
+
lost_sheep = 0;
for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
reg_addr = ecc_umclocalcap_addrs[i];
--
1.9.1
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[PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
v2: fix register access Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..6db3645 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, >gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(1) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
v2: fix register access Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..c73a476 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, >gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(0) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS | + PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..5f2ae77 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1069,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr += SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, >gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(0) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS | + PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/powerplay: add vclk/dclkSoftMin support for raven
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 9 +
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 2 ++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++-
4 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index f61da66..14e0321 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -279,6 +279,15 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr,
void *input,
}
} */
+ if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) !=
rv_data->vclk_soft_min) ||
+ ((hwmgr->uvd_arbiter.dclk_soft_min / 100) !=
rv_data->dclk_soft_min)) {
+ rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
+ rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
+ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ PPSMC_MSG_SetSoftMinVcn,
+ (rv_data->vclk_soft_min << 16) |
rv_data->vclk_soft_min);
+ }
+
if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
((hwmgr->gfx_arbiter.sclk_hard_min / 100) !=
rv_data->soc_actual_hard_min_freq)) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index afb8522..2472b50 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -280,6 +280,8 @@ struct rv_hwmgr {
uint32_tf_actual_hard_min_freq;
uint32_tfabric_actual_soft_min_freq;
+ uint32_tvclk_soft_min;
+ uint32_tdclk_soft_min;
uint32_tgfx_actual_soft_min_freq;
bool vcn_power_gated;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 3a0e6b1..f539d55 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -128,6 +128,8 @@ struct phm_uvd_arbiter {
uint32_t dclk;
uint32_t vclk_ceiling;
uint32_t dclk_ceiling;
+ uint32_t vclk_soft_min;
+ uint32_t dclk_soft_min;
};
struct phm_vce_arbiter {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index e0e106f..901c960c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -66,7 +66,12 @@
#define PPSMC_MSG_SetMinVddcrSocVoltage 0x22
#define PPSMC_MSG_SetMinVideoFclkFreq 0x23
#define PPSMC_MSG_SetMinDeepSleepDcefclk0x24
-#define PPSMC_Message_Count 0x25
+#define PPSMC_MSG_ForcePowerDownGfx 0x25
+#define PPSMC_MSG_SetPhyclkVoltageByFreq0x26
+#define PPSMC_MSG_SetDppclkVoltageByFreq0x27
+#define PPSMC_MSG_SetSoftMinVcn 0x28
+#define PPSMC_Message_Count 0x29
+
typedef uint16_t PPSMC_Result;
typedef int PPSMC_Msg;
--
1.9.1
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[PATCH 1/3] drm/amdgpu: add psp bootloader command list
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 10 ++
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 ++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 538fa9d..3776186 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -53,6 +53,16 @@ struct psp_ring
uint32_tring_size;
};
+enum psp_bootloader_command_list
+{
+ PSP_BL__LOAD_SYSDRV = 0x1,
+ PSP_BL__LOAD_SOSDRV = 0x2,
+ PSP_BL__NO_ECC = 0x3,
+ PSP_BL__PARTIAL_ECC = 0x30001,
+ PSP_BL__FULL_ECC= 0x30002,
+ PSP_BL__DEFAULT_ECC = 0x30003,
+};
+
struct psp_context
{
struct amdgpu_device*adev;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 2718e86..f93a66e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -190,7 +190,7 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
/* Provide the sys driver to bootrom */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 1 << 16;
+ psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
@@ -231,7 +231,7 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
/* Provide the PSP secure OS to bootrom */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 2 << 16;
+ psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
--
1.9.1
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[PATCH 3/3] drm/amdgpu: add psp ecc support for vega10
Disable ecc by default
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 60 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 2 ++
3 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index b04cc80..ec433b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -52,6 +52,8 @@ static int psp_sw_init(void *handle)
switch (adev->asic_type) {
case CHIP_VEGA10:
psp->init_microcode = psp_v3_1_init_microcode;
+ psp->bootloader_is_sos_running =
psp_v3_1_bootloader_is_sos_running;
+ psp->bootloader_set_ecc_mode = psp_v3_1_bootloader_set_ecc_mode;
psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
@@ -61,6 +63,7 @@ static int psp_sw_init(void *handle)
psp->cmd_submit = psp_v3_1_cmd_submit;
psp->compare_sram_data = psp_v3_1_compare_sram_data;
psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
+ psp->config.ecc_mode = PSP_ECC_MODE__NONE;
break;
case CHIP_RAVEN:
#if 0
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f93a66e..0a51dde 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -162,6 +162,66 @@ int psp_v3_1_init_microcode(struct psp_context *psp)
return err;
}
+bool psp_v3_1_bootloader_is_sos_running(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+
+ if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81) != 0)
+ return true;
+ else
+ return false;
+}
+
+int psp_v3_1_bootloader_set_ecc_mode(struct psp_context *psp)
+{
+ int ret = 0;
+ uint32_t sol_reg;
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t psp_gfxdrv_command_reg = 0;
+
+ /* Workaround: check bootloader version and skip old one */
+ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+ if (sol_reg < 0xB0C00)
+ return ret;
+
+ switch (psp->config.ecc_mode)
+ {
+ case PSP_ECC_MODE__NONE:
+ break;
+ case PSP_ECC_MODE__OFF:
+ psp_gfxdrv_command_reg = PSP_BL__NO_ECC;
+ break;
+ case PSP_ECC_MODE__ON:
+ psp_gfxdrv_command_reg = PSP_BL__FULL_ECC;
+ break;
+ case PSP_ECC_MODE__PARTIALON:
+ psp_gfxdrv_command_reg = PSP_BL__PARTIAL_ECC;
+ break;
+ default:
+ break;
+ }
+
+ if (psp_gfxdrv_command_reg == 0)
+ return ret;
+
+ /* Wait for bootloader to signify that is ready having bit 31 of
C2PMSG_35 set to 1 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+ 0x8000, 0x8000, false);
+ if (ret)
+ return ret;
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg);
+
+ /* There might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for bootloader to signify that is ready having bit 31 of
C2PMSG_35 set to 1 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+ 0x8000, 0x8000, false);
+
+ return ret;
+}
+
int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
{
int ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
index 9dcd0b2..3e52b5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
@@ -34,6 +34,8 @@
extern int psp_v3_1_init_microcode(struct psp_context *psp);
extern int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp);
+extern bool psp_v3_1_bootloader_is_sos_running(struct psp_context *psp);
+extern int psp_v3_1_bootloader_set_ecc_mode(struct psp_context *psp);
extern int psp_v3_1_bootloader_load_sos(struct psp_context *psp);
extern int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
struct psp_gfx_cmd_resp *cmd);
--
1.9.1
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[PATCH 0/3] *** Add PSP ECC support for Vega10 ***
Junwei Zhang (3): drm/amdgpu: add psp bootloader command list drm/amdgpu: add psp ecc support drm/amdgpu: add psp ecc support for vega10 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 20 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 32 + drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 64 +++-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 2 ++ 4 files changed, 113 insertions(+), 5 deletions(-) -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/3] drm/amdgpu: add psp ecc support
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 17 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 22 ++
2 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 1aa41af..b04cc80 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -256,6 +256,10 @@ static int psp_hw_start(struct psp_context *psp)
{
int ret;
+ ret = psp_bootloader_set_ecc_mode(psp);
+ if (ret)
+ return ret;
+
ret = psp_bootloader_load_sysdrv(psp);
if (ret)
return ret;
@@ -365,9 +369,16 @@ static int psp_load_fw(struct amdgpu_device *adev)
if (ret)
goto failed_mem;
- ret = psp_hw_start(psp);
- if (ret)
- goto failed_mem;
+ if (psp_bootloader_is_sos_running(psp) &&
+ psp->config.ecc_mode != PSP_ECC_MODE__NONE) {
+ if (psp_ring_create(psp, PSP_RING_TYPE__KM))
+ goto failed_mem;
+ if (psp_tmr_load(psp))
+ goto failed_mem;
+ } else {
+ if (psp_hw_start(psp))
+ goto failed_mem;
+ }
ret = psp_np_fw_load(psp);
if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 3776186..8ec9194 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -63,6 +63,19 @@ enum psp_bootloader_command_list
PSP_BL__DEFAULT_ECC = 0x30003,
};
+enum psp_ecc_mode
+{
+ PSP_ECC_MODE__NONE = 0,
+ PSP_ECC_MODE__OFF = 1,
+ PSP_ECC_MODE__ON = 2,
+ PSP_ECC_MODE__PARTIALON = 3,
+};
+
+struct psp_config
+{
+ enum psp_ecc_mode ecc_mode;
+};
+
struct psp_context
{
struct amdgpu_device*adev;
@@ -70,6 +83,8 @@ struct psp_context
struct psp_gfx_cmd_resp *cmd;
int (*init_microcode)(struct psp_context *psp);
+ int (*bootloader_set_ecc_mode)(struct psp_context *psp);
+ bool (*bootloader_is_sos_running)(struct psp_context *psp);
int (*bootloader_load_sysdrv)(struct psp_context *psp);
int (*bootloader_load_sos)(struct psp_context *psp);
int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
@@ -123,6 +138,9 @@ struct psp_context
struct amdgpu_bo*cmd_buf_bo;
uint64_tcmd_buf_mc_addr;
struct psp_gfx_cmd_resp *cmd_buf_mem;
+
+ /* psp config */
+ struct psp_config config;
};
struct amdgpu_psp_funcs {
@@ -140,6 +158,10 @@ struct amdgpu_psp_funcs {
(psp)->compare_sram_data((psp), (ucode), (type))
#define psp_init_microcode(psp) \
((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0)
+#define psp_bootloader_set_ecc_mode(psp) \
+ ((psp)->bootloader_set_ecc_mode ?
(psp)->bootloader_set_ecc_mode((psp)) : 0)
+#define psp_bootloader_is_sos_running(psp) \
+ ((psp)->bootloader_is_sos_running ?
(psp)->bootloader_is_sos_running((psp)) : 0)
#define psp_bootloader_load_sysdrv(psp) \
((psp)->bootloader_load_sysdrv ?
(psp)->bootloader_load_sysdrv((psp)) : 0)
#define psp_bootloader_load_sos(psp) \
--
1.9.1
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[PATCH] drm/amdgpu: disable firmware loading for psp v10
Now asd firmware is not ready for psp v10, will enable it when it's available Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c919579..1aa41af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -63,7 +63,9 @@ static int psp_sw_init(void *handle) psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk; break; case CHIP_RAVEN: +#if 0 psp->init_microcode = psp_v10_0_init_microcode; +#endif psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf; psp->ring_init = psp_v10_0_ring_init; psp->ring_create = psp_v10_0_ring_create; -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: read reg in each iterate of psp_wait_for loop
From: "Zhang, Jerry" <jerry.zh...@amd.com>
v2: fixes the SOS loading failure for PSP v3.1
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
Cc: sta...@vger.kernel.org
Acked-by: Alex Deucher <alexander.deuc...@amd.com> (v1)
Acked-by: Huang Rui <ray.hu...@amd.com> (v1)
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 --
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c919579..644941d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -98,9 +98,8 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
int i;
struct amdgpu_device *adev = psp->adev;
- val = RREG32(reg_index);
-
for (i = 0; i < adev->usec_timeout; i++) {
+ val = RREG32(reg_index);
if (check_changed) {
if (val != reg_val)
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 2718e86..23106e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -237,11 +237,9 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
/* there might be handshake issue with hardware which needs delay */
mdelay(20);
-#if 0
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
0, true);
-#endif
return ret;
}
--
1.9.1
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[PATCH 2/2] drm/amdgpu: enable sos status checking for vega10
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 2718e86..23106e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -237,11 +237,9 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp) /* there might be handshake issue with hardware which needs delay */ mdelay(20); -#if 0 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, true); -#endif return ret; } -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu: read reg in each iterate of psp_wait_for loop
From: "Zhang, Jerry" <jerry.zh...@amd.com>
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
Acked-by: Huang Rui <ray.hu...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c919579..644941d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -98,9 +98,8 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
int i;
struct amdgpu_device *adev = psp->adev;
- val = RREG32(reg_index);
-
for (i = 0; i < adev->usec_timeout; i++) {
+ val = RREG32(reg_index);
if (check_changed) {
if (val != reg_val)
return 0;
--
1.9.1
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[PATCH 1/4] drm/amdgpu: remove unncessary code in psp v10 ring init func
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 20
1 file changed, 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 8e0a24f..328c6f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -111,7 +111,6 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info
*ucode, struct psp_gfx_cm
int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
{
int ret = 0;
- unsigned int psp_ring_reg = 0;
struct psp_ring *ring;
struct amdgpu_device *adev = psp->adev;
@@ -131,25 +130,6 @@ int psp_v10_0_ring_init(struct psp_context *psp, enum
psp_ring_type ring_type)
return ret;
}
- /* Write low address of the ring to C2PMSG_69 */
- psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
- /* Write high address of the ring to C2PMSG_70 */
- psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
- /* Write size of ring to C2PMSG_71 */
- psp_ring_reg = ring->ring_size;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
- /* Write the ring initialization command to C2PMSG_64 */
- psp_ring_reg = ring_type;
- psp_ring_reg = psp_ring_reg << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
- /* Wait for response flag (bit 31) in C2PMSG_64 */
- psp_ring_reg = 0;
- while ((psp_ring_reg & 0x8000) == 0) {
- psp_ring_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64);
- }
-
return 0;
}
--
1.9.1
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[PATCH 4/4] drm/amdgpu: add ring_destroy for psp v10
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 27 +++
drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 2 ++
3 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8f4eafc..644941d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -67,6 +67,7 @@ static int psp_sw_init(void *handle)
psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
psp->ring_init = psp_v10_0_ring_init;
psp->ring_create = psp_v10_0_ring_create;
+ psp->ring_destroy = psp_v10_0_ring_destroy;
psp->cmd_submit = psp_v10_0_cmd_submit;
psp->compare_sram_data = psp_v10_0_compare_sram_data;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index fb29cd4..b4af32a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -210,6 +210,33 @@ int psp_v10_0_ring_create(struct psp_context *psp, enum
psp_ring_type ring_type)
return ret;
}
+int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type
ring_type)
+{
+ int ret = 0;
+ struct psp_ring *ring;
+ unsigned int psp_ring_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+
+ ring = >km_ring;
+
+ /* Write the ring destroy command to C2PMSG_64 */
+ psp_ring_reg = 3 << 16;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+ /* There might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for response flag (bit 31) in C2PMSG_64 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ 0x8000, 0x8000, false);
+
+ if (ring->ring_mem)
+ amdgpu_bo_free_kernel(>firmware.rbuf,
+ >ring_mem_mc_addr,
+ (void **)>ring_mem);
+ return ret;
+}
+
int psp_v10_0_cmd_submit(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
index 7e9a8cd..e76cde2 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v10_0_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type);
+extern int psp_v10_0_ring_destroy(struct psp_context *psp,
+ enum psp_ring_type ring_type);
extern int psp_v10_0_cmd_submit(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
--
1.9.1
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[PATCH 3/4] drm/amdgpu: add ring_create function for psp v10
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 31 +++
drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 2 ++
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index dc95633..8f4eafc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -66,6 +66,7 @@ static int psp_sw_init(void *handle)
psp->init_microcode = psp_v10_0_init_microcode;
psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
psp->ring_init = psp_v10_0_ring_init;
+ psp->ring_create = psp_v10_0_ring_create;
psp->cmd_submit = psp_v10_0_cmd_submit;
psp->compare_sram_data = psp_v10_0_compare_sram_data;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 7513f9c..fb29cd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -179,6 +179,37 @@ int psp_v10_0_ring_init(struct psp_context *psp, enum
psp_ring_type ring_type)
return 0;
}
+int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type
ring_type)
+{
+ int ret = 0;
+ unsigned int psp_ring_reg = 0;
+ struct psp_ring *ring = >km_ring;
+ struct amdgpu_device *adev = psp->adev;
+
+ /* Write low address of the ring to C2PMSG_69 */
+ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
+ /* Write high address of the ring to C2PMSG_70 */
+ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
+ /* Write size of ring to C2PMSG_71 */
+ psp_ring_reg = ring->ring_size;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
+ /* Write the ring initialization command to C2PMSG_64 */
+ psp_ring_reg = ring_type;
+ psp_ring_reg = psp_ring_reg << 16;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+ /* There might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for response flag (bit 31) in C2PMSG_64 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ 0x8000, 0x8000, false);
+
+ return ret;
+}
+
int psp_v10_0_cmd_submit(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
index 2f5a314e..7e9a8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -32,6 +32,8 @@ extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info
*ucode,
struct psp_gfx_cmd_resp *cmd);
extern int psp_v10_0_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type);
+extern int psp_v10_0_ring_create(struct psp_context *psp,
+enum psp_ring_type ring_type);
extern int psp_v10_0_cmd_submit(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
--
1.9.1
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[PATCH 2/4] drm/amdgpu: add init microcode function for psp v10
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 46 +
drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 1 +
3 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 71ce3ee..dc95633 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -63,6 +63,7 @@ static int psp_sw_init(void *handle)
psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
break;
case CHIP_RAVEN:
+ psp->init_microcode = psp_v10_0_init_microcode;
psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
psp->ring_init = psp_v10_0_ring_init;
psp->cmd_submit = psp_v10_0_cmd_submit;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 328c6f5..7513f9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -87,6 +87,52 @@
return 0;
}
+int psp_v10_0_init_microcode(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+ const char *chip_name;
+ char fw_name[30];
+ int err = 0;
+ const struct psp_firmware_header_v1_0 *hdr;
+
+ DRM_DEBUG("\n");
+
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+ chip_name = "raven";
+ break;
+ default: BUG();
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
+ err = request_firmware(>psp.asd_fw, fw_name, adev->dev);
+ if (err)
+ goto out;
+
+ err = amdgpu_ucode_validate(adev->psp.asd_fw);
+ if (err)
+ goto out;
+
+ hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
+ adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
+ adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
+ adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
+ adev->psp.asd_start_addr = (uint8_t *)hdr +
+
le32_to_cpu(hdr->header.ucode_array_offset_bytes);
+
+ return 0;
+out:
+ if (err) {
+ dev_err(adev->dev,
+ "psp v10.0: Failed to load firmware \"%s\"\n",
+ fw_name);
+ release_firmware(adev->psp.asd_fw);
+ adev->psp.asd_fw = NULL;
+ }
+
+ return err;
+}
+
int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct
psp_gfx_cmd_resp *cmd)
{
int ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
index 2022b7b..2f5a314e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -27,6 +27,7 @@
#include "amdgpu_psp.h"
+extern int psp_v10_0_init_microcode(struct psp_context *psp);
extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
struct psp_gfx_cmd_resp *cmd);
extern int psp_v10_0_ring_init(struct psp_context *psp,
--
1.9.1
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[PATCH 0/4] *** Prepare to support PSP v10 for Raven ***
Junwei Zhang (4): drm/amdgpu: remove unncessary code in psp v10 ring init func drm/amdgpu: add init microcode function for psp v10 drm/amdgpu: add ring_create function for psp v10 drm/amdgpu: add ring_destroy for psp v10 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 96 ++--- drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 5 ++ 3 files changed, 98 insertions(+), 6 deletions(-) -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: read reg in each iterate of psp_wait_for loop
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index ba743d4..71ce3ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -95,9 +95,8 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
int i;
struct amdgpu_device *adev = psp->adev;
- val = RREG32(reg_index);
-
for (i = 0; i < adev->usec_timeout; i++) {
+ val = RREG32(reg_index);
if (check_changed) {
if (val != reg_val)
return 0;
--
1.9.1
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[PATCH] drm/amdgpu: fix sem list soft lockup issue
sem should be delete from the previous sem list
then add to the new sem list.
If adding sem to the list which is same as previous one,
it will cause endless loop when traverses the sem list.
[ 264.133878] NMI watchdog: BUG: soft lockup - CPU#5 stuck for 22s!
...
[ 264.133928] task: a216ffbfbd00 task.stack: a216f422
[ 264.133929] RIP: 0010:[] []
amdgpu_sem_put+0x13/0x30 [amdgpu]
[ 264.133983] RSP: 0018:a216f4223cb0 EFLAGS: 00200286
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index ff20e11..aac43c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -84,8 +84,10 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
mutex_lock(>rings[i].sem_lock);
/* release all the reset inserted SEM here */
- list_for_each_entry_safe(sem, tmp, >rings[i].sem_list,
list)
+ list_for_each_entry_safe(sem, tmp, >rings[i].sem_list,
list) {
+ list_del_init(>list);
amdgpu_sem_put(sem);
+ }
mutex_unlock(>rings[i].sem_lock);
mutex_destroy(>rings[i].sem_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
index 0302ea6..a7149ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
@@ -371,6 +371,7 @@ static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv,
if (r)
goto err;
mutex_lock(>rings[out_ring->idx].sem_lock);
+ list_del_init(>list);
list_add(>list, >rings[out_ring->idx].sem_list);
mutex_unlock(>rings[out_ring->idx].sem_lock);
amdgpu_sem_get(sem);
--
1.9.1
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[PATCH 1/2] drm/amdgpu: export more gpu info for gfx9
v2: 64-bit aligned for gpu info
Signed-off-by: Ken Wang <qingqing.w...@amd.com>
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Reviewed-by: Qiang Yu <qiang...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 +++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++
include/uapi/drm/amdgpu_drm.h | 19 +++
4 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4a16e3c..503010a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -969,6 +969,9 @@ struct amdgpu_gfx_config {
unsigned mc_arb_ramcfg;
unsigned gb_addr_config;
unsigned num_rbs;
+ unsigned gs_vgt_table_depth;
+ unsigned gs_prim_buffer_depth;
+ unsigned max_gs_waves_per_vgt;
uint32_t tile_mode_array[32];
uint32_t macrotile_mode_array[16];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 1006d7c..42e5993 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -546,10 +546,21 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (amdgpu_ngg) {
dev_info.prim_buf_gpu_addr =
adev->gfx.ngg.buf[PRIM].gpu_addr;
+ dev_info.prim_buf_size = adev->gfx.ngg.buf[PRIM].size;
dev_info.pos_buf_gpu_addr =
adev->gfx.ngg.buf[POS].gpu_addr;
+ dev_info.pos_buf_size = adev->gfx.ngg.buf[POS].size;
dev_info.cntl_sb_buf_gpu_addr =
adev->gfx.ngg.buf[CNTL].gpu_addr;
+ dev_info.cntl_sb_buf_size =
adev->gfx.ngg.buf[CNTL].size;
dev_info.param_buf_gpu_addr =
adev->gfx.ngg.buf[PARAM].gpu_addr;
+ dev_info.param_buf_size = adev->gfx.ngg.buf[PARAM].size;
}
+ dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
+ dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
+ dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
+ dev_info.num_tcc_blocks =
adev->gfx.config.max_texture_channel_caches;
+ dev_info.gs_vgt_table_depth =
adev->gfx.config.gs_vgt_table_depth;
+ dev_info.gs_prim_buffer_depth =
adev->gfx.config.gs_prim_buffer_depth;
+ dev_info.max_gs_waves_per_vgt =
adev->gfx.config.max_gs_waves_per_vgt;
return copy_to_user(out, _info,
min((size_t)size, sizeof(dev_info))) ?
-EFAULT : 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 13da795..5249bc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -785,6 +785,9 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device
*adev)
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+ adev->gfx.config.gs_vgt_table_depth = 32;
+ adev->gfx.config.gs_prim_buffer_depth = 1792;
+ adev->gfx.config.max_gs_waves_per_vgt = 32;
gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
break;
default:
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index d76d525..086ab10 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -769,6 +769,25 @@ struct drm_amdgpu_info_device {
__u64 cntl_sb_buf_gpu_addr;
/* NGG Parameter Cache */
__u64 param_buf_gpu_addr;
+ __u32 prim_buf_size;
+ __u32 pos_buf_size;
+ __u32 cntl_sb_buf_size;
+ __u32 param_buf_size;
+ /* wavefront size*/
+ __u32 wave_front_size;
+ /* shader visible vgprs*/
+ __u32 num_shader_visible_vgprs;
+ /* CU per shader array*/
+ __u32 num_cu_per_sh;
+ /* number of tcc blocks*/
+ __u32 num_tcc_blocks;
+ /* gs vgt table depth*/
+ __u32 gs_vgt_table_depth;
+ /* gs primitive buffer depth*/
+ __u32 gs_prim_buffer_depth;
+ /* max gs wavefront per vgt*/
+ __u32 max_gs_waves_per_vgt;
+ __u32 _pad1;
};
struct drm_amdgpu_info_hw_ip {
--
1.9.1
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[PATCH 2/2] drm/amdgpu: bump version for exporting gpu info for gfx9
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ead00d7..857c3be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -64,9 +64,10 @@ * - 3.12.0 - Add query for double offchip LDS buffers * - 3.13.0 - Add PRT support * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality + * - 3.15.0 - Export more gpu info for gfx9 */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 14 +#define KMS_DRIVER_MINOR 15 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: extend vm flags to 64-bit in tracepoint
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 8676eff..998ff4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -221,7 +221,7 @@
__field(long, start)
__field(long, last)
__field(u64, offset)
-__field(u32, flags)
+__field(u64, flags)
),
TP_fast_assign(
@@ -231,7 +231,7 @@
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%08x",
+ TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%010llx",
__entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
@@ -245,7 +245,7 @@
__field(long, start)
__field(long, last)
__field(u64, offset)
-__field(u32, flags)
+__field(u64, flags)
),
TP_fast_assign(
@@ -255,7 +255,7 @@
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%08x",
+ TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%010llx",
__entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
@@ -266,7 +266,7 @@
TP_STRUCT__entry(
__field(u64, soffset)
__field(u64, eoffset)
-__field(u32, flags)
+__field(u64, flags)
),
TP_fast_assign(
@@ -274,7 +274,7 @@
__entry->eoffset = mapping->it.last + 1;
__entry->flags = mapping->flags;
),
- TP_printk("soffs=%010llx, eoffs=%010llx, flags=%08x",
+ TP_printk("soffs=%010llx, eoffs=%010llx, flags=%010llx",
__entry->soffset, __entry->eoffset, __entry->flags)
);
@@ -290,14 +290,14 @@
TRACE_EVENT(amdgpu_vm_set_ptes,
TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
-uint32_t incr, uint32_t flags),
+uint32_t incr, uint64_t flags),
TP_ARGS(pe, addr, count, incr, flags),
TP_STRUCT__entry(
__field(u64, pe)
__field(u64, addr)
__field(u32, count)
__field(u32, incr)
-__field(u32, flags)
+__field(u64, flags)
),
TP_fast_assign(
@@ -307,7 +307,7 @@
__entry->incr = incr;
__entry->flags = flags;
),
- TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%08x, count=%u",
+ TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%010Lx, count=%u",
__entry->pe, __entry->addr, __entry->incr,
__entry->flags, __entry->count)
);
--
1.9.1
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[PATCH] drm/amdgpu: fix trace error for amdgpu_vm_bo_unmap
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index f38e5e2..8676eff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -249,7 +249,7 @@ ), TP_fast_assign( - __entry->bo = bo_va->bo; + __entry->bo = bo_va ? bo_va->bo : NULL; __entry->start = mapping->it.start; __entry->last = mapping->it.last; __entry->offset = mapping->offset; -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH V3] drm/amdgpu: PRT support for gfx9 (v3)
From: "Zhang, Jerry" <jerry.zh...@amd.com>
v2: unify PRT bit for all ASICs
v3: move PRT flag checking in amdgpu_vm_bo_split_mapping()
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
Acked-by: David Zhou <david1.z...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 30754ef..d363a9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1143,6 +1143,12 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
flags &= ~AMDGPU_PTE_MTYPE_MASK;
flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
+ if ((mapping->flags & AMDGPU_PTE_PRT) &&
+ (adev->asic_type >= CHIP_VEGA10)) {
+ flags |= AMDGPU_PTE_PRT;
+ flags &= ~AMDGPU_PTE_VALID;
+ }
+
trace_amdgpu_vm_bo_update(mapping);
pfn = mapping->offset >> PAGE_SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 4904740..6c670d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -65,7 +65,8 @@
#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
-#define AMDGPU_PTE_PRT (1ULL << 63)
+/* TILED for VEGA10, reserved for older ASICs */
+#define AMDGPU_PTE_PRT (1ULL << 51)
/* VEGA10 only */
#define AMDGPU_PTE_MTYPE(a)((uint64_t)a << 57)
--
1.9.1
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[PATCH v2] drm/amdgpu: PRT support for gfx9 (v2)
v2: unify PRT bit for all ASICs
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
Acked-by: David Zhou <david1.z...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f804d38..f4087c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1473,6 +1473,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
spin_unlock(>status_lock);
list_for_each_entry(mapping, _va->invalids, list) {
+ if (mapping->flags & AMDGPU_PTE_PRT) {
+ flags |= AMDGPU_PTE_PRT;
+ flags &= ~AMDGPU_PTE_VALID;
+ }
+
r = amdgpu_vm_bo_split_mapping(adev, exclusive,
gtt_flags, pages_addr, vm,
mapping, flags, mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 0f547c6..8eba2d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -65,7 +65,8 @@
#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
-#define AMDGPU_PTE_PRT (1ULL << 63)
+/* TILED for VEGA10, reserved for older ASICs */
+#define AMDGPU_PTE_PRT (1ULL << 51)
/* VEGA10 only */
#define AMDGPU_PTE_MTYPE(a)((uint64_t)a << 57)
--
1.9.1
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[PATCH] drm/amdgpu: PRT support for gfx9
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9ff445c..51aedf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1269,6 +1269,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
spin_unlock(>status_lock);
list_for_each_entry(mapping, _va->invalids, list) {
+ if (mapping->flags & AMDGPU_PTE_TILED) {
+ flags |= AMDGPU_PTE_TILED;
+ flags &= ~AMDGPU_PTE_VALID;
+ }
+
r = amdgpu_vm_bo_split_mapping(adev, exclusive,
gtt_flags, pages_addr, vm,
mapping, flags, mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 4904740..8d25914 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -70,6 +70,7 @@
/* VEGA10 only */
#define AMDGPU_PTE_MTYPE(a)((uint64_t)a << 57)
#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
+#define AMDGPU_PTE_TILED (1ULL << 51)
/* How to programm VM fault handling */
#define AMDGPU_VM_FAULT_STOP_NEVER 0
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 51a1919..6d033ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -324,7 +324,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct
amdgpu_device *adev,
}
if (flags & AMDGPU_VM_PAGE_PRT)
- pte_flag |= AMDGPU_PTE_PRT;
+ pte_flag |= AMDGPU_PTE_TILED;
return pte_flag;
}
--
1.9.1
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[PATCH] drm/amdgpu: reserve space before adding a shared fence
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 157ae50..55af909 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -913,6 +913,9 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, if (shadow) amdgpu_sync_resv(adev, >sync, shadow->tbo.resv, AMDGPU_FENCE_OWNER_VM); + r = reservation_object_reserve_shared(parent->bo->tbo.resv); + if (r) + goto error_free; WARN_ON(params.ib->length_dw > ndw); r = amdgpu_job_submit(job, ring, >entity, -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix amdgpu_vm warning
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c: In function 'amdgpu_vm_bo_update_mapping': >> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1207:20: warning: comparison of distinct pointer types lacks a cast [enabled by default] Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index bc2650ef..2209a6a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1204,7 +1204,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, * reserve space for one command every (1 << BLOCK_SIZE) * entries or 2k dwords (whatever is smaller) */ - ncmds = (nptes >> min(adev->vm_manager.block_size, 11)) + 1; + ncmds = (nptes >> min(adev->vm_manager.block_size, (uint32_t)11)) + 1; /* padding, etc. */ ndw = 64; -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amdgpu: set vm size and block size by individual gmc by default (v2)
By default, the value is set by individual gmc.
if a specific value is input, it overrides the global value for all
v2: create helper funcs
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 38 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 +
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 ---
8 files changed, 60 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d0c742..8fce309 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,35 +1039,31 @@ static bool amdgpu_check_pot_argument(int arg)
return (arg & (arg - 1)) == 0;
}
-static void amdgpu_get_block_size(struct amdgpu_device *adev)
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
{
/* defines number of bits in page table versus page directory,
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
* page table and the remaining bits are in the page directory */
- if (amdgpu_vm_block_size == -1) {
-
- /* Total bits covered by PD + PTs */
- unsigned bits = ilog2(amdgpu_vm_size) + 18;
-
- /* Make sure the PD is 4K in size up to 8GB address space.
- Above that split equal between PD and PTs */
- if (amdgpu_vm_size <= 8)
- amdgpu_vm_block_size = bits - 9;
- else
- amdgpu_vm_block_size = (bits + 3) / 2;
+ if (amdgpu_vm_block_size == -1)
+ return;
- } else if (amdgpu_vm_block_size < 9) {
+ if (amdgpu_vm_block_size < 9) {
dev_warn(adev->dev, "VM page table size (%d) too small\n",
amdgpu_vm_block_size);
- amdgpu_vm_block_size = 9;
+ goto def_value;
}
if (amdgpu_vm_block_size > 24 ||
(amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
dev_warn(adev->dev, "VM page table size (%d) too large\n",
amdgpu_vm_block_size);
- amdgpu_vm_block_size = 9;
+ goto def_value;
}
+
+ return;
+
+def_value:
+ amdgpu_vm_block_size = -1;
}
static void amdgpu_check_vm_size(struct amdgpu_device *adev)
@@ -1096,8 +1092,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device
*adev)
return;
def_value:
- amdgpu_vm_size = 8;
- dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
+ amdgpu_vm_size = -1;
}
/**
@@ -1131,7 +1126,7 @@ static void amdgpu_check_arguments(struct amdgpu_device
*adev)
amdgpu_check_vm_size(adev);
- amdgpu_get_block_size(adev);
+ amdgpu_check_block_size(adev);
if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
!amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index bfd945b..6238e2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -86,7 +86,7 @@
unsigned amdgpu_ip_block_mask = 0x;
int amdgpu_bapm = -1;
int amdgpu_deep_color = 0;
-int amdgpu_vm_size = 64;
+int amdgpu_vm_size = -1;
int amdgpu_vm_block_size = -1;
int amdgpu_vm_fault_stop = 0;
int amdgpu_vm_debug = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8785420..bc2650ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2064,6 +2064,44 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
}
}
+static uint32_t amdgpu_get_block_size(uint64_t vm_size)
+{
+ /* Total bits covered by PD + PTs */
+ unsigned bits = ilog2(vm_size) + 18;
+
+ /* Make sure the PD is 4K in size up to 8GB address space.
+ Above that split equal between PD and PTs */
+ if (vm_size <= 8)
+ return (bits - 9);
+ else
+ return ((bits + 3) / 2);
+}
+
+/**
+ * amdgpu_vm_adjust_size - adjust vm size and block size
+ *
+ * @adev: amdgpu_device pointer
+ * @vm_size: the default vm size if it's set auto
+ */
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size)
+{
+ /* adjust vm size firstly */
+ if (amdgpu_vm_size == -1)
+ adev->vm_manager.vm_size = vm_size;
+ else
+
[PATCH] drm/amdgpu: set vm size and block size by individual gmc by default
By default, the value is set by individual gmc.
if a specific value is input, it overrides the global value for all
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +--
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +--
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 ++--
7 files changed, 74 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 65021df..d7f75ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v,
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
+uint32_t amdgpu_get_block_size(int vm_size);
+
/*
* Registers read & write functions.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d0c742..2f91c2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg)
return (arg & (arg - 1)) == 0;
}
-static void amdgpu_get_block_size(struct amdgpu_device *adev)
+uint32_t amdgpu_get_block_size(int vm_size)
+{
+ /* Total bits covered by PD + PTs */
+ unsigned bits = ilog2(vm_size) + 18;
+
+ /* Make sure the PD is 4K in size up to 8GB address space.
+ Above that split equal between PD and PTs */
+ if (vm_size <= 8)
+ return (bits - 9);
+ else
+ return ((bits + 3) / 2);
+}
+
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
{
/* defines number of bits in page table versus page directory,
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
* page table and the remaining bits are in the page directory */
- if (amdgpu_vm_block_size == -1) {
-
- /* Total bits covered by PD + PTs */
- unsigned bits = ilog2(amdgpu_vm_size) + 18;
-
- /* Make sure the PD is 4K in size up to 8GB address space.
- Above that split equal between PD and PTs */
- if (amdgpu_vm_size <= 8)
- amdgpu_vm_block_size = bits - 9;
- else
- amdgpu_vm_block_size = (bits + 3) / 2;
+ if (amdgpu_vm_block_size == -1)
+ return;
- } else if (amdgpu_vm_block_size < 9) {
+ if (amdgpu_vm_block_size < 9) {
dev_warn(adev->dev, "VM page table size (%d) too small\n",
amdgpu_vm_block_size);
- amdgpu_vm_block_size = 9;
+ goto def_value;
}
if (amdgpu_vm_block_size > 24 ||
(amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
dev_warn(adev->dev, "VM page table size (%d) too large\n",
amdgpu_vm_block_size);
- amdgpu_vm_block_size = 9;
+ goto def_value;
}
+
+ return;
+
+def_value:
+ amdgpu_vm_block_size = -1;
}
static void amdgpu_check_vm_size(struct amdgpu_device *adev)
@@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device
*adev)
return;
def_value:
- amdgpu_vm_size = 8;
- dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
+ amdgpu_vm_size = -1;;
}
/**
@@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device
*adev)
amdgpu_check_vm_size(adev);
- amdgpu_get_block_size(adev);
+ amdgpu_check_block_size(adev);
if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
!amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index bfd945b..6238e2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -86,7 +86,7 @@
unsigned amdgpu_ip_block_mask = 0x;
int amdgpu_bapm = -1;
int amdgpu_deep_color = 0;
-int amdgpu_vm_size = 64;
+int amdgpu_vm_size = -1;
int amdgpu_vm_block_size = -1;
int amdgpu_vm_fault_stop = 0;
int amdgpu_vm_debug = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 30d5c42..f46c52c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle)
[PATCH] drm/amdgpu: fix vm size and block size for VMPT (v3)
From: "Zhang, Jerry" <jerry.zh...@amd.com>
v2: set both of them in gmc
v3: move vm size and block size in vm manager
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 --
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +++-
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 --
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 9 +++--
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 9 +++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 21 +
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 2 +-
9 files changed, 52 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fbb4afb..1d0c742 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1041,14 +1041,6 @@ static bool amdgpu_check_pot_argument(int arg)
static void amdgpu_get_block_size(struct amdgpu_device *adev)
{
- /* from AI, asic starts to support multiple level VMPT */
- if (adev->asic_type >= CHIP_VEGA10) {
- if (amdgpu_vm_block_size != 9)
- dev_warn(adev->dev,
-"Multi-VMPT limits block size to one page!\n");
- amdgpu_vm_block_size = 9;
- return;
- }
/* defines number of bits in page table versus page directory,
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
* page table and the remaining bits are in the page directory */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 43adc4b..46d3f1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -100,13 +100,14 @@ static unsigned amdgpu_vm_num_entries(struct
amdgpu_device *adev,
if (level == 0)
/* For the root directory */
return adev->vm_manager.max_pfn >>
- (amdgpu_vm_block_size * adev->vm_manager.num_level);
+ (adev->vm_manager.block_size *
+adev->vm_manager.num_level);
else if (level == adev->vm_manager.num_level)
/* For the page tables on the leaves */
- return AMDGPU_VM_PTE_COUNT;
+ return AMDGPU_VM_PTE_COUNT(adev);
else
/* Everything in between */
- return 1 << amdgpu_vm_block_size;
+ return 1 << adev->vm_manager.block_size;
}
/**
@@ -271,7 +272,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device
*adev,
unsigned level)
{
unsigned shift = (adev->vm_manager.num_level - level) *
- amdgpu_vm_block_size;
+ adev->vm_manager.block_size;
unsigned pt_idx, from, to;
int r;
@@ -970,7 +971,7 @@ static struct amdgpu_bo *amdgpu_vm_get_pt(struct
amdgpu_pte_update_params *p,
unsigned idx, level = p->adev->vm_manager.num_level;
while (entry->entries) {
- idx = addr >> (amdgpu_vm_block_size * level--);
+ idx = addr >> (p->adev->vm_manager.block_size * level--);
idx %= amdgpu_bo_size(entry->bo) / 8;
entry = >entries[idx];
}
@@ -997,7 +998,8 @@ static void amdgpu_vm_update_ptes(struct
amdgpu_pte_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags)
{
- const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
+ struct amdgpu_device *adev = params->adev;
+ const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
uint64_t cur_pe_start, cur_nptes, cur_dst;
uint64_t addr; /* next GPU address to be updated */
@@ -1021,7 +1023,7 @@ static void amdgpu_vm_update_ptes(struct
amdgpu_pte_update_params *params,
if ((addr & ~mask) == (end & ~mask))
nptes = end - addr;
else
- nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
+ nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
cur_pe_start = amdgpu_bo_gpu_offset(pt);
cur_pe_start += (addr & mask) * 8;
@@ -1049,7 +1051,7 @@ static void amdgpu_vm_update_ptes(struct
amdgpu_pte_update_params *params,
if ((addr & ~mask) == (end & ~mask))
nptes = end - addr;
else
- nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
+ nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
next_pe_start = amdgpu_bo_gpu_offset(pt);
next_pe_start +=
[PATCH 2/2] drm/amdgpu: rename amdgpu_get_block_size to amdgpu_check_block_size
Here just check if the block size is reasonable,
otherwise set it as default vaule.
The entity value should be set globally or in gmc.
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 98555fd..714be3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,7 +1039,7 @@ static bool amdgpu_check_pot_argument(int arg)
return (arg & (arg - 1)) == 0;
}
-static void amdgpu_get_block_size(struct amdgpu_device *adev)
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
{
/* defines number of bits in page table versus page directory,
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
@@ -1131,7 +1131,7 @@ static void amdgpu_check_arguments(struct amdgpu_device
*adev)
amdgpu_check_vm_size(adev);
- amdgpu_get_block_size(adev);
+ amdgpu_check_block_size(adev);
if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
!amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
--
1.9.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2 v2] drm/amdgpu: fix vm size and block size for Vega10 VMPT
From: "Zhang, Jerry" <jerry.zh...@amd.com>
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 15 ---
2 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 363d73c..98555fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1041,14 +1041,6 @@ static bool amdgpu_check_pot_argument(int arg)
static void amdgpu_get_block_size(struct amdgpu_device *adev)
{
- /* from AI, asic starts to support multiple level VMPT */
- if (adev->asic_type >= CHIP_VEGA10) {
- if (amdgpu_vm_block_size != 9)
- dev_warn(adev->dev,
-"Multi-VMPT limits block size to one page!\n");
- amdgpu_vm_block_size = 9;
- return;
- }
/* defines number of bits in page table versus page directory,
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
* page table and the remaining bits are in the page directory */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index df69aae..081a676 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -546,6 +546,14 @@ static int gmc_v9_0_sw_init(void *handle)
} else {
/* XXX Don't know how to get VRAM type yet. */
adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
+
+ /*
+* To fulfill 4-level page support,
+* vm size is 256TB (48bit), maximum size of Vega10,
+* block size 512 (9bit)
+*/
+ amdgpu_vm_size = 1U << 18;
+ amdgpu_vm_block_size = 9;
}
/* This interrupt is VMC page fault.*/
@@ -557,13 +565,6 @@ static int gmc_v9_0_sw_init(void *handle)
if (r)
return r;
- /* Because of four level VMPTs, vm size is at least 512GB.
-* The maximum size is 256TB (48bit).
-*/
- if (amdgpu_vm_size < 512) {
- DRM_WARN("VM size is at least 512GB!\n");
- amdgpu_vm_size = 512;
- }
adev->vm_manager.max_pfn = (uint64_t)amdgpu_vm_size << 18;
/* Set the internal MC address mask
--
1.9.1
___
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[PATCH 2/2] drm/amdgpu: rename amdgpu_get_block_size to amdgpu_check_block_size
Here just check if the block size is reasonable,
otherwise set it as default vaule.
The entity actual vaule should be set globally or in gmc.
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 98555fd..714be3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,7 +1039,7 @@ static bool amdgpu_check_pot_argument(int arg)
return (arg & (arg - 1)) == 0;
}
-static void amdgpu_get_block_size(struct amdgpu_device *adev)
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
{
/* defines number of bits in page table versus page directory,
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
@@ -1131,7 +1131,7 @@ static void amdgpu_check_arguments(struct amdgpu_device
*adev)
amdgpu_check_vm_size(adev);
- amdgpu_get_block_size(adev);
+ amdgpu_check_block_size(adev);
if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
!amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
--
1.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix vm pte pde flags to 640bit for sdma of CI/SI
Missing the flags fixing for CI/SI Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 6fce52f..5f90a81 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -755,8 +755,8 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(addr); ib->ptr[ib->length_dw++] = incr; /* increment size */ diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 8715de2..c570e96 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -417,8 +417,8 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); ib->ptr[ib->length_dw++] = pe; /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = value; /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(value); ib->ptr[ib->length_dw++] = incr; /* increment size */ -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdgpu: set vm size as 256TB for Vega10
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1ad1113..4af4ea0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1080,6 +1080,11 @@ static void amdgpu_get_block_size(struct amdgpu_device
*adev)
static void amdgpu_check_vm_size(struct amdgpu_device *adev)
{
+ if (adev->asic_type >= CHIP_VEGA10) {
+ amdgpu_vm_size = 1U << 18; /* 256TB */
+ return;
+ }
+
if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
amdgpu_vm_size);
--
1.9.1
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[PATCH 1/2] drm/amdgpu: create a func to check vm size
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 51 ++
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3500da3..1ad1113 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1078,6 +1078,36 @@ static void amdgpu_get_block_size(struct amdgpu_device
*adev)
}
}
+static void amdgpu_check_vm_size(struct amdgpu_device *adev)
+{
+ if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
+ dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
+amdgpu_vm_size);
+ goto def_value;
+ }
+
+ if (amdgpu_vm_size < 1) {
+ dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
+amdgpu_vm_size);
+ goto def_value;
+ }
+
+ /*
+* Max GPUVM size for Cayman, SI, CI VI are 40 bits.
+*/
+ if (amdgpu_vm_size > 1024) {
+ dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
+amdgpu_vm_size);
+ goto def_value;
+ }
+
+ return;
+
+def_value:
+ amdgpu_vm_size = 8;
+ dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
+}
+
/**
* amdgpu_check_arguments - validate module params
*
@@ -1107,26 +1137,7 @@ static void amdgpu_check_arguments(struct amdgpu_device
*adev)
}
}
- if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
- dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
-amdgpu_vm_size);
- amdgpu_vm_size = 8;
- }
-
- if (amdgpu_vm_size < 1) {
- dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
-amdgpu_vm_size);
- amdgpu_vm_size = 8;
- }
-
- /*
-* Max GPUVM size for Cayman, SI and CI are 40 bits.
-*/
- if (amdgpu_vm_size > 1024) {
- dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
-amdgpu_vm_size);
- amdgpu_vm_size = 8;
- }
+ amdgpu_check_vm_size(adev);
amdgpu_get_block_size(adev);
--
1.9.1
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[PATCH v2] drm/amdgpu: fix vm pte pde flags to 64-bit for sdma (v2)
v2: fix for all sdma engines Change-Id: I15f8f429009058ba36c7340031c9fa178d716aef Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index bcc14ed..702fa5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -804,8 +804,8 @@ static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(addr); ib->ptr[ib->length_dw++] = incr; /* increment size */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 085cf63..cfd968e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1013,8 +1013,8 @@ static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(addr); ib->ptr[ib->length_dw++] = incr; /* increment size */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index dcbef50..6cfb100 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -968,8 +968,8 @@ static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(addr); ib->ptr[ib->length_dw++] = incr; /* increment size */ -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix vm pte pde flags to 64-bit for sdma v4
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index dcbef50..6cfb100 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -968,8 +968,8 @@ static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(addr); ib->ptr[ib->length_dw++] = incr; /* increment size */ -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH libdrm v2] amdgpu: add REPLACE and CLEAR checking for VA op (v2)
v2: fix indent Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- amdgpu/amdgpu_bo.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 71cd666..850fe8c 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -952,7 +952,9 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, struct drm_amdgpu_gem_va va; int r; - if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP) + if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP && + ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR) + return -EINVAL; memset(, 0, sizeof(va)); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] amdgpu: add REPLACE and CLEAR checking for VA op
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com> --- amdgpu/amdgpu_bo.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 71cd666..8fe3cfd 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -952,7 +952,10 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, struct drm_amdgpu_gem_va va; int r; - if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP) + if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP && + ops != AMDGPU_VA_OP_REPLACE && + ops != AMDGPU_VA_OP_CLEAR) + return -EINVAL; memset(, 0, sizeof(va)); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 0/2] *** [libdrm] add REPLACE and CLEAR for VA op ***
Based on latest PRT support by Nicolai Junwei Zhang (2): amdgpu: add new VA operations CLEAR and REPLACE amdgpu: add REPLACE and CLEAR checking for VA op amdgpu/amdgpu_bo.c | 5 - include/drm/amdgpu_drm.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
