Re: [PATCH] ARM: cache-armv7: remove superfluous instruction
On Tue, Oct 08, 2019 at 04:46:28PM +0200, Ahmad Fatoum wrote: > There are two tst r11, #0xf with nothing in between them that changes > r11. This a left over from the kernel code that checks for VMSA twice, > once to check if the page table should be setup and once to more to > flush the TLB. We do the setup in the caller already, so the tst serves > no useful purpose. Delete one. > > Signed-off-by: Ahmad Fatoum > --- > arch/arm/cpu/cache-armv7.S | 1 - > 1 file changed, 1 deletion(-) Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] ARM: cache-armv7: remove superfluous instruction
There are two tst r11, #0xf with nothing in between them that changes r11. This a left over from the kernel code that checks for VMSA twice, once to check if the page table should be setup and once to more to flush the TLB. We do the setup in the caller already, so the tst serves no useful purpose. Delete one. Signed-off-by: Ahmad Fatoum --- arch/arm/cpu/cache-armv7.S | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 6a8aff8bb12c..43ec9021330e 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -7,7 +7,6 @@ ENTRY(v7_mmu_cache_on) mov r12, lr #ifdef CONFIG_MMU mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 - tst r11, #0xf @ VMSA mov r0, #0 dsb @ drain write buffer tst r11, #0xf @ VMSA -- 2.23.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
