Hi Adam,
Yes one can generate a TCL script from Vivado to automate the IPI block
regeneration very easily.
My application was to do an image processing system that uses the HBM for image
buffering and use the XDMA/QDMA to transfer data to and from the FPGA to an
NVidia Quadro GPU (For more GPGPU processing).
Since the HBM exposes about 16 AXI-HP-MM ports this makes it attractive for
image processing as different kernels can interface into the HBM at the same
time and do parallel processing in images.
That was my use case.
I had to write some XDMA kernel mode drivers to enable smooth data flow between
the NVidia Quadro GPU and the FPGA.
Xilinx provides most of the code and the XDMA/QDMA PCIe interface enables this
for memory mapped DMA bridging.
It worked very well and one couldn’t saturate the HBM bandwidth as such we
ended up reducing the HBM clock to reduce power.
This is easily configurable on the IPI HBM block.
One has to be careful though when using multiple ports of the HBM to maintain
sequential consistency.
I am sure you can also use it for DSP applications and run parallel algorithms
on the different ports of the HBM.
I used the VCU-128 not the Alveo cards as I wanted more flexibility in the FPGA
firmware to control the FPGA firmware easily without the Alveo XRT shell.
Regards,
Benjamin Hlophe
> On 05 Oct 2021, at 20:00, Adam Isaacson wrote:
>
>
> Hi Benjamin and Jack,
>
> Nice to hear from you Benjamin :). Yes, I agree that IPI is much easier to
> use than RTL. We are targeting the toolflow to generate a Block Diagram with
> the HBM integrated within it. The idea is to connect and test in Vivado first.
> Then create a tcl script based on the block diagram and then get the toolflow
> to generate the tcl script for us. We will need to parameterise our yellow
> block to be inline with the IPI generation, so that is cumbersome, but once
> it is
> finalised then it won't be too much effort - I hope!
>
> I will definitely be in touch. Thanks, Benjamin, this is useful information.
> What were you using the HBM for? Are you continually writing and reading? Are
> you using Random memory access? Are you using
> sequential memory access? How are you testing the HBM?
>
> Kind regards,
>
> Adam
>
>> On Tue, Oct 5, 2021 at 12:55 PM Jack Hickish wrote:
>> Thanks Benjamin -- I've had a look at the IPI stuff and it seems like it
>> should be straightforward to use. I just find dealing with IPI in the
>> toolflow much clunkier than RTL. But between your work and Adam/Grant's I'm
>> sure it shouldn't take too long to get something working.
>> I hadn't thought about the XDMA integration -- I don't really have a
>> requirement for that but i can think of some handy use cases. Thanks for
>> bringing it to my attention.
>>
>> Cheers
>> Jack
>>
>>> On Tue, 5 Oct 2021 at 05:41, Benjamin H Hlophe
>>> wrote:
>>> Hi Adam,
>>>
>>> I found its much easier using IP Integrator to use the HBM (It has a lot of
>>> easier configuration on IPI).
>>>
>>> I did a design connecting the HBM to PCIe on the VCU128.
>>>
>>> Without a single line of HDL code just configuring the IP Integrator and
>>> the memory map.
>>>
>>> It works very well also Xilinx has the PCIe drivers for bridging the HBM to
>>> be visible to the XDMA or QDMA.
>>>
>>> <55237d0c-db3d-4702-8e97-429a8c7e1478.png>
>>>
>>> On Vivado 2020.1 if you just make these connections and a few
>>> configurations on the HBM IP you will get it working.
>>>
>>> Regards,
>>> Benjamin Hlophe
>>>
>>>
>>>
>>>>> On 04 Oct 2021, at 22:55, Adam Isaacson wrote:
>>>>>
>>>>
>>>> Great, I will be in touch :).
>>>>
>>>> Kind regards,
>>>>
>>>> Adam
>>>>
>>>>> On Mon, 04 Oct 2021, 10:10 PM Jack Hickish, wrote:
>>>>> That would be spectacular!
>>>>>
>>>>> Thanks Adam!
>>>>>
>>>>>> On Mon, 4 Oct 2021, 21:06 Adam Isaacson, wrote:
>>>>>> Hi Jack,
>>>>>>
>>>>>> This is exactly what I have been tasked with. I have a meeting with
>>>>>> Grant Hampson (CSIRO) who has the HBM working in RTL to find out more
>>>>>> information on the 15th Oct.
>>>>>>
>>>>>> Maybe we could work together on this?
>>>>>>
>>>>>> Kind regards,
>>>>>>
>