[PATCH] D69657: [AArch64][SVE] Implement several floating-point arithmetic intrinsics
This revision was automatically updated to reflect the committed changes. Closed by commit rG5ec34dfdf733: [AArch64][SVE] Implement several floating-point arithmetic intrinsics (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69657/new/ https://reviews.llvm.org/D69657 Files: llvm/include/llvm/IR/IntrinsicsAArch64.td llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td llvm/lib/Target/AArch64/SVEInstrFormats.td llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll Index: llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll === --- /dev/null +++ llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll @@ -0,0 +1,530 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +; +; FABD +; + +define @fabd_h( %pg, %a, %b) { +; CHECK-LABEL: fabd_h: +; CHECK: fabd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fabd_s( %pg, %a, %b) { +; CHECK-LABEL: fabd_s: +; CHECK: fabd z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fabd_d( %pg, %a, %b) { +; CHECK-LABEL: fabd_d: +; CHECK: fabd z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FADD +; + +define @fadd_h( %pg, %a, %b) { +; CHECK-LABEL: fadd_h: +; CHECK: fadd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fadd_s( %pg, %a, %b) { +; CHECK-LABEL: fadd_s: +; CHECK: fadd z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fadd_d( %pg, %a, %b) { +; CHECK-LABEL: fadd_d: +; CHECK: fadd z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FDIV +; + +define @fdiv_h( %pg, %a, %b) { +; CHECK-LABEL: fdiv_h: +; CHECK: fdiv z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fdiv_s( %pg, %a, %b) { +; CHECK-LABEL: fdiv_s: +; CHECK: fdiv z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fdiv_d( %pg, %a, %b) { +; CHECK-LABEL: fdiv_d: +; CHECK: fdiv z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FDIVR +; + +define @fdivr_h( %pg, %a, %b) { +; CHECK-LABEL: fdivr_h: +; CHECK: fdivr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fdivr_s( %pg, %a, %b) { +; CHECK-LABEL: fdivr_s: +; CHECK: fdivr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv4f32( %pg, +%a, +%b) + ret %out +} + +define @fdivr_d( %pg, %a, %b) { +; CHECK-LABEL: fdivr_d: +; CHECK: fdivr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv2f64( %pg, + %a, + %b) + ret %out +} + +; +; FMAX +; + +define @fmax_h( %pg, %a, %b) { +; CHECK-LABEL: fmax_h: +; CHECK: fmax z0.h, p0/m, z0.h,
[PATCH] D69657: [AArch64][SVE] Implement several floating-point arithmetic intrinsics
kmclaughlin updated this revision to Diff 227299. kmclaughlin added a comment. - Removed duplicate //AdvSIMD_Pred2VectorArg_Intrinsic// class after rebase CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69657/new/ https://reviews.llvm.org/D69657 Files: llvm/include/llvm/IR/IntrinsicsAArch64.td llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td llvm/lib/Target/AArch64/SVEInstrFormats.td llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll Index: llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll === --- /dev/null +++ llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll @@ -0,0 +1,530 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +; +; FABD +; + +define @fabd_h( %pg, %a, %b) { +; CHECK-LABEL: fabd_h: +; CHECK: fabd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fabd_s( %pg, %a, %b) { +; CHECK-LABEL: fabd_s: +; CHECK: fabd z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fabd_d( %pg, %a, %b) { +; CHECK-LABEL: fabd_d: +; CHECK: fabd z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FADD +; + +define @fadd_h( %pg, %a, %b) { +; CHECK-LABEL: fadd_h: +; CHECK: fadd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fadd_s( %pg, %a, %b) { +; CHECK-LABEL: fadd_s: +; CHECK: fadd z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fadd_d( %pg, %a, %b) { +; CHECK-LABEL: fadd_d: +; CHECK: fadd z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FDIV +; + +define @fdiv_h( %pg, %a, %b) { +; CHECK-LABEL: fdiv_h: +; CHECK: fdiv z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fdiv_s( %pg, %a, %b) { +; CHECK-LABEL: fdiv_s: +; CHECK: fdiv z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fdiv_d( %pg, %a, %b) { +; CHECK-LABEL: fdiv_d: +; CHECK: fdiv z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FDIVR +; + +define @fdivr_h( %pg, %a, %b) { +; CHECK-LABEL: fdivr_h: +; CHECK: fdivr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fdivr_s( %pg, %a, %b) { +; CHECK-LABEL: fdivr_s: +; CHECK: fdivr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv4f32( %pg, +%a, +%b) + ret %out +} + +define @fdivr_d( %pg, %a, %b) { +; CHECK-LABEL: fdivr_d: +; CHECK: fdivr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv2f64( %pg, + %a, + %b) + ret %out +} + +; +; FMAX +; + +define @fmax_h( %pg, %a, %b) { +; CHECK-LABEL: fmax_h: +; CHECK: fmax z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fmax.nxv8f16( %pg, +
[PATCH] D69657: [AArch64][SVE] Implement several floating-point arithmetic intrinsics
sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks @kmclaughlin, LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69657/new/ https://reviews.llvm.org/D69657 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D69657: [AArch64][SVE] Implement several floating-point arithmetic intrinsics
kmclaughlin created this revision. kmclaughlin added reviewers: huntergr, sdesmalen, dancgr. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a project: LLVM. Adds intrinsics for the following: - fabd, fadd, fsub & fsubr - fmul, fmulx, fdiv & fdivr - fmax, fmaxnm, fmin & fminnm - fscale & ftsmul Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D69657 Files: llvm/include/llvm/IR/IntrinsicsAArch64.td llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td llvm/lib/Target/AArch64/SVEInstrFormats.td llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll Index: llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll === --- /dev/null +++ llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll @@ -0,0 +1,530 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +; +; FABD +; + +define @fabd_h( %pg, %a, %b) { +; CHECK-LABEL: fabd_h: +; CHECK: fabd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fabd_s( %pg, %a, %b) { +; CHECK-LABEL: fabd_s: +; CHECK: fabd z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fabd_d( %pg, %a, %b) { +; CHECK-LABEL: fabd_d: +; CHECK: fabd z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fabd.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FADD +; + +define @fadd_h( %pg, %a, %b) { +; CHECK-LABEL: fadd_h: +; CHECK: fadd z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fadd_s( %pg, %a, %b) { +; CHECK-LABEL: fadd_s: +; CHECK: fadd z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fadd_d( %pg, %a, %b) { +; CHECK-LABEL: fadd_d: +; CHECK: fadd z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fadd.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FDIV +; + +define @fdiv_h( %pg, %a, %b) { +; CHECK-LABEL: fdiv_h: +; CHECK: fdiv z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fdiv_s( %pg, %a, %b) { +; CHECK-LABEL: fdiv_s: +; CHECK: fdiv z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv4f32( %pg, + %a, + %b) + ret %out +} + +define @fdiv_d( %pg, %a, %b) { +; CHECK-LABEL: fdiv_d: +; CHECK: fdiv z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdiv.nxv2f64( %pg, +%a, +%b) + ret %out +} + +; +; FDIVR +; + +define @fdivr_h( %pg, %a, %b) { +; CHECK-LABEL: fdivr_h: +; CHECK: fdivr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv8f16( %pg, + %a, + %b) + ret %out +} + +define @fdivr_s( %pg, %a, %b) { +; CHECK-LABEL: fdivr_s: +; CHECK: fdivr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv4f32( %pg, +%a, +%b) + ret %out +} + +define @fdivr_d( %pg, %a, %b) { +; CHECK-LABEL: fdivr_d: +; CHECK: fdivr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.fdivr.nxv2f64( %pg, + %a, + %b) + ret %out +} + +; +; FMAX +; + +define @fmax_h(