[PATCH] D77205: [X86] Add TSXLDTRK instructions.

2020-04-08 Thread Xiang Zhang via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa3dc9490004c: [X86] Add TSXLDTRK instructions. (authored by 
tianqing, committed by xiangzhangllvm).

Changed prior to commit:
  https://reviews.llvm.org/D77205?vs=256170=256189#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1881,3 +1881,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10880,3 +10880,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1033,3 +1033,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -694,3 +694,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -946,3 +946,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -839,3 +839,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
+
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

2020-04-08 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.

LGTM


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205



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[PATCH] D77205: [X86] Add TSXLDTRK instructions.

2020-04-08 Thread Wang Tianqing via Phabricator via cfe-commits 
tianqing updated this revision to Diff 256170.
tianqing added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1881,3 +1881,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10880,3 +10880,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1033,3 +1033,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -694,3 +694,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -946,3 +946,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -839,3 +839,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
+
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -400,6 +400,9 @@
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
+  /// Processor supports TSXLDTRK instruction
+  bool HasTSXLDTRK = false;
+
   ///

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

2020-04-08 Thread Wang Tianqing via Phabricator via cfe-commits 
tianqing added a comment.

Can I just check it in after the rebase?


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  https://reviews.llvm.org/D77205/new/

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[PATCH] D77205: [X86] Add TSXLDTRK instructions.

2020-04-02 Thread Wang Tianqing via Phabricator via cfe-commits 
tianqing updated this revision to Diff 254693.
tianqing added a comment.

Updated to resolve conflicts with https://reviews.llvm.org/D77193.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1881,3 +1881,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10880,3 +10880,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1033,3 +1033,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -694,3 +694,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -946,3 +946,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -839,3 +839,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -400,6 +400,9 @@
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
+  /// Processor supports TSXLDTRK instruction
+  bool HasTSXLDTRK =

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

2020-04-02 Thread Wang Tianqing via Phabricator via cfe-commits 
tianqing updated this revision to Diff 254694.
tianqing added a comment.

Removed extra "//".


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1881,3 +1881,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10880,3 +10880,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1033,3 +1033,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -694,3 +694,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -946,3 +946,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -839,3 +839,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
+
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -400,6 +400,9 @@
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
+  /// Processor supports TSXLDTRK instruction
+  bool HasTSXLDTRK = false;
+
   /// Processor has a single uop BEXTR

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

2020-04-01 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205



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[PATCH] D77205: [X86] Add TSXLDTRK instructions.

2020-04-01 Thread Wang Tianqing via Phabricator via cfe-commits 
tianqing created this revision.
tianqing added reviewers: craig.topper, RKSimon, LuoYuanke.
Herald added subscribers: cfe-commits, hiraditya, mgorny.
Herald added a project: clang.

For more details about these instructions, please refer to the latest ISE 
document: 
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1877,3 +1877,9 @@
 // CHECK: enqcmds 485498096, %rax
 // CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
 enqcmds 485498096, %rax
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10876,3 +10876,9 @@
 // CHECK: enqcmds 8128(%bx,%di), %ax
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f]
 enqcmds 8128(%bx,%di), %ax
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1029,3 +1029,9 @@
 // CHECK: enqcmds (%edi), %edi
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x3f]
 enqcmds (%edi), %edi
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -691,3 +691,9 @@
 
 # CHECK: enqcmds 485498096, %rax
 0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -943,3 +943,9 @@
 
 # CHECK: enqcmds 8128(%bx,%di), %ax
 0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -836,3 +836,9 @@
 
 # CHECK: enqcmds (%edi), %edi
 0x67,0xf3,0x0f,0x38,0xf8,0x3f
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
\ No