[llvm] [clang] [Clang][SVE2.1] Add floating-point variants of `svrevd_XX` (PR #75117)

2023-12-11 Thread Momchil Velikov via cfe-commits 

https://github.com/momchil-velikov created 
https://github.com/llvm/llvm-project/pull/75117

None

>From 4fe606a2cf764ae4281789727d241c91c3cb9c39 Mon Sep 17 00:00:00 2001
From: Momchil Velikov 
Date: Mon, 11 Dec 2023 23:25:07 +
Subject: [PATCH] [Clang][SVE2.1] Add floating-point variants of `svrevd_XX`

---
 clang/include/clang/Basic/arm_sve.td  |   4 +-
 .../aarch64-sve2-intrinsics/acle_sve2_revd.c  | 193 ++
 llvm/lib/Target/AArch64/SMEInstrFormats.td|   6 +
 .../CodeGen/AArch64/sve2-intrinsics-revd.ll   |  41 
 4 files changed, 242 insertions(+), 2 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 85656c00c5b3eb..f7c8db0a262ebd 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2041,7 +2041,7 @@ def SVBFMLSLB_LANE : SInst<"svbfmlslb_lane[_{d}]", 
"dd$$i", "f", MergeNone, "aar
 def SVBFMLSLT_LANE : SInst<"svbfmlslt_lane[_{d}]", "dd$$i", "f", MergeNone, 
"aarch64_sve_bfmlslt_lane", [IsOverloadNone], [ImmCheck<3, ImmCheck0_7>]>;
 }
 
-let TargetGuard = "sve2p1" in {
+let TargetGuard = "sve2p1|sme" in {
 def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone, 
"aarch64_sve_sclamp", [], []>;
 def SVUCLAMP : SInst<"svclamp[_{d}]", "", "UcUsUiUl", MergeNone, 
"aarch64_sve_uclamp", [], []>;
 
@@ -2052,7 +2052,7 @@ def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", 
MergeNone, "", [], []>;
 
 def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
 
-defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
+defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUlbhfd", "aarch64_sve_revd">;
 }
 
 let TargetGuard = "sve2p1|sme2" in {
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c 
b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
index 9d912c5d9e2767..fa005c16763c0f 100644
--- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
@@ -388,3 +388,196 @@ svuint32_t test_svrevd_u32_x(svbool_t pg, svuint32_t op) {
 svuint64_t test_svrevd_u64_x(svbool_t pg, svuint64_t op) {
   return SVE_ACLE_FUNC(svrevd, _u64, _x, )(pg, op);
 }
+
+
+// CHECK-LABEL: @test_svrevd_bf16_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8bf16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svrevd_bf16_zu10__SVBool_tu14__SVBfloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8bf16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svbfloat16_t test_svrevd_bf16_z(svbool_t pg, svbfloat16_t op) {
+  return SVE_ACLE_FUNC(svrevd, _bf16, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f16_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8f16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_f16_zu10__SVBool_tu13__SVFloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8f16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svfloat16_t test_svrevd_f16_z(svbool_t pg, svfloat16_t op) {
+  return SVE_ACLE_FUNC(svrevd, _f16, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f32_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv4f32( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_f32_zu10__SVBool_tu13__SVFloat32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv4f32( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svfloat32_t test_svrevd_f32_z(svbool_t pg, svfloat32_t op) {
+  return SVE_ACLE_FUNC(svrevd, _f32, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f64_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.

[llvm] [clang] [Clang][SVE2.1] Add floating-point variants of `svrevd_XX` (PR #75117)

2023-12-11 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Momchil Velikov (momchil-velikov)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/75117.diff


4 Files Affected:

- (modified) clang/include/clang/Basic/arm_sve.td (+2-2) 
- (modified) clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c (+193) 
- (modified) llvm/lib/Target/AArch64/SMEInstrFormats.td (+6) 
- (modified) llvm/test/CodeGen/AArch64/sve2-intrinsics-revd.ll (+41) 


``diff
diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 85656c00c5b3eb..f7c8db0a262ebd 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2041,7 +2041,7 @@ def SVBFMLSLB_LANE : SInst<"svbfmlslb_lane[_{d}]", 
"dd$$i", "f", MergeNone, "aar
 def SVBFMLSLT_LANE : SInst<"svbfmlslt_lane[_{d}]", "dd$$i", "f", MergeNone, 
"aarch64_sve_bfmlslt_lane", [IsOverloadNone], [ImmCheck<3, ImmCheck0_7>]>;
 }
 
-let TargetGuard = "sve2p1" in {
+let TargetGuard = "sve2p1|sme" in {
 def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone, 
"aarch64_sve_sclamp", [], []>;
 def SVUCLAMP : SInst<"svclamp[_{d}]", "", "UcUsUiUl", MergeNone, 
"aarch64_sve_uclamp", [], []>;
 
@@ -2052,7 +2052,7 @@ def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", 
MergeNone, "", [], []>;
 
 def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
 
-defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
+defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUlbhfd", "aarch64_sve_revd">;
 }
 
 let TargetGuard = "sve2p1|sme2" in {
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c 
b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
index 9d912c5d9e2767..fa005c16763c0f 100644
--- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
@@ -388,3 +388,196 @@ svuint32_t test_svrevd_u32_x(svbool_t pg, svuint32_t op) {
 svuint64_t test_svrevd_u64_x(svbool_t pg, svuint64_t op) {
   return SVE_ACLE_FUNC(svrevd, _u64, _x, )(pg, op);
 }
+
+
+// CHECK-LABEL: @test_svrevd_bf16_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8bf16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svrevd_bf16_zu10__SVBool_tu14__SVBfloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8bf16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svbfloat16_t test_svrevd_bf16_z(svbool_t pg, svbfloat16_t op) {
+  return SVE_ACLE_FUNC(svrevd, _bf16, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f16_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8f16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_f16_zu10__SVBool_tu13__SVFloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8f16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svfloat16_t test_svrevd_f16_z(svbool_t pg, svfloat16_t op) {
+  return SVE_ACLE_FUNC(svrevd, _f16, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f32_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv4f32( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_f32_zu10__SVBool_tu13__SVFloat32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv4f32( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svfloat32_t test_svrevd_f32_z(svbool_t pg, svfloat32_t op) {
+  return SVE_ACLE_FUNC(svrevd, _f32, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f64_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv2f64( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_s

[llvm] [clang] [Clang][SVE2.1] Add floating-point variants of `svrevd_XX` (PR #75117)

2023-12-12 Thread via cfe-commits 

https://github.com/CarolineConcatto approved this pull request.

Thank you Momchil!

https://github.com/llvm/llvm-project/pull/75117
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [Clang][SVE2.1] Add floating-point variants of `svrevd_XX` (PR #75117)

2023-12-18 Thread Momchil Velikov via cfe-commits 

https://github.com/momchil-velikov updated 
https://github.com/llvm/llvm-project/pull/75117

>From 979b240d2a084eb87db43d3fabfffa8d3351d294 Mon Sep 17 00:00:00 2001
From: Momchil Velikov 
Date: Mon, 11 Dec 2023 23:25:07 +
Subject: [PATCH 1/2] [Clang][SVE2.1] Add floating-point variants of
 `svrevd_XX`

---
 clang/include/clang/Basic/arm_sve.td  |   4 +-
 .../aarch64-sve2-intrinsics/acle_sve2_revd.c  | 193 ++
 llvm/lib/Target/AArch64/SMEInstrFormats.td|   6 +
 .../CodeGen/AArch64/sve2-intrinsics-revd.ll   |  41 
 4 files changed, 242 insertions(+), 2 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index a429a3c5fe378a..cbc2af73d6052e 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2077,11 +2077,11 @@ def SVBFMLSLB_LANE : SInst<"svbfmlslb_lane[_{d}]", 
"dd$$i", "f", MergeNone, "aar
 def SVBFMLSLT_LANE : SInst<"svbfmlslt_lane[_{d}]", "dd$$i", "f", MergeNone, 
"aarch64_sve_bfmlslt_lane", [IsOverloadNone], [ImmCheck<3, ImmCheck0_7>]>;
 }
 
-let TargetGuard = "sve2p1" in {
+let TargetGuard = "sve2p1|sme" in {
 def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone, 
"aarch64_sve_sclamp", [], []>;
 def SVUCLAMP : SInst<"svclamp[_{d}]", "", "UcUsUiUl", MergeNone, 
"aarch64_sve_uclamp", [], []>;
 
-defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
+defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUlbhfd", "aarch64_sve_revd">;
 }
 
 let TargetGuard = "sve2p1|sme2" in {
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c 
b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
index 9d912c5d9e2767..fa005c16763c0f 100644
--- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
@@ -388,3 +388,196 @@ svuint32_t test_svrevd_u32_x(svbool_t pg, svuint32_t op) {
 svuint64_t test_svrevd_u64_x(svbool_t pg, svuint64_t op) {
   return SVE_ACLE_FUNC(svrevd, _u64, _x, )(pg, op);
 }
+
+
+// CHECK-LABEL: @test_svrevd_bf16_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8bf16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svrevd_bf16_zu10__SVBool_tu14__SVBfloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8bf16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svbfloat16_t test_svrevd_bf16_z(svbool_t pg, svbfloat16_t op) {
+  return SVE_ACLE_FUNC(svrevd, _bf16, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f16_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8f16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_f16_zu10__SVBool_tu13__SVFloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8f16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svfloat16_t test_svrevd_f16_z(svbool_t pg, svfloat16_t op) {
+  return SVE_ACLE_FUNC(svrevd, _f16, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f32_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv4f32( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_f32_zu10__SVBool_tu13__SVFloat32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv4f32( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svfloat32_t test_svrevd_f32_z(svbool_t pg, svfloat32_t op) {
+  return SVE_ACLE_FUNC(svrevd, _f32, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_f64_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv2f64( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_f64_zu10__SVBool_tu13__SVFloat64_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@ll

[llvm] [clang] [Clang][SVE2.1] Add floating-point variants of `svrevd_XX` (PR #75117)

2023-12-18 Thread Momchil Velikov via cfe-commits 

https://github.com/momchil-velikov closed 
https://github.com/llvm/llvm-project/pull/75117
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits