[coreboot] Asus F2-A85M rom
dear humans, can anybody provide me a working rom for the F2-A85M with SeaBios? greetings the kinky nekoboi -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] fsp_broadwell_de: USB keyboard and mouse doesn't work.
Dear coreboot developers: I am trying to create CB firmware for Broadwell-D 1559 system using CamelBack Mountain CRB as mainboard selection, and the system boots Windows and Linux operating systems but USB keyboard and mouse doesn't work. I already enable/disabled EHCI/xHCI devices in devicetree without success. I tried Seabios and Tianocore without success. Anyone had experience this issue? Any advise will be appreciated. Thank you, Jose Trujillo.-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] More ACPI errors on Lenovo X201i
Hi Patrick, I found new ACPI errors on my Lenovo X201i: commit "60eca531df ec/lenovo/h8/acpi: Add WWAN ACPI methods" introduces the following error just before shutdown: thinkpad_acpi_ acpi_evalf(\WGSV, vd, ...) failed: AE_NOT_FOUND and commit "31fb846c59 ec/lenovo/h8/acpi: Apply state on wake" introduces the following errors on boot: ACPI Error: No handler for Region [ERAM] ((ptrval)) [EmbeddedControl] (20180313/evregion-132) ACPI Error: Region EmbeddedControl (ID=3) has no handler (20180313/exfldio-265) ACPI Error: Method parse/execution failed \_SB.PCI0.LPCB.EC.HKEY._INI, AE_NOT_EXIST (20180313/psparse-516) ACPI Error: AE_NOT_EXIST, during \_SB.PCI0.LPCB.EC.HKEY._INI execution (20180313/nsinit-670) Cheers, Matthias -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] USB to Serial Converters
On Sun, Jul 22, 2018 at 11:50 PM, zahra rahimkhani wrote: > Thank you very much. > I compiled coreboot and seabios and got Microcode and Fsp on it. > But I did not have output on serial port. > Could you tell me How set menuconfig that see outpot on serial port. > Thanks, It would be helpful if you can upload your .config somewhere such as paste.flashrom.org. My guess is that you don't have CONFIG_ENABLE_BUILTIN_COM1 selected (under "Chipset"), which is an option you have to set in addition to the stuff under "Console." > > On Mon, Jul 23, 2018 at 10:58 AM David Hendricks > wrote: >> >> Hi Zahra, >> >> On Mon, Jul 23, 2018 at 4:49 AM, zahra rahimkhani >> wrote: >> > Dear friends >> > >> > I compile seaBios and coreboot for Minnowboard max . >> > but I do not see output on Serial port . >> > >> > Does coreboot support USB to Serial Converters ? >> > or how do I add this feature ? >> >> The Minnowboard Max serial port does not go thru a USB to serial >> converter. However, you may need to enable some config options. >> Compare a sample config.txt from the supported mainboards page >> (https://coreboot.org/status/board-status.html) to your .config file >> to see if there is anything obviously missing. >> >> Also, do you have the microcode files from Intel? If not, you can >> download them from >> https://downloadmirror.intel.com/25063/eng/Baytrail_FSP_Gold4.tgz. >> >> >> > >> > Thanks , >> > >> > >> > -- >> > coreboot mailing list: coreboot@coreboot.org >> > https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] fsp_broadwell_de: USB keyboard and mouse doesn't work.
Hello Jose, On Mon, Jul 23, 2018 at 5:23 AM, Jose Trujillo via coreboot wrote: > Dear coreboot developers: > > I am trying to create CB firmware for Broadwell-D 1559 system using > CamelBack Mountain CRB as mainboard selection, and the system boots Windows > and Linux operating systems but USB keyboard and mouse doesn't work. > > I already enable/disabled EHCI/xHCI devices in devicetree without success. > I tried Seabios and Tianocore without success. > > Anyone had experience this issue? EHCI support may need to be enabled in FSP. What version of coreboot are you using? I added a Kconfig option to enable the EHCI controllers using UPD values: https://review.coreboot.org/c/coreboot/+/26042 > Any advise will be appreciated. > Thank you, > Jose Trujillo. > > -- > coreboot mailing list: coreboot@coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Doubts about link scripts
I try to read link scripts of coreboot. In addition to the x86 platform, code segments and data segments are contiguous during the bootblock/romstage phase. However, only CAR/SRAM can be used as memory in the bootblock/romstage stage, this should be separate from the flash where the program is located. Why this is not reflected in the link script? Does the machine have a special mechanism ? Looking forward to your reply !!! WangXiang-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot