Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
controller found in the MSM8x60 and IPQ/APQ8064 platforms.
The ADM supports both memory to memory transactions and memory
to/from peripheral device transactions. The controller also provides flow
control capabilities for transactions to/from peripheral devices.
The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.
Signed-off-by: Andy Gross
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile |1 +
drivers/dma/qcom_adm.c | 902
3 files changed, 913 insertions(+)
create mode 100644 drivers/dma/qcom_adm.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f2b2c4e..69bc15e 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -464,4 +464,14 @@ config QCOM_BAM_DMA
Enable support for the QCOM BAM DMA controller. This controller
provides DMA capabilities for a variety of on-chip devices.
+config QCOM_ADM
+ tristate "Qualcomm ADM support"
+ depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ ---help---
+ Enable support for the Qualcomm ADM DMA controller. This controller
+ provides DMA capabilities for both general purpose and on-chip
+ peripheral devices.
+
endif
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 2022b54..3b7ead6 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -50,3 +50,4 @@ obj-y += xilinx/
obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
+obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
diff --git a/drivers/dma/qcom_adm.c b/drivers/dma/qcom_adm.c
new file mode 100644
index 000..7381c38
--- /dev/null
+++ b/drivers/dma/qcom_adm.c
@@ -0,0 +1,902 @@
+/*
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dmaengine.h"
+#include "virt-dma.h"
+
+/* ADM registers - calculated from channel number and security domain */
+#define HI_CH_CMD_PTR(chan, ee)(4*chan + 0x20800*ee)
+#define HI_CH_RSLT(chan, ee) (0x40 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE0(chan, ee) (0x80 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE1(chan, ee) (0xc0 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE2(chan, ee) (0x100 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE3(chan, ee) (0x140 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE4(chan, ee) (0x180 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE5(chan, ee) (0x1c0 + 4*chan + 0x20800*ee)
+#define HI_CH_STATUS_SD(chan, ee) (0x200 + 4*chan + 0x20800*ee)
+#define HI_CH_CONF(chan) (0x240 + 4*chan)
+#define HI_CH_RSLT_CONF(chan, ee) (0x300 + 4*chan + 0x20800*ee)
+#define HI_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + 0x20800*ee)
+#define HI_CI_CONF(ci) (0x390 + 4*ci)
+#define HI_CRCI_CONF0 0x3d0
+#define HI_CRCI_CONF1 0x3d4
+#define HI_GP_CTL 0x3d8
+#define HI_CRCI_CTL(crci, ee) (0x400 + 0x4*crci + 0x20800*ee)
+
+/* channel status */
+#define CH_STATUS_VALIDBIT(1)
+
+/* channel result */
+#define CH_RSLT_VALID BIT(31)
+#define CH_RSLT_ERRBIT(3)
+#define CH_RSLT_FLUSH BIT(2)
+#define CH_RSLT_TPDBIT(1)
+
+/* channel conf */
+#define CH_CONF_MPU_DISABLEBIT(11)
+#define CH_CONF_PERM_MPU_CONF BIT(9)
+#define CH_CONF_FLUSH_RSLT_EN BIT(8)
+#define CH_CONF_FORCE_RSLT_EN BIT(7)
+#define CH_CONF_IRQ_EN BIT(6)
+
+/* channel result conf */
+#define CH_RSLT_CONF_FLUSH_EN BIT(1)
+#define CH_RSLT_CONF_IRQ_ENBIT(0)
+
+/* CRCI CTL */
+#define CRCI_CTL_MUX_SEL BIT(18)
+#define CRCI_CTL_RST BIT(17)
+
+/* CI configuration */
+#define CI_RANGE_END(x)(x << 24)
+#define CI_RANGE_START(x) (x << 16)
+#define CI_BURST_4_WORDS 0x4
+#define CI_BURST_8_WORDS 0x8
+
+/* GP CTL */
+#define GP_CTL_LP_EN BIT(12)
+#define GP_CTL_LP_CNT(x) (x << 8)
+
+/* Command pointer list entry */
+#define CPLE_LPBIT(31)
+#define CPLE_CMD_PTR_LIST BIT(29)
+
+/* Command list entry */
+#def
