[Bug 62997] Crashes on ARUBA unless R600_DEBUG=nodma
https://bugs.freedesktop.org/show_bug.cgi?id=62997 --- Comment #5 from udo --- It does crash, but without reboot. Gui disappears. Pure text mode screne is shown of first few seconds of boot. No network. Kernel alive. Apr 7 07:59:47 surfplank2 dbus[3118]: [system] Rejected send message, 2 matched rules; type="method_return", sender=":1.2" (uid=0 pid=3090 comm="/usr/lib/systemd/systemd-logind ") interface="(unset)" member ="(unset)" error name="(unset)" requested_reply="0" destination=":1.34" (uid=500 pid=4127 comm="gnome-session ") Apr 7 08:11:39 surfplank2 kernel: [406000.278385] radeon :00:01.0: GPU fault detected: 147 0x0f727102 Apr 7 08:11:39 surfplank2 kernel: [406000.278390] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x18F7 Apr 7 08:11:39 surfplank2 kernel: [406000.278393] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x02071002 Apr 7 08:11:39 surfplank2 kernel: [406000.278396] radeon :00:01.0: GPU fault detected: 147 0x0f627102 Apr 7 08:11:39 surfplank2 kernel: [406000.278399] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x Apr 7 08:11:39 surfplank2 kernel: [406000.278401] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x Apr 7 08:11:39 surfplank2 kernel: [406000.278404] radeon :00:01.0: GPU fault detected: 147 0x07527102 Apr 7 08:11:39 surfplank2 kernel: [406000.278406] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x Apr 7 08:11:39 surfplank2 kernel: [406000.278409] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x Apr 7 08:11:39 surfplank2 kernel: [406000.278411] radeon :00:01.0: GPU fault detected: 147 0x07627102 Apr 7 08:11:39 surfplank2 kernel: [406000.278413] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x Apr 7 08:11:39 surfplank2 kernel: [406000.278416] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x Apr 7 08:11:39 surfplank2 kernel: [406000.278418] radeon :00:01.0: GPU fault detected: 147 0x00a27102 Apr 7 08:11:39 surfplank2 kernel: [406000.278420] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x Apr 7 08:11:39 surfplank2 kernel: [406000.278423] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x Apr 7 08:11:39 surfplank2 kernel: [406000.278426] radeon :00:01.0: GPU fault detected: 147 0x00a27102 Apr 7 08:11:39 surfplank2 kernel: [406000.278428] radeon :00:01.0: VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x00Apr 7 08:17:11 surfplank2 kernel: imklog 5.8.10, log source = /proc/kmsg started. Apr 7 08:17:11 surfplank2 rsyslogd: [origin software="rsyslogd" swVersion="5.8.10" x-pid="3041" x-info="http://www.rsyslog.com";] start -- You are receiving this mail because: You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drivers/gpu/drm/nouveau: remove erroneous semicolon
On Sun, 2013-04-07 at 11:57 +0800, Chen Gang wrote: > On 2013年04月07日 11:49, Greg KH wrote: > > On Sun, Apr 07, 2013 at 09:03:55AM +0800, Chen Gang wrote: > >> Hello Greg KH: > >> when you have time, can you help to check this patch whether OK ? > > No. > Why ? does it also need a test ?? Greg's not the nouveau maintainer/babysitter and likely doesn't have the time/hardware/desire to test it. The patch should be simply be sent to David Airlie and dri-devel. It is a pretty obvious typo though. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drivers/gpu/drm/nouveau: remove erroneous semicolon
On Sun, 2013-04-07 at 11:57 +0800, Chen Gang wrote: > On 2013?04?07? 11:49, Greg KH wrote: > > On Sun, Apr 07, 2013 at 09:03:55AM +0800, Chen Gang wrote: > >> Hello Greg KH: > >> when you have time, can you help to check this patch whether OK ? > > No. > Why ? does it also need a test ?? Greg's not the nouveau maintainer/babysitter and likely doesn't have the time/hardware/desire to test it. The patch should be simply be sent to David Airlie and dri-devel. It is a pretty obvious typo though.
[PATCH] drivers/gpu/drm/nouveau: remove erroneous semicolon
On Sun, Apr 07, 2013 at 09:03:55AM +0800, Chen Gang wrote: > Hello Greg KH: > > when you have time, can you help to check this patch whether OK ? No.
drm/nouveau: Possible hardware corruption of older GeForce card
On Sat Mar 23 11:40:32 +1000, Ben Skeggs wrote: > On Fri, 2013-03-22 at 14:54 -0500, Calvin Owens wrote: > > On 03/21/13 02:56, Calvin Owens wrote: > > > On 03/21/13 02:24, Calvin Owens wrote: > > >> On 03/21/13 01:59, Ben Skeggs wrote: > > >>> On Thu, 2013-03-21 at 01:34 -0500, Calvin Owens wrote: > > DRM hasn't worked on my desktop machine (GeForce 9800) with Nouveau for > > a little while (v3.9-rc1 didn't), but worked as of commit e204378 on > > Linus' tree for one boot, and subsequently always fails. > > > > After running that version, v3.6, which has always worked in the past, > > also fails, which is obviously somewhat troubling. > > > > The card will POST, but when modesetting tries to happen, errors result > > and the console remains in VGA mode. On a second computer (on which I > > have also used this card in the past), I now get the same "PRAMIN > > readback failed" error and no DRM console. > > > > I don't want to get ahead of myself, since I have no idea what exactly > > is happening, but it certainly appears that booting e204378 somehow > > changed something on the hardware that is preventing nouveau > > modesetting > > from being successful in that and previous vesrions of the kernel. > > > > I was going to add debugging output from the nouveau tree HEAD, but it > > locks the machine hard with strange visual artifacts. Any other info I > > can provide? Any idea where I should start digging? > > > > Thanks, > > Calvin Owens > > > > (e204378 just happened to be HEAD when I pulled from Linus' tree; I > > can't narrow it down to something in Nouveau or DRM since I don't yet > > know how to undo the apparent hardware alteration) > > >>> Does doing a complete cold boot fix things temporarily until you run > > >>> with that revision again, or, is it of a permanent nature? > > >> No, it seems to be permanent. > > >> > > >>> If it's the latter, it sounds more like the hw (specifically, the ram > > >>> chips) is dying honestly... > > >> > > >> Is there some way to test that? The suddenness of it is what made me > > >> discount the possibility that the chip is dying - I've used this card > > >> almost daily for years in that desktop, so I would've expected > > >> intermittent failures rather than a sudden cutoff... but you could be > > >> right. > > >> > > > > > > Just noticed this: the semicolon fixed below causes > > > nv50_display_flip_stop to return immediately instead of waiting for the > > > memory writes to appear, which may be the cause of some of those > > > DMA-related errors I was seeing. (I'll resend the patch separately) > > > > > > diff --git a/drivers/gpu/drm/nouveau/nv50_display.c > > > b/drivers/gpu/drm/nouveau/nv50_display.c > > > index 2db5799..96bc2f3 100644 > > > --- a/drivers/gpu/drm/nouveau/nv50_display.c > > > +++ b/drivers/gpu/drm/nouveau/nv50_display.c > > > @@ -479,7 +479,7 @@ nv50_display_flip_wait(void *data) > > > { > > > struct nv50_display_flip *flip = data; > > > if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == > > > - flip->chan->data); > > > + flip->chan->data) > > > return true; > > > usleep_range(1, 2); > > > return false; > > > > > > > I hope this whole thing doesn't seem to melodramatic... my thinking was > > simply > > that, given that MTBF's of video cards tend to be quoted in the 5+ year > > range, > > the probability of one dying in the 2-hour window between my rebooting with > > that > > kernel version had to be extremely low. It seemed as though the null > > hypothesis > > was rather certainly disproven. > The symptoms you describe certainly indicate a failing RAM chip (or > multiple). Kernels prior to 3.7 allocated important structures at the > start of VRAM, and now are detecting a failure far earlier in the boot > process. Later kernels get further because these structures are now at > the end of VRAM, but, ultimately still fail eventually once the bad VRAM > is used. > > I can't think of any changes in nouveau that could have possibly caused > permanent damage to your board, and I've never caused any to my own > boards even with *loads* of random poking to reverse-engineer them in > the first place. So, this possibility also seems highly unlikely to me. > > > > > Is this worth pursuing? I can try to find an identical card and see if it > > happens again... but if you're convinced it's a non-issue, I'll just forget > > about it. > I think it's *more than likely* a non-issue, but it would be nice to be > 100% sure... > > Thanks, > Ben. I've not been able to find an identical card (except on Ebay selling for more than I paid for it in 2008...); however, with the patch I sent on 3/21 applied, I can occasionally get the card to boot with a corrupted screen: http://http.snarkywidgets.com/screen.pn
[Bug 62756] Rendering errors on rv790 with llvm and unigine heaven 3.0
https://bugs.freedesktop.org/show_bug.cgi?id=62756 --- Comment #12 from Andy Furniss --- (In reply to comment #11) > Created attachment 77534 [details] [review] > native inst support for mesa > > Sorry, I didn't notice that mesa didn't translate native instruction for > r700. > You'll need this patch, as well as the previous one ; it should fix the big > regression. Can you confirm this ? Yes, this fixes the big regression and I also no longer see the original regression. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20130406/40760153/attachment-0001.html>
BUG: kworker hangs the GPU on drm and i915 since 3.8.x under X11
Thanks for all your efforts. It is really fun to see such an immediate response. Daniel Vetter wrote: >On Sat, Apr 6, 2013 at 6:24 PM, George Amanakis >wrote: >> Indeed, I set explicitly drm_kms_helper.poll=0 since 2.35.x. See here: >> http://souriguha.wordpress.com/2011/03/08/how-to-solve-problem-with-thinkpadkslowd-kworker-on-linux-kernel-2-35-2-36/ >> >> Mouse and keyboard freezes intermittently some time after boot up. Actually >> the problem has to do with the GPU lagging and displaying the changes later. >> This results in an almost unusable desktop environment. Top will report the >> high CPU usage by 3-4 processes named kworker. With the >> drm_kms_helper.poll=0 it was until the 3.8.x kernel resolved. >> >> Since the 3.8.x kernels the exact same problem appeared again. The problem >> persists with the latest 3.9-rc5 too. > >Ah, so it seems to be a plain hpd irq storm (since you have massive >cpu loads), not edid readings taking forever (which would still cause >the mouse to lag horribly on 3.8 and earlier, but without cpu load). >The edid reading issues should be fixed in 3.9. For hpd irq storms >Egbert Eich from Suse is working on some patches to mitigate this. >Infrastructure prep work is already merged for 3.10, hopefully we can >merge the actual mitigation logic, too. > >I'll try no to forget to ping you once it's merged, so that you can >test it a bit. > >Cheers, Daniel >-- >Daniel Vetter >Software Engineer, Intel Corporation >+41 (0) 79 365 57 48 - http://blog.ffwll.ch
BUG: kworker hangs the GPU on drm and i915 since 3.8.x under X11
On Sat, Apr 6, 2013 at 6:24 PM, George Amanakis wrote: > Indeed, I set explicitly drm_kms_helper.poll=0 since 2.35.x. See here: > http://souriguha.wordpress.com/2011/03/08/how-to-solve-problem-with-thinkpadkslowd-kworker-on-linux-kernel-2-35-2-36/ > > Mouse and keyboard freezes intermittently some time after boot up. Actually > the problem has to do with the GPU lagging and displaying the changes later. > This results in an almost unusable desktop environment. Top will report the > high CPU usage by 3-4 processes named kworker. With the > drm_kms_helper.poll=0 it was until the 3.8.x kernel resolved. > > Since the 3.8.x kernels the exact same problem appeared again. The problem > persists with the latest 3.9-rc5 too. Ah, so it seems to be a plain hpd irq storm (since you have massive cpu loads), not edid readings taking forever (which would still cause the mouse to lag horribly on 3.8 and earlier, but without cpu load). The edid reading issues should be fixed in 3.9. For hpd irq storms Egbert Eich from Suse is working on some patches to mitigate this. Infrastructure prep work is already merged for 3.10, hopefully we can merge the actual mitigation logic, too. I'll try no to forget to ping you once it's merged, so that you can test it a bit. Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
[PATCH] drm/kms-helper: disable hpd_irq handling when poll=0
When inlining the actual hpd output probing in commit 69787f7da6b2adc4054357a661aaa1701a9ca76f Author: Daniel Vetter Date: Tue Oct 23 18:23:34 2012 + drm: run the hpd irq event code directly the check for the drm_kms_hlper.poll module option was lost. This regressed systems where this option is used to work-around output probing issues (like irq storms). Restore the old behaviour. Reported-by: George Amanakis Cc: George Amanakis Cc: Dave Airlie Cc: stable at vger.kernel.org (for 3.8) Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc_helper.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 7b2d378..3260736 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -1067,7 +1067,7 @@ void drm_helper_hpd_irq_event(struct drm_device *dev) enum drm_connector_status old_status; bool changed = false; - if (!dev->mode_config.poll_enabled) + if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll) return; mutex_lock(&dev->mode_config.mutex); -- 1.7.10.4
[PATCH 1/1] drm: Add 1600x1200 (UXGA) screen resolution to the built-in EDIDs
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[PATCH 0/1] drm: Add built-in EDID set of another common screen resolution
Several users were complaining that 1600x1200 screen resolution was lacking. Here is it. -Carsten.
Re: [PATCH 1/1] drm: Add 1600x1200 (UXGA) screen resolution to the built-in EDIDs
Dear Carsten, thank you for the patch. Am Samstag, den 06.04.2013, 18:01 +0200 schrieb Carsten Emde: > The 1600x1200 (UXGA) screen resolution was lacking in the set of > built-in selectable EDID screen resolutions that can be used to > repair misbehaving monitor firmware. > > This patch adds the related data set and expands the documentation. > > Signed-off-by: Carsten Emde > > --- > Documentation/EDID/1600x1200.S | 44 > > Documentation/EDID/HOWTO.txt| 12 +- > drivers/gpu/drm/drm_edid_load.c | 21 ++- > 3 files changed, 70 insertions(+), 7 deletions(-) Acked-by: Paul Menzel Thanks, Paul signature.asc Description: This is a digitally signed message part ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
BUG: kworker hangs the GPU on drm and i915 since 3.8.x under X11
On Sat, Apr 6, 2013 at 12:01 AM, George Amanakis wrote: > I mean that I can type, move the mouse pointer, open new windows but there > is a lag until these changes are displayed. Stuttering like. > > I ended up not reverting the aforementioned commit but modifying it. This > also solves the issue. Here is the patch: Indeed, the commit you've bisected too accidentally removed this check. I'll submit a patch.So I guess you've explicitly set drm_kms_helper.poll=0. Can you please elaborate what you're working around with this option? Any such case is a bug. Also, can you please test latest 3.9-rc kernels (without your patch, i.e. a broken configuration)? It contains some rework to make hpd detection less intrusive for normal desktop activity and should also greatly help for your case here. Thanks, Daniel > > diff -rupN a/drivers/gpu/drm/drm_crtc_helper.c > b/drivers/gpu/drm/drm_crtc_helper.c > --- a/drivers/gpu/drm/drm_crtc_helper.c2013-02-19 00:58:34.0 > +0100 > +++ b/drivers/gpu/drm/drm_crtc_helper.c2013-04-05 23:10:36.454936677 > +0200 > @@ -1067,7 +1067,7 @@ void drm_helper_hpd_irq_event(struct drm > enum drm_connector_status old_status; > bool changed = false; > > -if (!dev->mode_config.poll_enabled) > +if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll) > return; > > mutex_lock(&dev->mode_config.mutex); > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
Re: [PATCH 0/1] drm: Add built-in EDID set of another common screen resolution
Wow!!! I have been awaiting for this! I'm now working with my monitor at 1600x1200 flawlessly. Thank you so much, Carsten! I hope that everything goes fine and will finally arrive to the mainstream. There is a bunch of users with vintage CRTs and pre-wide-era TFTs for whom this patch may be useful. Jacobo ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 62756] Rendering errors on rv790 with llvm and unigine heaven 3.0
https://bugs.freedesktop.org/show_bug.cgi?id=62756 --- Comment #11 from vincent --- Created attachment 77534 --> https://bugs.freedesktop.org/attachment.cgi?id=77534&action=edit native inst support for mesa Sorry, I didn't notice that mesa didn't translate native instruction for r700. You'll need this patch, as well as the previous one ; it should fix the big regression. Can you confirm this ? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20130406/9a201d01/attachment.html>
[PATCH 02/11] drm/radeon: rework fallback handling
Am 06.04.2013 15:24, schrieb Christian K?nig: > From: Christian K?nig > > Let the CS module decide if we can fall back to VRAM or not. > > Signed-off-by: Christian K?nig Crap, just seen another typo in this patch. Going to resend a v2 of it soon. Christian. > --- > drivers/gpu/drm/radeon/radeon.h|5 ++-- > drivers/gpu/drm/radeon/radeon_cs.c | 51 > ++-- > drivers/gpu/drm/radeon/radeon_object.c |8 ++--- > 3 files changed, 36 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h > index 8263af3..7c2498c 100644 > --- a/drivers/gpu/drm/radeon/radeon.h > +++ b/drivers/gpu/drm/radeon/radeon.h > @@ -357,8 +357,9 @@ struct radeon_bo_list { > struct ttm_validate_buffer tv; > struct radeon_bo*bo; > uint64_tgpu_offset; > - unsignedrdomain; > - unsignedwdomain; > + boolwritten; > + unsigneddomain; > + unsignedalt_domain; > u32 tiling_flags; > }; > > diff --git a/drivers/gpu/drm/radeon/radeon_cs.c > b/drivers/gpu/drm/radeon/radeon_cs.c > index a3dd04d..8223cf8 100644 > --- a/drivers/gpu/drm/radeon/radeon_cs.c > +++ b/drivers/gpu/drm/radeon/radeon_cs.c > @@ -53,6 +53,7 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser > *p) > } > for (i = 0; i < p->nrelocs; i++) { > struct drm_radeon_cs_reloc *r; > + uint32_t domain; > > duplicate = false; > r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; > @@ -63,30 +64,36 @@ static int radeon_cs_parser_relocs(struct > radeon_cs_parser *p) > break; > } > } > - if (!duplicate) { > - p->relocs[i].gobj = drm_gem_object_lookup(ddev, > - p->filp, > - r->handle); > - if (p->relocs[i].gobj == NULL) { > - DRM_ERROR("gem object lookup failed 0x%x\n", > - r->handle); > - return -ENOENT; > - } > - p->relocs_ptr[i] = &p->relocs[i]; > - p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); > - p->relocs[i].lobj.bo = p->relocs[i].robj; > - p->relocs[i].lobj.wdomain = r->write_domain; > - p->relocs[i].lobj.rdomain = r->read_domains; > - p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; > - p->relocs[i].handle = r->handle; > - p->relocs[i].flags = r->flags; > - radeon_bo_list_add_object(&p->relocs[i].lobj, > - &p->validated); > - > - } else > + if (duplicate) { > p->relocs[i].handle = 0; > + continue; > + } > + > + p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, > + r->handle); > + if (p->relocs[i].gobj == NULL) { > + DRM_ERROR("gem object lookup failed 0x%x\n", > + r->handle); > + return -ENOENT; > + } > + p->relocs_ptr[i] = &p->relocs[i]; > + p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); > + p->relocs[i].lobj.bo = p->relocs[i].robj; > + p->relocs[i].lobj.written = !!r->write_domain; > + > + domain = r->write_domain ? r->write_domain : r->read_domains; > + p->relocs[i].lobj.domain = domain; > + if (domain == RADEON_GEM_DOMAIN_VRAM) > + domain |= RADEON_GEM_DOMAIN_GTT; > + p->relocs[i].lobj.alt_domain = domain; > + > + p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; > + p->relocs[i].handle = r->handle; > + > + radeon_bo_list_add_object(&p->relocs[i].lobj, > + &p->validated); > } > - return radeon_bo_list_validate(&p->validated); > + return radeon_bo_list_validate(&p->validated, p->ring); > } > > static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 > priority) > diff --git a/drivers/gpu/drm/radeon/radeon_object.c > b/drivers/gpu/drm/radeon/radeon_object.c > index d3aface..9633325 100644 > --- a/drivers/gpu/drm/radeon/radeon_object.c > +++ b/drivers/gpu/drm/radeon/radeon_object.c > @@ -339,7 +339,7 @@ void radeon_bo_fini(struct radeon_device *rdev) > void radeon_bo_list_add_object(struct radeon_bo_list *lobj, > struct list_head *he
[Bug 56311] New: radeon crashing xorg at radeon_drv.so on kernel 3.8.4
https://bugzilla.kernel.org/show_bug.cgi?id=56311 Summary: radeon crashing xorg at radeon_drv.so on kernel 3.8.4 Product: Drivers Version: 2.5 Platform: All OS/Version: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) AssignedTo: drivers_video-dri at kernel-bugs.osdl.org ReportedBy: linas_fi at ymail.com Regression: No After upgrading from linux 3.7.10-1 to 3.8.4-1 xorg started crashing. The backtraces point to radeon_drv.so I am using a Radeon HD 3600. It is also worth noting that the kernel was booted with radeon.no_wb=1 parameter. Downstream bug, including some backtraces: https://bugs.archlinux.org/task/34563 -- Configure bugmail: https://bugzilla.kernel.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are watching the assignee of the bug.
[PATCH 11/11] drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730 Signed-off-by: Christian K?nig Signed-off-by: Alex Deucher Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/evergreen.c |3 +++ drivers/gpu/drm/radeon/evergreend.h |3 +++ drivers/gpu/drm/radeon/ni.c |3 +++ drivers/gpu/drm/radeon/nid.h|3 +++ drivers/gpu/drm/radeon/rv770.c |5 + drivers/gpu/drm/radeon/rv770d.h |5 + drivers/gpu/drm/radeon/si.c |3 +++ drivers/gpu/drm/radeon/sid.h|3 +++ 8 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index a6e7186..c6d8017 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -2269,6 +2269,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev) WREG32(DMIF_ADDR_CONFIG, gb_addr_config); WREG32(HDP_ADDR_CONFIG, gb_addr_config); WREG32(DMA_TILING_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); if ((rdev->config.evergreen.max_backends == 1) && (rdev->flags & RADEON_IS_IGP)) { diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 43e7d3f..eabf92a 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -1033,6 +1033,9 @@ /* * UVD */ +#define UVD_UDEC_ADDR_CONFIG 0xef4c +#define UVD_UDEC_DB_ADDR_CONFIG0xef50 +#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 #define UVD_RBC_RB_RPTR0xf690 #define UVD_RBC_RB_WPTR0xf694 diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index ac944f5..9ed0571 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -624,6 +624,9 @@ static void cayman_gpu_init(struct radeon_device *rdev) WREG32(HDP_ADDR_CONFIG, gb_addr_config); WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); + WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); if ((rdev->config.cayman.max_backends_per_se == 1) && (rdev->flags & RADEON_IS_IGP)) { diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h index 3731f6c..358187a 100644 --- a/drivers/gpu/drm/radeon/nid.h +++ b/drivers/gpu/drm/radeon/nid.h @@ -491,6 +491,9 @@ #define UVD_SEMA_ADDR_LOW 0xEF00 #define UVD_SEMA_ADDR_HIGH 0xEF04 #define UVD_SEMA_CMD 0xEF08 +#define UVD_UDEC_ADDR_CONFIG 0xEF4C +#define UVD_UDEC_DB_ADDR_CONFIG0xEF50 +#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 #define UVD_RBC_RB_RPTR0xF690 #define UVD_RBC_RB_WPTR0xF694 diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 5ccc865..b8f5f44 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -866,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev) WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0x)); WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0x)); WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0x)); + if (rdev->family == CHIP_RV730) { + WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0x)); + WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0x)); + WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0x)); + } WREG32(CGTS_SYS_TCC_DISABLE, 0); WREG32(CGTS_TCC_DISABLE, 0); diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h index 162b177..6a52b20 100644 --- a/drivers/gpu/drm/radeon/rv770d.h +++ b/drivers/gpu/drm/radeon/rv770d.h @@ -136,6 +136,11 @@ #define DMA_TILING_CONFIG 0x3ec8 #define DMA_TILING_CONFIG2 0xd0b8 +/* RV730 only */ +#define UVD_UDEC_TILING_CONFIG 0xef40 +#define UVD_UDEC_DB_TILING_CONFIG 0xef44 +#define UVD_UDEC_DBW_TILING_CONFIG 0xef48 + #defineGC_USER_SHADER_PIPE_CONFIG 0x8954 #defineINACTIVE_QD_PIPES(x)((x) << 8) #defineINACTIVE_QD_PIPES_MASK 0xFF00 diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 472d9fb..34ffbcb 100644 --- a/drivers/g
[PATCH 10/11] drm/radeon: init UVD clocks to sane defaults
Just until we get proper DPM for that. Signed-off-by: Christian K?nig Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon_uvd.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 05a192e..30a9460 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c @@ -188,6 +188,8 @@ int radeon_uvd_resume(struct radeon_device *rdev) radeon_bo_unreserve(rdev->uvd.vcpu_bo); + radeon_set_uvd_clocks(rdev, 53300, 4); + return 0; } -- 1.7.9.5
[PATCH 09/11] drm/radeon: add set_uvd_clocks callback for r7xx v3
v2: avoid 64bit divide v3: rv740 uses the evegreen upll configuration Signed-off-by: Christian K?nig Signed-off-by: Alex Deucher Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon_asic.c |1 + drivers/gpu/drm/radeon/radeon_asic.h |1 + drivers/gpu/drm/radeon/rv770.c | 156 ++ drivers/gpu/drm/radeon/rv770d.h | 24 ++ 4 files changed, 182 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 03228cb..19bf122 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1183,6 +1183,7 @@ static struct radeon_asic rv770_asic = { .get_pcie_lanes = &r600_get_pcie_lanes, .set_pcie_lanes = &r600_set_pcie_lanes, .set_clock_gating = &radeon_atom_set_clock_gating, + .set_uvd_clocks = &rv770_set_uvd_clocks, }, .pflip = { .pre_page_flip = &rs600_pre_page_flip, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 365c964..2add526 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -424,6 +424,7 @@ int rv770_copy_dma(struct radeon_device *rdev, struct radeon_fence **fence); u32 rv770_get_xclk(struct radeon_device *rdev); int rv770_uvd_resume(struct radeon_device *rdev); +int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); /* * evergreen diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index fb9a0b8..5ccc865 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -42,6 +42,162 @@ static void rv770_gpu_init(struct radeon_device *rdev); void rv770_fini(struct radeon_device *rdev); static void rv770_pcie_gen2_enable(struct radeon_device *rdev); +int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); + +static int rv770_uvd_calc_post_div(unsigned target_freq, + unsigned vco_freq, + unsigned *div) +{ + /* Fclk = Fvco / PDIV */ + *div = vco_freq / target_freq; + + /* we alway need a frequency less than or equal the target */ + if ((vco_freq / *div) > target_freq) + *div += 1; + + /* out of range ? */ + if (*div > 30) + return -1; /* forget it */ + + *div -= 1; + return vco_freq / (*div + 1); +} + +static int rv770_uvd_send_upll_ctlreq(struct radeon_device *rdev) +{ + unsigned i; + + /* assert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); + + /* wait for CTLACK and CTLACK2 to get asserted */ + for (i = 0; i < 100; ++i) { + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; + if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + /* deassert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + + return 0; +} + +int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) +{ + /* start off with something large */ + int optimal_diff_score = 0x7FF; + unsigned optimal_fb_div = 0, optimal_vclk_div = 0; + unsigned optimal_dclk_div = 0, optimal_vco_freq = 0; + unsigned vco_freq, vco_min = 5, vco_max = 16; + unsigned ref_freq = rdev->clock.spll.reference_freq; + int r; + + /* RV740 uses evergreen uvd clk programming */ + if (rdev->family == CHIP_RV740) + return evergreen_set_uvd_clocks(rdev, vclk, dclk); + + /* loop through vco from low to high */ + vco_min = max(max(vco_min, vclk), dclk); + for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) { + uint64_t fb_div = (uint64_t)vco_freq * 43663; + int calc_clk, diff_score, diff_vclk, diff_dclk; + unsigned vclk_div, dclk_div; + + do_div(fb_div, ref_freq); + fb_div |= 1; + + /* fb div out of range ? */ + if (fb_div > 0x03FF) + break; /* it can oly get worse */ + + /* calc vclk with current vco freq. */ + calc_clk = rv770_uvd_calc_post_div(vclk, vco_freq, &vclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_vclk = vclk - calc_clk; + + /* calc dclk with current vco freq. */ + calc_clk = rv770_uvd_calc_post_div(dclk, vco_freq, &dclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_dclk = dclk - calc_clk; + + /* determine if this vco setting is better than current opt
[PATCH 08/11] drm/radeon: add set_uvd_clocks callback for SI
Signed-off-by: Christian K?nig Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon_asic.c |1 + drivers/gpu/drm/radeon/radeon_asic.h |1 + drivers/gpu/drm/radeon/si.c | 167 ++ drivers/gpu/drm/radeon/sid.h | 29 ++ 4 files changed, 198 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index a65312c..03228cb 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1887,6 +1887,7 @@ static struct radeon_asic si_asic = { .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = NULL, + .set_uvd_clocks = &si_set_uvd_clocks, }, .pflip = { .pre_page_flip = &evergreen_pre_page_flip, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 54a7ef7..365c964 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -545,5 +545,6 @@ int si_copy_dma(struct radeon_device *rdev, void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); u32 si_get_xclk(struct radeon_device *rdev); uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); +int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); #endif diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index cc9fe39..472d9fb 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -4666,3 +4666,170 @@ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev) mutex_unlock(&rdev->gpu_clock_mutex); return clock; } + +static int si_uvd_calc_post_div(unsigned target_freq, + unsigned vco_freq, + unsigned *div) +{ + /* target larger than vco frequency ? */ + if (vco_freq < target_freq) + return -1; /* forget it */ + + /* Fclk = Fvco / PDIV */ + *div = vco_freq / target_freq; + + /* we alway need a frequency less than or equal the target */ + if ((vco_freq / *div) > target_freq) + *div += 1; + + /* dividers above 5 must be even */ + if (*div > 5 && *div % 2) + *div += 1; + + /* out of range ? */ + if (*div >= 128) + return -1; /* forget it */ + + return vco_freq / *div; +} + +static int si_uvd_send_upll_ctlreq(struct radeon_device *rdev) +{ + unsigned i; + + /* assert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); + + /* wait for CTLACK and CTLACK2 to get asserted */ + for (i = 0; i < 100; ++i) { + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; + if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + /* deassert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + + return 0; +} + +int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) +{ + /* start off with something large */ + int optimal_diff_score = 0x7FF; + unsigned optimal_fb_div = 0, optimal_vclk_div = 0; + unsigned optimal_dclk_div = 0, optimal_vco_freq = 0; + unsigned vco_freq; + int r; + + /* loop through vco from low to high */ + for (vco_freq = 125000; vco_freq <= 25; vco_freq += 100) { + unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384; + int calc_clk, diff_score, diff_vclk, diff_dclk; + unsigned vclk_div, dclk_div; + + /* fb div out of range ? */ + if (fb_div > 0x03FF) + break; /* it can oly get worse */ + + /* calc vclk with current vco freq. */ + calc_clk = si_uvd_calc_post_div(vclk, vco_freq, &vclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_vclk = vclk - calc_clk; + + /* calc dclk with current vco freq. */ + calc_clk = si_uvd_calc_post_div(dclk, vco_freq, &dclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_dclk = dclk - calc_clk; + + /* determine if this vco setting is better than current optimal settings */ + diff_score = abs(diff_vclk) + abs(diff_dclk); + if (diff_score < optimal_diff_score) { + optimal_fb_div = fb_div; + optimal_vclk_div = vclk_div; + optimal_dclk_div = dclk_div; + optimal_vco_freq = vco_freq; + optimal_diff_score = diff_score; +
[PATCH 07/11] drm/radeon: add set_uvd_clocks callback for evergreen
From: Alex Deucher v2: remove unneeded register definitions Signed-off-by: Alex Deucher Signed-off-by: Christian K?nig Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/evergreen.c | 164 ++ drivers/gpu/drm/radeon/evergreend.h | 27 ++ drivers/gpu/drm/radeon/radeon_asic.c |3 + drivers/gpu/drm/radeon/radeon_asic.h |1 + 4 files changed, 195 insertions(+) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index bdd3d34..a6e7186 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -131,6 +131,170 @@ done: return r; } +static int evergreen_uvd_calc_post_div(unsigned target_freq, + unsigned vco_freq, + unsigned *div) +{ + /* target larger than vco frequency ? */ + if (vco_freq < target_freq) + return -1; /* forget it */ + + /* Fclk = Fvco / PDIV */ + *div = vco_freq / target_freq; + + /* we alway need a frequency less than or equal the target */ + if ((vco_freq / *div) > target_freq) + *div += 1; + + /* dividers above 5 must be even */ + if (*div > 5 && *div % 2) + *div += 1; + + /* out of range ? */ + if (*div >= 128) + return -1; /* forget it */ + + return vco_freq / *div; +} + +static int evergreen_uvd_send_upll_ctlreq(struct radeon_device *rdev) +{ + unsigned i; + + /* assert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); + + /* wait for CTLACK and CTLACK2 to get asserted */ + for (i = 0; i < 100; ++i) { + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; + if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + /* deassert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + + return 0; +} + +int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) +{ + /* start off with something large */ + int optimal_diff_score = 0x7FF; + unsigned optimal_fb_div = 0, optimal_vclk_div = 0; + unsigned optimal_dclk_div = 0, optimal_vco_freq = 0; + unsigned vco_freq; + int r; + + /* loop through vco from low to high */ + for (vco_freq = 125000; vco_freq <= 25; vco_freq += 100) { + unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384; + int calc_clk, diff_score, diff_vclk, diff_dclk; + unsigned vclk_div, dclk_div; + + /* fb div out of range ? */ + if (fb_div > 0x03FF) + break; /* it can oly get worse */ + + /* calc vclk with current vco freq. */ + calc_clk = evergreen_uvd_calc_post_div(vclk, vco_freq, &vclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_vclk = vclk - calc_clk; + + /* calc dclk with current vco freq. */ + calc_clk = evergreen_uvd_calc_post_div(dclk, vco_freq, &dclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_dclk = dclk - calc_clk; + + /* determine if this vco setting is better than current optimal settings */ + diff_score = abs(diff_vclk) + abs(diff_dclk); + if (diff_score < optimal_diff_score) { + optimal_fb_div = fb_div; + optimal_vclk_div = vclk_div; + optimal_dclk_div = dclk_div; + optimal_vco_freq = vco_freq; + optimal_diff_score = diff_score; + if (optimal_diff_score == 0) + break; /* it can't get better than this */ + } + } + + /* set VCO_MODE to 1 */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); + + /* toggle UPLL_SLEEP to 1 then back to 0 */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); + + /* deassert UPLL_RESET */ + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); + + mdelay(1); + + /* bypass vclk and dclk with bclk */ + WREG32_P(CG_UPLL_FUNC_CNTL_2, + VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), + ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); + + /* put PLL in bypass mode */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); + + r = evergreen_uvd_send_upll_ctlreq(rdev); + if (r) + return r; + + /* assert UPLL_RESET again */ + WREG32_P(
[PATCH 06/11] drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4)
From: Alex Deucher v2: write clk registers only once! v3: update cg scratch register properly v4: add TN support Signed-off-by: Alex Deucher Signed-off-by: Christian K?nig Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/evergreen.c | 47 ++ drivers/gpu/drm/radeon/evergreend.h | 10 drivers/gpu/drm/radeon/radeon_asic.c |2 ++ drivers/gpu/drm/radeon/radeon_asic.h |1 + 4 files changed, 60 insertions(+) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 18b66ff..bdd3d34 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -84,6 +84,53 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, } } +static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock, + u32 cntl_reg, u32 status_reg) +{ + int r, i; + struct atom_clock_dividers dividers; + +r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + clock, false, ÷rs); + if (r) + return r; + + WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK)); + + for (i = 0; i < 100; i++) { + if (RREG32(status_reg) & DCLK_STATUS) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + return 0; +} + +int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) +{ + int r = 0; + u32 cg_scratch = RREG32(CG_SCRATCH1); + + r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS); + if (r) + goto done; + cg_scratch &= 0x; + cg_scratch |= vclk / 100; /* Mhz */ + + r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS); + if (r) + goto done; + cg_scratch &= 0x; + cg_scratch |= (dclk / 100) << 16; /* Mhz */ + +done: + WREG32(CG_SCRATCH1, cg_scratch); + + return r; +} + void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) { u16 ctl, v; diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index c5d873e..b6491a3 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -53,6 +53,16 @@ #define RCU_IND_INDEX 0x100 #define RCU_IND_DATA 0x104 +/* fusion uvd clocks */ +#define CG_DCLK_CNTL0x610 +# define DCLK_DIVIDER_MASK0x7f +# define DCLK_DIR_CNTL_EN (1 << 8) +#define CG_DCLK_STATUS 0x614 +# define DCLK_STATUS (1 << 0) +#define CG_VCLK_CNTL0x618 +#define CG_VCLK_STATUS 0x61c +#defineCG_SCRATCH1 0x820 + #define GRBM_GFX_INDEX 0x802C #defineINSTANCE_INDEX(x) ((x) << 0) #defineSE_INDEX(x) ((x) << 16) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index a7a7b2b..d3992d9 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1373,6 +1373,7 @@ static struct radeon_asic sumo_asic = { .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = NULL, + .set_uvd_clocks = &sumo_set_uvd_clocks, }, .pflip = { .pre_page_flip = &evergreen_pre_page_flip, @@ -1744,6 +1745,7 @@ static struct radeon_asic trinity_asic = { .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = NULL, + .set_uvd_clocks = &sumo_set_uvd_clocks, }, .pflip = { .pre_page_flip = &evergreen_pre_page_flip, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 515db96..37f28a3 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -459,6 +459,7 @@ extern void evergreen_pm_prepare(struct radeon_device *rdev); extern void evergreen_pm_finish(struct radeon_device *rdev); extern void sumo_pm_init_profile(struct radeon_device *rdev); extern void btc_pm_init_profile(struct radeon_device *rdev); +int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); -- 1.7.9.5
[PATCH 05/11] drm/radeon: add radeon_atom_get_clock_dividers helper
Signed-off-by: Christian K?nig Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon.h |5 ++ drivers/gpu/drm/radeon/radeon_atombios.c | 107 ++ drivers/gpu/drm/radeon/radeon_mode.h | 23 +++ 3 files changed, 135 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 8c5b7e8..25b5b39 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -205,6 +205,11 @@ void radeon_pm_suspend(struct radeon_device *rdev); void radeon_pm_resume(struct radeon_device *rdev); void radeon_combios_get_power_modes(struct radeon_device *rdev); void radeon_atombios_get_power_modes(struct radeon_device *rdev); +int radeon_atom_get_clock_dividers(struct radeon_device *rdev, + u8 clock_type, + u32 clock, + bool strobe_mode, + struct atom_clock_dividers *dividers); void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); void rs690_pm_info(struct radeon_device *rdev); extern int rv6xx_get_temp(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index f22eb57..8c1779c 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -2654,6 +2654,113 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.current_vddc = 0; } +union get_clock_dividers { + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; +}; + +int radeon_atom_get_clock_dividers(struct radeon_device *rdev, + u8 clock_type, + u32 clock, + bool strobe_mode, + struct atom_clock_dividers *dividers) +{ + union get_clock_dividers args; + int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); + u8 frev, crev; + + memset(&args, 0, sizeof(args)); + memset(dividers, 0, sizeof(struct atom_clock_dividers)); + + if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) + return -EINVAL; + + switch (crev) { + case 1: + /* r4xx, r5xx */ + args.v1.ucAction = clock_type; + args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ + + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + + dividers->post_div = args.v1.ucPostDiv; + dividers->fb_div = args.v1.ucFbDiv; + dividers->enable_post_div = true; + break; + case 2: + case 3: + /* r6xx, r7xx, evergreen, ni */ + if (rdev->family <= CHIP_RV770) { + args.v2.ucAction = clock_type; + args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ + + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + + dividers->post_div = args.v2.ucPostDiv; + dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); + dividers->ref_div = args.v2.ucAction; + if (rdev->family == CHIP_RV770) { + dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? + true : false; + dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; + } else + dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; + } else { + if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { + args.v3.ulClock.ulComputeClockFlag = clock_type; + args.v3.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ + + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + + dividers->post_div = args.v3.ucPostDiv; + dividers->enable_post_div = (args.v3.ucCntlFlag & + ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; + dividers->enable_dithen = (args.v3.ucCntlFlag & + ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; + dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv
[PATCH 04/11] drm/radeon: add pm callback for setting uvd clocks
From: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Christian K?nig Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 051b8fd..8c5b7e8 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1313,6 +1313,7 @@ struct radeon_asic { int (*get_pcie_lanes)(struct radeon_device *rdev); void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); void (*set_clock_gating)(struct radeon_device *rdev, int enable); + int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); } pm; /* pageflipping */ struct { @@ -1879,6 +1880,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) +#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) -- 1.7.9.5
[PATCH 03/11] drm/radeon: UVD bringup v8
Just everything needed to decode videos using UVD. v6: just all the bugfixes and support for R7xx-SI merged in one patch v7: UVD_CGC_GATE is a write only register, lockup detection fix v8: split out VRAM fallback changes, remove support for RV770, add support for HEMLOCK, add buffer sizes checks Signed-off-by: Christian K?nig --- drivers/gpu/drm/radeon/Makefile|2 +- drivers/gpu/drm/radeon/evergreen.c | 40 +- drivers/gpu/drm/radeon/evergreend.h|7 + drivers/gpu/drm/radeon/ni.c| 49 +++ drivers/gpu/drm/radeon/nid.h |9 + drivers/gpu/drm/radeon/r600.c | 291 ++ drivers/gpu/drm/radeon/r600d.h | 61 +++ drivers/gpu/drm/radeon/radeon.h| 41 +- drivers/gpu/drm/radeon/radeon_asic.c | 63 +++ drivers/gpu/drm/radeon/radeon_asic.h | 19 + drivers/gpu/drm/radeon/radeon_cs.c | 28 +- drivers/gpu/drm/radeon/radeon_fence.c | 23 +- drivers/gpu/drm/radeon/radeon_kms.c|1 + drivers/gpu/drm/radeon/radeon_object.c |4 +- drivers/gpu/drm/radeon/radeon_object.h |2 +- drivers/gpu/drm/radeon/radeon_ring.c | 24 +- drivers/gpu/drm/radeon/radeon_test.c | 72 ++-- drivers/gpu/drm/radeon/radeon_uvd.c| 664 drivers/gpu/drm/radeon/rv770.c | 132 +++ drivers/gpu/drm/radeon/rv770d.h| 14 + drivers/gpu/drm/radeon/si.c| 32 ++ drivers/gpu/drm/radeon/sid.h |6 + include/uapi/drm/radeon_drm.h |1 + 23 files changed, 1533 insertions(+), 52 deletions(-) create mode 100644 drivers/gpu/drm/radeon/radeon_uvd.c diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index bf17252..86c5e36 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ - si_blit_shaders.o radeon_prime.o + si_blit_shaders.o radeon_prime.o radeon_uvd.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 305a657..18b66ff 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -3360,6 +3360,9 @@ restart_ih: DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); break; } + case 124: /* UVD */ + DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); + radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); break; case 146: case 147: @@ -3571,7 +3574,7 @@ int evergreen_copy_dma(struct radeon_device *rdev, static int evergreen_startup(struct radeon_device *rdev) { - struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; + struct radeon_ring *ring; int r; /* enable pcie gen2 link */ @@ -3638,6 +3641,17 @@ static int evergreen_startup(struct radeon_device *rdev) return r; } + r = rv770_uvd_resume(rdev); + if (!r) { + r = radeon_fence_driver_start_ring(rdev, + R600_RING_TYPE_UVD_INDEX); + if (r) + dev_err(rdev->dev, "UVD fences init error (%d).\n", r); + } + + if (r) + rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; + /* Enable IRQ */ r = r600_irq_init(rdev); if (r) { @@ -3647,6 +3661,7 @@ static int evergreen_startup(struct radeon_device *rdev) } evergreen_irq_set(rdev); + ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, R600_CP_RB_RPTR, R600_CP_RB_WPTR, 0, 0xf, RADEON_CP_PACKET2); @@ -3670,6 +3685,19 @@ static int evergreen_startup(struct radeon_device *rdev) if (r) return r; + ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; + if (ring->ring_size) { + r = radeon_ring_init(rdev, ring, ring->ring_size, +R600_WB_UVD_RPTR_OFFSET, +UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, +0, 0xf, RADEON_CP_PACKET2); + if (!r) + r = r600_uvd_init(rdev); + + if (r) + DRM_ERROR("radeon: error initializing UVD (%d).\n", r); + } + r = radeon_ib_pool_init(rdev); if (r) {
[PATCH 02/11] drm/radeon: rework fallback handling
From: Christian K?nig Let the CS module decide if we can fall back to VRAM or not. Signed-off-by: Christian K?nig --- drivers/gpu/drm/radeon/radeon.h|5 ++-- drivers/gpu/drm/radeon/radeon_cs.c | 51 ++-- drivers/gpu/drm/radeon/radeon_object.c |8 ++--- 3 files changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 8263af3..7c2498c 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -357,8 +357,9 @@ struct radeon_bo_list { struct ttm_validate_buffer tv; struct radeon_bo*bo; uint64_tgpu_offset; - unsignedrdomain; - unsignedwdomain; + boolwritten; + unsigneddomain; + unsignedalt_domain; u32 tiling_flags; }; diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index a3dd04d..8223cf8 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -53,6 +53,7 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) } for (i = 0; i < p->nrelocs; i++) { struct drm_radeon_cs_reloc *r; + uint32_t domain; duplicate = false; r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; @@ -63,30 +64,36 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) break; } } - if (!duplicate) { - p->relocs[i].gobj = drm_gem_object_lookup(ddev, - p->filp, - r->handle); - if (p->relocs[i].gobj == NULL) { - DRM_ERROR("gem object lookup failed 0x%x\n", - r->handle); - return -ENOENT; - } - p->relocs_ptr[i] = &p->relocs[i]; - p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); - p->relocs[i].lobj.bo = p->relocs[i].robj; - p->relocs[i].lobj.wdomain = r->write_domain; - p->relocs[i].lobj.rdomain = r->read_domains; - p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; - p->relocs[i].handle = r->handle; - p->relocs[i].flags = r->flags; - radeon_bo_list_add_object(&p->relocs[i].lobj, - &p->validated); - - } else + if (duplicate) { p->relocs[i].handle = 0; + continue; + } + + p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, + r->handle); + if (p->relocs[i].gobj == NULL) { + DRM_ERROR("gem object lookup failed 0x%x\n", + r->handle); + return -ENOENT; + } + p->relocs_ptr[i] = &p->relocs[i]; + p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); + p->relocs[i].lobj.bo = p->relocs[i].robj; + p->relocs[i].lobj.written = !!r->write_domain; + + domain = r->write_domain ? r->write_domain : r->read_domains; + p->relocs[i].lobj.domain = domain; + if (domain == RADEON_GEM_DOMAIN_VRAM) + domain |= RADEON_GEM_DOMAIN_GTT; + p->relocs[i].lobj.alt_domain = domain; + + p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; + p->relocs[i].handle = r->handle; + + radeon_bo_list_add_object(&p->relocs[i].lobj, + &p->validated); } - return radeon_bo_list_validate(&p->validated); + return radeon_bo_list_validate(&p->validated, p->ring); } static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index d3aface..9633325 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -339,7 +339,7 @@ void radeon_bo_fini(struct radeon_device *rdev) void radeon_bo_list_add_object(struct radeon_bo_list *lobj, struct list_head *head) { - if (lobj->wdomain) { + if (lobj->written) { list_add(&lobj->tv.head, head); } else { list_add_tail(&lobj->tv.head, head); @@ -360,15 +360,15 @@ int radeon_bo_list_validate(struct l
[PATCH 01/11] drm/radeon: UVD doesn't needs VM on SI v2
v2: update error message and comment Signed-off-by: Christian K?nig --- drivers/gpu/drm/radeon/radeon_cs.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 70d3824..a3dd04d 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -241,15 +241,15 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) return -EINVAL; } - /* we only support VM on SI+ */ - if ((p->rdev->family >= CHIP_TAHITI) && - ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { - DRM_ERROR("VM required on SI+!\n"); + if (radeon_cs_get_ring(p, ring, priority)) return -EINVAL; - } - if (radeon_cs_get_ring(p, ring, priority)) + /* we only support VM on some SI+ rings */ + if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) && + ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { + DRM_ERROR("Ring %d requires VM!\n", p->ring); return -EINVAL; + } } /* deal with non-vm */ -- 1.7.9.5
[PATCH 00/11] drm/radeon: basic UVD support v2
Hello everyone, This is the second round of this patchset. Do to public demand I uploaded this patchset as branch uvd-3.9 to git://people.freedesktop.org/~deathsimple/linux. Compared to the first round I changed the error message in patch #1, patch #2 was split out of patch #3 and patch #3 itself got buffer size checking and a few minor bugfixes. The other patches are unchanged. Please review, Christian.
Is there IGP DCE5?
I was surprised that my BARTS in a Samsung notebook doesn't have a RADEON_IS_IGP flag. Are there any DCE5 devices that are IGP? Btw. who does set that "flags" anyway? Flags are passed to the radeon_driver_load_kms function from drm_pci.c: dev->driver->load(dev, ent->driver_data); (so driver_data becomes flags). But I can't find where that "driver_data" (AKA flags) is set. -- Rafał ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 62756] Rendering errors on rv790 with llvm and unigine heaven 3.0
https://bugs.freedesktop.org/show_bug.cgi?id=62756 --- Comment #12 from Andy Furniss --- (In reply to comment #11) > Created attachment 77534 [details] [review] > native inst support for mesa > > Sorry, I didn't notice that mesa didn't translate native instruction for > r700. > You'll need this patch, as well as the previous one ; it should fix the big > regression. Can you confirm this ? Yes, this fixes the big regression and I also no longer see the original regression. -- You are receiving this mail because: You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: BUG: kworker hangs the GPU on drm and i915 since 3.8.x under X11
On Sat, Apr 6, 2013 at 6:24 PM, George Amanakis wrote: > Indeed, I set explicitly drm_kms_helper.poll=0 since 2.35.x. See here: > http://souriguha.wordpress.com/2011/03/08/how-to-solve-problem-with-thinkpadkslowd-kworker-on-linux-kernel-2-35-2-36/ > > Mouse and keyboard freezes intermittently some time after boot up. Actually > the problem has to do with the GPU lagging and displaying the changes later. > This results in an almost unusable desktop environment. Top will report the > high CPU usage by 3-4 processes named kworker. With the > drm_kms_helper.poll=0 it was until the 3.8.x kernel resolved. > > Since the 3.8.x kernels the exact same problem appeared again. The problem > persists with the latest 3.9-rc5 too. Ah, so it seems to be a plain hpd irq storm (since you have massive cpu loads), not edid readings taking forever (which would still cause the mouse to lag horribly on 3.8 and earlier, but without cpu load). The edid reading issues should be fixed in 3.9. For hpd irq storms Egbert Eich from Suse is working on some patches to mitigate this. Infrastructure prep work is already merged for 3.10, hopefully we can merge the actual mitigation logic, too. I'll try no to forget to ping you once it's merged, so that you can test it a bit. Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
BUG: kworker hangs the GPU on drm and i915 since 3.8.x under X11
Indeed, I set explicitly drm_kms_helper.poll=0 since 2.35.x. See here: http://souriguha.wordpress.com/2011/03/08/how-to-solve-problem-with-thinkpadkslowd-kworker-on-linux-kernel-2-35-2-36/ Mouse and keyboard freezes intermittently some time after boot up. Actually the problem has to do with the GPU lagging and displaying the changes later. This results in an almost unusable desktop environment. Top will report the high CPU usage by 3-4 processes named kworker. With the drm_kms_helper.poll=0 it was until the 3.8.x kernel resolved. Since the 3.8.x kernels the exact same problem appeared again. The problem persists with the latest 3.9-rc5 too. ? Thanks, George From: Daniel Vetter To: George Amanakis Cc: "alexander.deucher at amd.com" ; "airlied at redhat.com" ; dri-devel ; intel-gfx Sent: Saturday, April 6, 2013 5:11 PM Subject: Re: BUG: kworker hangs the GPU on drm and i915 since 3.8.x under X11 Indeed, the commit you've bisected too accidentally removed this check. I'll submit a patch.So I guess you've explicitly set drm_kms_helper.poll=0. Can you please elaborate what you're working around with this option? Any such case is a bug. Also, can you please test latest 3.9-rc kernels (without your patch, i.e. a broken configuration)? It contains some rework to make hpd detection less intrusive for normal desktop activity and should also greatly help for your case here. Thanks, Daniel > > diff -rupN a/drivers/gpu/drm/drm_crtc_helper.c > b/drivers/gpu/drm/drm_crtc_helper.c > --- a/drivers/gpu/drm/drm_crtc_helper.c? ? 2013-02-19 00:58:34.0 > +0100 > +++ b/drivers/gpu/drm/drm_crtc_helper.c? ? 2013-04-05 23:10:36.454936677 > +0200 > @@ -1067,7 +1067,7 @@ void drm_helper_hpd_irq_event(struct drm >? ? ? enum drm_connector_status old_status; >? ? ? bool changed = false; > > -? ? if (!dev->mode_config.poll_enabled) > +? ? if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll) >? ? ? ? ? return; > >? ? ? mutex_lock(&dev->mode_config.mutex); > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20130406/5fb4d304/attachment-0001.html>
[PATCH 1/1] drm: Add 1600x1200 (UXGA) screen resolution to the built-in EDIDs
The 1600x1200 (UXGA) screen resolution was lacking in the set of built-in selectable EDID screen resolutions that can be used to repair misbehaving monitor firmware. This patch adds the related data set and expands the documentation. Signed-off-by: Carsten Emde --- Documentation/EDID/1600x1200.S | 44 Documentation/EDID/HOWTO.txt| 12 +- drivers/gpu/drm/drm_edid_load.c | 21 ++- 3 files changed, 70 insertions(+), 7 deletions(-) Index: linux/Documentation/EDID/1600x1200.S === --- /dev/null +++ linux/Documentation/EDID/1600x1200.S @@ -0,0 +1,44 @@ +/* + 1600x1200.S: EDID data set for standard 1600x1200 60 Hz monitor + + Copyright (C) 2013 Carsten Emde + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2 + of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. +*/ + +/* EDID */ +#define VERSION 1 +#define REVISION 3 + +/* Display */ +#define CLOCK 162000 /* kHz */ +#define XPIX 1600 +#define YPIX 1200 +#define XY_RATIO XY_RATIO_4_3 +#define XBLANK 560 +#define YBLANK 50 +#define XOFFSET 64 +#define XPULSE 192 +#define YOFFSET (63+1) +#define YPULSE (63+3) +#define DPI 72 +#define VFREQ 60 /* Hz */ +#define TIMING_NAME "Linux UXGA" +#define ESTABLISHED_TIMINGS_BITS 0x00 /* none */ +#define HSYNC_POL 1 +#define VSYNC_POL 1 +#define CRC 0x9d + +#include "edid.S" Index: linux/Documentation/EDID/HOWTO.txt === --- linux.orig/Documentation/EDID/HOWTO.txt +++ linux/Documentation/EDID/HOWTO.txt @@ -18,12 +18,12 @@ CONFIG_DRM_LOAD_EDID_FIRMWARE was introd individually prepared or corrected EDID data set in the /lib/firmware directory from where it is loaded via the firmware interface. The code (see drivers/gpu/drm/drm_edid_load.c) contains built-in data sets for -commonly used screen resolutions (1024x768, 1280x1024, 1680x1050, -1920x1080) as binary blobs, but the kernel source tree does not contain -code to create these data. In order to elucidate the origin of the -built-in binary EDID blobs and to facilitate the creation of individual -data for a specific misbehaving monitor, commented sources and a -Makefile environment are given here. +commonly used screen resolutions (1024x768, 1280x1024, 1600x1200, +1680x1050, 1920x1080) as binary blobs, but the kernel source tree does +not contain code to create these data. In order to elucidate the origin +of the built-in binary EDID blobs and to facilitate the creation of +individual data for a specific misbehaving monitor, commented sources +and a Makefile environment are given here. To create binary EDID and C source code files from the existing data material, simply type "make". Index: linux/drivers/gpu/drm/drm_edid_load.c === --- linux.orig/drivers/gpu/drm/drm_edid_load.c +++ linux/drivers/gpu/drm/drm_edid_load.c @@ -31,10 +31,11 @@ module_param_string(edid_firmware, edid_ MODULE_PARM_DESC(edid_firmware, "Do not probe monitor, use specified EDID blob " "from built-in data or /lib/firmware instead. "); -#define GENERIC_EDIDS 4 +#define GENERIC_EDIDS 5 static char *generic_edid_name[GENERIC_EDIDS] = { "edid/1024x768.bin", "edid/1280x1024.bin", + "edid/1600x1200.bin", "edid/1680x1050.bin", "edid/1920x1080.bin", }; @@ -79,6 +80,24 @@ static u8 generic_edid[GENERIC_EDIDS][12 { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x16, 0x01, 0x03, 0x6d, 0x37, 0x29, 0x78, + 0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25, + 0x20, 0x50, 0x54, 0x00, 0x00, 0x00, 0xa9, 0x40, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x48, 0x3f, + 0x40, 0x30, 0x62, 0xb0, 0x32, 0x40, 0x40, 0xc0, + 0x13, 0x00, 0x2b, 0xa0, 0x21, 0x00, 0x00, 0x1e, + 0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e, + 0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20, + 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b, + 0x3d, 0x4a, 0x4c, 0x11, 0x00, 0x0a, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, + 0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x55, + 0x58, 0x47, 0x41, 0x0a,
[PATCH 0/1] drm: Add built-in EDID set of another common screen resolution
Several users were complaining that 1600x1200 screen resolution was lacking. Here is it. -Carsten. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 62756] Rendering errors on rv790 with llvm and unigine heaven 3.0
https://bugs.freedesktop.org/show_bug.cgi?id=62756 --- Comment #11 from vincent --- Created attachment 77534 --> https://bugs.freedesktop.org/attachment.cgi?id=77534&action=edit native inst support for mesa Sorry, I didn't notice that mesa didn't translate native instruction for r700. You'll need this patch, as well as the previous one ; it should fix the big regression. Can you confirm this ? -- You are receiving this mail because: You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/kms-helper: disable hpd_irq handling when poll=0
When inlining the actual hpd output probing in commit 69787f7da6b2adc4054357a661aaa1701a9ca76f Author: Daniel Vetter Date: Tue Oct 23 18:23:34 2012 + drm: run the hpd irq event code directly the check for the drm_kms_hlper.poll module option was lost. This regressed systems where this option is used to work-around output probing issues (like irq storms). Restore the old behaviour. Reported-by: George Amanakis Cc: George Amanakis Cc: Dave Airlie Cc: sta...@vger.kernel.org (for 3.8) Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc_helper.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 7b2d378..3260736 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -1067,7 +1067,7 @@ void drm_helper_hpd_irq_event(struct drm_device *dev) enum drm_connector_status old_status; bool changed = false; - if (!dev->mode_config.poll_enabled) + if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll) return; mutex_lock(&dev->mode_config.mutex); -- 1.7.10.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 56311] New: radeon crashing xorg at radeon_drv.so on kernel 3.8.4
https://bugzilla.kernel.org/show_bug.cgi?id=56311 Summary: radeon crashing xorg at radeon_drv.so on kernel 3.8.4 Product: Drivers Version: 2.5 Platform: All OS/Version: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) AssignedTo: drivers_video-...@kernel-bugs.osdl.org ReportedBy: linas...@ymail.com Regression: No After upgrading from linux 3.7.10-1 to 3.8.4-1 xorg started crashing. The backtraces point to radeon_drv.so I am using a Radeon HD 3600. It is also worth noting that the kernel was booted with radeon.no_wb=1 parameter. Downstream bug, including some backtraces: https://bugs.archlinux.org/task/34563 -- Configure bugmail: https://bugzilla.kernel.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: BUG: kworker hangs the GPU on drm and i915 since 3.8.x under X11
On Sat, Apr 6, 2013 at 12:01 AM, George Amanakis wrote: > I mean that I can type, move the mouse pointer, open new windows but there > is a lag until these changes are displayed. Stuttering like. > > I ended up not reverting the aforementioned commit but modifying it. This > also solves the issue. Here is the patch: Indeed, the commit you've bisected too accidentally removed this check. I'll submit a patch.So I guess you've explicitly set drm_kms_helper.poll=0. Can you please elaborate what you're working around with this option? Any such case is a bug. Also, can you please test latest 3.9-rc kernels (without your patch, i.e. a broken configuration)? It contains some rework to make hpd detection less intrusive for normal desktop activity and should also greatly help for your case here. Thanks, Daniel > > diff -rupN a/drivers/gpu/drm/drm_crtc_helper.c > b/drivers/gpu/drm/drm_crtc_helper.c > --- a/drivers/gpu/drm/drm_crtc_helper.c2013-02-19 00:58:34.0 > +0100 > +++ b/drivers/gpu/drm/drm_crtc_helper.c2013-04-05 23:10:36.454936677 > +0200 > @@ -1067,7 +1067,7 @@ void drm_helper_hpd_irq_event(struct drm > enum drm_connector_status old_status; > bool changed = false; > > -if (!dev->mode_config.poll_enabled) > +if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll) > return; > > mutex_lock(&dev->mode_config.mutex); > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 02/11] drm/radeon: rework fallback handling
Am 06.04.2013 15:24, schrieb Christian König: From: Christian König Let the CS module decide if we can fall back to VRAM or not. Signed-off-by: Christian König Crap, just seen another typo in this patch. Going to resend a v2 of it soon. Christian. --- drivers/gpu/drm/radeon/radeon.h|5 ++-- drivers/gpu/drm/radeon/radeon_cs.c | 51 ++-- drivers/gpu/drm/radeon/radeon_object.c |8 ++--- 3 files changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 8263af3..7c2498c 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -357,8 +357,9 @@ struct radeon_bo_list { struct ttm_validate_buffer tv; struct radeon_bo*bo; uint64_tgpu_offset; - unsignedrdomain; - unsignedwdomain; + boolwritten; + unsigneddomain; + unsignedalt_domain; u32 tiling_flags; }; diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index a3dd04d..8223cf8 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -53,6 +53,7 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) } for (i = 0; i < p->nrelocs; i++) { struct drm_radeon_cs_reloc *r; + uint32_t domain; duplicate = false; r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; @@ -63,30 +64,36 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) break; } } - if (!duplicate) { - p->relocs[i].gobj = drm_gem_object_lookup(ddev, - p->filp, - r->handle); - if (p->relocs[i].gobj == NULL) { - DRM_ERROR("gem object lookup failed 0x%x\n", - r->handle); - return -ENOENT; - } - p->relocs_ptr[i] = &p->relocs[i]; - p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); - p->relocs[i].lobj.bo = p->relocs[i].robj; - p->relocs[i].lobj.wdomain = r->write_domain; - p->relocs[i].lobj.rdomain = r->read_domains; - p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; - p->relocs[i].handle = r->handle; - p->relocs[i].flags = r->flags; - radeon_bo_list_add_object(&p->relocs[i].lobj, - &p->validated); - - } else + if (duplicate) { p->relocs[i].handle = 0; + continue; + } + + p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, + r->handle); + if (p->relocs[i].gobj == NULL) { + DRM_ERROR("gem object lookup failed 0x%x\n", + r->handle); + return -ENOENT; + } + p->relocs_ptr[i] = &p->relocs[i]; + p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); + p->relocs[i].lobj.bo = p->relocs[i].robj; + p->relocs[i].lobj.written = !!r->write_domain; + + domain = r->write_domain ? r->write_domain : r->read_domains; + p->relocs[i].lobj.domain = domain; + if (domain == RADEON_GEM_DOMAIN_VRAM) + domain |= RADEON_GEM_DOMAIN_GTT; + p->relocs[i].lobj.alt_domain = domain; + + p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; + p->relocs[i].handle = r->handle; + + radeon_bo_list_add_object(&p->relocs[i].lobj, + &p->validated); } - return radeon_bo_list_validate(&p->validated); + return radeon_bo_list_validate(&p->validated, p->ring); } static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index d3aface..9633325 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -339,7 +339,7 @@ void radeon_bo_fini(struct radeon_device *rdev) void radeon_bo_list_add_object(struct radeon_bo_list *lobj, struct list_head *head) { - if (lobj->wdomain) { + if (lobj->written) { list_add(&lobj
[PATCH 11/11] drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730 Signed-off-by: Christian König Signed-off-by: Alex Deucher Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/evergreen.c |3 +++ drivers/gpu/drm/radeon/evergreend.h |3 +++ drivers/gpu/drm/radeon/ni.c |3 +++ drivers/gpu/drm/radeon/nid.h|3 +++ drivers/gpu/drm/radeon/rv770.c |5 + drivers/gpu/drm/radeon/rv770d.h |5 + drivers/gpu/drm/radeon/si.c |3 +++ drivers/gpu/drm/radeon/sid.h|3 +++ 8 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index a6e7186..c6d8017 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -2269,6 +2269,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev) WREG32(DMIF_ADDR_CONFIG, gb_addr_config); WREG32(HDP_ADDR_CONFIG, gb_addr_config); WREG32(DMA_TILING_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); if ((rdev->config.evergreen.max_backends == 1) && (rdev->flags & RADEON_IS_IGP)) { diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 43e7d3f..eabf92a 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -1033,6 +1033,9 @@ /* * UVD */ +#define UVD_UDEC_ADDR_CONFIG 0xef4c +#define UVD_UDEC_DB_ADDR_CONFIG0xef50 +#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 #define UVD_RBC_RB_RPTR0xf690 #define UVD_RBC_RB_WPTR0xf694 diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index ac944f5..9ed0571 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -624,6 +624,9 @@ static void cayman_gpu_init(struct radeon_device *rdev) WREG32(HDP_ADDR_CONFIG, gb_addr_config); WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); + WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); + WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); if ((rdev->config.cayman.max_backends_per_se == 1) && (rdev->flags & RADEON_IS_IGP)) { diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h index 3731f6c..358187a 100644 --- a/drivers/gpu/drm/radeon/nid.h +++ b/drivers/gpu/drm/radeon/nid.h @@ -491,6 +491,9 @@ #define UVD_SEMA_ADDR_LOW 0xEF00 #define UVD_SEMA_ADDR_HIGH 0xEF04 #define UVD_SEMA_CMD 0xEF08 +#define UVD_UDEC_ADDR_CONFIG 0xEF4C +#define UVD_UDEC_DB_ADDR_CONFIG0xEF50 +#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 #define UVD_RBC_RB_RPTR0xF690 #define UVD_RBC_RB_WPTR0xF694 diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 5ccc865..b8f5f44 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -866,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev) WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0x)); WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0x)); WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0x)); + if (rdev->family == CHIP_RV730) { + WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0x)); + WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0x)); + WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0x)); + } WREG32(CGTS_SYS_TCC_DISABLE, 0); WREG32(CGTS_TCC_DISABLE, 0); diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h index 162b177..6a52b20 100644 --- a/drivers/gpu/drm/radeon/rv770d.h +++ b/drivers/gpu/drm/radeon/rv770d.h @@ -136,6 +136,11 @@ #define DMA_TILING_CONFIG 0x3ec8 #define DMA_TILING_CONFIG2 0xd0b8 +/* RV730 only */ +#define UVD_UDEC_TILING_CONFIG 0xef40 +#define UVD_UDEC_DB_TILING_CONFIG 0xef44 +#define UVD_UDEC_DBW_TILING_CONFIG 0xef48 + #defineGC_USER_SHADER_PIPE_CONFIG 0x8954 #defineINACTIVE_QD_PIPES(x)((x) << 8) #defineINACTIVE_QD_PIPES_MASK 0xFF00 diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 472d9fb..34ffbcb 100644 --- a/dri
[PATCH 10/11] drm/radeon: init UVD clocks to sane defaults
Just until we get proper DPM for that. Signed-off-by: Christian König Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon_uvd.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 05a192e..30a9460 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c @@ -188,6 +188,8 @@ int radeon_uvd_resume(struct radeon_device *rdev) radeon_bo_unreserve(rdev->uvd.vcpu_bo); + radeon_set_uvd_clocks(rdev, 53300, 4); + return 0; } -- 1.7.9.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 09/11] drm/radeon: add set_uvd_clocks callback for r7xx v3
v2: avoid 64bit divide v3: rv740 uses the evegreen upll configuration Signed-off-by: Christian König Signed-off-by: Alex Deucher Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon_asic.c |1 + drivers/gpu/drm/radeon/radeon_asic.h |1 + drivers/gpu/drm/radeon/rv770.c | 156 ++ drivers/gpu/drm/radeon/rv770d.h | 24 ++ 4 files changed, 182 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 03228cb..19bf122 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1183,6 +1183,7 @@ static struct radeon_asic rv770_asic = { .get_pcie_lanes = &r600_get_pcie_lanes, .set_pcie_lanes = &r600_set_pcie_lanes, .set_clock_gating = &radeon_atom_set_clock_gating, + .set_uvd_clocks = &rv770_set_uvd_clocks, }, .pflip = { .pre_page_flip = &rs600_pre_page_flip, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 365c964..2add526 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -424,6 +424,7 @@ int rv770_copy_dma(struct radeon_device *rdev, struct radeon_fence **fence); u32 rv770_get_xclk(struct radeon_device *rdev); int rv770_uvd_resume(struct radeon_device *rdev); +int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); /* * evergreen diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index fb9a0b8..5ccc865 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -42,6 +42,162 @@ static void rv770_gpu_init(struct radeon_device *rdev); void rv770_fini(struct radeon_device *rdev); static void rv770_pcie_gen2_enable(struct radeon_device *rdev); +int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); + +static int rv770_uvd_calc_post_div(unsigned target_freq, + unsigned vco_freq, + unsigned *div) +{ + /* Fclk = Fvco / PDIV */ + *div = vco_freq / target_freq; + + /* we alway need a frequency less than or equal the target */ + if ((vco_freq / *div) > target_freq) + *div += 1; + + /* out of range ? */ + if (*div > 30) + return -1; /* forget it */ + + *div -= 1; + return vco_freq / (*div + 1); +} + +static int rv770_uvd_send_upll_ctlreq(struct radeon_device *rdev) +{ + unsigned i; + + /* assert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); + + /* wait for CTLACK and CTLACK2 to get asserted */ + for (i = 0; i < 100; ++i) { + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; + if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + /* deassert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + + return 0; +} + +int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) +{ + /* start off with something large */ + int optimal_diff_score = 0x7FF; + unsigned optimal_fb_div = 0, optimal_vclk_div = 0; + unsigned optimal_dclk_div = 0, optimal_vco_freq = 0; + unsigned vco_freq, vco_min = 5, vco_max = 16; + unsigned ref_freq = rdev->clock.spll.reference_freq; + int r; + + /* RV740 uses evergreen uvd clk programming */ + if (rdev->family == CHIP_RV740) + return evergreen_set_uvd_clocks(rdev, vclk, dclk); + + /* loop through vco from low to high */ + vco_min = max(max(vco_min, vclk), dclk); + for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) { + uint64_t fb_div = (uint64_t)vco_freq * 43663; + int calc_clk, diff_score, diff_vclk, diff_dclk; + unsigned vclk_div, dclk_div; + + do_div(fb_div, ref_freq); + fb_div |= 1; + + /* fb div out of range ? */ + if (fb_div > 0x03FF) + break; /* it can oly get worse */ + + /* calc vclk with current vco freq. */ + calc_clk = rv770_uvd_calc_post_div(vclk, vco_freq, &vclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_vclk = vclk - calc_clk; + + /* calc dclk with current vco freq. */ + calc_clk = rv770_uvd_calc_post_div(dclk, vco_freq, &dclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_dclk = dclk - calc_clk; + + /* determine if this vco setting is better than current op
[PATCH 08/11] drm/radeon: add set_uvd_clocks callback for SI
Signed-off-by: Christian König Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon_asic.c |1 + drivers/gpu/drm/radeon/radeon_asic.h |1 + drivers/gpu/drm/radeon/si.c | 167 ++ drivers/gpu/drm/radeon/sid.h | 29 ++ 4 files changed, 198 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index a65312c..03228cb 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1887,6 +1887,7 @@ static struct radeon_asic si_asic = { .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = NULL, + .set_uvd_clocks = &si_set_uvd_clocks, }, .pflip = { .pre_page_flip = &evergreen_pre_page_flip, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 54a7ef7..365c964 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -545,5 +545,6 @@ int si_copy_dma(struct radeon_device *rdev, void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); u32 si_get_xclk(struct radeon_device *rdev); uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); +int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); #endif diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index cc9fe39..472d9fb 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -4666,3 +4666,170 @@ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev) mutex_unlock(&rdev->gpu_clock_mutex); return clock; } + +static int si_uvd_calc_post_div(unsigned target_freq, + unsigned vco_freq, + unsigned *div) +{ + /* target larger than vco frequency ? */ + if (vco_freq < target_freq) + return -1; /* forget it */ + + /* Fclk = Fvco / PDIV */ + *div = vco_freq / target_freq; + + /* we alway need a frequency less than or equal the target */ + if ((vco_freq / *div) > target_freq) + *div += 1; + + /* dividers above 5 must be even */ + if (*div > 5 && *div % 2) + *div += 1; + + /* out of range ? */ + if (*div >= 128) + return -1; /* forget it */ + + return vco_freq / *div; +} + +static int si_uvd_send_upll_ctlreq(struct radeon_device *rdev) +{ + unsigned i; + + /* assert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); + + /* wait for CTLACK and CTLACK2 to get asserted */ + for (i = 0; i < 100; ++i) { + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; + if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + /* deassert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + + return 0; +} + +int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) +{ + /* start off with something large */ + int optimal_diff_score = 0x7FF; + unsigned optimal_fb_div = 0, optimal_vclk_div = 0; + unsigned optimal_dclk_div = 0, optimal_vco_freq = 0; + unsigned vco_freq; + int r; + + /* loop through vco from low to high */ + for (vco_freq = 125000; vco_freq <= 25; vco_freq += 100) { + unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384; + int calc_clk, diff_score, diff_vclk, diff_dclk; + unsigned vclk_div, dclk_div; + + /* fb div out of range ? */ + if (fb_div > 0x03FF) + break; /* it can oly get worse */ + + /* calc vclk with current vco freq. */ + calc_clk = si_uvd_calc_post_div(vclk, vco_freq, &vclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_vclk = vclk - calc_clk; + + /* calc dclk with current vco freq. */ + calc_clk = si_uvd_calc_post_div(dclk, vco_freq, &dclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_dclk = dclk - calc_clk; + + /* determine if this vco setting is better than current optimal settings */ + diff_score = abs(diff_vclk) + abs(diff_dclk); + if (diff_score < optimal_diff_score) { + optimal_fb_div = fb_div; + optimal_vclk_div = vclk_div; + optimal_dclk_div = dclk_div; + optimal_vco_freq = vco_freq; + optimal_diff_score = diff_score; +
[PATCH 07/11] drm/radeon: add set_uvd_clocks callback for evergreen
From: Alex Deucher v2: remove unneeded register definitions Signed-off-by: Alex Deucher Signed-off-by: Christian König Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/evergreen.c | 164 ++ drivers/gpu/drm/radeon/evergreend.h | 27 ++ drivers/gpu/drm/radeon/radeon_asic.c |3 + drivers/gpu/drm/radeon/radeon_asic.h |1 + 4 files changed, 195 insertions(+) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index bdd3d34..a6e7186 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -131,6 +131,170 @@ done: return r; } +static int evergreen_uvd_calc_post_div(unsigned target_freq, + unsigned vco_freq, + unsigned *div) +{ + /* target larger than vco frequency ? */ + if (vco_freq < target_freq) + return -1; /* forget it */ + + /* Fclk = Fvco / PDIV */ + *div = vco_freq / target_freq; + + /* we alway need a frequency less than or equal the target */ + if ((vco_freq / *div) > target_freq) + *div += 1; + + /* dividers above 5 must be even */ + if (*div > 5 && *div % 2) + *div += 1; + + /* out of range ? */ + if (*div >= 128) + return -1; /* forget it */ + + return vco_freq / *div; +} + +static int evergreen_uvd_send_upll_ctlreq(struct radeon_device *rdev) +{ + unsigned i; + + /* assert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); + + /* wait for CTLACK and CTLACK2 to get asserted */ + for (i = 0; i < 100; ++i) { + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; + if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + /* deassert UPLL_CTLREQ */ + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + + return 0; +} + +int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) +{ + /* start off with something large */ + int optimal_diff_score = 0x7FF; + unsigned optimal_fb_div = 0, optimal_vclk_div = 0; + unsigned optimal_dclk_div = 0, optimal_vco_freq = 0; + unsigned vco_freq; + int r; + + /* loop through vco from low to high */ + for (vco_freq = 125000; vco_freq <= 25; vco_freq += 100) { + unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384; + int calc_clk, diff_score, diff_vclk, diff_dclk; + unsigned vclk_div, dclk_div; + + /* fb div out of range ? */ + if (fb_div > 0x03FF) + break; /* it can oly get worse */ + + /* calc vclk with current vco freq. */ + calc_clk = evergreen_uvd_calc_post_div(vclk, vco_freq, &vclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_vclk = vclk - calc_clk; + + /* calc dclk with current vco freq. */ + calc_clk = evergreen_uvd_calc_post_div(dclk, vco_freq, &dclk_div); + if (calc_clk == -1) + break; /* vco is too big, it has to stop. */ + diff_dclk = dclk - calc_clk; + + /* determine if this vco setting is better than current optimal settings */ + diff_score = abs(diff_vclk) + abs(diff_dclk); + if (diff_score < optimal_diff_score) { + optimal_fb_div = fb_div; + optimal_vclk_div = vclk_div; + optimal_dclk_div = dclk_div; + optimal_vco_freq = vco_freq; + optimal_diff_score = diff_score; + if (optimal_diff_score == 0) + break; /* it can't get better than this */ + } + } + + /* set VCO_MODE to 1 */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); + + /* toggle UPLL_SLEEP to 1 then back to 0 */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); + + /* deassert UPLL_RESET */ + WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); + + mdelay(1); + + /* bypass vclk and dclk with bclk */ + WREG32_P(CG_UPLL_FUNC_CNTL_2, + VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), + ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); + + /* put PLL in bypass mode */ + WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); + + r = evergreen_uvd_send_upll_ctlreq(rdev); + if (r) + return r; + + /* assert UPLL_RESET again */ + WREG32_P
[PATCH 06/11] drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4)
From: Alex Deucher v2: write clk registers only once! v3: update cg scratch register properly v4: add TN support Signed-off-by: Alex Deucher Signed-off-by: Christian König Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/evergreen.c | 47 ++ drivers/gpu/drm/radeon/evergreend.h | 10 drivers/gpu/drm/radeon/radeon_asic.c |2 ++ drivers/gpu/drm/radeon/radeon_asic.h |1 + 4 files changed, 60 insertions(+) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 18b66ff..bdd3d34 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -84,6 +84,53 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, } } +static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock, + u32 cntl_reg, u32 status_reg) +{ + int r, i; + struct atom_clock_dividers dividers; + +r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + clock, false, ÷rs); + if (r) + return r; + + WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK)); + + for (i = 0; i < 100; i++) { + if (RREG32(status_reg) & DCLK_STATUS) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + return 0; +} + +int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) +{ + int r = 0; + u32 cg_scratch = RREG32(CG_SCRATCH1); + + r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS); + if (r) + goto done; + cg_scratch &= 0x; + cg_scratch |= vclk / 100; /* Mhz */ + + r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS); + if (r) + goto done; + cg_scratch &= 0x; + cg_scratch |= (dclk / 100) << 16; /* Mhz */ + +done: + WREG32(CG_SCRATCH1, cg_scratch); + + return r; +} + void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) { u16 ctl, v; diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index c5d873e..b6491a3 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -53,6 +53,16 @@ #define RCU_IND_INDEX 0x100 #define RCU_IND_DATA 0x104 +/* fusion uvd clocks */ +#define CG_DCLK_CNTL0x610 +# define DCLK_DIVIDER_MASK0x7f +# define DCLK_DIR_CNTL_EN (1 << 8) +#define CG_DCLK_STATUS 0x614 +# define DCLK_STATUS (1 << 0) +#define CG_VCLK_CNTL0x618 +#define CG_VCLK_STATUS 0x61c +#defineCG_SCRATCH1 0x820 + #define GRBM_GFX_INDEX 0x802C #defineINSTANCE_INDEX(x) ((x) << 0) #defineSE_INDEX(x) ((x) << 16) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index a7a7b2b..d3992d9 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1373,6 +1373,7 @@ static struct radeon_asic sumo_asic = { .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = NULL, + .set_uvd_clocks = &sumo_set_uvd_clocks, }, .pflip = { .pre_page_flip = &evergreen_pre_page_flip, @@ -1744,6 +1745,7 @@ static struct radeon_asic trinity_asic = { .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = NULL, + .set_uvd_clocks = &sumo_set_uvd_clocks, }, .pflip = { .pre_page_flip = &evergreen_pre_page_flip, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 515db96..37f28a3 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -459,6 +459,7 @@ extern void evergreen_pm_prepare(struct radeon_device *rdev); extern void evergreen_pm_finish(struct radeon_device *rdev); extern void sumo_pm_init_profile(struct radeon_device *rdev); extern void btc_pm_init_profile(struct radeon_device *rdev); +int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); -- 1.7.9.5 __
[PATCH 05/11] drm/radeon: add radeon_atom_get_clock_dividers helper
Signed-off-by: Christian König Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon.h |5 ++ drivers/gpu/drm/radeon/radeon_atombios.c | 107 ++ drivers/gpu/drm/radeon/radeon_mode.h | 23 +++ 3 files changed, 135 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 8c5b7e8..25b5b39 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -205,6 +205,11 @@ void radeon_pm_suspend(struct radeon_device *rdev); void radeon_pm_resume(struct radeon_device *rdev); void radeon_combios_get_power_modes(struct radeon_device *rdev); void radeon_atombios_get_power_modes(struct radeon_device *rdev); +int radeon_atom_get_clock_dividers(struct radeon_device *rdev, + u8 clock_type, + u32 clock, + bool strobe_mode, + struct atom_clock_dividers *dividers); void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); void rs690_pm_info(struct radeon_device *rdev); extern int rv6xx_get_temp(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index f22eb57..8c1779c 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -2654,6 +2654,113 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.current_vddc = 0; } +union get_clock_dividers { + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; +}; + +int radeon_atom_get_clock_dividers(struct radeon_device *rdev, + u8 clock_type, + u32 clock, + bool strobe_mode, + struct atom_clock_dividers *dividers) +{ + union get_clock_dividers args; + int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); + u8 frev, crev; + + memset(&args, 0, sizeof(args)); + memset(dividers, 0, sizeof(struct atom_clock_dividers)); + + if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) + return -EINVAL; + + switch (crev) { + case 1: + /* r4xx, r5xx */ + args.v1.ucAction = clock_type; + args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ + + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + + dividers->post_div = args.v1.ucPostDiv; + dividers->fb_div = args.v1.ucFbDiv; + dividers->enable_post_div = true; + break; + case 2: + case 3: + /* r6xx, r7xx, evergreen, ni */ + if (rdev->family <= CHIP_RV770) { + args.v2.ucAction = clock_type; + args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ + + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + + dividers->post_div = args.v2.ucPostDiv; + dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); + dividers->ref_div = args.v2.ucAction; + if (rdev->family == CHIP_RV770) { + dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? + true : false; + dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; + } else + dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; + } else { + if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { + args.v3.ulClock.ulComputeClockFlag = clock_type; + args.v3.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ + + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + + dividers->post_div = args.v3.ucPostDiv; + dividers->enable_post_div = (args.v3.ucCntlFlag & + ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; + dividers->enable_dithen = (args.v3.ucCntlFlag & + ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; + dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDi
[PATCH 04/11] drm/radeon: add pm callback for setting uvd clocks
From: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Christian König Reviewed-by: Jerome Glisse --- drivers/gpu/drm/radeon/radeon.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 051b8fd..8c5b7e8 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1313,6 +1313,7 @@ struct radeon_asic { int (*get_pcie_lanes)(struct radeon_device *rdev); void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); void (*set_clock_gating)(struct radeon_device *rdev, int enable); + int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); } pm; /* pageflipping */ struct { @@ -1879,6 +1880,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) +#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) -- 1.7.9.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 02/11] drm/radeon: rework fallback handling
From: Christian König Let the CS module decide if we can fall back to VRAM or not. Signed-off-by: Christian König --- drivers/gpu/drm/radeon/radeon.h|5 ++-- drivers/gpu/drm/radeon/radeon_cs.c | 51 ++-- drivers/gpu/drm/radeon/radeon_object.c |8 ++--- 3 files changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 8263af3..7c2498c 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -357,8 +357,9 @@ struct radeon_bo_list { struct ttm_validate_buffer tv; struct radeon_bo*bo; uint64_tgpu_offset; - unsignedrdomain; - unsignedwdomain; + boolwritten; + unsigneddomain; + unsignedalt_domain; u32 tiling_flags; }; diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index a3dd04d..8223cf8 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -53,6 +53,7 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) } for (i = 0; i < p->nrelocs; i++) { struct drm_radeon_cs_reloc *r; + uint32_t domain; duplicate = false; r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; @@ -63,30 +64,36 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) break; } } - if (!duplicate) { - p->relocs[i].gobj = drm_gem_object_lookup(ddev, - p->filp, - r->handle); - if (p->relocs[i].gobj == NULL) { - DRM_ERROR("gem object lookup failed 0x%x\n", - r->handle); - return -ENOENT; - } - p->relocs_ptr[i] = &p->relocs[i]; - p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); - p->relocs[i].lobj.bo = p->relocs[i].robj; - p->relocs[i].lobj.wdomain = r->write_domain; - p->relocs[i].lobj.rdomain = r->read_domains; - p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; - p->relocs[i].handle = r->handle; - p->relocs[i].flags = r->flags; - radeon_bo_list_add_object(&p->relocs[i].lobj, - &p->validated); - - } else + if (duplicate) { p->relocs[i].handle = 0; + continue; + } + + p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, + r->handle); + if (p->relocs[i].gobj == NULL) { + DRM_ERROR("gem object lookup failed 0x%x\n", + r->handle); + return -ENOENT; + } + p->relocs_ptr[i] = &p->relocs[i]; + p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); + p->relocs[i].lobj.bo = p->relocs[i].robj; + p->relocs[i].lobj.written = !!r->write_domain; + + domain = r->write_domain ? r->write_domain : r->read_domains; + p->relocs[i].lobj.domain = domain; + if (domain == RADEON_GEM_DOMAIN_VRAM) + domain |= RADEON_GEM_DOMAIN_GTT; + p->relocs[i].lobj.alt_domain = domain; + + p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; + p->relocs[i].handle = r->handle; + + radeon_bo_list_add_object(&p->relocs[i].lobj, + &p->validated); } - return radeon_bo_list_validate(&p->validated); + return radeon_bo_list_validate(&p->validated, p->ring); } static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index d3aface..9633325 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -339,7 +339,7 @@ void radeon_bo_fini(struct radeon_device *rdev) void radeon_bo_list_add_object(struct radeon_bo_list *lobj, struct list_head *head) { - if (lobj->wdomain) { + if (lobj->written) { list_add(&lobj->tv.head, head); } else { list_add_tail(&lobj->tv.head, head); @@ -360,15 +360,15 @@ int radeon_bo_list_validate(struc
[PATCH 00/11] drm/radeon: basic UVD support v2
Hello everyone, This is the second round of this patchset. Do to public demand I uploaded this patchset as branch uvd-3.9 to git://people.freedesktop.org/~deathsimple/linux. Compared to the first round I changed the error message in patch #1, patch #2 was split out of patch #3 and patch #3 itself got buffer size checking and a few minor bugfixes. The other patches are unchanged. Please review, Christian. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 01/11] drm/radeon: UVD doesn't needs VM on SI v2
v2: update error message and comment Signed-off-by: Christian König --- drivers/gpu/drm/radeon/radeon_cs.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 70d3824..a3dd04d 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -241,15 +241,15 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) return -EINVAL; } - /* we only support VM on SI+ */ - if ((p->rdev->family >= CHIP_TAHITI) && - ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { - DRM_ERROR("VM required on SI+!\n"); + if (radeon_cs_get_ring(p, ring, priority)) return -EINVAL; - } - if (radeon_cs_get_ring(p, ring, priority)) + /* we only support VM on some SI+ rings */ + if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) && + ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { + DRM_ERROR("Ring %d requires VM!\n", p->ring); return -EINVAL; + } } /* deal with non-vm */ -- 1.7.9.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
system death under oom - 3.7.9
On Sat, Apr 6, 2013 at 5:01 AM, Ilia Mirkin wrote: > On Mon, Apr 1, 2013 at 4:14 PM, Christoph Lameter wrote: >> On Wed, 27 Mar 2013, Ilia Mirkin wrote: >> >>> The GPF happens at +160, which is in the argument setup for the >>> cmpxchg in slab_alloc_node. I think it's the call to >>> get_freepointer(). There was a similar bug report a while back, >>> https://lkml.org/lkml/2011/5/23/199, and the recommendation was to run >>> with slub debugging. Is that still the case, or is there a simpler >>> explanation? I can't reproduce this at will, not sure how many times >>> this has happened but definitely not many. >> >> slub debugging will help to track down the cause of the memory corruption. > > OK, with slub_debug=FZP, I get (after a while): > > http://pastebin.com/cbHiKhdq > > Which definitely makes it look like something in the nouveau > context/whatever alloc failure path causes some stomping to happen. (I > don't suppose it's reasonable to warn when the stomping happens > through some sort of page protection... would explode the size since > each n-byte object would be at least 4K, but might be worth it for > debugging...) OK, after staring for a while at this code, I found an issue, and looks like it's already fixed by cfd376b6bfccf33782a0748a9c70f7f752f8b869 (drm/nouveau/vm: fix memory corruption when pgt allocation fails), which didn't make it into 3.7.9, but is in 3.7.10. Time to upgrade, I guess. Thanks for the various suggestions.
system death under oom - 3.7.9
On Mon, Apr 1, 2013 at 4:14 PM, Christoph Lameter wrote: > On Wed, 27 Mar 2013, Ilia Mirkin wrote: > >> The GPF happens at +160, which is in the argument setup for the >> cmpxchg in slab_alloc_node. I think it's the call to >> get_freepointer(). There was a similar bug report a while back, >> https://lkml.org/lkml/2011/5/23/199, and the recommendation was to run >> with slub debugging. Is that still the case, or is there a simpler >> explanation? I can't reproduce this at will, not sure how many times >> this has happened but definitely not many. > > slub debugging will help to track down the cause of the memory corruption. OK, with slub_debug=FZP, I get (after a while): http://pastebin.com/cbHiKhdq Which definitely makes it look like something in the nouveau context/whatever alloc failure path causes some stomping to happen. (I don't suppose it's reasonable to warn when the stomping happens through some sort of page protection... would explode the size since each n-byte object would be at least 4K, but might be worth it for debugging...)
Re: system death under oom - 3.7.9
On Sat, Apr 6, 2013 at 5:01 AM, Ilia Mirkin wrote: > On Mon, Apr 1, 2013 at 4:14 PM, Christoph Lameter wrote: >> On Wed, 27 Mar 2013, Ilia Mirkin wrote: >> >>> The GPF happens at +160, which is in the argument setup for the >>> cmpxchg in slab_alloc_node. I think it's the call to >>> get_freepointer(). There was a similar bug report a while back, >>> https://lkml.org/lkml/2011/5/23/199, and the recommendation was to run >>> with slub debugging. Is that still the case, or is there a simpler >>> explanation? I can't reproduce this at will, not sure how many times >>> this has happened but definitely not many. >> >> slub debugging will help to track down the cause of the memory corruption. > > OK, with slub_debug=FZP, I get (after a while): > > http://pastebin.com/cbHiKhdq > > Which definitely makes it look like something in the nouveau > context/whatever alloc failure path causes some stomping to happen. (I > don't suppose it's reasonable to warn when the stomping happens > through some sort of page protection... would explode the size since > each n-byte object would be at least 4K, but might be worth it for > debugging...) OK, after staring for a while at this code, I found an issue, and looks like it's already fixed by cfd376b6bfccf33782a0748a9c70f7f752f8b869 (drm/nouveau/vm: fix memory corruption when pgt allocation fails), which didn't make it into 3.7.9, but is in 3.7.10. Time to upgrade, I guess. Thanks for the various suggestions. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Graphics and Display Microconference @LPC2013
Hello everybody, I've submitted a graphics and display microconference for the Linux Plumbers Conference 2013, and just realized that I haven't announced the proposal on the dri-devel and linux-fbdev mailing lists. The proposal is available at http://wiki.linuxplumbersconf.org/2013:graphics_and_display. Please send me feedback on the proposed topics, and add your name to the attendees list if you plan to participate. -- Regards, Laurent Pinchart
[Bug 55941] Hybrid graphics i915/radeon. Switch to radeon results to black screen
https://bugzilla.kernel.org/show_bug.cgi?id=55941 --- Comment #5 from laurent.debian at gmail.com 2013-04-06 02:03:48 --- By the way this it should be the duplicated of Bug 55311. -- Configure bugmail: https://bugzilla.kernel.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are watching the assignee of the bug.
Re: system death under oom - 3.7.9
On Mon, Apr 1, 2013 at 4:14 PM, Christoph Lameter wrote: > On Wed, 27 Mar 2013, Ilia Mirkin wrote: > >> The GPF happens at +160, which is in the argument setup for the >> cmpxchg in slab_alloc_node. I think it's the call to >> get_freepointer(). There was a similar bug report a while back, >> https://lkml.org/lkml/2011/5/23/199, and the recommendation was to run >> with slub debugging. Is that still the case, or is there a simpler >> explanation? I can't reproduce this at will, not sure how many times >> this has happened but definitely not many. > > slub debugging will help to track down the cause of the memory corruption. OK, with slub_debug=FZP, I get (after a while): http://pastebin.com/cbHiKhdq Which definitely makes it look like something in the nouveau context/whatever alloc failure path causes some stomping to happen. (I don't suppose it's reasonable to warn when the stomping happens through some sort of page protection... would explode the size since each n-byte object would be at least 4K, but might be worth it for debugging...) ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4] drm: Add struct drm_rect and assorted utility functions
Hi Ville, Thanks for the patch. On Friday 05 April 2013 16:19:36 ville.syrjala at linux.intel.com wrote: > From: Ville Syrj?l? > > struct drm_rect represents a simple rectangle. The utility > functions are there to help driver writers. > > v2: Moved the region stuff into its own file, made the smaller funcs > static inline, used 64bit maths in the scaled clipping function to > avoid overflows (instead it will saturate to INT_MIN or INT_MAX). > v3: Renamed drm_region to drm_rect, drm_region_clip to > drm_rect_intersect, and drm_region_subsample to drm_rect_downscale. > v4: Renamed some function parameters, improve kernel-doc comments a bit, > and actually generate documentation for drm_rect.[ch]. > > Signed-off-by: Ville Syrj?l? > --- > Documentation/DocBook/drm.tmpl | 2 + > drivers/gpu/drm/Makefile | 3 +- > drivers/gpu/drm/drm_rect.c | 96 ++ > include/drm/drm_rect.h | 132 ++ > 4 files changed, 232 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/drm_rect.c > create mode 100644 include/drm/drm_rect.h [snip] > diff --git a/drivers/gpu/drm/drm_rect.c b/drivers/gpu/drm/drm_rect.c > new file mode 100644 > index 000..a9861bd > --- /dev/null > +++ b/drivers/gpu/drm/drm_rect.c [snip] > +/** > + * drm_rect_clip_scaled - perform a scaled clip operation > + * @src: source window rectangle > + * @dst: destination window rectangle > + * @clip: clip rectangle > + * @hscale: horizontal scaling factor > + * @vscale: vertical scaling factor > + * > + * Clip rectangle @dst by rectangle @clip. Clip rectangle @src by the > + * same amounts multiplied by @hscale and @vscale. > + * > + * RETUTRNS: s/RETUTRNS/RETURNS/ > + * %true if rectangle @dst is still visible after being clipped, > + * %false otherwise > + */ Otherwise, Reviewed-by: Laurent Pinchart -- Regards, Laurent Pinchart
[Bug 55941] Hybrid graphics i915/radeon. Switch to radeon results to black screen
https://bugzilla.kernel.org/show_bug.cgi?id=55941 laurent.debian at gmail.com changed: What|Removed |Added CC||laurent.debian at gmail.com --- Comment #4 from laurent.debian at gmail.com 2013-04-06 01:55:28 --- I have been very puzzled when reading your last message Alex, since I got (on debian) the exact same problem with a Mux system intel Ironlake/radeon Hd5650. The same issue occurs with kernel 3.7.6 (compiled by me) while the switch works correctly one the "distrib" kernel 3.2.0-4-ppae. Another issue appears with kernel 3.8.5 (with the NEW default modesetting bla for radeon..) but in that case X seems to crash (well i don't really now what's happening only got the little "-" on the top left of my screen) I would be glad to give any addiotionnal infos relevant or to file a bug myself. (In reply to comment #3) > You have a muxless powerxpress system so there are no displays physically > connected to the radeon card. The only way to utilize the radeon card is for > offscreen rendering (radeon renders application frame and the frame is copied > to the intel card for display). You need the new gpu hotplug features in > xserver 1.13.x or 1.14 to utilize the card in that manner. -- Configure bugmail: https://bugzilla.kernel.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are watching the assignee of the bug.
[Bug 61182] r600g causes KWin crashes with kernel 3.8
https://bugs.freedesktop.org/show_bug.cgi?id=61182 --- Comment #29 from Marek Ol??k --- r600g crashes because it's mapping a MSAA resource in order to clear the CMASK to zeros. The problem is MSAA resources occupy a lot of memory and the system is failing to map the whole resource. The solution is easy: we should clear the CMASK and HTILE buffers using DMA or streamout and not with the CPU. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20130406/3d1640b5/attachment.html>
[Bug 49981] On HD6850, Power Profile doesn't change if 2 screen is attached.
https://bugs.freedesktop.org/show_bug.cgi?id=49981 --- Comment #32 from Benjamin Lee --- On my TURKS chip (HD 6750M) the radeon_pm_print_states() output shows that I should be using POWER_STATE_TYPE_POWERSAVE instead of POWER_STATE_TYPE_BATTERY. I don't know if this is true for all TURKS chips or what other chips are affected, but the following patch against 3.9-rc5 fixes power profiles on my MacBookPro8,2. diff -ruN linux-3.9-rc5.orig/drivers/gpu/drm/radeon/evergreen.c linux-3.9-rc5/drivers/gpu/drm/radeon/evergreen.c --- linux-3.9-rc5.orig/drivers/gpu/drm/radeon/evergreen.c 2013-03-31 15:12:43.0 -0700 +++ linux-3.9-rc5/drivers/gpu/drm/radeon/evergreen.c2013-04-05 17:45:04.179779729 -0700 @@ -343,7 +343,9 @@ * MH and SH. Difference is that we always use the high clock index for * mclk. */ - if (rdev->flags & RADEON_IS_MOBILITY) + if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_TURKS)) + idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_POWERSAVE, 0); + else if (rdev->flags & RADEON_IS_MOBILITY) idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); else idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20130406/2db48b4e/attachment.html>
[Bug 61182] r600g causes KWin crashes with kernel 3.8
1 0x447e3163 in KWin::EffectsHandlerImpl::paintScreen (this=0x94d9ff0, mask=0, region=..., data=...) at /usr/src/debug/kde-workspace-4.10.2/kwin/effects.cpp:254 #32 0x447be77f in KWin::Scene::paintScreen (this=0x93b0348, mask=0xbfc4bc0c, region=0xbfc4bc7c) at /usr/src/debug/kde-workspace-4.10.2/kwin/scene.cpp:140 #33 0x447cfe6b in KWin::SceneOpenGL::paint (this=0x93b0348, damage=..., toplevels=...) at /usr/src/debug/kde-workspace-4.10.2/kwin/scene_opengl.cpp:308 #34 0x447b7a68 in KWin::Compositor::performCompositing (this=this at entry=0x92e0d20) at /usr/src/debug/kde-workspace-4.10.2/kwin/composite.cpp:610 #35 0x447b85f3 in KWin::Compositor::slotCompositingOptionsInitialized (this=0x92e0d20) at /usr/src/debug/kde-workspace-4.10.2/kwin/composite.cpp:275 #36 0x447334d8 in qt_static_metacall (_c=QMetaObject::InvokeMetaMethod, _a=0xbfc4befc, _id=14, _o=0x92e0d20) at /usr/src/debug/kde-workspace-4.10.2/i686-redhat-linux-gnu/kwin/moc_composite.cpp:112 #37 KWin::Compositor::qt_static_metacall (_o=0x92e0d20, _c=QMetaObject::InvokeMetaMethod, _id=14, _a=0xbfc4befc) at /usr/src/debug/kde-workspace-4.10.2/i686-redhat-linux-gnu/kwin/moc_composite.cpp:92 #38 0x4222328e in QMetaObject::activate (sender=0x9294a10, m=0x42376d60 , local_signal_index=1, argv=0x0) at kernel/qobject.cpp:3539 #39 0x422728e6 in QFutureWatcherBase::finished (this=0x9294a10) at .moc/release-shared/moc_qfuturewatcher.cpp:140 #40 0x420e56ec in QFutureWatcherBasePrivate::sendCallOutEvent (this=this at entry=0x9304420, event=event at entry=0xb4000468) at concurrent/qfuturewatcher.cpp:439 #41 0x420e59f2 in QFutureWatcherBase::event (this=0x9294a10, event=0xb4000468) at concurrent/qfuturewatcher.cpp:344 #42 0x4273306c in QApplicationPrivate::notify_helper (this=0x9178238, receiver=0x9294a10, e=0xb4000468) at kernel/qapplication.cpp:4562 #43 0x42737b2f in QApplication::notify (this=0xb4000468, receiver=0x9294a10, e=0xb4000468) at kernel/qapplication.cpp:3944 #44 0x4760e5c2 in KApplication::notify (this=0xbfc4c778, receiver=0x9294a10, event=0xb4000468) at /usr/src/debug/kdelibs-4.10.2/kdeui/kernel/kapplication.cpp:311 #45 0x447603e0 in notify (e=0xb4000468, o=0x9294a10, this=0xbfc4c778) at /usr/src/debug/kde-workspace-4.10.2/kwin/main.cpp:371 #46 KWin::Application::notify (this=0xbfc4c778, o=0x9294a10, e=0xb4000468) at /usr/src/debug/kde-workspace-4.10.2/kwin/main.cpp:367 #47 0x4220c0be in QCoreApplication::notifyInternal (this=0xbfc4c778, receiver=0x9294a10, event=0xb4000468) at kernel/qcoreapplication.cpp:946 #48 0x42210065 in sendEvent (event=, receiver=) at kernel/qcoreapplication.h:231 #49 QCoreApplicationPrivate::sendPostedEvents (receiver=0x0, event_type=0, data=0x9120e58) at kernel/qcoreapplication.cpp:1570 #50 0x422102ed in QCoreApplication::sendPostedEvents (receiver=0x0, event_type=0) at kernel/qcoreapplication.cpp:1463 #51 0x427e65ae in sendPostedEvents () at ../../src/corelib/kernel/qcoreapplication.h:236 #52 QEventDispatcherX11::processEvents (this=0x9121c08, flags=...) at kernel/qeventdispatcher_x11.cpp:75 #53 0x4220ab5d in QEventLoop::processEvents (this=this at entry=0xbfc4c5f8, flags=...) at kernel/qeventloop.cpp:149 #54 0x4220ae59 in QEventLoop::exec (this=0xbfc4c5f8, flags=...) at kernel/qeventloop.cpp:204 #55 0x4221039b in QCoreApplication::exec () at kernel/qcoreapplication.cpp:1218 #56 0x42730ee5 in QApplication::exec () at kernel/qapplication.cpp:3823 #57 0x44762e95 in kdemain (argc=1, argv=0xbfc4c864) at /usr/src/debug/kde-workspace-4.10.2/kwin/main.cpp:537 #58 0x080487dc in main (argc=1, argv=0xbfc4c864) at /usr/src/debug/kde-workspace-4.10.2/i686-redhat-linux-gnu/kwin/kwin_dummy.cpp:3 Bisect pointed to the same commit as above: 35840ab189595b817fa8b1a1df8cc92474a7c38d is the first bad commit commit 35840ab189595b817fa8b1a1df8cc92474a7c38d Author: Marek Ol??k Date: Mon Dec 3 05:36:08 2012 +0100 -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20130406/f41ff48c/attachment-0001.html>
[Bug 63192] New: [nouveau] drmModeSetCursor->nouveau_bo_rd32->ioread32 provides high cpu load when using weston drm-compositor
https://bugs.freedesktop.org/show_bug.cgi?id=63192 Priority: medium Bug ID: 63192 Assignee: dri-devel at lists.freedesktop.org Summary: [nouveau] drmModeSetCursor->nouveau_bo_rd32->ioread32 provides high cpu load when using weston drm-compositor Severity: normal Classification: Unclassified OS: Linux (All) Reporter: vova7890 at mail.ru Hardware: x86-64 (AMD64) Status: NEW Version: DRI CVS Component: DRM/other Product: DRI Weston runned in drm-mode provide very high cpu load on mouse moving. I don`t think that the bug of weston, seems problem in nouveau drm. At launch weston have a log: ... [24465.734894] nouveau W[ PFIFO][:02:00.0] INTR 0x0001: 0x0004 [24465.748153] nouveau W[ PFIFO][:02:00.0] INTR 0x0001: 0x0004 [24521.950788] nouveau W[ PFIFO][:02:00.0] INTR 0x0001: 0x0004 [24521.955032] nouveau W[ PFIFO][:02:00.0] INTR 0x0001: 0x0004 ... ioread32_native(ioread32 on litle-endian) using 100% of cpu core. If in weston comment out drmModeSetCursor - cpu load is normal, but no see cursor ofcourse. They copying cursor(64x64) from bo-object. Seems TTM iomem access provide very high cpu load... On radeon it works smoothly and no have very high cpu load. Kernel 3.9-rc5 (x86_64) Wayland/Weston: git Mesa: git libdrm: git -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20130406/94746016/attachment.html>