On Fri, Mar 23, 2018 at 12:49:49PM +0530, Sharat Masetty wrote:
> Add the registers needed for configuring the system cache slice info and
> other parameters in the GPU.
>
Reviewed-by: Jordan Crouse
> Signed-off-by: Sharat Masetty
> ---
> drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> index 17d1241..29ce813 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> @@ -1596,5 +1596,9 @@ static inline uint32_t
> A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
>
> #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x000a
>
> +#define REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0 0x0001
> +
> +#define REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1 0x0002
> +
>
> #endif /* A6XX_XML */
> --
> 1.9.1
>
> ___
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> freedr...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
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