RE: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC
> -Original Message- > From: Jani Nikula > Sent: Wednesday, March 8, 2023 4:57 PM > To: Shankar, Uma ; Kandpal, Suraj > ; dri-devel@lists.freedesktop.org; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for > DSC > > On Wed, 08 Mar 2023, "Shankar, Uma" wrote: > >> -Original Message- > >> From: Kandpal, Suraj > >> Sent: Wednesday, February 22, 2023 11:02 AM > >> To: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org > >> Cc: Shankar, Uma ; Nautiyal, Ankit K > >> ; Kandpal, Suraj > >> ; Kulkarni, Vandita > >> > >> Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC > > > > Nit: drm/i915/dsc would be better. > > > > Looks Good to me. > > Reviewed-by: Uma Shankar > > Except since c3f059483671 ("drm/i915/display: split out DSC and DSS > registers") the DSC registers need to go to display/intel_vdsc_regs.h. Oh ok, thanks Jani for spotting it. Regards, Uma Shankar > BR, > Jani. > > > > >> Adding new DSC register which are introducted MTL onwards > >> > >> Signed-off-by: Suraj Kandpal > >> Reviewed-by: Vandita Kulkarni > >> --- > >> drivers/gpu/drm/i915/i915_reg.h | 28 > >> 1 file changed, 28 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h > >> b/drivers/gpu/drm/i915/i915_reg.h index 596efc940ee7..9e25e21d37e4 > >> 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -7715,6 +7715,8 @@ enum skl_power_gate { > >> #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) > _MMIO_PIPE((pipe) - > >> PIPE_B, \ > >> > >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ > >> > >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) > >> +#define DSC_NATIVE_422_ENABLEBIT(23) > >> +#define DSC_NATIVE_420_ENABLEBIT(22) > >> #define DSC_ALT_ICH_SEL (1 << 20) > >> #define DSC_VBR_ENABLE (1 << 19) > >> #define DSC_422_ENABLE (1 << 18) > >> @@ -7959,6 +7961,32 @@ enum skl_power_gate { > >> #define DSC_SLICE_PER_LINE(slice_per_line) > >> ((slice_per_line) << 16) > >> #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) > >> ((slice_chunk_size) > >> << 0) > >> > >> +/* MTL Display Stream Compression registers */ > >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4 > >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4 > >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4 > >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4 > >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) > >>_MMIO_PIPE((pipe) - PIPE_B, \ > >> + > >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \ > >> + > >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC) > >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) > >>_MMIO_PIPE((pipe) - PIPE_B, \ > >> + > >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \ > >> + > >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC) > >> +#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27) > >> + > >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8 > >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8 > >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8 > >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8 > >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) > >>_MMIO_PIPE((pipe) - PIPE_B, \ > >> + > >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \ > >> + > >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC) > >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) > >>_MMIO_PIPE((pipe) - PIPE_B, \ > >> + > >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \ > >> + > >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC) > >> +#define DSC_NSL_BPG_OFFSET(offset)((offset) << 16) > >> +#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0) > >> + > >> /* Icelake Rate Control Buffer Threshold Registers */ > >> #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) > >> #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) > >> -- > >> 2.25.1 > > > > -- > Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC
On Wed, 08 Mar 2023, "Shankar, Uma" wrote: >> -Original Message- >> From: Kandpal, Suraj >> Sent: Wednesday, February 22, 2023 11:02 AM >> To: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org >> Cc: Shankar, Uma ; Nautiyal, Ankit K >> ; Kandpal, Suraj ; >> Kulkarni, >> Vandita >> Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC > > Nit: drm/i915/dsc would be better. > > Looks Good to me. > Reviewed-by: Uma Shankar Except since c3f059483671 ("drm/i915/display: split out DSC and DSS registers") the DSC registers need to go to display/intel_vdsc_regs.h. BR, Jani. > >> Adding new DSC register which are introducted MTL onwards >> >> Signed-off-by: Suraj Kandpal >> Reviewed-by: Vandita Kulkarni >> --- >> drivers/gpu/drm/i915/i915_reg.h | 28 >> 1 file changed, 28 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h >> b/drivers/gpu/drm/i915/i915_reg.h >> index 596efc940ee7..9e25e21d37e4 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -7715,6 +7715,8 @@ enum skl_power_gate { >> #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - >> PIPE_B, \ >> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ >> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) >> +#define DSC_NATIVE_422_ENABLE BIT(23) >> +#define DSC_NATIVE_420_ENABLE BIT(22) >> #define DSC_ALT_ICH_SEL(1 << 20) >> #define DSC_VBR_ENABLE (1 << 19) >> #define DSC_422_ENABLE (1 << 18) >> @@ -7959,6 +7961,32 @@ enum skl_power_gate { >> #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) >> #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) >> ((slice_chunk_size) >> << 0) >> >> +/* MTL Display Stream Compression registers */ >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4 >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4 >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4 >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4 >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) >> _MMIO_PIPE((pipe) - PIPE_B, \ >> + >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \ >> + >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC) >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) >> _MMIO_PIPE((pipe) - PIPE_B, \ >> + >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \ >> + >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC) >> +#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27) >> + >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8 >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8 >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8 >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8 >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) >> _MMIO_PIPE((pipe) - PIPE_B, \ >> + >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \ >> + >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC) >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) >> _MMIO_PIPE((pipe) - PIPE_B, \ >> + >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \ >> + >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC) >> +#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16) >> +#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0) >> + >> /* Icelake Rate Control Buffer Threshold Registers */ >> #define DSCA_RC_BUF_THRESH_0_MMIO(0x6B230) >> #define DSCA_RC_BUF_THRESH_0_UDW_MMIO(0x6B230 + 4) >> -- >> 2.25.1 > -- Jani Nikula, Intel Open Source Graphics Center
RE: [PATCH 3/7] drm/i915: Adding the new registers for DSC
> -Original Message- > From: Kandpal, Suraj > Sent: Wednesday, February 22, 2023 11:02 AM > To: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org > Cc: Shankar, Uma ; Nautiyal, Ankit K > ; Kandpal, Suraj ; > Kulkarni, > Vandita > Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC Nit: drm/i915/dsc would be better. Looks Good to me. Reviewed-by: Uma Shankar > Adding new DSC register which are introducted MTL onwards > > Signed-off-by: Suraj Kandpal > Reviewed-by: Vandita Kulkarni > --- > drivers/gpu/drm/i915/i915_reg.h | 28 > 1 file changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 596efc940ee7..9e25e21d37e4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7715,6 +7715,8 @@ enum skl_power_gate { > #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - > PIPE_B, \ > > _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ > > _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) > +#define DSC_NATIVE_422_ENABLE BIT(23) > +#define DSC_NATIVE_420_ENABLE BIT(22) > #define DSC_ALT_ICH_SEL (1 << 20) > #define DSC_VBR_ENABLE (1 << 19) > #define DSC_422_ENABLE (1 << 18) > @@ -7959,6 +7961,32 @@ enum skl_power_gate { > #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) > #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) > ((slice_chunk_size) > << 0) > > +/* MTL Display Stream Compression registers */ > +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB0x782B4 > +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB0x783B4 > +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC0x784B4 > +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC0x785B4 > +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) > _MMIO_PIPE((pipe) - PIPE_B, \ > + > _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \ > + > _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC) > +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) > _MMIO_PIPE((pipe) - PIPE_B, \ > + > _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \ > + > _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC) > +#define DSC_SL_BPG_OFFSET(offset)((offset) << 27) > + > +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB0x782B8 > +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB0x783B8 > +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC0x784B8 > +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC0x785B8 > +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) > _MMIO_PIPE((pipe) - PIPE_B, \ > + > _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \ > + > _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC) > +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) > _MMIO_PIPE((pipe) - PIPE_B, \ > + > _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \ > + > _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC) > +#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16) > +#define DSC_SL_OFFSET_ADJ(offset)((offset) << 0) > + > /* Icelake Rate Control Buffer Threshold Registers */ > #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) > #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) > -- > 2.25.1
[PATCH 3/7] drm/i915: Adding the new registers for DSC
Adding new DSC register which are introducted MTL onwards Signed-off-by: Suraj Kandpal Reviewed-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_reg.h | 28 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 596efc940ee7..9e25e21d37e4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7715,6 +7715,8 @@ enum skl_power_gate { #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) +#define DSC_NATIVE_422_ENABLE BIT(23) +#define DSC_NATIVE_420_ENABLE BIT(22) #define DSC_ALT_ICH_SEL (1 << 20) #define DSC_VBR_ENABLE(1 << 19) #define DSC_422_ENABLE(1 << 18) @@ -7959,6 +7961,32 @@ enum skl_power_gate { #define DSC_SLICE_PER_LINE(slice_per_line)((slice_per_line) << 16) #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) +/* MTL Display Stream Compression registers */ +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4 +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4 +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4 +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4 +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)_MMIO_PIPE((pipe) - PIPE_B, \ + _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \ + _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC) +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)_MMIO_PIPE((pipe) - PIPE_B, \ + _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \ + _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC) +#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27) + +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8 +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8 +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8 +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8 +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)_MMIO_PIPE((pipe) - PIPE_B, \ + _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \ + _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC) +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)_MMIO_PIPE((pipe) - PIPE_B, \ + _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \ + _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC) +#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16) +#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0) + /* Icelake Rate Control Buffer Threshold Registers */ #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) -- 2.25.1