subject:"\\\[PATCH v2 5\\\/7\\\] drm\\\/msm\\\/adreno\\\: Add A702 support"

Re: [PATCH v2 5/7] drm/msm/adreno: Add A702 support

2024-06-06 Thread Konrad Dybcio

On 23.05.2024 2:14 PM, Connor Abbott wrote:
> On Fri, Feb 23, 2024 at 9:28 PM Konrad Dybcio  
> wrote:
>>
>> The A702 is a weird mix of 600 and 700 series.. Perhaps even a
>> testing ground for some A7xx features with good ol' A6xx silicon.
>> It's basically A610 that's been beefed up with some new registers
>> and hw features (like APRIV!), that was then cut back in size,
>> memory bus and some other ways.
>>
>> Add support for it, tested with QCM2290 / RB1.
>>
>> Signed-off-by: Konrad Dybcio 
>> ---

[...]

>> +
>> +   if (adreno_is_a702(gpu)) {
>> +   gpu->ubwc_config.highest_bank_bit = 14;
>> +   gpu->ubwc_config.min_acc_len = 1;
>> +   gpu->ubwc_config.ubwc_mode = 2;
> 
> I just noticed, but this is wrong. ubwc_mode is a 1 bit field and what
> this is actually doing is overwriting hbb_lo, making the highest bank
> bit 15 instead of 14.

You're right, this should be a 0. Thanks!

Konrad

Re: [PATCH v2 5/7] drm/msm/adreno: Add A702 support

2024-05-23 Thread Connor Abbott

On Fri, Feb 23, 2024 at 9:28 PM Konrad Dybcio  wrote:
>
> The A702 is a weird mix of 600 and 700 series.. Perhaps even a
> testing ground for some A7xx features with good ol' A6xx silicon.
> It's basically A610 that's been beefed up with some new registers
> and hw features (like APRIV!), that was then cut back in size,
> memory bus and some other ways.
>
> Add support for it, tested with QCM2290 / RB1.
>
> Signed-off-by: Konrad Dybcio 
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c  | 92 
> +++---
>  drivers/gpu/drm/msm/adreno/adreno_device.c | 18 ++
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h| 16 +-
>  3 files changed, 117 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index c9c55e2ea584..2a491a486ca1 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -837,6 +837,65 @@ const struct adreno_reglist a690_hwcg[] = {
> {}
>  };
>
> +const struct adreno_reglist a702_hwcg[] = {
> +   { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0220 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x0081 },
> +   { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0xf3cf },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x0002 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x0001 },
> +   { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x0007 },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x0120 },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x2220 },
> +   { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
> +   { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x0011 },
> +   { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422 },
> +   { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x },
> +   { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x0222 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x0002 },
> +   { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x0200 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
> +   { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x0004 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x0002 },
> +   { REG_A6XX_RBBM_ISDB_CNT, 0x0182 },
> +   { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x },
> +   { REG_A6XX_RBBM_SP_HYST_CNT, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x0222 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x0111 },
> +   { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x0555 },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x0222 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x0022 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x },
> +   { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x0002 },
> +   { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x },
> +   { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x },
> +   {}
> +};
> +
>  const struct adreno_reglist a730_hwcg[] = {
> { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x0222 },
> { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0202 },
> @@ -968,6 +1027,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool 
> state)
> clock_cntl_on = 0x8aa8aa02;
> else if (adreno_is_a610(adreno_gpu))
> clock_cntl_on = 0xaaa8aa82;
> +   else if (adreno_is_a702(adreno_gpu))
> +   clock_cntl_on = 0xaa82;
> else
> clock_cntl_on = 0x8aa8aa82;
>
> @@ -989,14 +1050,14 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool 
> state)
> return;
>
> /* Disable SP clock before programming HWCG registers */
> -   if

[PATCH v2 5/7] drm/msm/adreno: Add A702 support

2024-02-23 Thread Konrad Dybcio

The A702 is a weird mix of 600 and 700 series.. Perhaps even a
testing ground for some A7xx features with good ol' A6xx silicon.
It's basically A610 that's been beefed up with some new registers
and hw features (like APRIV!), that was then cut back in size,
memory bus and some other ways.

Add support for it, tested with QCM2290 / RB1.

Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c  | 92 +++---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 18 ++
 drivers/gpu/drm/msm/adreno/adreno_gpu.h| 16 +-
 3 files changed, 117 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index c9c55e2ea584..2a491a486ca1 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -837,6 +837,65 @@ const struct adreno_reglist a690_hwcg[] = {
{}
 };
 
+const struct adreno_reglist a702_hwcg[] = {
+   { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0220 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x0081 },
+   { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0xf3cf },
+   { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x0002 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x0001 },
+   { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x0007 },
+   { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x0120 },
+   { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x2220 },
+   { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
+   { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
+   { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x },
+   { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x0011 },
+   { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
+   { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422 },
+   { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x },
+   { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x0222 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x0002 },
+   { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x },
+   { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x },
+   { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x0200 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
+   { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x0004 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x0002 },
+   { REG_A6XX_RBBM_ISDB_CNT, 0x0182 },
+   { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x },
+   { REG_A6XX_RBBM_SP_HYST_CNT, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x0222 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x0111 },
+   { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x0555 },
+   { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x0222 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x0022 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x },
+   { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x0002 },
+   { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x },
+   { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x },
+   {}
+};
+
 const struct adreno_reglist a730_hwcg[] = {
{ REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x0222 },
{ REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0202 },
@@ -968,6 +1027,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
clock_cntl_on = 0x8aa8aa02;
else if (adreno_is_a610(adreno_gpu))
clock_cntl_on = 0xaaa8aa82;
+   else if (adreno_is_a702(adreno_gpu))
+   clock_cntl_on = 0xaa82;
else
clock_cntl_on = 0x8aa8aa82;
 
@@ -989,14 +1050,14 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool 
state)
return;
 
/* Disable SP clock before programming HWCG registers */
-   if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
+   if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
 
for (i = 0; (reg = _gpu->info->hwcg[i],

Re: [PATCH v2 5/7] drm/msm/adreno: Add A702 support

Re: [PATCH v2 5/7] drm/msm/adreno: Add A702 support

[PATCH v2 5/7] drm/msm/adreno: Add A702 support

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