RE: [PATCH v7 5/6] drm/i915/panelreplay: enable/disable panel replay
> -Original Message- > From: Manna, Animesh > Sent: Wednesday, October 11, 2023 4:40 PM > To: intel-...@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Manna, Animesh > ; Hogander, Jouni ; > Murthy, Arun R ; Nikula, Jani > > Subject: [PATCH v7 5/6] drm/i915/panelreplay: enable/disable panel replay > > TRANS_DP2_CTL register is programmed to enable panel replay from source > and sink is enabled through panel replay dpcd configuration address. > > Bspec: 1407940617 > > v1: Initial version. > v2: > - Use pr_* flags instead psr_* flags. [Jouni] > - Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni] > > v3: Cover letter updated and selective fetch condition check is added before > updating its bit in PSR2_MAN_TRK_CTL register. [Jouni] > > v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. > [Jouni] > > v5: Added PSR2_MAN_TRK_CTL programming as needed for Continuous Full > Frame (CFF) update. > > v6: Rebased on latest. > > Note: Initial plan is to enable panel replay in full-screen live active frame > update mode. In a incremental approach panel replay will be enabled in > selctive > update mode if there is any gap in curent implementation. > > Cc: Jouni Högander > Cc: Arun R Murthy > Cc: Jani Nikula > Signed-off-by: Animesh Manna > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++- > .../drm/i915/display/intel_display_types.h| 1 + > drivers/gpu/drm/i915/display/intel_psr.c | 63 ++- > 3 files changed, 55 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 9151d5add960..16f98a7a5f20 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2717,10 +2717,15 @@ static void intel_ddi_pre_enable_dp(struct > intel_atomic_state *state, > const struct drm_connector_state > *conn_state) { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > - if (HAS_DP20(dev_priv)) > + if (HAS_DP20(dev_priv)) { > intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), > crtc_state); > + if (crtc_state->has_panel_replay) > + drm_dp_dpcd_writeb(_dp->aux, > PANEL_REPLAY_CONFIG, > +DP_PANEL_REPLAY_ENABLE); > + } > > if (DISPLAY_VER(dev_priv) >= 14) > mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 95b318f7b2b8..d8f35054bc11 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1704,6 +1704,7 @@ struct intel_psr { > u16 su_y_granularity; > bool source_panel_replay_support; > bool sink_panel_replay_support; > + bool panel_replay_enabled; > u32 dc3co_exitline; > u32 dc3co_exit_delay; > struct delayed_work dc3co_work; > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index a2e0637c53fb..80de831c2f60 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -608,8 +608,11 @@ static void intel_psr_enable_sink(struct intel_dp > *intel_dp) > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > u8 dpcd_val = DP_PSR_ENABLE; > > - /* Enable ALPM at sink for psr2 */ > + if (intel_dp->psr.panel_replay_enabled) > + return; > + > if (intel_dp->psr.psr2_enabled) { > + /* Enable ALPM at sink for psr2 */ Unrelated change Upon removing this Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy --- > drm_dp_dpcd_writeb(_dp->aux, > DP_RECEIVER_ALPM_CONFIG, > DP_ALPM_ENABLE | > DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); > @@ -759,6 +762,17 @@ static int psr2_block_count(struct intel_dp *intel_dp) > return psr2_block_count_lines(intel_dp) / 4; } > > +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) { > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + > + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), > + 0, > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); > + > +
[PATCH v7 5/6] drm/i915/panelreplay: enable/disable panel replay
TRANS_DP2_CTL register is programmed to enable panel replay from source and sink is enabled through panel replay dpcd configuration address. Bspec: 1407940617 v1: Initial version. v2: - Use pr_* flags instead psr_* flags. [Jouni] - Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni] v3: Cover letter updated and selective fetch condition check is added before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni] v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. [Jouni] v5: Added PSR2_MAN_TRK_CTL programming as needed for Continuous Full Frame (CFF) update. v6: Rebased on latest. Note: Initial plan is to enable panel replay in full-screen live active frame update mode. In a incremental approach panel replay will be enabled in selctive update mode if there is any gap in curent implementation. Cc: Jouni Högander Cc: Arun R Murthy Cc: Jani Nikula Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++- .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_psr.c | 63 ++- 3 files changed, 55 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 9151d5add960..16f98a7a5f20 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2717,10 +2717,15 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - if (HAS_DP20(dev_priv)) + if (HAS_DP20(dev_priv)) { intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), crtc_state); + if (crtc_state->has_panel_replay) + drm_dp_dpcd_writeb(_dp->aux, PANEL_REPLAY_CONFIG, + DP_PANEL_REPLAY_ENABLE); + } if (DISPLAY_VER(dev_priv) >= 14) mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 95b318f7b2b8..d8f35054bc11 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1704,6 +1704,7 @@ struct intel_psr { u16 su_y_granularity; bool source_panel_replay_support; bool sink_panel_replay_support; + bool panel_replay_enabled; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a2e0637c53fb..80de831c2f60 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -608,8 +608,11 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE; - /* Enable ALPM at sink for psr2 */ + if (intel_dp->psr.panel_replay_enabled) + return; + if (intel_dp->psr.psr2_enabled) { + /* Enable ALPM at sink for psr2 */ drm_dp_dpcd_writeb(_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); @@ -759,6 +762,17 @@ static int psr2_block_count(struct intel_dp *intel_dp) return psr2_block_count_lines(intel_dp) / 4; } +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), +0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); + + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, +TRANS_DP2_PANEL_REPLAY_ENABLE); +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1323,18 +1337,23 @@ void intel_psr_get_config(struct intel_encoder *encoder, return; intel_dp = _port->dp; - if (!CAN_PSR(intel_dp)) + if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) return; mutex_lock(_dp->psr.lock); if (!intel_dp->psr.enabled) goto unlock; - /* -* Not possible to read EDP_PSR/PSR2_CTL registers as it is -* enabled/disabled because of frontbuffer tracking and others. -*/ - pipe_config->has_psr = true; + if (intel_dp->psr.panel_replay_enabled) { + pipe_config->has_panel_replay = true; + } else { + /*