Re: BPi-M3 under stable/11 details: boots but with only 4 cores used for SMP --of 8 cores present. . .

[Mark Millard]

On 2016-Oct-24, at 2:00 PM, Emmanuel Vadot  wrote:


> Hello Mark,
> 
> The A83T is BIG/Little IIRC and we don't support that. That's why you
> only see 4 cores on the 8.

That is not what I get from reading the A83T documentation. All the CPU 
references are to the same type of CPU for each of the 8. But there is a 
NUMA-ish pair of "clusters" of "CPU"s without a common L2-cache or other cache 
across the clusters.

http://linux-sunxi.org/A83T says . . .

> This SoC does NOT comply with the ARM big.LITTLE architecture, therefore it 
> is in no way energy efficent and gets very hot.


> CPU:
>   • ARM Cortex-A7 Octa-Core


A83T_Datasheet_v1.3_20150510.pdf says:

> Main features of A83T include:
> • CPU architecture: Based on an octa-core CortexTM-A7 CPU architecture, . . ..


> 2.1. CPU Architecture
> 
>   • ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
> 
>   • NEON with SIMD and VFPv4
> 
>   • Support LPAE
> 
>   • 32KB I-cache and 32KB D-cache per CPU
> 
>   • 1MB L2-cache

The "A883T Block Diagram (Figure 3-1 page labeled 12) simply says "A7 x 8".

A83T_User_Manual_v1.5.1_20150513.pdf has some more detailed diagrams and more 
information. . .

There are two CPU Clusters (0 and  1). It is more of a NUMA context due to 
caching within each cluster that is not across the clusters. This document's 
wording is more explicit, mentioning clusters for the L2-cache level (page 
labeled 51) in even its basic description of caches in the A83T archtiecture:

> 2.1.1. CPU Architecture
> 
> The A83T platform is based on octa-core CortexTM-A7 CPU architecture.
> 
>   •   ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
> 
>   •   NEON with SIMD and VFPv4 support
> 
>   •   Support LPAE
> 
>   •   32KB I-cache and 32KB D-cache per CPU
> 
>   •   1MB L2-cache(512KB per Cluster)


See this document's Figure 3-1 "System Bus Tree" (on the page labeled 66).

From what I read one can control clock frequencies per cluster but it is 
allowed to have them both the same all the time that frequencies are stable for 
a while.

And I'll stop with the details that I see with that.

There may be some folks around with knowledge of more detail that might well be 
able to say "but it is not NUMA like for these details . . .". By no mean have 
I analyzed all the consequences of all the details.

But I find no evidence of BIG/Little use of different classes of cores at 
necessarily different cock rates and the like. As much as I've looked at looks 
more symmetric than that.



> cpulist0 shows 8 core because every core in is the dtb.
> 
> On Mon, 24 Oct 2016 09:04:35 -0700
> Mark Millard  wrote:
> 
>> The is for a Banana Pi M3 V1.2 board with the barrel power connector. The 5V 
>> 2A supply that I had to fit the barrel hole can not power the board 
>> sufficiently to boot --even when no fan is being powered. In order to boot 
>> with a fan I have both that and an official rpi3 power supply plugged in. 
>> The rpi3 power supply will not power the GPIO fan connections but can boot 
>> the board by itself (V5.1v and 2.5A but cell phone charger 
>> cabling/connections). I've got a heat sink on the CPU as well.
>> 
>>> root@bananapi-m3:~ # uname -apKU
>>> FreeBSD bananapi-m3 11.0-STABLE FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 24 
>>> 00:41:16 PDT 2016 
>>> markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
>>>   arm armv6 1100505 1
>>> 100505
>> 
>>> root@bananapi-m3:~ # freebsd-version -ku
>>> 11.0-STABLE
>>> 11.0-STABLE
>> 
>> In the below note that "FreeBSD/SMP: Multiprocessor System Detected: 4 CPUs" 
>> but cpulist0 shows cpu0 through cpu7. For now: So much for seeing how 
>> buildworld/buildkernel would go using all 8 cores.
>> 
>> (Note: the serial connection tends to drop some text sometimes. That may 
>> have happened some for the below.)
>> 
>>> root@bananapi-m3:~ # dmesg | more
>>> Copyright (c) 1992-2016 The FreeBSD Project.
>>> Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
>>>   The Regents of the University of California. All rights reserved.
>>> FreeBSD is a registered trademark of The FreeBSD Foundation.
>>> FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 24 00:41:16 PDT 2016
>>>   
>>> markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
>>>  arm
>>> FreeBSD clang version 3.8.0 (tags/RELEASE_380/final 262564) (based on LLVM 
>>> 3.8.0)
>>> VT: init without driver.
>>> CPU: Cortex A7 rev 5 (Cortex-A core)
>>> Supported features: ARM_ISA THUMB2 JAZELLE THUMBEE ARMv4 Security_Ext
>>> WB enabled LABT branch prediction disabled
>>> LoUU:2 LoC:3 LoUIS:2 
>>> Cache level 1: 
>>> 32KB/64B 4-way data cache WB Read-Alloc Write-Alloc
>>> 32KB/32B 2-way instruction cache Read-Alloc
>>> Cache level 2: 
>>> 512KB/64B 8-way unified cache WB Read-Alloc Write-Alloc
>>> real memory  = 2147483648 (2048 MB)
>>> avail memory = 2090852352 (1993 MB)
>>> 

Re: BPi-M3 under stable/11 details: boots but with only 4 cores used for SMP --of 8 cores present. . .

[Mark Millard]

> On 2016-Oct-24, at 3:47 PM, Emmanuel Vadot  wrote:
> 
> 
> Ah yes, well same thing, we don't support cluster :)

I wonder if the second cluster is well powered down (as best it can be as early 
as it can be). I could not even boot without special power connections (beyond 
2A supply for the 5V/5.1V used). 2.5A worked (no fan to power). It took two 
supplies to also provide fan power over a couple of the GPIO pins and still be 
able to boot.

And, yes, reading about the A83T does suggest that FreeBSD will never put that 
kind of NUMA handling effort into it, like it does for some bigger iron that is 
far more in use.

It would probably be a good idea if wiki pages and such referencing the A83T 
and its status be explicit about the "at most 4 cores in use" status. Using 
more than 4 cores is the primary reason to get/use a A83T (and to put up with 
handling power and heat issues).

> On Mon, 24 Oct 2016 15:42:40 -0700
> Mark Millard  wrote:
> 
>> On 2016-Oct-24, at 2:00 PM, Emmanuel Vadot  wrote:
>> 
>> 
>>> Hello Mark,
>>> 
>>> The A83T is BIG/Little IIRC and we don't support that. That's why you
>>> only see 4 cores on the 8.
>> 
>> That is not what I get from reading the A83T documentation. All the CPU 
>> references are to the same type of CPU for each of the 8. But there is a 
>> NUMA-ish pair of "clusters" of "CPU"s without a common L2-cache or other 
>> cache across the clusters.
>> 
>> http://linux-sunxi.org/A83T says . . .
>> 
>>> This SoC does NOT comply with the ARM big.LITTLE architecture, therefore it 
>>> is in no way energy efficent and gets very hot.
>> 
>> 
>>> CPU:
>>> ? ARM Cortex-A7 Octa-Core
>> 
>> 
>> A83T_Datasheet_v1.3_20150510.pdf says:
>> 
>>> Main features of A83T include:
>>> ? CPU architecture: Based on an octa-core CortexTM-A7 CPU architecture, . . 
>>> ..
>> 
>> 
>>> 2.1. CPU Architecture
>>> 
>>> ? ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
>>> 
>>> ? NEON with SIMD and VFPv4
>>> 
>>> ? Support LPAE
>>> 
>>> ? 32KB I-cache and 32KB D-cache per CPU
>>> 
>>> ? 1MB L2-cache
>> 
>> The "A883T Block Diagram (Figure 3-1 page labeled 12) simply says "A7 x 8".
>> 
>> A83T_User_Manual_v1.5.1_20150513.pdf has some more detailed diagrams and 
>> more information. . .
>> 
>> There are two CPU Clusters (0 and  1). It is more of a NUMA context due to 
>> caching within each cluster that is not across the clusters. This document's 
>> wording is more explicit, mentioning clusters for the L2-cache level (page 
>> labeled 51) in even its basic description of caches in the A83T archtiecture:
>> 
>>> 2.1.1. CPU Architecture
>>> 
>>> The A83T platform is based on octa-core CortexTM-A7 CPU architecture.
>>> 
>>> ? ?  ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
>>> 
>>> ? ?  NEON with SIMD and VFPv4 support
>>> 
>>> ? ?  Support LPAE
>>> 
>>> ? ?  32KB I-cache and 32KB D-cache per CPU
>>> 
>>> ? ?  1MB L2-cache(512KB per Cluster)
>> 
>> 
>> See this document's Figure 3-1 "System Bus Tree" (on the page labeled 66).
>> 
>> From what I read one can control clock frequencies per cluster but it is 
>> allowed to have them both the same all the time that frequencies are stable 
>> for a while.
>> 
>> And I'll stop with the details that I see with that.
>> 
>> There may be some folks around with knowledge of more detail that might well 
>> be able to say "but it is not NUMA like for these details . . .". By no mean 
>> have I analyzed all the consequences of all the details.
>> 
>> But I find no evidence of BIG/Little use of different classes of cores at 
>> necessarily different cock rates and the like. As much as I've looked at 
>> looks more symmetric than that.
>> 
>> 
>> 
>>> cpulist0 shows 8 core because every core in is the dtb.
>>> 
>>> On Mon, 24 Oct 2016 09:04:35 -0700
>>> Mark Millard  wrote:
>>> 
 The is for a Banana Pi M3 V1.2 board with the barrel power connector. The 
 5V 2A supply that I had to fit the barrel hole can not power the board 
 sufficiently to boot --even when no fan is being powered. In order to boot 
 with a fan I have both that and an official rpi3 power supply plugged in. 
 The rpi3 power supply will not power the GPIO fan connections but can boot 
 the board by itself (V5.1v and 2.5A but cell phone charger 
 cabling/connections). I've got a heat sink on the CPU as well.
 
> root@bananapi-m3:~ # uname -apKU
> FreeBSD bananapi-m3 11.0-STABLE FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 
> 24 00:41:16 PDT 2016 
> markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
>   arm armv6 1100505 1
> 100505
 
> root@bananapi-m3:~ # freebsd-version -ku
> 11.0-STABLE
> 11.0-STABLE
 
 In the below note that "FreeBSD/SMP: Multiprocessor System Detected: 4 
 CPUs" but cpulist0 shows cpu0 through cpu7. For now: So much for seeing 
 how buildworld/buildkernel would go 

Re: BPi-M3 under stable/11 details: boots but with only 4 cores used for SMP --of 8 cores present. . .

[Emmanuel Vadot]

 Ah yes, well same thing, we don't support cluster :)

On Mon, 24 Oct 2016 15:42:40 -0700
Mark Millard  wrote:

> On 2016-Oct-24, at 2:00 PM, Emmanuel Vadot  wrote:
> 
> 
> > Hello Mark,
> > 
> > The A83T is BIG/Little IIRC and we don't support that. That's why you
> > only see 4 cores on the 8.
> 
> That is not what I get from reading the A83T documentation. All the CPU 
> references are to the same type of CPU for each of the 8. But there is a 
> NUMA-ish pair of "clusters" of "CPU"s without a common L2-cache or other 
> cache across the clusters.
> 
> http://linux-sunxi.org/A83T says . . .
> 
> > This SoC does NOT comply with the ARM big.LITTLE architecture, therefore it 
> > is in no way energy efficent and gets very hot.
> 
> 
> > CPU:
> > ? ARM Cortex-A7 Octa-Core
> 
> 
> A83T_Datasheet_v1.3_20150510.pdf says:
> 
> > Main features of A83T include:
> > ? CPU architecture: Based on an octa-core CortexTM-A7 CPU architecture, . . 
> > ..
> 
> 
> > 2.1. CPU Architecture
> > 
> > ? ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
> > 
> > ? NEON with SIMD and VFPv4
> > 
> > ? Support LPAE
> > 
> > ? 32KB I-cache and 32KB D-cache per CPU
> > 
> > ? 1MB L2-cache
> 
> The "A883T Block Diagram (Figure 3-1 page labeled 12) simply says "A7 x 8".
> 
> A83T_User_Manual_v1.5.1_20150513.pdf has some more detailed diagrams and more 
> information. . .
> 
> There are two CPU Clusters (0 and  1). It is more of a NUMA context due to 
> caching within each cluster that is not across the clusters. This document's 
> wording is more explicit, mentioning clusters for the L2-cache level (page 
> labeled 51) in even its basic description of caches in the A83T archtiecture:
> 
> > 2.1.1. CPU Architecture
> > 
> > The A83T platform is based on octa-core CortexTM-A7 CPU architecture.
> > 
> > ? ?  ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
> > 
> > ? ?  NEON with SIMD and VFPv4 support
> > 
> > ? ?  Support LPAE
> > 
> > ? ?  32KB I-cache and 32KB D-cache per CPU
> > 
> > ? ?  1MB L2-cache(512KB per Cluster)
> 
> 
> See this document's Figure 3-1 "System Bus Tree" (on the page labeled 66).
> 
> From what I read one can control clock frequencies per cluster but it is 
> allowed to have them both the same all the time that frequencies are stable 
> for a while.
> 
> And I'll stop with the details that I see with that.
> 
> There may be some folks around with knowledge of more detail that might well 
> be able to say "but it is not NUMA like for these details . . .". By no mean 
> have I analyzed all the consequences of all the details.
> 
> But I find no evidence of BIG/Little use of different classes of cores at 
> necessarily different cock rates and the like. As much as I've looked at 
> looks more symmetric than that.
> 
> 
> 
> > cpulist0 shows 8 core because every core in is the dtb.
> > 
> > On Mon, 24 Oct 2016 09:04:35 -0700
> > Mark Millard  wrote:
> > 
> >> The is for a Banana Pi M3 V1.2 board with the barrel power connector. The 
> >> 5V 2A supply that I had to fit the barrel hole can not power the board 
> >> sufficiently to boot --even when no fan is being powered. In order to boot 
> >> with a fan I have both that and an official rpi3 power supply plugged in. 
> >> The rpi3 power supply will not power the GPIO fan connections but can boot 
> >> the board by itself (V5.1v and 2.5A but cell phone charger 
> >> cabling/connections). I've got a heat sink on the CPU as well.
> >> 
> >>> root@bananapi-m3:~ # uname -apKU
> >>> FreeBSD bananapi-m3 11.0-STABLE FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 
> >>> 24 00:41:16 PDT 2016 
> >>> markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
> >>>   arm armv6 1100505 1
> >>> 100505
> >> 
> >>> root@bananapi-m3:~ # freebsd-version -ku
> >>> 11.0-STABLE
> >>> 11.0-STABLE
> >> 
> >> In the below note that "FreeBSD/SMP: Multiprocessor System Detected: 4 
> >> CPUs" but cpulist0 shows cpu0 through cpu7. For now: So much for seeing 
> >> how buildworld/buildkernel would go using all 8 cores.
> >> 
> >> (Note: the serial connection tends to drop some text sometimes. That may 
> >> have happened some for the below.)
> >> 
> >>> root@bananapi-m3:~ # dmesg | more
> >>> Copyright (c) 1992-2016 The FreeBSD Project.
> >>> Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
> >>>   The Regents of the University of California. All rights reserved.
> >>> FreeBSD is a registered trademark of The FreeBSD Foundation.
> >>> FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 24 00:41:16 PDT 2016
> >>>   
> >>> markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
> >>>  arm
> >>> FreeBSD clang version 3.8.0 (tags/RELEASE_380/final 262564) (based on 
> >>> LLVM 3.8.0)
> >>> VT: init without driver.
> >>> CPU: Cortex A7 rev 5 (Cortex-A core)
> >>> Supported features: ARM_ISA THUMB2 JAZELLE THUMBEE ARMv4 

Re: BPi-M3 under stable/11 details: boots but with only 4 cores used for SMP --of 8 cores present. . .

[Emmanuel Vadot]

 Hello Mark,

 The A83T is BIG/Little IIRC and we don't support that. That's why you
only see 4 cores on the 8.
 cpulist0 shows 8 core because every core in is the dtb.

On Mon, 24 Oct 2016 09:04:35 -0700
Mark Millard  wrote:

> The is for a Banana Pi M3 V1.2 board with the barrel power connector. The 5V 
> 2A supply that I had to fit the barrel hole can not power the board 
> sufficiently to boot --even when no fan is being powered. In order to boot 
> with a fan I have both that and an official rpi3 power supply plugged in. The 
> rpi3 power supply will not power the GPIO fan connections but can boot the 
> board by itself (V5.1v and 2.5A but cell phone charger cabling/connections). 
> I've got a heat sink on the CPU as well.
> 
> > root@bananapi-m3:~ # uname -apKU
> > FreeBSD bananapi-m3 11.0-STABLE FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 24 
> > 00:41:16 PDT 2016 
> > markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
> >   arm armv6 1100505 1
> > 100505
> 
> > root@bananapi-m3:~ # freebsd-version -ku
> > 11.0-STABLE
> > 11.0-STABLE
> 
> In the below note that "FreeBSD/SMP: Multiprocessor System Detected: 4 CPUs" 
> but cpulist0 shows cpu0 through cpu7. For now: So much for seeing how 
> buildworld/buildkernel would go using all 8 cores.
> 
> (Note: the serial connection tends to drop some text sometimes. That may have 
> happened some for the below.)
> 
> > root@bananapi-m3:~ # dmesg | more
> > Copyright (c) 1992-2016 The FreeBSD Project.
> > Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
> >The Regents of the University of California. All rights reserved.
> > FreeBSD is a registered trademark of The FreeBSD Foundation.
> > FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 24 00:41:16 PDT 2016
> >
> > markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
> >  arm
> > FreeBSD clang version 3.8.0 (tags/RELEASE_380/final 262564) (based on LLVM 
> > 3.8.0)
> > VT: init without driver.
> > CPU: Cortex A7 rev 5 (Cortex-A core)
> > Supported features: ARM_ISA THUMB2 JAZELLE THUMBEE ARMv4 Security_Ext
> > WB enabled LABT branch prediction disabled
> > LoUU:2 LoC:3 LoUIS:2 
> > Cache level 1: 
> > 32KB/64B 4-way data cache WB Read-Alloc Write-Alloc
> > 32KB/32B 2-way instruction cache Read-Alloc
> > Cache level 2: 
> > 512KB/64B 8-way unified cache WB Read-Alloc Write-Alloc
> > real memory  = 2147483648 (2048 MB)
> > avail memory = 2090852352 (1993 MB)
> > FreeBSD/SMP: Multiprocessor System Detected: 4 CPUs
> > random: entropy device external interface
> > kbd0 at kbdmux0
> > ofwbus0: 
> > aw_ccu0:  on ofwbus0
> > clk_fixed0:  on aw_ccu0
> > clk_fixed1:  mem 0x1c20028-0x1c2002b on aw_ccu0
> > clk_fixed3:  on aw_ccu0
> > aw_ahbclk0:  mem 0x1c20054-0x1c20057 on aw_ccu0
> > aw_apbclk0:  mem 0x1c20054-0x1c20057 on aw_ccu0
> > aw_apbclk1:  mem 0x1c20058-0x1c2005b on aw_ccu0
> > aw_ahbclk1:  mem 0x1c2005c-0x1c2005f on aw_ccu0
> > aw_gate0:  mem 0x1c20060-0x1c2006f on aw_ccu0
> > aw_mmcclk0:  mem 0x1c20088-0x1c2clk1:  > Clock> mem 0x1c2008c-0x1c2008f on aw_ccu0
> > aw_mmcclk2:  mem 0x1c20090-0x1c20093 on aw_ccu0
> > aw_cpusclk0:  mem 0x1f01400-0x1f01403 on aw_ccu0
> > clk_fixed4:  on aw_ccu0
> > aw_apbclk2:  mem 0x1f0140c-0x1f0140f on aw_ccu0
> > aw_gate1:  mem 0x1f01428-0x1f0142b on aw_ccu0
> > aw_pll1:  mem 0x1c20044-0x1c20047 on aw_ccu0
> > aw_usbclk0:  mem 0x1c200cc-0x1c200cf on aw_ccu0
> > clk_fixed5:  mem 0x1c00030-0x1c00033 on aw_ccu0
> > simplebus0:  on ofwbus0
> > aw_reset0:  mem 0x1c202c0-0x1c202cb on simplebus0
> > aw_reset1:  mem 0x1c202d0-0x1c202d3 on simplebus0
> > aw_reset2:  mem 0x1c202d8-0x1c202db on simplebus0
> > aw_reset3:  mem 0x1f014b0-0x1f014b3 on simplebus0
> > iichb0:  mem 0x1c2ac00-0x1c2afff 
> > on simplebus0
> > iicbus0: hb0
> > iichb1:  mem 0x1c2b000-0x1c2b3ff 
> > on simplebus0
> > iicbus1:  on iichb1
> > iichb2:  mem 0x1c2b400-0x1c2b7ff 
> > on simplebus0
> > iicbus2:  on iichb2
> > regfix0:  on ofwbus0
> > regfix1:  on ofwbus0
> > regfix2:  on ofwbus0
> > regfix3:  on ofwbus0
> > regfix4:  on ofwbus0
> > aw_sid0:  mem 0x1c14000-0x1c143ff on 
> > simplebus0
> > awusbphy0:  on simplebu,0x1c86000-0x1c87fff on simplebus0
> > gic0: pn 0x20, arch 0x2, rev 0x1, implementer 0x43b irqs 224
> > gpio0:  mem 0x1c20800-0x1c20bff on 
> > simplebus0
> > gpiobus0:  on gpio0
> > gpio1:  mem 0x1f02c00-0x1f02fff on 
> > simplebus0
> > gpiobus1:  on gpio1
> > aw_nmi0:  mem 0x1f00c0c-0x1f00c43 on simplebus0
> > generic_timer0:  on ofwbus0
> > Timecounter "cy 2400 Hz quality 1000
> > Event timer "ARM MPCore Eventtimer" frequency 2400 Hz quality 1000
> > cpulist0:  on ofwbus0
> > cpu0:  on cpulist0
> > cpu1:  on cpulist0
> > cpu2:  on cpulist0
> > cpu3:  on cpulist0
> > cpu4:  on cpulist0
> > cpu5:  on cpulist0
> > cpu6:  on cpulist0
> > cpu7:  on cpulist0
> > a10_mmc0:  mem 0x1c0f000-0x1c0 
> > on simplebus0
> > mmc0:  on a10_mmc0
> > a10_mmc1:  mem 0x1c11000-0x1c11fff 
> > on 

BPi-M3 under stable/11 details: boots but with only 4 cores used for SMP --of 8 cores present. . .

[Mark Millard]

The is for a Banana Pi M3 V1.2 board with the barrel power connector. The 5V 2A 
supply that I had to fit the barrel hole can not power the board sufficiently 
to boot --even when no fan is being powered. In order to boot with a fan I have 
both that and an official rpi3 power supply plugged in. The rpi3 power supply 
will not power the GPIO fan connections but can boot the board by itself (V5.1v 
and 2.5A but cell phone charger cabling/connections). I've got a heat sink on 
the CPU as well.

> root@bananapi-m3:~ # uname -apKU
> FreeBSD bananapi-m3 11.0-STABLE FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 24 
> 00:41:16 PDT 2016 
> markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
>   arm armv6 1100505 1
> 100505

> root@bananapi-m3:~ # freebsd-version -ku
> 11.0-STABLE
> 11.0-STABLE

In the below note that "FreeBSD/SMP: Multiprocessor System Detected: 4 CPUs" 
but cpulist0 shows cpu0 through cpu7. For now: So much for seeing how 
buildworld/buildkernel would go using all 8 cores.

(Note: the serial connection tends to drop some text sometimes. That may have 
happened some for the below.)

> root@bananapi-m3:~ # dmesg | more
> Copyright (c) 1992-2016 The FreeBSD Project.
> Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
>The Regents of the University of California. All rights reserved.
> FreeBSD is a registered trademark of The FreeBSD Foundation.
> FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 24 00:41:16 PDT 2016
>
> markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src/sys/ALLWINNER
>  arm
> FreeBSD clang version 3.8.0 (tags/RELEASE_380/final 262564) (based on LLVM 
> 3.8.0)
> VT: init without driver.
> CPU: Cortex A7 rev 5 (Cortex-A core)
> Supported features: ARM_ISA THUMB2 JAZELLE THUMBEE ARMv4 Security_Ext
> WB enabled LABT branch prediction disabled
> LoUU:2 LoC:3 LoUIS:2 
> Cache level 1: 
> 32KB/64B 4-way data cache WB Read-Alloc Write-Alloc
> 32KB/32B 2-way instruction cache Read-Alloc
> Cache level 2: 
> 512KB/64B 8-way unified cache WB Read-Alloc Write-Alloc
> real memory  = 2147483648 (2048 MB)
> avail memory = 2090852352 (1993 MB)
> FreeBSD/SMP: Multiprocessor System Detected: 4 CPUs
> random: entropy device external interface
> kbd0 at kbdmux0
> ofwbus0: 
> aw_ccu0:  on ofwbus0
> clk_fixed0:  on aw_ccu0
> clk_fixed1:  mem 0x1c20028-0x1c2002b on aw_ccu0
> clk_fixed3:  on aw_ccu0
> aw_ahbclk0:  mem 0x1c20054-0x1c20057 on aw_ccu0
> aw_apbclk0:  mem 0x1c20054-0x1c20057 on aw_ccu0
> aw_apbclk1:  mem 0x1c20058-0x1c2005b on aw_ccu0
> aw_ahbclk1:  mem 0x1c2005c-0x1c2005f on aw_ccu0
> aw_gate0:  mem 0x1c20060-0x1c2006f on aw_ccu0
> aw_mmcclk0:  mem 0x1c20088-0x1c2clk1:  Clock> mem 0x1c2008c-0x1c2008f on aw_ccu0
> aw_mmcclk2:  mem 0x1c20090-0x1c20093 on aw_ccu0
> aw_cpusclk0:  mem 0x1f01400-0x1f01403 on aw_ccu0
> clk_fixed4:  on aw_ccu0
> aw_apbclk2:  mem 0x1f0140c-0x1f0140f on aw_ccu0
> aw_gate1:  mem 0x1f01428-0x1f0142b on aw_ccu0
> aw_pll1:  mem 0x1c20044-0x1c20047 on aw_ccu0
> aw_usbclk0:  mem 0x1c200cc-0x1c200cf on aw_ccu0
> clk_fixed5:  mem 0x1c00030-0x1c00033 on aw_ccu0
> simplebus0:  on ofwbus0
> aw_reset0:  mem 0x1c202c0-0x1c202cb on simplebus0
> aw_reset1:  mem 0x1c202d0-0x1c202d3 on simplebus0
> aw_reset2:  mem 0x1c202d8-0x1c202db on simplebus0
> aw_reset3:  mem 0x1f014b0-0x1f014b3 on simplebus0
> iichb0:  mem 0x1c2ac00-0x1c2afff on 
> simplebus0
> iicbus0: hb0
> iichb1:  mem 0x1c2b000-0x1c2b3ff on 
> simplebus0
> iicbus1:  on iichb1
> iichb2:  mem 0x1c2b400-0x1c2b7ff on 
> simplebus0
> iicbus2:  on iichb2
> regfix0:  on ofwbus0
> regfix1:  on ofwbus0
> regfix2:  on ofwbus0
> regfix3:  on ofwbus0
> regfix4:  on ofwbus0
> aw_sid0:  mem 0x1c14000-0x1c143ff on 
> simplebus0
> awusbphy0:  on simplebu,0x1c86000-0x1c87fff on simplebus0
> gic0: pn 0x20, arch 0x2, rev 0x1, implementer 0x43b irqs 224
> gpio0:  mem 0x1c20800-0x1c20bff on 
> simplebus0
> gpiobus0:  on gpio0
> gpio1:  mem 0x1f02c00-0x1f02fff on 
> simplebus0
> gpiobus1:  on gpio1
> aw_nmi0:  mem 0x1f00c0c-0x1f00c43 on simplebus0
> generic_timer0:  on ofwbus0
> Timecounter "cy 2400 Hz quality 1000
> Event timer "ARM MPCore Eventtimer" frequency 2400 Hz quality 1000
> cpulist0:  on ofwbus0
> cpu0:  on cpulist0
> cpu1:  on cpulist0
> cpu2:  on cpulist0
> cpu3:  on cpulist0
> cpu4:  on cpulist0
> cpu5:  on cpulist0
> cpu6:  on cpulist0
> cpu7:  on cpulist0
> a10_mmc0:  mem 0x1c0f000-0x1c0 on 
> simplebus0
> mmc0:  on a10_mmc0
> a10_mmc1:  mem 0x1c11000-0x1c11fff on 
> simplebus0
> mmc1:  on a10_mmc1
> gpioc0:  on gpio0
> aw_wdog0:  mem 0x1c20ca0-0x1c20cbf on simplebus0
> uart0:  mem 0x1c28000-0x1c283ff on 
> simplebus0
> uart0: console (480769,n,8,1)
> gpioc1:  on gpio1
> iichb3:  mem 0x1f03400-0x1f037ff on simplebus0
> iicbus3:  on iichb3
> iic0:  on iicbus3
> axp81x_pmu0:  at addr 0x746 on iicbus3
> gpiobus2:  on axp81x_pmu0
> gpioled0:  at pin 0 on gpiobus2
> gpioled1:  at pin 1 on gpiobus2
> gpioc2:  on axp81x_pmu0
> iic1:  on iicbus0
> iic2:  on