[Bug target/110217] [avr] SREG: use BSET and BCLR instead of load/modify/write

[gjl at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110217

--- Comment #4 from Georg-Johann Lay  ---
At least CLI / SBI won't glitch at O0, same for ATOMIC_BLOCK.

For SBI et al. you are right, they rely on insn combine. The right approach
would have been compiler built-ins or API using inline asm. But the time to
introduce such interfaces was 20 or so years ago...

[Bug target/110217] [avr] SREG: use BSET and BCLR instead of load/modify/write

[gjl at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110217

--- Comment #3 from Georg-Johann Lay  ---
At least CLI / SBI won't glitch at O0, same for ATOMIC_BLOCK.

For SBI et al. you are right, they rely on insn combine. The right approach
would have been compiler built-ins or API using inline asm. But the time to
introduce such interfaces was 20 or so years ago...

[Bug target/110217] [avr] SREG: use BSET and BCLR instead of load/modify/write

[mx682x at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110217

--- Comment #2 from mx682x at gmail dot com ---
I see, thank you for you input.

> Apart from that, the proposed patch won't work for indirect addressing, or
> when the compiler is turning direct addresses to indirect addresses (using
> CSE etc, common subexpression elimination and similar strategies).
> 
> Also the patch relies on insn combine which only runs when optimization is
> on, thus any application which relies on that optimization will glitch at
> -O0.

However, just out of curiosity, doesn't this also apply to the "Single-Cycle
I/O access" instructions cbi/sbi? Afterall, I've just duplicated the respective
code and andjusted the predicate for the address.

[Bug target/110217] [avr] SREG: use BSET and BCLR instead of load/modify/write

[gjl at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110217

Georg-Johann Lay  changed:

   What|Removed |Added

   Severity|normal  |enhancement

--- Comment #1 from Georg-Johann Lay  ---
The only case where this might make sense is for bit 7 (the I-flag), however
the established coding style is to use cli() and sei() from AVR-LibC, cf.
documentation of #include :

https://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html

For more sophitsticated use cases there is even ATOMIC_BLOCK and friends
provided by #include , cf:

https://www.nongnu.org/avr-libc/user-manual/group__util__atomic.html

This has the additional benefit of being more readable than bit manipulations.  

Apart from that, the proposed patch won't work for indirect addressing, or when
the compiler is turning direct addresses to indirect addresses (using CSE etc,
common subexpression elimination and similar strategies).

Also the patch relies on insn combine which only runs when optimization is on,
thus any application which relies on that optimization will glitch at -O0.

So I am inclined to "won't fix" this PR.

Maybe you just missed avr/interrupt.h and / or util/atomic.h ?

If you must not use AVR-LibC for some reason, then the next best approach is to
use __builtin_avr_sei(), cf. AVR built-in functions:

https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/AVR-Built-in-Functions.html

Or implement it as static inline function that does __asm volatile ("sei" :::
"memory") if you are not allowed to use built-ins.