[AARCH64][Insn classification unification 4/N] load/store types
Hi, This patch is part of the ongoing work to unify instruction classification between the ARM and AARCH64 backends. This patch adds "load_acq" and "store_rel" types for classifying load acquire and store release instructions respectively. It also updates the ARMv8 pipeline descriptions. OK for trunk? Thanks Sofiane - ChangeLog: * config/arm/types.md (define_attr "type"): Add "load_acq" and "store_rel". * config/arm/cortex-a53.md (cortex_a53_load1): Update for attribute changes. (cortex_a53_store1): Likewise. arm-a64-fine-tune-load-store.diff Description: Binary data
[AARCH64][Insn classification unification 2/N] Add cortex-a53 pipeline description
Hi, This patch is part of the ongoing work to unify instruction classification between the ARM and AARCH64 backends. This patch wires up the cortex-a53 pipeline description defined in the ARM backend to be used in the AARCH46 backend. OK for trunk? Thanks Sofiane - ChangeLog * config.gcc (aarch64*-*-*): Add aarch-common.o to extra_objs. Add aarch-common-protos.h to extra_headers. (aarch64*-*-*): Add arm/aarch-common-protos.h to tm_p_file. * config/aarch64/aarch64.md: Include "../arm/cortex-a53.md" * config/aarch64/t-aarch64 (aarch-common.o): Define. aarch64-add-a53-pipeline.diff Description: Binary data
[ARM][Insn classification refactoring 7/N] Factor out common scheduling dependency routines
Hi, This patch is part of the ongoing work of ARM/AARCH64 instruction classification cleanup. This patches moves the scheduling dependency routines from arm.c into a new file aarch-common.c, preparing them to be used in AARCH64. OK for trunk? Thanks Sofiane - ChangeLog: * config.gcc (arm*-*-*): Add aarch-common.o to extra_objs. Add aarch-common-protos.h to extra_headers. (arm*-*-*): Add arm/aarch-common-protos.h to tm_p_file. * config/arm/arm.c (arm_early_load_addr_dep): Move from here to ... (arm_early_store_addr_dep): Likewise. (arm_no_early_alu_shift_dep: Likewise. (arm_no_early_alu_shift_value_dep: Likewise. (arm_no_early_mul_dep: Likewise. (arm_no_early_store_addr_dep: Likewise. (arm_mac_accumulator_is_mul_result: Likewise. (arm_mac_accumulator_is_result: Likewise. * config/arm/aarch-common.c: ... here. New file. * config/arm/arm-protos.h (arm_early_load_addr_dep): Move from here to ... (arm_early_store_addr_dep): Likewise. (arm_no_early_alu_shift_dep: Likewise. (arm_no_early_alu_shift_value_dep: Likewise. (arm_no_early_mul_dep: Likewise. (arm_no_early_store_addr_dep: Likewise. (arm_mac_accumulator_is_mul_result: Likewise. (arm_mac_accumulator_is_result: Likewise. * config/arm/aarch-common-protos.h: ... here. New file. * config/arm/t-arm (aarch-common.o): Define. arm-factor-common-sched-checks.diff Description: Binary data
[ARM][Insn classification refactoring 7/N] Factor out "type" attribute
Hi, This patch is part of the ongoing work of ARM/AARCH64 instruction classification cleanup. This patches moves the "type" attribute, and the related "mul32" and "mul64" from arm.md to a new file types.md, preparing it to be included in AARCH64. OK for trunk? Thanks Sofiane - ChangeLog: * config/arm/arm.md: Include new file "types.md". (define_attr "type"): Move from here to ... (define_attr "mul32"): Likewise. (define_attr "mul64"): Likewise. * config/arm/types.md: ... here. New file. arm-factor-type-attr.diff Description: Binary data
[ARM][Insn classification refactoring 6/N] Delete "insn" attribute and update MOV classification
Hi, This patch is part of the ongoing work of ARM instruction classification cleanup. This patch deletes the "insn" attribute and moves the MOV/MVN instruction classification to the "type" attribute, where it is split into several types for a finer-grained classification. This has been tested with a full arm-none-eabi toolchain build and regression run, as well as using random code generation tests to compare the output versus a baseline compiler. OK for trunk? Thanks Sofiane - ChangeLog: * config/arm/arm.md (attribute "insn"): Delete. (attribute "type"): Add "mov_imm", "mov_reg", "mov_shift", "mov_shift_reg", "mvn_imm", "mvn_reg", "mvn_shift" and "mvn_shift_reg". (not_shiftsi): Update for attribute change. (not_shiftsi_compare0): Likewise. (not_shiftsi_compare0_scratch): Likewise. (arm_one_cmplsi2): Likewise. (thumb1_one_cmplsi2): Likewise. (notsi_compare0): Likewise. (notsi_compare0_scratch): Likewise. (thumb1_movdi_insn): Likewise. (arm_movsi_insn): Likewise. (movhi_insn_arch4): Likewise. (movhi_bytes): Likewise. (arm_movqi_insn): Likewise. (thumb1_movqi_insn): Likewise. (arm32_movhf): Likewise. (thumb1_movhf): Likewise. (arm_movsf_soft_insn): Likewise. (thumb1_movsf_insn): Likewise. (thumb_movdf_insn): Likewise. (movsicc_insn): Likewise. (movsfcc_soft_insn): Likewise. (and_scc): Likewise. (cond_move): Likewise. (if_move_not): Likewise. (if_not_move): Likewise. (if_shift_move): Likewise. (if_move_shift): Likewise. (if_shift_shift): Likewise. (if_not_arith): Likewise. (if_arith_not): Likewise. (cond_move_not): Likewise. * config/arm/neon.md (neon_mov): Update for attribute change. (neon_mov): Likewise. * config/arm/vfp.md (arm_movsi_vfp): Update for attribute change. (thumb2_movsi_vfp): Likewise. (movsf_vfp): Likewise. (thumb2_movsf_vfp): Likewise. * config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute change. (cortexa7_older_only): Likewise. (cortexa7_younger): Likewise. * config/arm/arm1020e.md (1020alu_op): Update for attribute change. (1020alu_shift_op): Likewise. (1020alu_shift_reg_op): Likewise. * config/arm/arm1026ejs.md (alu_op): Update for attribute change. (alu_shift_op): Likewise. (alu_shift_reg_op): Likewise. * config/arm/arm1136jfs.md (11_alu_op): Update for attribute change. (11_alu_shift_op): Likewise. (11_alu_shift_reg_op): Likewise. * config/arm/arm926ejs.md (9_alu_op): Update for attribute change. (9_alu_shift_reg_op): Likewise. * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change. (cortex_a15_alu_shift): Likewise. (cortex_a15_alu_shift_reg): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute change. (cortex_a5_alu_shift): Likewise. * config/arm/cortex-a53.md (cortex_a53_alu): Update for attribute change. (cortex_a53_alu_shift): Likewise. * config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute change. (cortex_a7_alu_reg): Likewise. (cortex_a7_alu_shift): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. (cortex_a8_alu_shift): Likewise. (cortex_a8_alu_shift_reg): Likewise. (cortex_a8_mov): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change. (cortex_a9_dp_shift): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute change. * config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute change. (cortex_r4_mov): Likewise. (cortex_r4_alu_shift): Likewise. (cortex_r4_alu_shift_reg): Likewise. * config/arm/fa526.md (526_alu_op): Update for attribute change. (526_alu_shift_op): Likewise. * config/arm/fa606te.md (606te_alu_op): Update for attribute change. * config/arm/fa626te.md (626te_alu_op): Update for attribute change. (626te_alu_shift_op): Likewise. * config/arm/fa726te.md (726te_shift_op): Update for attribute change. (726te_alu_op): Likewise. (726te_alu_shift_op): Likewise. (726te_alu_shift_reg_op): Likewise. * config/arm/fmp626.md (mp626_alu_op): Update for attribute change. (mp626_alu_shift_op): Likewise. * config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute change. (pj4_alu_e1_conds): Likewise. (pj4_alu): Likewise. (pj4_alu_conds): Likewise. (pj4_shift): Likewise. (pj4_shift_conds): Likewise. (pj4_alu_shift): Likewise. (pj4_alu_shift_conds): Likewise.
[ARM][Insn classification refactoring 4/N] Cleanup "insn" attribute
Hi, This patch is the part of the ongoing work of ARM instruction classification cleanup. This patch deletes redundant values "mrs", "msr", "xtab" and "sat" from the "insn" attribute, and moves the "clz" value to the "type" attribute. The remaining values "mov" and "mvn" will be dealt with in a separate patch. This has been tested with a full arm-none-eabi toolchain build and regression run, as well as using random code generation tests to compare the output versus a baseline compiler. OK for trunk? Thanks Sofiane arm-clear-insn-attr.diff Description: Binary data
[ARM][Insn classification refactoring 2/N] Update instruction classification documentation
Hi, This patch updates the documentation for "type" attribute. It complements the changes proposed in the previous patch OK for trunk? - Thanks Sofiane arm-update-insn-class-doc.diff Description: Binary data
[ARM][Insn classification refactoring 1/N] Move mult/div attribute values from "insn" to "type
Hi, This is the first of a series of patches to implement a single, unified and fine grained instruction classification attribute. The first few patches will propose a refactoring of the instruction classifications we currently have in place. This first patch moves the multiplication and division attribute values from "insn" to "type". OK for trunk? - Thanks Sofiane arm-move-mult-div-insn.diff Description: Binary data
[AArch64] Add r<-w alternative to aarch64_dup_lane
Hi, This patch adds a r<-w alternative to the aarch64_dup_lane pattern and updates the testcase gcc.target/aarch64/scalar_intrinsics.c accordingly. The patch has been successfully tested on a full regression run in aarch64-none-elf. OK for trunk? - Thanks Sofiane aarch64-dup-alternative.diff Description: Binary data
[AArch64] Fix move_lo_quad_ move
Hi, This patch fixes a bug in the move_lo_quad_ pattern. The pattern, shown below, issues a scalar MOV instruction for vector modes: (define_insn "move_lo_quad_" [(set (match_operand:VQ 0 "register_operand" "=w,w,w") (vec_concat:VQ (match_operand: 1 "register_operand" "w,r,r") (vec_duplicate: (const_int 0] "TARGET_SIMD" "@ mov\\t%d0, %d1 fmov\t%d0, %1 ... This is fixed by using DUP for the first alternative instead. This passes the full regression test suite in aarch64-elf. OK for trunk? - Thanks Sofiane aarch64-mov-lo-quad-fix.patch Description: Binary data
[AArch64] Split simd combine
Hi, This patch split the simd aarch64_combine pattern. This passes the full regression test suite in aarch64-elf. OK for trunk? - Thanks Sofiane aarch64-split-simd-combine.diff Description: Binary data
[AARCH64] Set "simd" attribute for *movdi_aarch64 pattern
Hi, This patch defines the "simd" attribute for the *movdi_aarch64 pattern. Tested successfully with a full regression run on aarch64-elf. OK for trunk? Thanks Sofiane aarch64-set-simd-att.diff Description: Binary data
[AARCH64] Refactor simd_mov split
Hi, This patch refactors the simd_mov split and fixes a few coding style issues. Tested successfully on a full aarch64-elf regression run. OK for trunk? Thanks Sofiane aarch64-refactor-simd-mov.diff Description: Binary data
[AArch64] Split aarch64_combine pattern
Hi, The attached patch is part of the ongoing work to enhance instruction scheduling opportunities in AArch64. This patch splits the aarch64_combine pattern, which used to issue 2 consecutive instructions. Tested successfully with a full aarch64-elf regression run. OK for trunk? Thanks Sofiane aarch64-split-simd-combine.diff Description: Binary data
[AARCH64] Split aarch64_simd_mov pattern
Hi, The attached patch is part of the ongoing work to enhance instruction scheduling opportunities in AArch64. This patch splits 2 alternatives of the aarch64_simd_mov pattern, which used to issue 2 consecutive instructions. Tested successfully with a full aarch64-elf regression run. OK for trunk? Thanks Sofiane aarch64-split-simd-mov.diff Description: Binary data
[AARCH64] Split movtf_aarch64 pattern
Hi, The attached patch is part of the ongoing work to enhance instruction scheduling opportunities in AArch64. This patch splits a few alternatives of the movtf_aarch64 pattern, which used to issue 2 consecutive instructions. Tested successfully with a full aarch64-elf regression run. OK for trunk? Thanks Sofiane aarch64-split-movtf.diff Description: Binary data
[AARCH64] Fix mov_aarch64/SHORT regression
Hi, This patch fixes a regression caused by recent changes to *mov_aarch64/SHORT. One of the pattern alternatives is trying to issue a SIMD instruction with -mgeneral-regs-only. The proposed fix is to define the "simd" attribute on the pattern in question. Thanks Sofiane - ChangeLog: gcc/ * config/aarch64/aarch64.md (*mov_aarch64): Add simd attribute. testsuite/ * gcc.target/aarch64/scalar-mov.c: New test. aarch64-fix-mov-simd-bug.diff Description: Binary data
Add AARCH64 to config-list.mk
Hi, This patch adds AARCH64 support to contrib/config-list.mk. Thanks Sofiane - ChangeLog: 2013-04-22 Sofiane Naci * config-list.mk (LIST): Add aarch64-elf and aarch64-linux-gnu. aarch64-update-config-list.patch Description: Binary data
[AARCH64] Add SHORT scalar load/store using B/H registers
Hi, This patch adds support in AArch64 for scalar loads and stores to and from B/H registers. This has been tested with a full regression run on aarch64-elf. OK for trunk and 4.8? Thanks Sofiane - 2013-03-28 Sofiane Naci * config/aarch64/aarch64.md (*mov_aarch64): Add variants for scalar load/store operations using B/H registers. (*zero_extend2_aarch64): Likewise. aarch64-scalar-load-store.patch Description: Binary data
[AARCH64] Add SHORT scalar move
Hi, This patch adds support in AArch64 for scalar moves to and from vector registers in SHORT modes. This has been tested with a full regression run on aarch64-elf. OK for trunk and 4.8? Thanks Sofiane - 2013-03-28 Sofiane Naci * config/aarch64/aarch64.md (*mov_aarch64): Add alternatives for scalar move. * config/aarch64/aarch64.c (aarch64_simd_scalar_immediate_valid_for_move): New. * config/aarch64/aarch64-protos.h (aarch64_simd_scalar_immediate_valid_for_move): New. * config/aarch64/constraints.md (Dh, Dq): New. * config/aarch64/iterators.md (hq): New. aarch64-scalar-move.patch Description: Binary data
[PATCH][AARCH64] Restrict "m" constraint for narrow moves
Hi, Loads and stores with PC-relative addresses are not supported for SHORT modes. This patch fixes a silent bug and implements this restriction for the generic "m" constraint. Tested successfully on aarch64-none-elf. OK for trunk? Thanks Sofiane - 2013-03-25 Sofiane Naci * config/aarch64/aarch64.c (aarch64_classify_address): Support PC-relative load in SI modes and above only. aarch64-restrict-m-constraint.patch Description: Binary data
[AARCH64-4.7] Merge from upstream gcc-4_7-branch r194062
Hi, I have just merged upstream gcc-4_7-branch into ARM/aarch64-4.7-branch, up to r194062. This merge didn't cause any regressions. Thanks Sofiane
[AARCH64-4.7] Merge from upstream gcc-4_7-branch r193800
Hi, I have just merged upstream gcc-4_7-branch into ARM/aarch64-4.7-branch, up to r193800. This merge didn't cause any regressions. Thanks Sofiane
[PATCH][AARCH64] Refactor constant generation
Hi, Constant building in the AArch64 backend spits out assembly code, which affects scheduling of the generated code. This patch rewrites the code to use RTL patterns. A full aarch64-none-elf regression run shows no issues. Thanks Sofiane - ChangeLog: 2012-11-26 Sofiane Naci * config/aarch64/aarch64.c (aarch64_build_constant): Update prototype. Call emit_move_insn instead of printing movi/movn/movz instructions. Call gen_insv_immdi instead of printing movk instruction. (aarch64_add_constant): Update prototype. Generate RTL instead of priting add/sub instructions. (aarch64_output_mi_thunk): Update calls to aarch64_build_constant and aarch64_add_constant. aarch64-refactor-const-gen.patch Description: Binary data
[AARCH64-4.7] Merge from upstream gcc-4_7-branch r192902
Hi, I have just merged upstream gcc-4_7-branch into ARM/aarch64-4.7-branch, up to r192902. Thanks Sofiane
[AARCH64] Merge from upstream trunk r192598
Hi, I have merged upstream trunk into ARM/aarch64-branch, up to r192598. Thanks Sofiane
[AARCH64-4.7] Merge from upstream gcc-4_7-branch r192597
Hi, I have just merged upstream gcc-4_7-branch on the aarch64-4.7-branch up to r192597. Thanks Sofiane
[AARCH64-4.7] Fix constraint and attribute for logical immediate instructions
Hi, I've just committed the attached patch on ARM/AArch64-4.7 branch. It fixes a constraint and a scheduling attribute for the3 pattern. Thanks Sofiane aarch64-update-logical-imm.patch Description: Binary data
[AARCH64] Fix constraint and attribute for logical immediate instructions
Hi, I've just committed the attached patch on ARM/AArch64 branch. It fixes a constraint and a scheduling attribute for the3 pattern. Thanks Sofiane aarch64-update-logical-imm.patch Description: Binary data
[AARCH64] Merge from upstream trunk r192445
Hi, I have just merged upstream trunk on the aarch64-branch up to r192445. Thanks Sofiane
[AARCH64-4.7] Merge from upstream gcc-4_7-branch r192444
Hi, I have just merged upstream gcc-4_7-branch on the aarch64-4.7-branch up to r192444. Thanks Sofiane
[AARCH64] Merge from upstream trunk r192192
Hi, I have just merged upstream trunk on the aarch64-branch up to r192192. Thanks Sofiane
[AARCH64-4.7] Merge from upstream gcc-4_7-branch r192191
Hi, I have just merged upstream gcc-4_7-branch on the aarch64-4.7-branch up to r192191. Thanks Sofiane
[AARCH64-4.7] Merge from upstream gcc-4_7-branch r191881
Hi, I have just merged upstream gcc-4_7-branch on the aarch64-4.7-branch up to r191881. Thanks Sofiane
[AARCH64] Merge from upstream trunk r191882
Hi, I have just merged upstream trunk on the aarch64-branch up to r191882. Thanks Sofiane
[PATCH, WWWDOCS] Document AArch64-4.7 branch
Hi, This patch documents the AArch64-4.7 branch in wwwdocs/htdocs/svn.html. OK? Thanks Sofiane - Proposed ChangeLog: * htdocs/svn.html: Document aarch64-4.7 branch. aarch64-4.7-branch-wwwdocs.patch Description: Binary data
[AArch64] Merge from upstream trunk r191370
Hi, I have just merged upstream trunk on the aarch64-branch up to r191370. Thanks Sofiane
RE: [AArch64, AArch64-4.7] Fix target ordering in config.gcc.
Now with the patch properly attached. Apologies. Sofiane > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Sofiane Naci > Sent: 13 September 2012 13:18 > To: gcc-patches@gcc.gnu.org > Subject: [AArch64, AArch64-4.7] Fix target ordering in config.gcc. > > Hi, > > I've just committed the attached patch on the branches > >ARM/aarch64-branch >ARM/aarch64-4.7-branch > > to fix the target ordering in supported_defaults in config.gcc. > > Thank you > Sofiane > > > > aarch64-fix-order-config.patch Description: Binary data
[AArch64, AArch64-4.7] Fix target ordering in config.gcc.
Hi, I've just committed the attached patch on the branches ARM/aarch64-branch ARM/aarch64-4.7-branch to fix the target ordering in supported_defaults in config.gcc. Thank you Sofiane
[AArch64] Merge from upstream trunk r191124
Hi, I have just merged upstream trunk on the aarch64-branch up to r191124. As a result, I have also updated the AArch64 backend with the attached patch. Thanks Sofiane aarch64-191124-rebase.patch Description: Binary data
[AARCH64] AArch64 backport to 4.7
[AARCH64] AArch64 backport to 4.7. This series of patches implements a back port of the AArch64 backend to gcc-4.7. This patch series is not intended to be applied directly to the gcc-4_7-branch branch. We have pushed a new branch into SVN to host this back port, located at: svn://gcc.gnu.org/gcc/branches/ARM/aarch64-4.7-branch This branch will track 4.7. Patches to this branch should be tagged "[AARCH64-4.7]" and must be approved by ARM personnel. The branch was constructed using the following steps: . Copied gcc-4_7-branch. . Copied the AArch64 port from ARM/aarch64-branch. . Applied the attached AArch64 backport patch. . Applied the attached backport patch to implement integer iterators. . Updated config.sub and config.guess from upstream gnuconfig. Thank you aarch64-backport.patch Description: Binary data aarch64-int-iterators-backport.patch Description: Binary data
[AArch64] Merge from upstream trunk r190706
Hi, I've just merged upstream trunk on the aarch64-branch up to r190706. Thanks Sofiane
RE: [AARCH64] [PATCH 2/3] AArch64 Port
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Joseph S. Myers
> Sent: 25 May 2012 15:24
> To: Marcus Shawcroft
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [AARCH64] [PATCH 2/3] AArch64 Port
>
> On Fri, 25 May 2012, Marcus Shawcroft wrote:
>
> > Index: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.x
> > ===
> > --- gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.x (revision
> 0)
> > +++ gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.x (revision
> 0)
> > @@ -0,0 +1,5 @@
> > +if { [istarget aarch64_be-*-*] } then {
> > + return 1
> > +}
> > +
> > +return 0
>
> This isn't a suitable way of enabling a test only for one endianness,
> since a test may be run with -mbig-endian or -mlittle-endian with a
> compiler defaulting to the other endianness. You need to test an
> effective-target keyword instead.
>
> > Index: gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.x
> > ===
> > --- gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.x (revision
> 0)
> > +++ gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.x (revision
> 0)
> > @@ -0,0 +1,5 @@
> > +if { [istarget aarch64_be-*-*] } then {
> > + return 1
> > +}
> > +
> > +return 0
>
> Likewise.
Thanks. This is now fixed in:
r190482 | sofiane | 2012-08-17 16:02:20 +0100 (Fri, 17 Aug 2012) | 9 lines
[AArch64] Use effective-target to check for big endian
Sofiane
RE: [AARCH64] [PATCH 1/3] AArch64 Port
Hi,
Thanks for the feedback. I respond here to the remaining issues:
> > Index: gcc/doc/extend.texi
> > ===
> > --- gcc/doc/extend.texi (revision 187870)
> > +++ gcc/doc/extend.texi (working copy)
> > @@ -935,7 +935,8 @@
> >
> > Not all targets support additional floating point types.
> @code{__float80}
> > and @code{__float128} types are supported on i386, x86_64 and ia64
> targets.
> > -The @code{__float128} type is supported on hppa HP-UX targets.
> > +The @code{__float128} type is supported on hppa HP-UX targets and
> ARM AArch64
> > +targets.
>
> I don't see any good reason to support it on AArch64, since it's the
> same as "long double" there. (It's on PA HP-UX as a workaround for
> libquadmath requiring the type rather than being able to with with a
> type called either "long double" or "__float128" - libquadmath being
> used on PA HP-UX as a workaround for the system libm lacking much long
> double support. But that shouldn't be an issue for new targets such
> as AArch64 GNU/Linux. And my understanding from N1582 is that the C
> bindings for IEEE 754-2008, being worked on for a five-part ISO/IEC
> TS, are expected to use names such as _Float128, not __float128, as
> standard names for supported IEEE floating-point types.)
Support for __float128 has been removed.
Fixed in:
r189655 | sofiane | 2012-07-19 13:24:57 +0100 (Thu, 19 Jul 2012) | 19 lines
[AArch64] Remove __float128 support.
> > +@opindex mbig-endian
> > +Generate big-endian code. This is the default when GCC is configured
> for an
> > +@samp{aarch64*be-*-*} target.
>
> In general, throughout Texinfo changes, two spaces after "." at the
> end of a sentence.
>
> > +@item -march=@var{name}
> > +@opindex march
> > +Specify the name of the target architecture, optionally suffixed by
> one or
> > +more feature modifiers. This option has the form
> > +@samp{-march=[+[no]]}, where the only value for
> @samp{}
> > +is @samp{armv8}, and the possible values for @samp{} are
> > +@samp{crypto}, @samp{fp}, @samp{simd}.
>
> It's unfortunate that you've chosen this complicated syntax that means
> the generic support for enumerated option arguments cannot be used
> (and so --help information cannot list supported CPUs and features).
> A simpler syntax where -march takes just an architecture name and
> features have separate options would seem better, and more in line
> with most other architectures supported by GCC.
>
> There are several Texinfo problems above. Instead of you
> should use @var{feature}, and since the '[' and ']' are not literal
> text they should be inside @r{} - the proper way of writing
> @samp{-march=[+[no]]} would be
> @option{-march=@var{arch}@r{[}+@r{[}no@r{]}@var{feature}@r{]}}.
>
> Also, could you document what the feature names mean?
Documentation formatting has been fixed to conform to the required styling.
Also the documentation has been updated to clarify ambiguous parts or add
missing ones.
Fixed in:
r188895 | belagod | 2012-06-22 18:23:05 +0100 (Fri, 22 Jun 2012) | 11 lines
[AArch64] Fix documentation layout.
> > +@item -mcpu=@var{name}
> > +@opindex mcpu
> > +Specify the name of the target processor, optionally suffixed by one
> or more
> > +feature modifiers. This option has the form @samp{-
> cpu=[+[no]]},
> > +where the possible values for @samp{} are @samp{generic},
> @samp{large},
> > +and the possible values for @samp{} are @samp{crypto},
> @samp{fp},
> > +@samp{simd}.
>
> Same comments apply.
Same as above.
Fixed in:
r188895 | belagod | 2012-06-22 18:23:05 +0100 (Fri, 22 Jun 2012) | 11 lines
[AArch64] Fix documentation layout.
> > +This option is very similar to the -mcpu= option, except that
> instead of
>
> @option{-mcpu=}. And does -mtune= take feature names or just plain CPU
> names?
Same as above.
Fixed in:
r188895 | belagod | 2012-06-22 18:23:05 +0100 (Fri, 22 Jun 2012) | 11 lines
[AArch64] Fix documentation layout.
> > + if (mvn == 0)
> > + {
> > + if (widthc != 'd')
> > + sprintf (templ,"movi\t%%0.%d%c, %%1, lsl %d ",(64/width),
> > + widthc, shift);
> > + else
> > + sprintf (templ,"movi\t%%d0, %%1");
> > + }
> > + else
> > + sprintf (templ,"mvni\t%%0.%d%c, %%1, lsl %d",(64/width),
> > + widthc, shift);
>
> Presumably you have some logic for why the 40-byte buffer size is
> enough, but could you use snprintf with sizeof (templ) specified in
> the call to protect against any mistakes in that logic? Also, spaces
> after commas and around the "/" in the division, and the second line
> in the function call should be lined up immediately after the opening
> '(', not further right. (Check for and fix all these issues elsewhere
> in the port as well; I've just pointed out a representative instance
> of them.)
sprinsf has been replaced with snprintf and sizeof (tem
[AArch64] Do not mix statements with declarations
Hi, I've just committed the attached patch on the AArch64 branch to fix a style issue related to mixing statements with declarations. Thanks Sofiane - r190486 | sofiane | 2012-08-17 16:26:47 +0100 (Fri, 17 Aug 2012) | 7 lines 2012-08-17 Marcus Shawcroft [AArch64] Do not mix statements and declarations. * config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Do not mix statements with declarations. aarch64-do-not-mix-stmt-decl.patch Description: Binary data
[AArch64] implement FSQRT in RTL.
Hi, I've just committed the attached patch on the AArch64 branch to implement FSQRT in RTL. Thanks Sofiane - r190485 | sofiane | 2012-08-17 16:22:28 +0100 (Fri, 17 Aug 2012) | 12 lines 2012-08-17 Tejas Belagod [AArch64] Implement FSQRT in RTL. * config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_data): Add sqrt to the list of intrinsic descriptors. * config/aarch64/aarch64-simd.md (sqrt2): Insn pattern for sqrt. (aarch64_sqrt): Builtin expansion. * config/aarch64/arm_neon.h: Remove asm implementations of vsqrt. Add builtin implementation of vsqrt. aarch64-fsqrt.patch Description: Binary data
[AArch64] implement vmlsq_laneq_*
Hi, I've just committed the attached patch on the AArch64 branch to implement vmlsq_laneq_*. Thanks Sofiane - r190484 | sofiane | 2012-08-17 16:15:49 +0100 (Fri, 17 Aug 2012) | 11 lines Tejas Belagod [AArch64] Implement vmlsq_laneq_*. gcc/ * config/aarch64/arm_neon.h (vmlsq_laneq_f32, vmlsq_laneq_s16, vmlsq_laneq_u16, vmlsq_laneq_s32, vmlsq_laneq_u32): New. testsuite/ * gcc.target/aarch64/vmlsq_laneq.c: New. aarch64-vmlsq-laneq.patch Description: Binary data
[AArch64] Use effective-target keyword to test for endianness
Hi, I've just committed the attached patch on the AArch64 branch to use effective-target keyword to test for endianness. Thanks Sofiane - r190482 | sofiane | 2012-08-17 16:02:20 +0100 (Fri, 17 Aug 2012) | 9 lines [AArch64] Use effective-target to check for big endian gcc/testsuite * lib/target-supports.exp (check_effective_target_aarch64_big_endian): New. * gcc.target/aarch64/aapcs64/func-ret-3.c: Add dg-require-effective-target. * gcc.target/aarch64/aapcs64/func-ret-4.c: Likewise. * gcc.target/aarch64/aapcs64/func-ret-3.x: Delete. * gcc.target/aarch64/aapcs64/func-ret-4.x: Delete. aarch64-be-effective-target.patch Description: Binary data
[AArch64] Add new testcases and improve diagnostics
Hi, I've just committed the attached patch on the AArch64 branch to add new testcases and improve diagnostics. Thanks Sofiane - r190481 | sofiane | 2012-08-17 15:53:50 +0100 (Fri, 17 Aug 2012) | 11 lines [AArch64] Add new testcases to improve diagnostics. gcc/ * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Fix diagnostics. gcc/testsuite * gcc.target/aarch64/arch-diagnostics-*.c: New testcase. * gcc.target/aarch64/arg-type-diagnostics-1.c: Likewise. * gcc.target/aarch64/cpu-diagnostics-*.c: Likewise. aarch64-add-diagnostics.patch Description: Binary data
[AArch64] Merge from upstream trunk r190154
Hi, I've just merged upstream trunk on the aarch64-branch up to r190335. Thanks Sofiane
[AArch64] Merge from upstream trunk r190154
Hi, I've just merged upstream trunk on the aarch64-branch up to r190154. Thanks Sofiane
[AArch64] Merge from upstream trunk r189905
Hi, I've just merged upstream trunk on the aarch64-branch up to r189905. Thanks Sofiane
[AArch64] Merge from upstream trunk reverted
Hi, I've just reverted my recent merge from upstream trunk on the aarch64-branch (r190119). A cleaner and broader merge will follow. Thanks Sofiane
[AArch64] Improve diagnostics
Hi, I've just committed this patch on the AArch64 branch to improve diagnostics and error messages. Thanks Sofiane > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Sofiane Naci > Sent: 13 June 2012 14:30 > To: gcc-patches@gcc.gnu.org > Subject: [PATCH, GCC][AArch64] Fix diagnostics issues > > Hi, > > This patch fixes some diagnostics wording and formatting issues in the > AArch64 port. > A patch that adds missing test cases for some of these diagnostics will be > sent separately. > > Thanks > Sofiane > > - > > 2012-06-11 Sofiane Naci > > [AArch64] Fix diagnosis issues. > > * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Use > error_at and fix quoting in error message. > * config/aarch64/aarch64.c > (aarch64_parse_extension): Update error messages and fix quoting. > (aarch64_parse_arch): Likewise. > (aarch64_parse_cpu): Likewise. > (aarch64_parse_tune): Likewise. aarch64-improve-diagnostics.patch Description: Binary data
[AArch64] Remove support for __float128
Hi, I've just committed this patch on the AArch64 branch to remove __float128 support. Thanks Sofiane > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Sofiane Naci > Sent: 11 June 2012 15:52 > To: gcc-patches@gcc.gnu.org > Subject: [PATCH, GCC][AArch64] Remove support for __float128 > > Hi, > > This patch removes __float128 support in the AArch64 port. > > Thanks > Sofiane > > - > > gcc/ChangeLog: > > 2012-06-11 Sofiane Naci > > [AArch64] Remove __float128 support. > > * config/aarch64/aarch64.c > (aarch64_mangle_type): Remove function. > (aarch64_init_builtins): Remove __float128 support. > (aarch64_expand_builtin): Likewise. > (TARGET_MANGLE_TYPE): Remove definition. > * config/aarch64/aarch64.h (enum aarch64_builtins): Update. > * doc/extend.texi: Remove __float128 documentation. > > > gcc/testsuite/ChangeLog: > > 2012-06-11 Sofiane Naci > > [AArch64] Remove __float128 support. > > * gcc.dg/const-float128-ped.c: Remove AArch64 from list of > targets. > * gcc.dg/const-float128.c: Likewise. > * gcc.dg/torture/fp-int-convert-float128-timode.c: Likewise. > * gcc.dg/torture/fp-int-convert-float128.c: Likewise. aarch64-remove-float128.patch Description: Binary data
[AArch64] Fix bound check diagnostics.
Hi, I've just committed this patch on the AArch64 branch to improve bound checks diagnostics. Thanks Sofiane > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Sofiane Naci > Sent: 14 June 2012 10:38 > To: gcc-patches@gcc.gnu.org > Subject: [PATCH, GCC][AArch64] Fix bound check diagnostics. > > Hi, > > This patch improves bound check diagnostics code. > > Thanks > Sofiane > > - > > 2012-06-13 Sofiane Naci > > [AArch64] Fix bound check diagnostics. > > * gcc/config/aarch64/aarch64.c > (bounds_check): Remove. > (aarch64_simd_lane_bounds): Replace call to bounds_check with > function > body. > (aarch64_simd_const_bounds): Likewise. aarch64-bound-check-diagnostics.patch Description: Binary data
[PATCH, GCC][AArch64] Update LINK_SPEC
Hi,
This patch updates LINK_SPEC in the AArch64 port.
Thanks
Sofiane
-
2012-06-14 Sofiane Naci
[AArch64] Update LINK_SPEC.
* config/aarch64/aarch64-linux.h (LINUX_TARGET_LINK_SPEC): Remove
%{version:-v}, %{b} and %{!dynamic-linker}.
aarch64-linux-specs.patch
Description: Binary data
[PATCH, GCC][AArch64] Fix bound check diagnostics.
Hi, This patch improves bound check diagnostics code. Thanks Sofiane - 2012-06-13 Sofiane Naci [AArch64] Fix bound check diagnostics. * gcc/config/aarch64/aarch64.c (bounds_check): Remove. (aarch64_simd_lane_bounds): Replace call to bounds_check with function body. (aarch64_simd_const_bounds): Likewise. aarch64-bound-check-diagnostics.patch Description: Binary data
RE: [PATCH, GCC][AArch64] Use Enums for code models option selection
Hi, I discovered a bug in my previous patch, so I attach a new one. The ChangeLog hasn't changed. OK to commit? Thanks Sofiane > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Sofiane Naci > Sent: 31 May 2012 10:55 > To: gcc-patches@gcc.gnu.org > Subject: [PATCH, GCC][AArch64] Use Enums for code models option selection > > Hi, > > This patch re-factors code models option selection in the AArch64 port: > > . Renaming variables such as mem_model to cmodel, for better clarity. > . Using the generic support for enumerated option arguments. > . Fixing touched code layout and formatting issues. > > Thanks > Sofiane > > - > > ChangeLog: > > 2012-05-31 Sofiane Naci > > [AArch64] Use Enums for code models option selection. > > * config/aarch64/aarch64-elf-raw.h (AARCH64_DEFAULT_MEM_MODEL): > Delete. > * config/aarch64/aarch64-linux.h (AARCH64_DEFAULT_MEM_MODEL): > Delete. > * config/aarch64/aarch64-opts.h (enum aarch64_code_model): New. > * config/aarch64/aarch64-protos.h: Update comments. > * config/aarch64/aarch64.c: Update comments. > (aarch64_default_mem_model): Rename to aarch64_code_model. > (aarch64_expand_mov_immediate): Remove error message. > (aarch64_select_rtx_section): Remove assertion and update comment. > (aarch64_override_options): Move memory model initialization from > here. > (struct aarch64_mem_model): Delete. > (aarch64_memory_models[]): Delete. > (initialize_aarch64_memory_model): Rename to > initialize_aarch64_code_model > and update. > (aarch64_classify_symbol): Handle AARCH64_CMODEL_TINY and > AARCH64_CMODEL_TINY_PIC > * config/aarch64/aarch64.h > (enum aarch64_memory_model): Delete. > (aarch64_default_mem_model): Rename to aarch64_cmodel. > (HAS_LONG_COND_BRANCH): Update. > (HAS_LONG_UNCOND_BRANCH): Update. > * config/aarch64/aarch64.opt > (cmodel): New. > (mcmodel): Update. aarch64-use-enums-for-cmodels.patch Description: Binary data
[PATCH, GCC][AArch64] Fix diagnostics issues
Hi, This patch fixes some diagnostics wording and formatting issues in the AArch64 port. A patch that adds missing test cases for some of these diagnostics will be sent separately. Thanks Sofiane - 2012-06-11 Sofiane Naci [AArch64] Fix diagnosis issues. * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Use error_at and fix quoting in error message. * config/aarch64/aarch64.c (aarch64_parse_extension): Update error messages and fix quoting. (aarch64_parse_arch): Likewise. (aarch64_parse_cpu): Likewise. (aarch64_parse_tune): Likewise. aarch64-improve-diagnostics.patch Description: Binary data
[PATCH, GCC][AArch64] Remove support for __float128
Hi, This patch removes __float128 support in the AArch64 port. Thanks Sofiane - gcc/ChangeLog: 2012-06-11 Sofiane Naci [AArch64] Remove __float128 support. * config/aarch64/aarch64.c (aarch64_mangle_type): Remove function. (aarch64_init_builtins): Remove __float128 support. (aarch64_expand_builtin): Likewise. (TARGET_MANGLE_TYPE): Remove definition. * config/aarch64/aarch64.h (enum aarch64_builtins): Update. * doc/extend.texi: Remove __float128 documentation. gcc/testsuite/ChangeLog: 2012-06-11 Sofiane Naci [AArch64] Remove __float128 support. * gcc.dg/const-float128-ped.c: Remove AArch64 from list of targets. * gcc.dg/const-float128.c: Likewise. * gcc.dg/torture/fp-int-convert-float128-timode.c: Likewise. * gcc.dg/torture/fp-int-convert-float128.c: Likewise. aarch64-remove-float128.patch Description: Binary data
[PATCH, GCC DOC][AArch64] Fix layout in AArch64 target-specific documentation
Hi, This patch fixes several layout, formatting and wording issues in the AArch64 target-specific documentation. Thanks Sofiane - 2012-06-11 Sofiane Naci [AArch64] Fix documentation layout. * doc/invoke.texi: Fix white spaces after dots. Change aarch64*be-*-* to aarch64_be-*-*. Add documentation for -mcmodel=tiny. (-march): Fix formatting. (-mcpu): Likewise. (-mtune): Rephrase. (-march and -mcpu feature modifiers): New subsubsection. aarch64-fix-doc.patch Description: Binary data
[PATCH, GCC][AArch64] Use Enums for TLS dialect option selection
Hi, This patch re-factors TLS dialect option selection in the AArch64 port to use the generic support for enumerated option arguments. Thanks Sofiane - 2012-06-01 Sofiane Naci [AArch64] Use Enums for TLS option selection. * config/aarch64/aarch64-opts.h (enum aarch64_tls_type): New. * config/aarch64/aarch64.c (aarch64_tls_dialect): Remove. (tls_symbolic_operand_type): Update comment. (aarch64_override_options): Remove TLS option setup code. * config/aarch64/aarch64.h (TARGET_TLS_TRADITIONAL): Remove. (TARGET_TLS_DESC): Update definition. (enum tls_dialect): Remove. (enum tls_dialect aarch64_tls_dialect) Remove. * config/aarch64/aarch64.opt (tls_type): New. (mtls-dialect): Update. aarch64-use-enums-for-tls.patch Description: Binary data
[AArch64] Use snprintf instead sprintf
Hi, This patch replaces instances of sprintf with snprintf with sizeof(..) in the AArch64 port. It also fixes layout issues in the code it touches. Thanks Sofiane - ChangeLog 2012-06-01 Sofiane Naci [AArch64] Replace sprintf with snprintf. * config/aarch64/aarch64.c (aarch64_elf_asm_constructor): Replace sprintf with snprintf. (aarch64_elf_asm_destructor): Likewise. (aarch64_output_casesi): Likewise. (aarch64_output_asm_insn): Likewise. * config/aarch64/aarch64-builtins.c (init_aarch64_simd_builtins): Likewise. * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Replace sprintf with snprintf, and fix code layout. aarch64-snprintf.patch Description: Binary data
[PATCH, GCC][AArch64] Use Enums for code models option selection
Hi, This patch re-factors code models option selection in the AArch64 port: . Renaming variables such as mem_model to cmodel, for better clarity. . Using the generic support for enumerated option arguments. . Fixing touched code layout and formatting issues. Thanks Sofiane - ChangeLog: 2012-05-31 Sofiane Naci [AArch64] Use Enums for code models option selection. * config/aarch64/aarch64-elf-raw.h (AARCH64_DEFAULT_MEM_MODEL): Delete. * config/aarch64/aarch64-linux.h (AARCH64_DEFAULT_MEM_MODEL): Delete. * config/aarch64/aarch64-opts.h (enum aarch64_code_model): New. * config/aarch64/aarch64-protos.h: Update comments. * config/aarch64/aarch64.c: Update comments. (aarch64_default_mem_model): Rename to aarch64_code_model. (aarch64_expand_mov_immediate): Remove error message. (aarch64_select_rtx_section): Remove assertion and update comment. (aarch64_override_options): Move memory model initialization from here. (struct aarch64_mem_model): Delete. (aarch64_memory_models[]): Delete. (initialize_aarch64_memory_model): Rename to initialize_aarch64_code_model and update. (aarch64_classify_symbol): Handle AARCH64_CMODEL_TINY and AARCH64_CMODEL_TINY_PIC * config/aarch64/aarch64.h (enum aarch64_memory_model): Delete. (aarch64_default_mem_model): Rename to aarch64_cmodel. (HAS_LONG_COND_BRANCH): Update. (HAS_LONG_UNCOND_BRANCH): Update. * config/aarch64/aarch64.opt (cmodel): New. (mcmodel): Update. aarch64-use-enums-for-cmodels.patch Description: Binary data
