This patch reduces code size by putting each of the shift library functions from
libgcc in their own section. This means that, for example, a 16-bit logical
left shift does not result in code to perform a 32-bit logical left shift being
included in the final executable, as the linker can now garbage collect unused
sections.
For the following program, the below code size reduction is observed:
int a, b;
int
main (void)
{
a = a << b;
return 0;
}
Current trunk:
textdata bss dec hex filename
572 12 22 606 25e a.out
With patch:
textdata bss dec hex filename
466 12 22 500 1f4 a.out
Ok for trunk?
>From 8017a4b453ae1b07bbeb75f7f7613a5bc5605159 Mon Sep 17 00:00:00 2001
From: Jozef Lawrynowicz
Date: Mon, 13 May 2019 17:42:08 +0100
Subject: [PATCH 1/4] MSP430: Put the library functions for bitwise shifts in
their own sections
libgcc/ChangeLog
2019-06-04 Jozef Lawrynowicz
* config/msp430/slli.S (__mspabi_slli_n): Put function in its own
section.
(__mspabi_slli): Likewise.
(__mspabi_slll_n): Likewise.
(__mspabi_slll): Likewise.
* config/msp430/srai.S (__mspabi_srai_n): Likewise.
(__mspabi_srai): Likewise.
(__mspabi_sral_n): Likewise.
(__mspabi_sral): Likewise.
* config/msp430/srli.S (__mspabi_srli_n): Likewise.
(__mspabi_srli): Likewise.
(__mspabi_srll_n): Likewise.
(__mspabi_srll): Likewise.
---
libgcc/config/msp430/slli.S | 8 ++--
libgcc/config/msp430/srai.S | 8 ++--
libgcc/config/msp430/srli.S | 8 ++--
3 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/libgcc/config/msp430/slli.S b/libgcc/config/msp430/slli.S
index 9d151a97f5d..89ca35a9304 100644
--- a/libgcc/config/msp430/slli.S
+++ b/libgcc/config/msp430/slli.S
@@ -22,8 +22,9 @@
.text
-/* Logical Left Shift - R12 -> R12 */
+/* Logical Left Shift - R12 -> R12. */
+ .section .text.__mspabi_slli_n
.macro _slli n
.global __mspabi_slli_\n
__mspabi_slli_\n:
@@ -51,6 +52,7 @@ __mspabi_slli_\n:
RET
#endif
+ .section .text.__mspabi_slli
1: ADD.W #-1,R13
ADD.W R12,R12
.global __mspabi_slli
@@ -63,8 +65,9 @@ __mspabi_slli:
RET
#endif
-/* Logical Left Shift - R12:R13 -> R12:R13 */
+/* Logical Left Shift - R12:R13 -> R12:R13. */
+ .section .text.__mspabi_slll_n
.macro _slll n
.global __mspabi_slll_\n
__mspabi_slll_\n:
@@ -93,6 +96,7 @@ __mspabi_slll_\n:
RET
#endif
+ .section .text.__mspabi_slll
1: ADD.W #-1,R14
ADD.W R12,R12
ADDC.W R13,R13
diff --git a/libgcc/config/msp430/srai.S b/libgcc/config/msp430/srai.S
index 33c9b5ee62d..564f7989a8c 100644
--- a/libgcc/config/msp430/srai.S
+++ b/libgcc/config/msp430/srai.S
@@ -22,13 +22,14 @@
.text
+ .section .text.__mspabi_srai_n
.macro _srai n
.global __mspabi_srai_\n
__mspabi_srai_\n:
RRA.W R12
.endm
-/* Logical Right Shift - R12 -> R12 */
+/* Arithmetic Right Shift - R12 -> R12. */
_srai 15
_srai 14
_srai 13
@@ -50,6 +51,7 @@ __mspabi_srai_\n:
RET
#endif
+ .section .text.__mspabi_srai
1: ADD.W #-1,R13
RRA.W R12,R12
.global __mspabi_srai
@@ -62,8 +64,9 @@ __mspabi_srai:
RET
#endif
-/* Logical Right Shift - R12:R13 -> R12:R13 */
+/* Arithmetic Right Shift - R12:R13 -> R12:R13. */
+ .section .text.__mspabi_sral_n
.macro _sral n
.global __mspabi_sral_\n
__mspabi_sral_\n:
@@ -92,6 +95,7 @@ __mspabi_sral_\n:
RET
#endif
+ .section .text.__mspabi_sral
1: ADD.W #-1,R14
RRA.W R13
RRC.W R12
diff --git a/libgcc/config/msp430/srli.S b/libgcc/config/msp430/srli.S
index dbe37f67a7d..4dd32ea4002 100644
--- a/libgcc/config/msp430/srli.S
+++ b/libgcc/config/msp430/srli.S
@@ -22,6 +22,7 @@
.text
+ .section .text.__mspabi_srli_n
.macro _srli n
.global __mspabi_srli_\n
__mspabi_srli_\n:
@@ -29,7 +30,7 @@ __mspabi_srli_\n:
RRC.W R12
.endm
-/* Logical Right Shift - R12 -> R12 */
+/* Logical Right Shift - R12 -> R12. */
_srli 15
_srli 14
_srli 13
@@ -51,6 +52,7 @@ __mspabi_srli_\n:
RET
#endif
+ .section .text.__mspabi_srli
1: ADD.W #-1,R13
CLRC
RRC.W R12,R12
@@ -64,8 +66,9 @@ __mspabi_srli:
RET
#endif
-/* Logical Right Shift - R12:R13 -> R12:R13 */
+/* Logical Right Shift - R12:R13 -> R12:R13. */
+ .section .text.__mspabi_srll_n
.macro _srll n
.global __mspabi_srll_\n
__mspabi_srll_\n:
@@ -95,6 +98,7 @@ __mspabi_srll_\n:
RET
#endif
+ .section .text.__mspabi_srll
1: ADD.W #-1,R14
CLRC
RRC.W R13
--
2.17.1