[PATCH 09/13] [APX EGPR] Handle legacy insn that only support GPR16 (1/5)
From: Kong Lingling These legacy insn in opcode map0/1 only support GPR16, and do not have vex/evex counterpart, directly adjust constraints and add gpr32 attr to patterns. insn list: 1. xsave/xsave64, xrstor/xrstor64 2. xsaves/xsaves64, xrstors/xrstors64 3. xsavec/xsavec64 4. xsaveopt/xsaveopt64 5. fxsave64/fxrstor64 gcc/ChangeLog: * config/i386/i386.md (): Set attr gpr32 0 and constraint jm. (_rex64): Likewise. (_rex64): Likewise. (64): Likewise. (fxsave64): Likewise. (fxstore64): Likewise. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add apxf check. * gcc.target/i386/apx-legacy-insn-check-norex2.c: New test. * gcc.target/i386/apx-legacy-insn-check-norex2-asm.c: New assembler test. Co-authored-by: Hongyu Wang Co-authored-by: Hongtao Liu --- gcc/config/i386/i386.md | 18 +++ .../i386/apx-legacy-insn-check-norex2-asm.c | 5 .../i386/apx-legacy-insn-check-norex2.c | 30 +++ gcc/testsuite/lib/target-supports.exp | 10 +++ 4 files changed, 57 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index b9eaea78f00..6cf86b798a8 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -25626,11 +25626,12 @@ (define_insn "fxsave" (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "fxsave64" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=jm") (unspec_volatile:BLK [(const_int 0)] UNSPECV_FXSAVE64))] "TARGET_64BIT && TARGET_FXSR" "fxsave64\t%0" [(set_attr "type" "other") + (set_attr "gpr32" "0") (set_attr "memory" "store") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25646,11 +25647,12 @@ (define_insn "fxrstor" (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "fxrstor64" - [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")] + [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "jm")] UNSPECV_FXRSTOR64)] "TARGET_64BIT && TARGET_FXSR" "fxrstor64\t%0" [(set_attr "type" "other") + (set_attr "gpr32" "0") (set_attr "memory" "load") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25704,7 +25706,7 @@ (define_insn "" (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "_rex64" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=jm") (unspec_volatile:BLK [(match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] @@ -25713,11 +25715,12 @@ (define_insn "_rex64" "\t%0" [(set_attr "type" "other") (set_attr "memory" "store") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=jm") (unspec_volatile:BLK [(match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] @@ -25726,6 +25729,7 @@ (define_insn "" "\t%0" [(set_attr "type" "other") (set_attr "memory" "store") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25743,7 +25747,7 @@ (define_insn "" (define_insn "_rex64" [(unspec_volatile:BLK - [(match_operand:BLK 0 "memory_operand" "m") + [(match_operand:BLK 0 "memory_operand" "jm") (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] ANY_XRSTOR)] @@ -25751,12 +25755,13 @@ (define_insn "_rex64" "\t%0" [(set_attr "type" "other") (set_attr "memory" "load") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "64" [(unspec_volatile:BLK - [(match_operand:BLK 0 "memory_operand" "m") + [(match_operand:BLK 0 "memory_operand" "jm") (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] ANY_XRSTOR64)] @@ -25764,6 +25769,7 @@ (define_insn "64" "64\t%0" [(set_attr "type" "other") (set_attr "memory" "load") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) diff --git a/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c new file mode 100644 index 000..7ecc861435f ---
Re: [PATCH 09/13] [APX EGPR] Handle legacy insn that only support GPR16 (1/5)
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote: > > From: Kong Lingling > > These legacy insn in opcode map0/1 only support GPR16, > and do not have vex/evex counterpart, directly adjust constraints and > add gpr32 attr to patterns. > > insn list: > 1. xsave/xsave64, xrstor/xrstor64 > 2. xsaves/xsaves64, xrstors/xrstors64 > 3. xsavec/xsavec64 > 4. xsaveopt/xsaveopt64 > 5. fxsave64/fxrstor64 IMO, instructions should be handled with a reversed approach. Add "h" constraint (and memory constraint that can handle EGPR) to instructions that CAN use EGPR (together with a relevant "enabled" attribute. We have had the same approach with "x" to "v" transition with SSE registers. If we "forgot" to add "v" to the instruction, it still worked, but not to its full potential w.r.t available registers. Uros. > > gcc/ChangeLog: > > * config/i386/i386.md (): Set attr gpr32 0 and constraint > Bt. > (_rex64): Likewise. > (_rex64): Likewise. > (64): Likewise. > (fxsave64): Likewise. > (fxstore64): Likewise. > > gcc/testsuite/ChangeLog: > > * lib/target-supports.exp: Add apxf check. > * gcc.target/i386/apx-legacy-insn-check-norex2.c: New test. > * gcc.target/i386/apx-legacy-insn-check-norex2-asm.c: New assembler > test. > --- > gcc/config/i386/i386.md | 18 +++ > .../i386/apx-legacy-insn-check-norex2-asm.c | 5 > .../i386/apx-legacy-insn-check-norex2.c | 30 +++ > gcc/testsuite/lib/target-supports.exp | 10 +++ > 4 files changed, 57 insertions(+), 6 deletions(-) > create mode 100644 > gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c > create mode 100644 > gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index b9eaea78f00..83ad01b43c1 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -25626,11 +25626,12 @@ (define_insn "fxsave" > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "fxsave64" > - [(set (match_operand:BLK 0 "memory_operand" "=m") > + [(set (match_operand:BLK 0 "memory_operand" "=Bt") > (unspec_volatile:BLK [(const_int 0)] UNSPECV_FXSAVE64))] >"TARGET_64BIT && TARGET_FXSR" >"fxsave64\t%0" >[(set_attr "type" "other") > + (set_attr "gpr32" "0") > (set_attr "memory" "store") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) > @@ -25646,11 +25647,12 @@ (define_insn "fxrstor" > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "fxrstor64" > - [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")] > + [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "Bt")] > UNSPECV_FXRSTOR64)] >"TARGET_64BIT && TARGET_FXSR" >"fxrstor64\t%0" >[(set_attr "type" "other") > + (set_attr "gpr32" "0") > (set_attr "memory" "load") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) > @@ -25704,7 +25706,7 @@ (define_insn "" > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "_rex64" > - [(set (match_operand:BLK 0 "memory_operand" "=m") > + [(set (match_operand:BLK 0 "memory_operand" "=Bt") > (unspec_volatile:BLK > [(match_operand:SI 1 "register_operand" "a") > (match_operand:SI 2 "register_operand" "d")] > @@ -25713,11 +25715,12 @@ (define_insn "_rex64" >"\t%0" >[(set_attr "type" "other") > (set_attr "memory" "store") > + (set_attr "gpr32" "0") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "" > - [(set (match_operand:BLK 0 "memory_operand" "=m") > + [(set (match_operand:BLK 0 "memory_operand" "=Bt") > (unspec_volatile:BLK > [(match_operand:SI 1 "register_operand" "a") > (match_operand:SI 2 "register_operand" "d")] > @@ -25726,6 +25729,7 @@ (define_insn "" >"\t%0" >[(set_attr "type" "other") > (set_attr "memory" "store") > + (set_attr "gpr32" "0") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) > > @@ -25743,7 +25747,7 @@ (define_insn "" > > (define_insn "_rex64" > [(unspec_volatile:BLK > - [(match_operand:BLK 0 "memory_operand" "m") > + [(match_operand:BLK 0 "memory_operand" "Bt") >(match_operand:SI 1 "register_operand" "a") >(match_operand:SI 2 "register_operand" "d")] > ANY_XRSTOR)] > @@ -25751,12 +25755,13 @@ (define_insn "_rex64" >"\t%0" >[(set_attr "type" "other") > (set_attr "memory" "load") > + (set_attr "gpr32" "0") > (set (attr "length") > (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) > > (define_insn "64" > [(unspec_volatile:BLK > - [(match_operand:BLK 0
[PATCH 09/13] [APX EGPR] Handle legacy insn that only support GPR16 (1/5)
From: Kong Lingling These legacy insn in opcode map0/1 only support GPR16, and do not have vex/evex counterpart, directly adjust constraints and add gpr32 attr to patterns. insn list: 1. xsave/xsave64, xrstor/xrstor64 2. xsaves/xsaves64, xrstors/xrstors64 3. xsavec/xsavec64 4. xsaveopt/xsaveopt64 5. fxsave64/fxrstor64 gcc/ChangeLog: * config/i386/i386.md (): Set attr gpr32 0 and constraint Bt. (_rex64): Likewise. (_rex64): Likewise. (64): Likewise. (fxsave64): Likewise. (fxstore64): Likewise. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add apxf check. * gcc.target/i386/apx-legacy-insn-check-norex2.c: New test. * gcc.target/i386/apx-legacy-insn-check-norex2-asm.c: New assembler test. --- gcc/config/i386/i386.md | 18 +++ .../i386/apx-legacy-insn-check-norex2-asm.c | 5 .../i386/apx-legacy-insn-check-norex2.c | 30 +++ gcc/testsuite/lib/target-supports.exp | 10 +++ 4 files changed, 57 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index b9eaea78f00..83ad01b43c1 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -25626,11 +25626,12 @@ (define_insn "fxsave" (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "fxsave64" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=Bt") (unspec_volatile:BLK [(const_int 0)] UNSPECV_FXSAVE64))] "TARGET_64BIT && TARGET_FXSR" "fxsave64\t%0" [(set_attr "type" "other") + (set_attr "gpr32" "0") (set_attr "memory" "store") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25646,11 +25647,12 @@ (define_insn "fxrstor" (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "fxrstor64" - [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")] + [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "Bt")] UNSPECV_FXRSTOR64)] "TARGET_64BIT && TARGET_FXSR" "fxrstor64\t%0" [(set_attr "type" "other") + (set_attr "gpr32" "0") (set_attr "memory" "load") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25704,7 +25706,7 @@ (define_insn "" (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "_rex64" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=Bt") (unspec_volatile:BLK [(match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] @@ -25713,11 +25715,12 @@ (define_insn "_rex64" "\t%0" [(set_attr "type" "other") (set_attr "memory" "store") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "" - [(set (match_operand:BLK 0 "memory_operand" "=m") + [(set (match_operand:BLK 0 "memory_operand" "=Bt") (unspec_volatile:BLK [(match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] @@ -25726,6 +25729,7 @@ (define_insn "" "\t%0" [(set_attr "type" "other") (set_attr "memory" "store") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) @@ -25743,7 +25747,7 @@ (define_insn "" (define_insn "_rex64" [(unspec_volatile:BLK - [(match_operand:BLK 0 "memory_operand" "m") + [(match_operand:BLK 0 "memory_operand" "Bt") (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] ANY_XRSTOR)] @@ -25751,12 +25755,13 @@ (define_insn "_rex64" "\t%0" [(set_attr "type" "other") (set_attr "memory" "load") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) (define_insn "64" [(unspec_volatile:BLK - [(match_operand:BLK 0 "memory_operand" "m") + [(match_operand:BLK 0 "memory_operand" "Bt") (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "register_operand" "d")] ANY_XRSTOR64)] @@ -25764,6 +25769,7 @@ (define_insn "64" "64\t%0" [(set_attr "type" "other") (set_attr "memory" "load") + (set_attr "gpr32" "0") (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) diff --git a/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c b/gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c new file mode 100644 index 000..7ecc861435f --- /dev/null +++
