RE: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of vext.vf
Committed, thanks Juzhe. Pan From: juzhe.zh...@rivai.ai Sent: Wednesday, April 24, 2024 2:46 PM To: Li, Pan2 ; gcc-patches Cc: kito.cheng ; Robin Dapp ; Li, Pan2 Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of vext.vf LGTM. juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: pan2.li<mailto:pan2...@intel.com> Date: 2024-04-24 10:48 To: gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; kito.cheng<mailto:kito.ch...@gmail.com>; rdapp.gcc<mailto:rdapp@gmail.com>; Pan Li<mailto:pan2...@intel.com> Subject: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of vext.vf From: Pan Li mailto:pan2...@intel.com>> We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 62685890d88 RISC-V: Support highpart overlap for vext.vf The below test suites are passed for this patch * The rv64gcv fully regression test with isl build. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/unop_v_constraint-2.c: Adjust asm check cond. * gcc.target/riscv/rvv/base/pr112431-4.c: New test. * gcc.target/riscv/rvv/base/pr112431-5.c: New test. * gcc.target/riscv/rvv/base/pr112431-6.c: New test. Signed-off-by: Pan Li mailto:pan2...@intel.com>> --- .../gcc.target/riscv/rvv/base/pr112431-4.c| 104 ++ .../gcc.target/riscv/rvv/base/pr112431-5.c| 68 .../gcc.target/riscv/rvv/base/pr112431-6.c| 51 + .../riscv/rvv/base/unop_v_constraint-2.c | 2 +- 4 files changed, 224 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c new file mode 100644 index 000..cecf796e10c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, + size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, + size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, + size_t sum15) +{ + return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 + + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; +} + +size_t +foo (char const *buf, size_t len) +{ + size_t sum = 0; + size_t vl = __riscv_vsetvlmax_e8m8 (); + size_t step = vl * 4; + const char *it = buf, *end = buf + len; + for (; it + step <= end;) +{ + vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + + asm volatile("nop" ::: "memory"); + vint16m2_t vw0 = __riscv_vsext_vf2_i16m2 (v0, vl); + vint16m2_t vw1 = __riscv_vsext_vf2_i16m2 (v1, vl); + vint16m2_t vw2 = __riscv_vsext_vf2_i16m2 (v2, vl); + vint16m2_t vw3 = __riscv_vsext_vf2_i16m2 (v3, vl); + vint16m2_t vw4 = __riscv_vsext_vf2_i16m2 (v4, vl); + vint16m2_t vw5 = __riscv_vsext_vf2_i16m2 (v5, vl); + vint16m2_t vw6 = __riscv_vsext_vf2_i16m2 (v6, vl); + vint16m2_t vw7 = __riscv_vsext_vf2_i16m2 (v7, vl); + vint16m2_t vw8 = __riscv_vsext_vf2_i16m2 (v8, vl); + vint16m2_t vw9 = __riscv_vsext_vf2_i16m2 (v9, vl); + vint16m2_t vw10 = __riscv_vsext_vf2_i16m2 (v10, vl); + vint16m2_t vw11 = __riscv_vsext_vf2_i1
Re: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of vext.vf
LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2024-04-24 10:48 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li Subject: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of vext.vf From: Pan Li We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 62685890d88 RISC-V: Support highpart overlap for vext.vf The below test suites are passed for this patch * The rv64gcv fully regression test with isl build. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/unop_v_constraint-2.c: Adjust asm check cond. * gcc.target/riscv/rvv/base/pr112431-4.c: New test. * gcc.target/riscv/rvv/base/pr112431-5.c: New test. * gcc.target/riscv/rvv/base/pr112431-6.c: New test. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/base/pr112431-4.c| 104 ++ .../gcc.target/riscv/rvv/base/pr112431-5.c| 68 .../gcc.target/riscv/rvv/base/pr112431-6.c| 51 + .../riscv/rvv/base/unop_v_constraint-2.c | 2 +- 4 files changed, 224 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c new file mode 100644 index 000..cecf796e10c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, + size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, + size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, + size_t sum15) +{ + return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 + + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; +} + +size_t +foo (char const *buf, size_t len) +{ + size_t sum = 0; + size_t vl = __riscv_vsetvlmax_e8m8 (); + size_t step = vl * 4; + const char *it = buf, *end = buf + len; + for (; it + step <= end;) +{ + vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + + asm volatile("nop" ::: "memory"); + vint16m2_t vw0 = __riscv_vsext_vf2_i16m2 (v0, vl); + vint16m2_t vw1 = __riscv_vsext_vf2_i16m2 (v1, vl); + vint16m2_t vw2 = __riscv_vsext_vf2_i16m2 (v2, vl); + vint16m2_t vw3 = __riscv_vsext_vf2_i16m2 (v3, vl); + vint16m2_t vw4 = __riscv_vsext_vf2_i16m2 (v4, vl); + vint16m2_t vw5 = __riscv_vsext_vf2_i16m2 (v5, vl); + vint16m2_t vw6 = __riscv_vsext_vf2_i16m2 (v6, vl); + vint16m2_t vw7 = __riscv_vsext_vf2_i16m2 (v7, vl); + vint16m2_t vw8 = __riscv_vsext_vf2_i16m2 (v8, vl); + vint16m2_t vw9 = __riscv_vsext_vf2_i16m2 (v9, vl); + vint16m2_t vw10 = __riscv_vsext_vf2_i16m2 (v10, vl); + vint16m2_t vw11 = __riscv_vsext_vf2_i16m2 (v11, vl); + vint16m2_t vw12 = __riscv_vsext_vf2_i16m2 (v12, vl); + vint16m2_t vw13 = __riscv_vsext_vf2_i16m2 (v13, vl); + vint16m2_t vw14 = __riscv_vsext_vf2_i16m2 (v14, vl); + vint16m2_t vw15 = __riscv_vsext_vf2_i16m2 (v15, vl); + + asm volatile("nop" ::: "memory"); + size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0); + size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1); + size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2); + size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3); + size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4); + size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5); + size_t