RE: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap

2024-04-19 Thread Li, Pan2 
Committed, thanks Juzhe.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Saturday, April 20, 2024 9:20 AM
To: Li, Pan2 ; gcc-patches 
Cc: kito.cheng ; Robin Dapp ; Li, 
Pan2 
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap

LGTM.


juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: pan2.li<mailto:pan2...@intel.com>
Date: 2024-04-20 09:04
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@gmail.com>; rdapp.gcc<mailto:rdapp@gmail.com>; 
Pan Li<mailto:pan2...@intel.com>
Subject: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
From: Pan Li mailto:pan2...@intel.com>>

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr112431-42.c: New test.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
---
.../gcc.target/riscv/rvv/base/pr112431-42.c   | 30 +++
1 file changed, 30 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
new file mode 100644
index 000..fa5dac58a20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ffast-math" } */
+
+#include 
+
+int64_t
+reduc_plus_int (int *__restrict a, int n)
+{
+  int64_t r = 0;
+  for (int i = 0; i < n; ++i)
+r += a[i];
+  return r;
+}
+
+double
+reduc_plus_float (float *__restrict a, int n)
+{
+  double r = 0;
+  for (int i = 0; i < n; ++i)
+r += a[i];
+  return r;
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */
+/* { dg-final { scan-assembler-times {vfwadd\.wv} 1 } } */
--
2.34.1

Re: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap

2024-04-19 Thread juzhe.zh...@rivai.ai 
LGTM.



juzhe.zh...@rivai.ai
 
From: pan2.li
Date: 2024-04-20 09:04
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
From: Pan Li 
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/pr112431-42.c: New test.
 
Signed-off-by: Pan Li 
---
.../gcc.target/riscv/rvv/base/pr112431-42.c   | 30 +++
1 file changed, 30 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
new file mode 100644
index 000..fa5dac58a20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ffast-math" } */
+
+#include 
+
+int64_t
+reduc_plus_int (int *__restrict a, int n)
+{
+  int64_t r = 0;
+  for (int i = 0; i < n; ++i)
+r += a[i];
+  return r;
+}
+
+double
+reduc_plus_float (float *__restrict a, int n)
+{
+  double r = 0;
+  for (int i = 0; i < n; ++i)
+r += a[i];
+  return r;
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */
+/* { dg-final { scan-assembler-times {vfwadd\.wv} 1 } } */
-- 
2.34.1