Re: gEDA-user: pcb, howto partition power planes?
On Tue, Oct 28, 2008 at 02:49:37PM -0400, DJ Delorie wrote: What about high precision ADCs? I'm working on a design using ADE7753 power monitor chips (16-bit ADCs) , and their own app note (AN564) shows a ferrite isolating analog ground, and a 10R resistor isolating AVdd. http://www.tentlabs.com/Components/Shuntcomp/assets/Supply_decoupling.pdf -- The reason [limited term of copyright is] important is this: Publishers are in the business of expanding capital. The writers who supply them are in the business of expanding civilization itself. -- John Bloom ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Steve, I don't see these other attempts. Eric Winsor Steve Meier wrote: Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Ok ok ok go to my home page and look for links to hs table of contents and hs section 1 through 4 http://www.alchemyresearch.com/ Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Were you trying to format them with HTML? I bet the HTML filters on the mailing list were cutting out the links. On Oct 30, 2008, at 2:44 PM, Eric Winsor wrote: Steve, I don't see these other attempts. Eric Winsor Steve Meier wrote: Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
No the first attempt was a cut and paste that didn't bring the url with it though an html filter would have removed it. The second and third attempts I was responding only too myself. Good thing too as I was getting frustrated with how my email tool automatically breaks lines into pieces. And the urls are convoluted. Steve Meier On Thu, 2008-10-30 at 19:14 -0700, Steven Michalske wrote: Were you trying to format them with HTML? I bet the HTML filters on the mailing list were cutting out the links. On Oct 30, 2008, at 2:44 PM, Eric Winsor wrote: Steve, I don't see these other attempts. Eric Winsor Steve Meier wrote: Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Tue, 2008-10-28 at 20:47 -0400, DJ Delorie wrote: Joerg [EMAIL PROTECTED] writes: By now I'd say Prehistoric Digital Assistant. The only guy I know who actually still uses one is our pastor. I have one I use every day, but it's in my watch. So that watch isn't on a wrist band it is on an adjustable crane hook. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I have one I use every day, but it's in my watch. So that watch isn't on a wrist band it is on an adjustable crane hook. Heh, I suppose. FYI it's a Timex Ironman USB. Very useful watch. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ Delorie wrote: I have one I use every day, but it's in my watch. So that watch isn't on a wrist band it is on an adjustable crane hook. Heh, I suppose. FYI it's a Timex Ironman USB. Very useful watch. But can you talk to it with Linux? Eric (who still uses a VR3 - mostly to play DJ's Ace of Penguins Freecell) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
But can you talk to it with Linux? I don't, but I think you can. There's an SDK and emulator from the timex yahoo group folks. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. What about high precision ADCs? I'm working on a design using ADE7753 power monitor chips (16-bit ADCs) , and their own app note (AN564) shows a ferrite isolating analog ground, and a 10R resistor isolating AVdd. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). I gotta agree strongly with Joerg. ALthough many app notes recommend a split ground plane for mixed signal designs, in the real world it's next to impossible to split the plane properly. That is, with signals (both digital and analog) running all over your board, power, etc., it's almost impossible to gerrymander your AGND and DGND planes to follow their respective signal traces and feeds. Therefore, the folks at National Semiconductor push the idea that you place analog and digital components as far away from one anther as possible on your board. Also, keep analog and digital signal tracks as separated as possible. But use a *single* solid ground plane everywhere for the best noise performance. I've used this advice in practice, and have had no problems (at least with radiation and noise). Here are some app notes discussing this in greater detail: http://www.hottconsultants.com/techtips/split-gnd-plane.html http://www.national.com/nationaledge/nov04/adc_article.html Cheers, Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
App notes and example designs are special cases: there is only one chip straddling the analog and digital divide. If you have more than one (e.g., both an ADC and a DAC) all those ideas pretty much go out the window, and you're better off with a single ground plane. I have 16 of these chips, all talking to a single MCU. The 8 on one side have their own analog power/gnd, and the 8 on the other side have their own. The board will go inside my circuit breaker panel box, powered by a USB cable. board: http://www.delorie.com/pcb/powermeter.jpg http://www.delorie.com/pcb/powermeter.pcb ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Tue, Oct 28, 2008 at 02:49:37PM -0400, DJ Delorie wrote: What about high precision ADCs? I'm working on a design using ADE7753 power monitor chips (16-bit ADCs) , and their own app note (AN564) shows a ferrite isolating analog ground, and a 10R resistor isolating AVdd. http://www.amazon.com/Linear-Circuit-Handbook-Engineering-Devices/dp/0750687037 I highly recommend that book. It's extremely practical. Unlike most electronics books that can't say anything truly meaningful without slipping into differential equations, this keeps everything at a very accessible level. They specifically address the issue that appnotes always design simple, single mixed-signal device PCBs and give no hint as to how to expand that to a multi-chip design. If you 'search inside' for 'split' and take the link that starts at page 873 you might be able to get what you want. -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ Delorie wrote: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. What about high precision ADCs? I'm working on a design using ADE7753 power monitor chips (16-bit ADCs) , and their own app note (AN564) shows a ferrite isolating analog ground, and a 10R resistor isolating AVdd. Ok, goes a bit OT here but maybe it helps others as well. Will take a bit longer to explain scenarios. Personally I would not split but make sure sensitive inputs are fed differentially. The datasheet shows some uncertainty about this: Page 8 says, quote To keep ground noise around the ADE7753 to a minimum, the quiet ground plane should connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane. ... while figures 29 and 30 have both grounds tied together. Yes, in AN564 there is an inductor connecting both grounds. This concept falls apart when you have more than one converter or when stuff from the external world needs to connect to the analog side in non-diff fashion. But the real concerns are others. Examples follow, and I've seen them all. a. Since power meters are mostly mounted to an outside wall in the US this is what can happen during a thunderstorm. Split grounds act as a dipole antenna with the current maximum at the joint, or in case of AN564 an inductor. Lighting hits uncle Leroy's oak tree, a gigantic EM pulse develops, reaches the meter, finds a nice and receptive dipole antenna in the form of a split plane, fssst ... *BANG*. Meter's gone. b. Uncle Leroy has a huge antenna next to the garage where the meter is located. Inside the garage is that humongous CB amplifier that he tells everybody never to talk about because it's, ahem, not quite legit. He keys the mike, AM-modulated RF floods the woods and develops a varying voltage across that inductor that peaks high enough to upset the ADC in the meter. Upon which the meter probably goes into some kind of lock-down. c. Someone walks up to the meter and then his cell phone rings. One never knows but the chip might have some bipolar (BJT) paths between the two grounds. While it isn't sensitive to GHz frequencies per se just a wee bit of that RF can rectify at a few BJT junctions in there. Since the transmissions are burst-like the rectified signal consists of pulses of who-knows-what characteristic. This might cause more or less serious ADC conversion errors. I could go on. Bottomline is that you never really know what kind of outside disturbances a piece of electronics might be exposed to and how a chip will react to noise. Maybe not now, but what if some new 4G standard pops up in the maketplace that turns out to be a real bear in terms of susceptibility? In contrast, isolating an analog supply voltage can be a very smart thing to do. As long as either side of the isolation resistor or inductor is bypassed really well. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ - On Tue, Oct 28, 2008 at 03:09:37PM -0400, DJ Delorie wrote: App notes and example designs are special cases: there is only one chip straddling the analog and digital divide. If you have more than one (e.g., both an ADC and a DAC) all those ideas pretty much go out the window, and you're better off with a single ground plane. I have 16 of these chips, all talking to a single MCU. The 8 on one side have their own analog power/gnd, and the 8 on the other side have their own. Split power supplies: almost always good. Split ground planes: almost always bad. Two layer boards are a special challenge, because you never quite get a full ground plane. Your board looks decent. What kind of voltage resolution are you looking for (e.g., what IC are Uxx0)? The first thing that leaps out at me is the large loop for power supply filtering on those chips (both AGND to AVdd, and DGND to DVdd). Oh, and do you really want REF filtered to digital ground? If you have noise troubles with that layout, I can offer suggestions to improve it. Hint: it will involve more closely approximating a real ground plane over the whole board. One major trouble with split ground planes is when tracks cross the split, and the return path becomes high inductance. Your board doesn't suffer too badly from that disease. Most cases that look like that are actually differential signals, where the plane is not part of the circuit. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Your board looks decent. What kind of voltage resolution are you looking for (e.g., what IC are Uxx0)? Those are the ADE7753 chips. In theory, they're accurate enough to meet all the IEC standards for power metering, but in my case, I only need to know where all my kWh are going so I know where to start conserving electricity for best gains. The first thing that leaps out at me is the large loop for power supply filtering on those chips (both AGND to AVdd, and DGND to DVdd). The alternative was to put the bypass caps on the back, and I was trying to avoid that (it makes assembly a little harder). Oh, and do you really want REF filtered to digital ground? Er, no, that's a mistake. I've noticed that before but keep forgetting to fix it. One major trouble with split ground planes is when tracks cross the split, and the return path becomes high inductance. Your board doesn't suffer too badly from that disease. Most cases that look like that are actually differential signals, where the plane is not part of the circuit. The chip is laid out with the analog pins on one side, and the digital ones on the other side, so for the most part the signals stay over their own planes anyway. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ - On Tue, Oct 28, 2008 at 12:49:51PM -0700, Larry Doolittle wrote: Your board looks decent. What kind of voltage resolution are you looking for (e.g., what IC are Uxx0)? I see now, ADE7753ARSZ, $3.834 in 25's at DigiKey. 16-bit Sigma-Delta under the hood. Good luck with that. The first thing that leaps out at me is the large loop for power supply filtering on those chips (both AGND to AVdd, and DGND to DVdd). Oh, and do you really want REF filtered to digital ground? No, you don't. If you have noise troubles with that layout, I can offer suggestions to improve it. Hint: it will involve more closely approximating a real ground plane over the whole board. I guess your layout will need at least one more rev before you can get to the noise limit of that chip. OTOH, maybe that isn't the goal. I do really like the idea behind that board! I have a Kill-A-Watt at home. It's really handy, but a real multi-channel power datalogger would be even better. I thought about building one myself many years ago, but never got the traditional Round Tuit. Don't let my snarky comments about grounds keep you from building yours. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Stuart Brorson wrote: [...] Therefore, the folks at National Semiconductor push the idea that you place analog and digital components as far away from one anther as possible on your board. Also, keep analog and digital signal tracks as separated as possible. But use a *single* solid ground plane everywhere for the best noise performance. I've used this advice in practice, and have had no problems (at least with radiation and noise). That's because Bob Pease and Robert Widlar used to work there. And those guys really know ;-) Or knew, in Robert Widlar's case :-( -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I guess your layout will need at least one more rev before you can get to the noise limit of that chip. OTOH, maybe that isn't the goal. My goal is: figure out why my electric bill is so high :-) I do really like the idea behind that board! I have a Kill-A-Watt at home. It's really handy, but a real multi-channel power datalogger would be even better. I thought about building one myself many years ago, but never got the traditional Round Tuit. Don't let my snarky comments about grounds keep you from building yours. Well, I'm having a bunch of boards made - maybe ten or so. I need four for my house, and our lab rat at work wants one. I'll have extras :-) I'm going to hand-etch one board to test out the concept first, though. That means no vias under components and a few other design rules. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
yes it helps immensely to have a low pass filter issolating a device from the power planes. Steve Meier On Tue, 2008-10-28 at 14:49 -0400, DJ Delorie wrote: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. What about high precision ADCs? I'm working on a design using ADE7753 power monitor chips (16-bit ADCs) , and their own app note (AN564) shows a ferrite isolating analog ground, and a 10R resistor isolating AVdd. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ Delorie wrote: I guess your layout will need at least one more rev before you can get to the noise limit of that chip. OTOH, maybe that isn't the goal. My goal is: figure out why my electric bill is so high :-) Another nice tool: Maybe you could borrow a FLIR camera. That would show every ever so slight hot spot in a room, like something that consumes a couple of watts of standby power but has long since been forgotten. I do really like the idea behind that board! I have a Kill-A-Watt at home. It's really handy, but a real multi-channel power datalogger would be even better. I thought about building one myself many years ago, but never got the traditional Round Tuit. Don't let my snarky comments about grounds keep you from building yours. Well, I'm having a bunch of boards made - maybe ten or so. I need four for my house, and our lab rat at work wants one. I'll have extras :-) I'm going to hand-etch one board to test out the concept first, though. That means no vias under components and a few other design rules. Tried to load your layout but got an error and I could not find any pointers via web search. Error parsing file ... line: 801 description: font position out of range Then again this is the first time I tried PCB Designer on Ubuntu in VirtualBox. Maybe some settings are messed up. WRT to energy savings, if you find some gizmo that consumes next to nothing but has to run and its transformer gobbles up 95%+ you could try to replace i.e. a 115V-12V transformer with a 230V-24V. Modern transformers are often operated a hair below or right at the onset of saturation. -- Regards, Joerg http://www.analogconsultants.com/ gmail domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Joerg - On Tue, Oct 28, 2008 at 02:07:30PM -0700, Joerg wrote: Tried to load your layout but got an error and I could not find any pointers via web search. Error parsing file ... line: 801 description: font position out of range I hit this too. I just deleted the Symbol that tarts on line 800. The board didn't seem any the worse for wear. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Another nice tool: Maybe you could borrow a FLIR camera. That would show every ever so slight hot spot in a room, like something that consumes a couple of watts of standby power but has long since been forgotten. That won't help me figure out how often the well pump runs. It's 480 feet down, on the far side of the yard. And even though I CAN get to the septic pump, I'm not going to ;-) We're talking megawatt-hours, not tiny dribbles. Our house uses about 23 MWh each year. I expect this project to pay for itself FAST. description: font position out of range Oops, I have a new version of pcb that supports accented characters. Fixed. WRT to energy savings, if you find some gizmo that consumes next to nothing but has to run and its transformer gobbles up 95%+ you could try to replace i.e. a 115V-12V transformer with a 230V-24V. Modern transformers are often operated a hair below or right at the onset of saturation. Interesting. At the moment, though, I don't have any idea where the power is going. I suspect my computers are eating a big chunk, but there are a LOT of other things in the house that are suspect. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Nearly impossible? I disagree here it is standard practice. Analog signals come in and go out the left side of the board and digital is in the center to the right side. Top analog is separated from the bottom analog. Here is the deal. We start with a signal less the one milli volt and we increase it over 1000 times. Any noise that crosses over from the digital into the analog gets multiplied up by that gain as well. Steve Meier On Tue, 2008-10-28 at 15:02 -0400, Stuart Brorson wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). I gotta agree strongly with Joerg. ALthough many app notes recommend a split ground plane for mixed signal designs, in the real world it's next to impossible to split the plane properly. That is, with signals (both digital and analog) running all over your board, power, etc., it's almost impossible to gerrymander your AGND and DGND planes to follow their respective signal traces and feeds. Therefore, the folks at National Semiconductor push the idea that you place analog and digital components as far away from one anther as possible on your board. Also, keep analog and digital signal tracks as separated as possible. But use a *single* solid ground plane everywhere for the best noise performance. I've used this advice in practice, and have had no problems (at least with radiation and noise). Here are some app notes discussing this in greater detail: http://www.hottconsultants.com/techtips/split-gnd-plane.html http://www.national.com/nationaledge/nov04/adc_article.html Cheers, Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Tue, Oct 28, 2008 at 5:31 PM, DJ Delorie [EMAIL PROTECTED] wrote: At the moment, though, I don't have any idea where the power is going. I suspect my computers are eating a big chunk, but there are a LOT of other things in the house that are suspect. You may want to check power factor. The power factor of most PC power supplies is not that good. Don't you have a number of PCs running 24x7? (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
You may want to check power factor. Perhaps you're thinking of power efficiency? You don't pay for power factor problems (imaginary power). Don't you have a number of PCs running 24x7? Yup, at least six of them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Tue, Oct 28, 2008 at 6:53 PM, DJ Delorie [EMAIL PROTECTED] wrote: You may want to check power factor. Perhaps you're thinking of power efficiency? You don't pay for power factor problems (imaginary power). Efficiency is probably low. Power factor is probably low too. I believe the utility charges for Volt-Amperes (VA). For PF 1 you are paying. My guess for a typical PC power supply would be 60-70% efficient and a PF of 0.7 - 0.75. Just guesses. Don't you have a number of PCs running 24x7? Yup, at least six of them. If you need another fun project --- Rack mount power distribution box with a PF corrected front end (PF 0.99) and some high efficiency DC-DC converters. ;-) (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I believe the utility charges for Volt-Amperes (VA). Nope, they charge for real watts. If your PF is too far from 1, they make you install capacitors (usually, or inductors) to balance your load to keep the PF near 1. It doesn't change your electric bill, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
-Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of DJ Delorie Sent: Tuesday, October 28, 2008 6:54 PM To: geda-user@moria.seul.org Subject: Re: gEDA-user: pcb, howto partition power planes? You may want to check power factor. Perhaps you're thinking of power efficiency? You don't pay for power factor problems (imaginary power). True, but a lot of the the electric company's so-called watt-hour meters are actually amp-hour meters, or at least they used to be. So stuff with a poor power factor will hurt your electric bill even if they don't pull many watts. Don't you have a number of PCs running 24x7? Yup, at least six of them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Tue, Oct 28, 2008 at 7:11 PM, DJ Delorie [EMAIL PROTECTED] wrote: I believe the utility charges for Volt-Amperes (VA). Nope, they charge for real watts. If your PF is too far from 1, they make you install capacitors (usually, or inductors) to balance your load to keep the PF near 1. It doesn't change your electric bill, though. By keeping PF close to one VA == Watts so it wouldn't affect your bill. If you were billed for VA then it would. I haven't heard of a power factor requirement for a residence. Is that unique to NH? (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I haven't heard of a power factor requirement for a residence. I was referring to businesses, which often have enough inductive motors to cause problems. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ Delorie wrote: Another nice tool: Maybe you could borrow a FLIR camera. That would show every ever so slight hot spot in a room, like something that consumes a couple of watts of standby power but has long since been forgotten. That won't help me figure out how often the well pump runs. It's 480 feet down, on the far side of the yard. And even though I CAN get to the septic pump, I'm not going to ;-) That's going to be more serious work. Holding tanks, fine control of pressure and so on. Almost like adjusting the carburetor of a vintage Alfa Romeo to get it to run lean and clean (where they said only Giuseppe can really do that). Oh, and if you have teenage girls tell them that the daily shower does not have to exceed 30 minutes/person ;-) We're talking megawatt-hours, not tiny dribbles. Our house uses about 23 MWh each year. I expect this project to pay for itself FAST. description: font position out of range Oops, I have a new version of pcb that supports accented characters. Fixed. Works now. You've got some traces and parts already crossing that barrier, compromising it. I can understand that you are cautious about the point-blank statement turn it all into one common plane I and others made. What I recommend to clients in that case is to sprinkle resistors pads across. Maybe 12-15 in your case. Then you can later stuff them with zero ohms (or close to that). Or leave them out. On PCB Designer it looks like there is plenty of space between the ADCs and elsewhere. This avoids nasty rework in case the ground split does fly into your face. WRT to energy savings, if you find some gizmo that consumes next to nothing but has to run and its transformer gobbles up 95%+ you could try to replace i.e. a 115V-12V transformer with a 230V-24V. Modern transformers are often operated a hair below or right at the onset of saturation. Interesting. At the moment, though, I don't have any idea where the power is going. I suspect my computers are eating a big chunk, but there are a LOT of other things in the house that are suspect. Well, 23MWh is huge. Unless you guys heat with electricity. Computers will be a mere drop in the bucket there. Recording runtimes of the big motors, compressors etc. would probably help a lot. Also, current surges like when the pump cycles. That can give you an indication of how well investments such as additional holding tanks would pay off. -- Regards, Joerg http://www.analogconsultants.com/ gmail domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Oct 28, 2008, at 7:21 PM, Joerg wrote: Well, 23MWh is huge. Unless you guys heat with electricity. Computers will be a mere drop in the bucket there. Are you sure? Real computers have wheels. ;) -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
That's going to be more serious work. Holding tanks, fine control of pressure and so on. Well, it's more like oh, the well uses X kwh, can't do anything about that. Oh, and if you have teenage girls tell them that the daily shower does not have to exceed 30 minutes/person ;-) I have two teenagers, but my son is the water worshiper. I do know that *heating* water is only a minor cost in our grand scheme of things. I can understand that you are cautious about the point-blank statement Not cautious - I realize I just don't know enough about this to judge. This avoids nasty rework in case the ground split does fly into your face. Hmmm... The AVdd and reset signals go between the grounds. I don't expect I need as much perfection in this to warrant serious investigation into noise, just a design that works well enough in a robust way. I suspect I'll end up just merging the ground and power planes, and providing per-chip Vdd isolation (it's just a resistor). Well, 23MWh is huge. Unless you guys heat with electricity. Nope! Heat is half wood, half oil, with a little passive solar (windows) thown in for fun. Oh, and all that waste heat from the electricity, but it's not the primary heat. Recording runtimes of the big motors, compressors etc. would probably help a lot. Also, current surges like when the pump cycles. That can give you an indication of how well investments such as additional holding tanks would pay off. Yup. Hard tellin', not knowin'. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Dave McGuire wrote: On Oct 28, 2008, at 7:21 PM, Joerg wrote: Well, 23MWh is huge. Unless you guys heat with electricity. Computers will be a mere drop in the bucket there. Are you sure? Real computers have wheels. ;) Nah, real computers like the ones my pa dealt with have hooks on top so they can be lifted by a crane. -- Regards, Joerg http://www.analogconsultants.com/ gmail domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Joerg [EMAIL PROTECTED] writes: By now I'd say Prehistoric Digital Assistant. The only guy I know who actually still uses one is our pastor. I have one I use every day, but it's in my watch. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Oct 28, 2008, at 8:45 PM, Joerg wrote: If I ever get back to working on an open source PDA I will be sure to include a crane hook. PDA == Preposterous Digital Assistant =) By now I'd say Prehistoric Digital Assistant. The only guy I know who actually still uses one is our pastor. PDAs? I see them in use every day, by myself included. Most of them have built-in cellphones nowadays. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Dave McGuire wrote: On Oct 28, 2008, at 8:45 PM, Joerg wrote: If I ever get back to working on an open source PDA I will be sure to include a crane hook. PDA == Preposterous Digital Assistant =) By now I'd say Prehistoric Digital Assistant. The only guy I know who actually still uses one is our pastor. PDAs? I see them in use every day, by myself included. Most of them have built-in cellphones nowadays. Ok, yes, those are different. People out here in California use iPhones a lot. But to be honest most of the time I see anyone fidget around with it and not making a call they are playing some kind of game on it. -- Regards, Joerg http://www.analogconsultants.com/ gmail domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ Delorie wrote: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. What about high precision ADCs? I'm working on a design using ADE7753 power monitor chips (16-bit ADCs) , and their own app note (AN564) shows a ferrite isolating analog ground, and a 10R resistor isolating AVdd. Ask, Which common is the one with the lowest ohms to the current source of power? If it is so called analog ground, then the ferrite will allow noise on the digital chips. If not, the analog will be the noisy one...not as intended. All the benefits of shields go away when you're not referring them back to one point, usually the negative terminal of a battery, or power supply that your other analog circuits reference. Putting inductance on all the in or outgoing power wires except grounds, not letting ground wires go out along long wires, and connecting the main ground to a conductive box around your circuits will keep them quiet, and maybe even safe from RF. And the star connection from one point concept like Duncan said. I really have not had any experience where we changed a design a lot and saw the results of separate grounds planes -- I have not used them. Larry Doolittle wrote: I have seen exactly one case where a split (very carefully done) on the ground plane was needed to avoid a source of ground return crosstalk. I'd like to hear more about that, if you will. Thanks, John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Larry Doolittle wrote: All modern PCs come with high efficiency DC-DC converters built-in. They just get fed from rectified line voltage. Feed them 300VDC (from the aforementioned PF corrected front end) and they work much better. At least that's what some server farms have started doing. Hmmm... that's getting close to what I've wondered why you hear nothing of it -- running them on lower DC to match the power consumers low volts... Sure, I know, power distribution voltage drops are less when you step up, flow low current, then step down. but a server farm can be a cabinet with a zillion blades nowadays...why not use a thick DC cable to run clusters? At least, I have not heard of it yet. JG -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
John - On Tue, Oct 28, 2008 at 10:11:38PM -0500, John Griessen wrote: Larry Doolittle wrote: I have seen exactly one case where a split (very carefully done) on the ground plane was needed to avoid a source of ground return crosstalk. I'd like to hear more about that, if you will. The ADC and its input connector (vertical SMA) were in the middle of the board. On one side was a power supply, and on the other some variable load (I forget what, maybe a DAC). Low frequency return currents travelling along the ground plane created (with Ohm's law) voltages that mimicked changes in the input pin. The ground plane needed a C shaped cut, with the SMA and its four ground posts in the middle and the ADC input on the right, to keep the interfering current away from the signal, or more precisely its return path. I hope that made sense. It was hard to find, but pretty clear to us after the fact. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb, howto partition power planes?
Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I typically deal with this by separating the planes at the schematic level using a bead-core inductor. The two planes are then on different nets at the PCB level. This not only makes it easier to do the routing but they also serve an electrical purpose of isolating the two planes from a high frequency viewpoint, whilst connecting them at DC. On Mon, 2008-10-27 at 16:39 +0100, Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Am Montag, den 27.10.2008, 11:59 -0400 schrieb Neil Webster: I typically deal with this by separating the planes at the schematic level using a bead-core inductor. The two planes are then on different nets at the PCB level. This not only makes it easier to do the routing but they also serve an electrical purpose of isolating the two planes from a high frequency viewpoint, whilst connecting them at DC. Yes, I also have GND and AGND in my schematics. My question is more in this direction: How do I best divide a copper area (physically) into subsections with complicated shape/outline. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I typically deal with this by separating the planes at the schematic level using a bead-core inductor. Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Am Montag, den 27.10.2008, 19:47 +0200 schrieb Duncan Drennan: Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. I think so too -- but it may depend on what we build. Indeed I have seen recommendations to employ inductors in newsgroup sci.electronics.design. I use an analog ground where my OpAmps reside, and a digital ground for FPGA, uC. Situation is more complicated for DC/DC-converters or ADC, there are detailed shapes for ground and power planes in some datasheets. But my question currently is not how it should look, but how I build it best with pcb. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? This is my question. It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. I would be also interested in how this is handled in other pcb programs. Best regards, Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Mon, 27 Oct 2008 19:47:32 +0200, Duncan Drennan wrote: How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? If you want to partially divide a polygon: * Draw lines on copper with zero thickness but finite clearance. If you want to completely dissect a polygon: * Divide the polygon with thin tracks. Parts will render invisible. * Let the mouse hover over the visible part of the polygon. Use the command MorphPolygon(Object) to make each snippet a polygon on its own. Alternatively you can select the polygon and apply the variant MorphPolygon(Selected) ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Am Montag, den 27.10.2008, 18:17 + schrieb Kai-Martin Knaak: On Mon, 27 Oct 2008 19:47:32 +0200, Duncan Drennan wrote: How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? If you want to partially divide a polygon: * Draw lines on copper with zero thickness but finite clearance. Does this really result in legal Gerber files -- would be not so nice if a few manufacturers can not handle it. If you want to completely dissect a polygon: * Divide the polygon with thin tracks. Parts will render invisible. * Let the mouse hover over the visible part of the polygon. Use the command MorphPolygon(Object) to make each snippet a polygon on its own. Alternatively you can select the polygon and apply the variant MorphPolygon(Selected) Thanks -- this was what I was missing. I think I read about MorphPolygon() on this list, but I did not know how to use it correctly. Best regards, Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I agree with Niel, I separate my ground planes with a symbol for a power inductor. I do this at the schematic level and then I read the layout suggestions typically provided by the A/D data sheet on where to connect the planes. For the fab I put in the power inductor foot print. You can then use the power inductor or not. You can leave it open or you can short it. I also do similar activities for power supplies separating the board power from board sections. Makes it very easy to debug the board from one section to the next. Steve Meier On Mon, 2008-10-27 at 19:47 +0200, Duncan Drennan wrote: I typically deal with this by separating the planes at the schematic level using a bead-core inductor. Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On the issue of powering boards I have been playing with some really neat programmable power supply controllers (surface mount chip) that support power supply modules. Prices of the modules seem to be comparable to the prices of the individual components one would need to build various forms of switching power supplies. The controllers set the duty cycle, phase and frequency of the switching power supplies. This makes it possible to insure that two switchers are switching out of phase with each other. Other parameters which are controlled are delays from power up and rate of power up. So one other trick I use is to isolate each power supply from the rest of the board with a jumper (large diameter holes to support a fat wire). Then when we first turn on the board, we program the power supplies check out their voltages, ringing etc and then we connect them via the jumper to the rest of the board. Steve Meier On Mon, 2008-10-27 at 14:43 -0700, Steve Meier wrote: I agree with Niel, I separate my ground planes with a symbol for a power inductor. I do this at the schematic level and then I read the layout suggestions typically provided by the A/D data sheet on where to connect the planes. For the fab I put in the power inductor foot print. You can then use the power inductor or not. You can leave it open or you can short it. I also do similar activities for power supplies separating the board power from board sections. Makes it very easy to debug the board from one section to the next. Steve Meier On Mon, 2008-10-27 at 19:47 +0200, Duncan Drennan wrote: I typically deal with this by separating the planes at the schematic level using a bead-core inductor. Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Mon, 27 Oct 2008 19:47:52 +0100, Stefan Salewski wrote: * Draw lines on copper with zero thickness but finite clearance. Does this really result in legal Gerber files -- would be not so nice if a few manufacturers can not handle it. I didn't check the Gerber specs. My favorite fab (Basista) did not complain when I started to (miss) use this feature. They just rendered it like pcb and gerbv showed on the screen. If you want to completely dissect a polygon: * Divide the polygon with thin tracks. Parts will render invisible. * Let the mouse hover over the visible part of the polygon. Use the command MorphPolygon(Object) to make each snippet a polygon on its own. Alternatively you can select the polygon and apply the variant MorphPolygon(Selected) Note to Peter Clifton: There is a quirk in the Cairo enabled version. It does the morphing action and removes the old polygon. But it fails to automatically draw the newly produced polygons. I had to resort to the save-and-revert trick to get the new polygons on the screen. ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
