Re: [Intel-gfx] [PATCH 4/4] drm/i915: Extend skl+ crc sources with more planes
On Thu, Feb 14, 2019 at 11:29:08PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 14, 2019 at 12:47:23PM -0800, Rodrigo Vivi wrote:
> > On Thu, Feb 14, 2019 at 09:22:19PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > On skl the crc registers were extended to provide plane crcs
> > > for up to 7 planes. Add the new crc sources.
> > >
> > > The current code uses the ivb+ register definitions for skl+
> > > which does happen to work as the plane1, plane2, and dmux/pf
> > > bits happen the match what ivb+ had. So no bug in the current
> > > code.
> > >
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 5 ++
> > > drivers/gpu/drm/i915/i915_reg.h | 9
> > > drivers/gpu/drm/i915/intel_pipe_crc.c | 76 ++-
> > > 3 files changed, 88 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 4e11d970cbcf..8607c1e9ed02 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1196,6 +1196,11 @@ enum intel_pipe_crc_source {
> > > INTEL_PIPE_CRC_SOURCE_NONE,
> > > INTEL_PIPE_CRC_SOURCE_PLANE1,
> > > INTEL_PIPE_CRC_SOURCE_PLANE2,
> > > + INTEL_PIPE_CRC_SOURCE_PLANE3,
> > > + INTEL_PIPE_CRC_SOURCE_PLANE4,
> > > + INTEL_PIPE_CRC_SOURCE_PLANE5,
> > > + INTEL_PIPE_CRC_SOURCE_PLANE6,
> > > + INTEL_PIPE_CRC_SOURCE_PLANE7,
> > > INTEL_PIPE_CRC_SOURCE_PIPE,
> > > /* TV/DP on pre-gen5/vlv can't use the pipe source. */
> > > INTEL_PIPE_CRC_SOURCE_TV,
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 0df8c6e76da7..5286536e9cb8 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4017,6 +4017,15 @@ enum {
> > > /* Pipe A CRC regs */
> > > #define _PIPE_CRC_CTL_A 0x60050
> > > #define PIPE_CRC_ENABLE(1 << 31)
> > > +/* skl+ source selection */
> > > +#define PIPE_CRC_SOURCE_PLANE_1_SKL(0 << 28)
> > > +#define PIPE_CRC_SOURCE_PLANE_2_SKL(2 << 28)
> > > +#define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
> > > +#define PIPE_CRC_SOURCE_PLANE_3_SKL(6 << 28)
> > > +#define PIPE_CRC_SOURCE_PLANE_4_SKL(7 << 28)
> > > +#define PIPE_CRC_SOURCE_PLANE_5_SKL(5 << 28)
> > > +#define PIPE_CRC_SOURCE_PLANE_6_SKL(3 << 28)
> > > +#define PIPE_CRC_SOURCE_PLANE_7_SKL(1 << 28)
> >
> > I got myself staring at spec for a while trying to
> > understand the logic of this sequence...
>
> Did you find any logic in it? I honestly can't remember anymore why I
> did it like this.
no no... I'm not criticizing you. Your way is the most
clean and organized one.
My surprise came from the fact that I couldn't find
any logic on how those bits got selected at first place. ;)
>
> >
> >
> > Reviewed-by: Rodrigo Vivi
> >
> >
> >
> > > /* ivb+ source selection */
> > > #define PIPE_CRC_SOURCE_PRIMARY_IVB(0 << 29)
> > > #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
> > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > index 66bb7b031537..e521f82ba5d9 100644
> > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > @@ -34,6 +34,11 @@ static const char * const pipe_crc_sources[] = {
> > > [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
> > > [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
> > > [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
> > > + [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
> > > + [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
> > > + [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
> > > + [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
> > > + [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
> > > [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
> > > [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
> > > [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
> > > @@ -368,6 +373,50 @@ static int ivb_pipe_crc_ctl_reg(struct
> > > drm_i915_private *dev_priv,
> > > return 0;
> > > }
> > >
> > > +static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> > > + enum pipe pipe,
> > > + enum intel_pipe_crc_source *source,
> > > + uint32_t *val,
> > > + bool set_wa)
> > > +{
> > > + if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> > > + *source = INTEL_PIPE_CRC_SOURCE_PIPE;
> > > +
> > > + switch (*source) {
> > > + case INTEL_PIPE_CRC_SOURCE_PLANE1:
> > > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
> > > + break;
> > > + case INTEL_PIPE_CRC_SOURCE_PLANE2:
> > > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
> > > + break;
> > > + case INTEL_PIPE_CRC_SOURCE_PLANE3:
> > > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
> > > + break;
> > > + case INTEL_PIPE_CRC_SOURCE_PLANE4:
> > > + *v
[Intel-gfx] [PATCH 2/2] drm/i915/guc: Calling guc_disable_communication in all suspend paths
This aim of this patch is to call guc_disable_communication in all
suspend paths. The reason to introduce this is to resolve a bug that
occured due to suspend late not being called in the hibernate devices
path.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_reset.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 23 +++
drivers/gpu/drm/i915/intel_uc.h | 1 +
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 12e74decd7a2..36e5c9c64285 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -673,7 +673,7 @@ static void reset_prepare(struct drm_i915_private *i915)
for_each_engine(engine, i915, id)
reset_prepare_engine(engine);
- intel_uc_sanitize(i915);
+ intel_uc_reset_prepare(i915);
revoke_mmaps(i915);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index e711eb3268bc..2d360d53757f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -332,8 +332,6 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
GEM_BUG_ON(!HAS_GUC(i915));
- guc_disable_communication(guc);
-
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
@@ -451,6 +449,23 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
guc_disable_communication(guc);
}
+/**
+ * intel_uc_reset_prepare - Prepare for reset
+ * @i915: device private
+ *
+ * Preparing for full gpu reset.
+ */
+void intel_uc_reset_prepare(struct drm_i915_private *i915)
+{
+ struct intel_guc *guc = &i915->guc;
+
+ if (!USES_GUC(i915))
+ return;
+
+ guc_disable_communication(guc);
+ intel_uc_sanitize(i915);
+}
+
int intel_uc_suspend(struct drm_i915_private *i915)
{
struct intel_guc *guc = &i915->guc;
@@ -468,7 +483,7 @@ int intel_uc_suspend(struct drm_i915_private *i915)
return err;
}
- gen9_disable_guc_interrupts(i915);
+ guc_disable_communication(guc);
return 0;
}
@@ -484,7 +499,7 @@ int intel_uc_resume(struct drm_i915_private *i915)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- gen9_enable_guc_interrupts(i915);
+ guc_enable_communication(guc);
err = intel_guc_resume(guc);
if (err) {
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 870faf9011b9..c14729786652 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -38,6 +38,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv);
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
int intel_uc_init(struct drm_i915_private *dev_priv);
void intel_uc_fini(struct drm_i915_private *dev_priv);
+void intel_uc_reset_prepare(struct drm_i915_private *i915);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
int intel_uc_resume(struct drm_i915_private *dev_priv);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/guc: Splitting CT channel open/close functions
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_guc.c| 12
drivers/gpu/drm/i915/intel_guc_ct.c | 85 +
drivers/gpu/drm/i915/intel_guc_ct.h | 3 +
3 files changed, 77 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 8660af3fd755..8ecb47087457 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -203,11 +203,19 @@ int intel_guc_init(struct intel_guc *guc)
goto err_log;
GEM_BUG_ON(!guc->ads_vma);
+ if (HAS_GUC_CT(dev_priv)) {
+ ret = intel_guc_ct_init(&guc->ct);
+ if (ret)
+ goto err_ads;
+ }
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
return 0;
+err_ads:
+ intel_guc_ads_destroy(guc);
err_log:
intel_guc_log_destroy(&guc->log);
err_shared:
@@ -222,6 +230,10 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
i915_ggtt_disable_guc(dev_priv);
+
+ if (HAS_GUC_CT(dev_priv))
+ intel_guc_ct_fini(&guc->ct);
+
intel_guc_ads_destroy(guc);
intel_guc_log_destroy(&guc->log);
guc_shared_data_destroy(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c
b/drivers/gpu/drm/i915/intel_guc_ct.c
index a52883e9146f..fbf9da247975 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -140,9 +140,9 @@ static int guc_action_deregister_ct_buffer(struct intel_guc
*guc,
return err;
}
-static bool ctch_is_open(struct intel_guc_ct_channel *ctch)
+static bool ctch_is_enabled(struct intel_guc_ct_channel *ctch)
{
- return ctch->vma != NULL;
+ return ctch->is_enabled;
}
static int ctch_init(struct intel_guc *guc,
@@ -217,22 +217,14 @@ static void ctch_fini(struct intel_guc *guc,
i915_vma_unpin_and_release(&ctch->vma, I915_VMA_RELEASE_MAP);
}
-static int ctch_open(struct intel_guc *guc,
+static int ctch_enable(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
u32 base;
int err;
int i;
- CT_DEBUG_DRIVER("CT: channel %d reopen=%s\n",
- ctch->owner, yesno(ctch_is_open(ctch)));
-
- if (!ctch->vma) {
- err = ctch_init(guc, ctch);
- if (unlikely(err))
- goto err_out;
- GEM_BUG_ON(!ctch->vma);
- }
+ GEM_BUG_ON(!ctch->vma);
/* vma should be already allocated and map'ed */
base = intel_guc_ggtt_offset(guc, ctch->vma);
@@ -255,7 +247,7 @@ static int ctch_open(struct intel_guc *guc,
base + PAGE_SIZE/4 * CTB_RECV,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
if (unlikely(err))
- goto err_fini;
+ goto err_out;
err = guc_action_register_ct_buffer(guc,
base + PAGE_SIZE/4 * CTB_SEND,
@@ -263,23 +255,25 @@ static int ctch_open(struct intel_guc *guc,
if (unlikely(err))
goto err_deregister;
+ ctch->is_enabled = true;
+
return 0;
err_deregister:
guc_action_deregister_ct_buffer(guc,
ctch->owner,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
-err_fini:
- ctch_fini(guc, ctch);
err_out:
DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
return err;
}
-static void ctch_close(struct intel_guc *guc,
+static void ctch_disable(struct intel_guc *guc,
struct intel_guc_ct_channel *ctch)
{
- GEM_BUG_ON(!ctch_is_open(ctch));
+ GEM_BUG_ON(!ctch_is_enabled(ctch));
+
+ ctch->is_enabled = false;
guc_action_deregister_ct_buffer(guc,
ctch->owner,
@@ -287,7 +281,6 @@ static void ctch_close(struct intel_guc *guc,
guc_action_deregister_ct_buffer(guc,
ctch->owner,
INTEL_GUC_CT_BUFFER_TYPE_RECV);
- ctch_fini(guc, ctch);
}
static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
@@ -481,7 +474,7 @@ static int ctch_send(struct intel_guc_ct *ct,
u32 fence;
int err;
- GEM_BUG_ON(!ctch_is_open(ctch));
+ GEM_BUG_ON(!ctch_is_enabled(ctch));
GEM_BUG_ON(!len);
GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
GEM_BUG_ON(!response_buf && response_buf_size);
@@ -817,7 +810,7 @@ static void ct_process_host_channel(struct intel_guc_ct *ct)
u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one
[Intel-gfx] [PATCH 0/2] GuC suspend paths cleanup
The work was started to fix bugs that were seen on the suspend and hibernate devices path.The initial issue to be seen was a warning with the CTB. In parallel there were issues seen on the suspend paths. This series works to resolve the errors in the GuC cleanup paths and be compatible with lockless reset. Sujaritha Sundaresan (2): drm/i915/guc: Splitting CT channel open/close functions drm/i915/guc: Calling guc_disable_communication in all suspend paths drivers/gpu/drm/i915/i915_reset.c | 2 +- drivers/gpu/drm/i915/intel_guc.c| 12 drivers/gpu/drm/i915/intel_guc_ct.c | 85 + drivers/gpu/drm/i915/intel_guc_ct.h | 3 + drivers/gpu/drm/i915/intel_uc.c | 23 ++-- drivers/gpu/drm/i915/intel_uc.h | 1 + 6 files changed, 98 insertions(+), 28 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Always use an active engine while resetting
== Series Details ==
Series: drm/i915/selftests: Always use an active engine while resetting
URL : https://patchwork.freedesktop.org/series/56633/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5601_full -> Patchwork_12218_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12218_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12218_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12218_full:
### IGT changes ###
Possible regressions
* igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
- shard-apl: PASS -> FAIL
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr2_su@frontbuffer}:
- shard-iclb: NOTRUN -> {SKIP}
Known issues
Here are the changes found in Patchwork_12218_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_workarounds:
- shard-iclb: PASS -> DMESG-FAIL [fdo#108954]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-b-crc-primary-basic:
- shard-iclb: NOTRUN -> FAIL [fdo#107725]
* igt@kms_color@pipe-b-ctm-0-75:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#109624]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-kbl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-apl: PASS -> FAIL [fdo#109350]
* igt@kms_fbcon_fbt@fbc:
- shard-iclb: PASS -> DMESG-WARN [fdo#109593]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_flip@modeset-vs-vblank-race-interruptible:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +1
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-kbl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
- shard-hsw: PASS -> FAIL [fdo#99912]
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: PASS -> FAIL [fdo#104894]
* igt@pm_rpm@dpms-lpsp:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] +3
Possible fixes
* igt@gem_eio@in-flight-suspend:
- shard-kbl: INCOMPLETE [fdo#103665] / [fdo#106702] -> PASS
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-kbl: DMESG-WARN [fdo#108566] -> PASS
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: FAIL [fdo#102887] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
- shard-iclb: FAIL [fdo#103167] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_sysfs_edid_timing:
- shard-iclb: FAIL [fdo#100047] -> PASS
* igt@pm_backlight@basic-brightness:
- shard-iclb: INCOMPLETE [fdo#107820] -> PASS
* igt@pm_rpm@debugfs-read:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS +3
* igt@pm_rpm@universal-planes:
- shard-iclb: DMESG-WARN [fdo#108654] / [fdo#108756] -> PASS
Warnings
[Intel-gfx] [PATCH V4 i-g-t] Skip VBlank tests in modules without VBlank
The kms_flip test relies on VBlank support, and this situation may
exclude some virtual drivers to take advantage of this set of tests.
This commit adds a mechanism that checks if a module has VBlank. If the
target module has VBlank support, kms_flip will run all the VBlank
tests; otherwise, the VBlank tests will be skipped. Additionally, this
commit improves the test coverage by checks if the function
drmWaitVBlank() returns EOPNOTSUPP (i.e., no VBlank support).
Changes since V3:
Daniel Vetter:
- Add documentation for kms_vblank_status()
Changes since V2:
- Add new branch coverage to check if VBlank is enabled or not
- Update commit message
- Change function name from kms_has_vblank to kms_vblank_status
Changes since V1:
Chris Wilson:
- Change function name from igt_there_is_vblank to kms_has_vblank
- Move vblank function check from igt_aux to igt_kms
- Utilizes memset in dummy_vbl variable
- Directly return the result of drmWaitVBlank()
Signed-off-by: Rodrigo Siqueira
---
lib/igt_kms.c| 20
lib/igt_kms.h| 2 ++
tests/kms_flip.c | 27 +--
3 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 85a911e1..81fbafe0 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1654,6 +1654,26 @@ void igt_assert_plane_visible(int fd, enum pipe pipe,
bool visibility)
igt_assert_eq(visible, visibility);
}
+/**
+ * kms_vblank_status:
+ * @fd: DRM fd
+ *
+ * Get the VBlank status after an attempt to call drmWaitVBlank(). This
+ * function is useful for checking if a driver has support or not for VBlank.
+ *
+ * Returns: The errno code generated by drmWaitVBlank()
+ */
+int kms_vblank_status(int fd)
+{
+ drmVBlank dummy_vbl;
+
+ memset(&dummy_vbl, 0, sizeof(drmVBlank));
+ dummy_vbl.request.type = DRM_VBLANK_ABSOLUTE;
+
+ drmWaitVBlank(fd, &dummy_vbl);
+ return errno;
+}
+
/*
* A small modeset API
*/
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 679d4e84..259eaa75 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -230,6 +230,8 @@ void kmstest_wait_for_pageflip(int fd);
unsigned int kmstest_get_vblank(int fd, int pipe, unsigned int flags);
void igt_assert_plane_visible(int fd, enum pipe pipe, bool visibility);
+int kms_vblank_status(int fd);
+
/*
* A small modeset API
*/
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 798fc4e8..efc59328 100755
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -73,6 +73,7 @@
#define TEST_TS_CONT (1 << 27)
#define TEST_BO_TOOBIG (1 << 28)
+#define TEST_NO_VBLANK (1 << 29)
#define TEST_BASIC (1 << 30)
#define EVENT_FLIP (1 << 0)
@@ -125,6 +126,18 @@ struct event_state {
int seq_step;
};
+static bool vblank_dependence(int flags)
+{
+ int vblank_flags = TEST_VBLANK | TEST_VBLANK_BLOCK |
+ TEST_VBLANK_ABSOLUTE | TEST_VBLANK_EXPIRED_SEQ |
+ TEST_TS_CONT | TEST_CHECK_TS | TEST_VBLANK_RACE;
+
+ if (flags & vblank_flags)
+ return true;
+
+ return false;
+}
+
static float timeval_float(const struct timeval *tv)
{
return tv->tv_sec + tv->tv_usec / 100.0f;
@@ -493,11 +506,11 @@ static void check_state(const struct test_output *o,
const struct event_state *e
/* check only valid if no modeset happens in between, that increments by
* (1 << 23) on each step. This bounding matches the one in
* DRM_IOCTL_WAIT_VBLANK. */
- if (!(o->flags & (TEST_DPMS | TEST_MODESET)))
+ if (!(o->flags & (TEST_DPMS | TEST_MODESET | TEST_NO_VBLANK))) {
igt_assert_f(es->current_seq - (es->last_seq + o->seq_step) <=
1UL << 23,
"unexpected %s seq %u, should be >= %u\n",
es->name, es->current_seq, es->last_seq +
o->seq_step);
-
+ }
/* Check that the vblank frame didn't wrap unexpectedly. */
if (o->flags & TEST_TS_CONT) {
/* Ignore seq_step here since vblank waits time out immediately
@@ -1184,6 +1197,7 @@ static void run_test_on_crtc_set(struct test_output *o,
int *crtc_idxs,
unsigned bo_size = 0;
uint64_t tiling;
int i;
+ int vblank_status = 0;
switch (crtc_count) {
case 1:
@@ -1267,6 +1281,15 @@ static void run_test_on_crtc_set(struct test_output *o,
int *crtc_idxs,
}
igt_assert(fb_is_bound(o, o->fb_ids[0]));
+ vblank_status = kms_vblank_status(drm_fd);
+ if (vblank_status == EOPNOTSUPP) {
+ if (vblank_dependence(o->flags))
+ igt_require_f(!(vblank_status == EOPNOTSUPP),
+ "Vblank: %s\n", strerror(vblank_status));
+ else
+ o->flags |= TEST_NO_VBLANK;
+ }
+
/* quiescent the hw a bit so ensure we don't miss a single frame */
if (o->flags
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Extend skl+ crc sources with more planes
On Thu, Feb 14, 2019 at 12:47:23PM -0800, Rodrigo Vivi wrote:
> On Thu, Feb 14, 2019 at 09:22:19PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On skl the crc registers were extended to provide plane crcs
> > for up to 7 planes. Add the new crc sources.
> >
> > The current code uses the ivb+ register definitions for skl+
> > which does happen to work as the plane1, plane2, and dmux/pf
> > bits happen the match what ivb+ had. So no bug in the current
> > code.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 5 ++
> > drivers/gpu/drm/i915/i915_reg.h | 9
> > drivers/gpu/drm/i915/intel_pipe_crc.c | 76 ++-
> > 3 files changed, 88 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 4e11d970cbcf..8607c1e9ed02 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1196,6 +1196,11 @@ enum intel_pipe_crc_source {
> > INTEL_PIPE_CRC_SOURCE_NONE,
> > INTEL_PIPE_CRC_SOURCE_PLANE1,
> > INTEL_PIPE_CRC_SOURCE_PLANE2,
> > + INTEL_PIPE_CRC_SOURCE_PLANE3,
> > + INTEL_PIPE_CRC_SOURCE_PLANE4,
> > + INTEL_PIPE_CRC_SOURCE_PLANE5,
> > + INTEL_PIPE_CRC_SOURCE_PLANE6,
> > + INTEL_PIPE_CRC_SOURCE_PLANE7,
> > INTEL_PIPE_CRC_SOURCE_PIPE,
> > /* TV/DP on pre-gen5/vlv can't use the pipe source. */
> > INTEL_PIPE_CRC_SOURCE_TV,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 0df8c6e76da7..5286536e9cb8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4017,6 +4017,15 @@ enum {
> > /* Pipe A CRC regs */
> > #define _PIPE_CRC_CTL_A0x60050
> > #define PIPE_CRC_ENABLE (1 << 31)
> > +/* skl+ source selection */
> > +#define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28)
> > +#define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28)
> > +#define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
> > +#define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28)
> > +#define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28)
> > +#define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28)
> > +#define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28)
> > +#define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28)
>
> I got myself staring at spec for a while trying to
> understand the logic of this sequence...
Did you find any logic in it? I honestly can't remember anymore why I
did it like this.
>
>
> Reviewed-by: Rodrigo Vivi
>
>
>
> > /* ivb+ source selection */
> > #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
> > #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
> > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > index 66bb7b031537..e521f82ba5d9 100644
> > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > @@ -34,6 +34,11 @@ static const char * const pipe_crc_sources[] = {
> > [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
> > [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
> > [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
> > + [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
> > + [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
> > + [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
> > + [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
> > + [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
> > [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
> > [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
> > [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
> > @@ -368,6 +373,50 @@ static int ivb_pipe_crc_ctl_reg(struct
> > drm_i915_private *dev_priv,
> > return 0;
> > }
> >
> > +static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> > + enum pipe pipe,
> > + enum intel_pipe_crc_source *source,
> > + uint32_t *val,
> > + bool set_wa)
> > +{
> > + if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> > + *source = INTEL_PIPE_CRC_SOURCE_PIPE;
> > +
> > + switch (*source) {
> > + case INTEL_PIPE_CRC_SOURCE_PLANE1:
> > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
> > + break;
> > + case INTEL_PIPE_CRC_SOURCE_PLANE2:
> > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
> > + break;
> > + case INTEL_PIPE_CRC_SOURCE_PLANE3:
> > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
> > + break;
> > + case INTEL_PIPE_CRC_SOURCE_PLANE4:
> > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
> > + break;
> > + case INTEL_PIPE_CRC_SOURCE_PLANE5:
> > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
> > + break;
> > + case INTEL_PIPE_CRC_SOURCE_PLANE6:
> > + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
> > + break;
> > + case INTEL_PIPE_CRC_SOURCE_PLANE7:
> >
Re: [Intel-gfx] [RFC PATCH 34/42] drm/i915/query: Expose memory regions through the query uAPI
Quoting Chris Wilson (2019-02-14 21:15:17) > Quoting Matthew Auld (2019-02-14 14:57:32) > > From: Abdiel Janulgue > > > > Returns the available memory region areas supported by the HW. > > This should include references to the Vulkan spec to show how it can be > used to convey the information required by anv (and what must be > inferred by userspace). That reference should be dotted around the > commitmg, the uapi.h and the code. > > https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/vkspec.html#memory And also https://www.khronos.org/registry/OpenCL/specs/opencl-2.0.pdf 3.3 Memory Model It is not as explicit for probing as Vk, but I expect will useful to keep a crossreference or two. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 34/42] drm/i915/query: Expose memory regions through the query uAPI
Quoting Matthew Auld (2019-02-14 14:57:32) > From: Abdiel Janulgue > > Returns the available memory region areas supported by the HW. This should include references to the Vulkan spec to show how it can be used to convey the information required by anv (and what must be inferred by userspace). That reference should be dotted around the commitmg, the uapi.h and the code. https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/vkspec.html#memory -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 34/42] drm/i915/query: Expose memory regions through the query uAPI
Quoting Chris Wilson (2019-02-14 16:33:55)
> Quoting Chris Wilson (2019-02-14 16:31:13)
> > Quoting Matthew Auld (2019-02-14 14:57:32)
> > > int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file
> > > *file)
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index 26d2274b5d2b..5a102a5cb415 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -1744,6 +1744,7 @@ struct drm_i915_perf_oa_config {
> > > struct drm_i915_query_item {
> > > __u64 query_id;
> > > #define DRM_I915_QUERY_TOPOLOGY_INFO1
> > > +#define DRM_I915_QUERY_MEMREGION_INFO 3
> >
> > Ahem.
> >
> > > /*
> > > * When set to zero by userspace, this is filled with the size of
> > > the
> > > @@ -1832,7 +1833,6 @@ struct drm_i915_query_topology_info {
> > > * Offset in data[] at which the EU masks are stored.
> > > */
> > > __u16 eu_offset;
> > > -
> > > /*
> > > * Stride at which each of the EU masks for each subslice are
> > > stored.
> > > */
> > > @@ -1841,6 +1841,44 @@ struct drm_i915_query_topology_info {
> > > __u8 data[];
> > > };
> > >
> > > +struct drm_i915_memory_region_info {
> > > +
> > > + /** Base type of a region
> > > +*/
> > > +#define I915_SYSTEM_MEMORY 0
> > > +#define I915_DEVICE_MEMORY 1
> > > +
> > > + /** The region id is encoded in a layout which makes it possible
> > > to
> > > +* retrieve the following information:
> > > +*
> > > +* Base type: log2(ID >> 16)
> > > +* Instance: log2(ID & 0x)
> > > +*/
> > > + __u32 id;
> > > +
> > > + /** Reserved field. MBZ */
> > > + __u32 rsvd0;
> > > +
> > > + /** Unused for now. MBZ */
> > > + __u64 flags;
> > > +
> > > + __u64 size;
> > > +
> > > + /** Reserved fields must be cleared to zero. */
> > > + __u64 rsvd1[4];
> > > +};
> >
> > If you were to apply this to stolen memory as an example, can you spot
> > how much information is missing?
> >
> > Userspace would need to know total size, largest allocation chunk (i.e
> > largest object), rough estimate of availability, and most importantly a
> > list of API that is not allowed (such as CPU mmap, fencing). There's
> > without a doubt more that would be needed to actually wire it up to Vk.
>
> Cross-process/ppgtt and cross-device sharing for example...
Another concept along the lines of MAP_PRIVATE above, is pure scratch. A
WO memory region that is not guaranteed to retain its state between
execution and is never swapped out but zapped under pressure. The use
being for things like kernel scratch allocations (for register spilling
and whatnot). Though small in the grand scheme of things, a context may
need 10+MiB of scratch (since even a small amount required per-thread
becomes a large amount) per stage.
I'm just looking to see what possibilities we may explore :)
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Extend skl+ crc sources with more planes
On Thu, Feb 14, 2019 at 09:22:19PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On skl the crc registers were extended to provide plane crcs
> for up to 7 planes. Add the new crc sources.
>
> The current code uses the ivb+ register definitions for skl+
> which does happen to work as the plane1, plane2, and dmux/pf
> bits happen the match what ivb+ had. So no bug in the current
> code.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 ++
> drivers/gpu/drm/i915/i915_reg.h | 9
> drivers/gpu/drm/i915/intel_pipe_crc.c | 76 ++-
> 3 files changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4e11d970cbcf..8607c1e9ed02 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1196,6 +1196,11 @@ enum intel_pipe_crc_source {
> INTEL_PIPE_CRC_SOURCE_NONE,
> INTEL_PIPE_CRC_SOURCE_PLANE1,
> INTEL_PIPE_CRC_SOURCE_PLANE2,
> + INTEL_PIPE_CRC_SOURCE_PLANE3,
> + INTEL_PIPE_CRC_SOURCE_PLANE4,
> + INTEL_PIPE_CRC_SOURCE_PLANE5,
> + INTEL_PIPE_CRC_SOURCE_PLANE6,
> + INTEL_PIPE_CRC_SOURCE_PLANE7,
> INTEL_PIPE_CRC_SOURCE_PIPE,
> /* TV/DP on pre-gen5/vlv can't use the pipe source. */
> INTEL_PIPE_CRC_SOURCE_TV,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0df8c6e76da7..5286536e9cb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4017,6 +4017,15 @@ enum {
> /* Pipe A CRC regs */
> #define _PIPE_CRC_CTL_A 0x60050
> #define PIPE_CRC_ENABLE(1 << 31)
> +/* skl+ source selection */
> +#define PIPE_CRC_SOURCE_PLANE_1_SKL(0 << 28)
> +#define PIPE_CRC_SOURCE_PLANE_2_SKL(2 << 28)
> +#define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
> +#define PIPE_CRC_SOURCE_PLANE_3_SKL(6 << 28)
> +#define PIPE_CRC_SOURCE_PLANE_4_SKL(7 << 28)
> +#define PIPE_CRC_SOURCE_PLANE_5_SKL(5 << 28)
> +#define PIPE_CRC_SOURCE_PLANE_6_SKL(3 << 28)
> +#define PIPE_CRC_SOURCE_PLANE_7_SKL(1 << 28)
I got myself staring at spec for a while trying to
understand the logic of this sequence...
Reviewed-by: Rodrigo Vivi
> /* ivb+ source selection */
> #define PIPE_CRC_SOURCE_PRIMARY_IVB(0 << 29)
> #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index 66bb7b031537..e521f82ba5d9 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -34,6 +34,11 @@ static const char * const pipe_crc_sources[] = {
> [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
> [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
> [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
> + [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
> + [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
> + [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
> + [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
> + [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
> [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
> [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
> [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
> @@ -368,6 +373,50 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
> *dev_priv,
> return 0;
> }
>
> +static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> + enum pipe pipe,
> + enum intel_pipe_crc_source *source,
> + uint32_t *val,
> + bool set_wa)
> +{
> + if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> + *source = INTEL_PIPE_CRC_SOURCE_PIPE;
> +
> + switch (*source) {
> + case INTEL_PIPE_CRC_SOURCE_PLANE1:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_PLANE2:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_PLANE3:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_PLANE4:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_PLANE5:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_PLANE6:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_PLANE7:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_PIPE:
> + *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
> + break;
> + case INTEL_PIPE_CRC_SOURCE_NONE:
> +
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove the broken DP CRC support for g4x
On Thu, Feb 14, 2019 at 12:38:22PM -0800, Rodrigo Vivi wrote:
> On Thu, Feb 14, 2019 at 09:22:18PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > DP CRCs don't really work on g4x. If you want any CRCs on DP you must
> > select the CRC source before the port is enabled, otherwise the CRC
> > source select bits simply ignore any writes to them. And once the port
> > is enabled we mustn't change the CRC source select until the port is
> > disabled. That almost works, but not quite :( Eventually the CRC source
> > select bits get permanently stuck one way or the other, and after that
> > a reboot (or possibly a display reset) is needed to get working CRCs
> > on that pipe (not matter which CRC source we try to use).
> >
> > Additionally the DFT scrambler reset bits we're trying to use don't
> > seem to exist on g4x. There are some potentially relevant looking bits
> > in the pipe registers, but when I tried it I got stable looking CRCs
> > without setting any bits for this.
> >
> > If there is a way to make DP CRCs work reliably on g4x, I wasn't
> > able to find it. So let's just remove the broken code we have.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_pipe_crc.c | 80 ---
> > 1 file changed, 11 insertions(+), 69 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > index fe0ff89b980b..66bb7b031537 100644
> > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > @@ -191,8 +191,6 @@ static int i9xx_pipe_crc_ctl_reg(struct
> > drm_i915_private *dev_priv,
> > enum intel_pipe_crc_source *source,
> > u32 *val)
> > {
> > - bool need_stable_symbols = false;
> > -
> > if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
> > int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
> > if (ret)
> > @@ -208,56 +206,23 @@ static int i9xx_pipe_crc_ctl_reg(struct
> > drm_i915_private *dev_priv,
> > return -EINVAL;
> > *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
> > break;
> > - case INTEL_PIPE_CRC_SOURCE_DP_B:
> > - if (!IS_G4X(dev_priv))
> > - return -EINVAL;
> > - *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
> > - need_stable_symbols = true;
> > - break;
> > - case INTEL_PIPE_CRC_SOURCE_DP_C:
> > - if (!IS_G4X(dev_priv))
> > - return -EINVAL;
> > - *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
> > - need_stable_symbols = true;
> > - break;
> > - case INTEL_PIPE_CRC_SOURCE_DP_D:
> > - if (!IS_G4X(dev_priv))
> > - return -EINVAL;
> > - *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
> > - need_stable_symbols = true;
> > - break;
> > case INTEL_PIPE_CRC_SOURCE_NONE:
> > *val = 0;
> > break;
> > default:
> > + /*
> > +* The DP CRC source doesn't work on g4x.
> > +* It can be made to work to some degree by selecting
> > +* the correct CRC source before the port is enabled,
> > +* and not touching the CRC source bits again until
> > +* the port is disabled. But even then the bits
> > +* eventually get stuck and a reboot is needed to get
> > +* working CRCs on the pipe again. Let's simply
> > +* refuse to use DP CRCs on g4x.
> > +*/
> > return -EINVAL;
>
> is this the right return now? maybe ENOENT?
> (just brainstorming without looking to igt tests)
We return -EINVAL for all other unsupported sources, so this
seems consistent.
>
> But I know how terrible unreliable crcs are and this patch
> looks the right way, so:
>
> Reviewed-by: Rodrigo Vivi
>
>
>
> > }
> >
> > - /*
> > -* When the pipe CRC tap point is after the transcoders we need
> > -* to tweak symbol-level features to produce a deterministic series of
> > -* symbols for a given frame. We need to reset those features only once
> > -* a frame (instead of every nth symbol):
> > -* - DC-balance: used to ensure a better clock recovery from the data
> > -* link (SDVO)
> > -* - DisplayPort scrambling: used for EMI reduction
> > -*/
> > - if (need_stable_symbols) {
> > - u32 tmp = I915_READ(PORT_DFT2_G4X);
> > -
> > - WARN_ON(!IS_G4X(dev_priv));
> > -
> > - I915_WRITE(PORT_DFT_I9XX,
> > - I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
> > -
> > - if (pipe == PIPE_A)
> > - tmp |= PIPE_A_SCRAMBLE_RESET;
> > - else
> > - tmp |= PIPE_B_SCRAMBLE_RESET;
> > -
> > - I915_WRITE(PORT_DFT2_G4X, tmp);
> > - }
> > -
> > return 0;
> > }
> >
>
Re: [Intel-gfx] [PATCH 4/6] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
Swati Sharma kirjoitti 13.2.2019 klo 15.25:
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each component, valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: For each component, valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: For each component valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
The following pixel formats are packed format that follows 4:4:4
chroma sampling. Channels are arranged in the order UYVA in
increasing memory order.
Y410: Each color component occupies 10 bits and X component
takes 2 bits, thus each pixel occupies 32 bits.
Y412: Each color component is 16 bits where valid data
occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
Thus, each pixel occupies 64 bits.
Y416: Each color component occupies 16 bits for valid data,
doesn't require any padding bits. Thus, each pixel
occupies 64 bits.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 6 ++
include/uapi/drm/drm_fourcc.h | 18 +-
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index ba7e19d..45c9882 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -226,6 +226,12 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Y0L0,.depth = 0,
.num_planes = 1,
.char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 },
.block_h = { 2, 0, 0 },
.hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index bab2029..6e20ced 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,7 +151,23 @@
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /* [31:0]
X:Y:Cb:Cr 8:8:8:8 little endian */
^^
one tab removed?
With that fixed this is
Reviewed-by: Juha-Pekka Heikkila
+
+/*
+ * packed Y2xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb
+ */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0]
Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0]
Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0]
Y0:Cb0:Y1:Cr1 16:16:16:16 little endian per 2 Y pixels */
+
+/*
+ * packed Y4xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb except Y410
+ */
+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0]
X:V:Y:U 2:10:10:10 little endian */
+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2')
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove the broken DP CRC support for g4x
On Thu, Feb 14, 2019 at 09:22:18PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> DP CRCs don't really work on g4x. If you want any CRCs on DP you must
> select the CRC source before the port is enabled, otherwise the CRC
> source select bits simply ignore any writes to them. And once the port
> is enabled we mustn't change the CRC source select until the port is
> disabled. That almost works, but not quite :( Eventually the CRC source
> select bits get permanently stuck one way or the other, and after that
> a reboot (or possibly a display reset) is needed to get working CRCs
> on that pipe (not matter which CRC source we try to use).
>
> Additionally the DFT scrambler reset bits we're trying to use don't
> seem to exist on g4x. There are some potentially relevant looking bits
> in the pipe registers, but when I tried it I got stable looking CRCs
> without setting any bits for this.
>
> If there is a way to make DP CRCs work reliably on g4x, I wasn't
> able to find it. So let's just remove the broken code we have.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pipe_crc.c | 80 ---
> 1 file changed, 11 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index fe0ff89b980b..66bb7b031537 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -191,8 +191,6 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private
> *dev_priv,
>enum intel_pipe_crc_source *source,
>u32 *val)
> {
> - bool need_stable_symbols = false;
> -
> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
> int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
> if (ret)
> @@ -208,56 +206,23 @@ static int i9xx_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> return -EINVAL;
> *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
> break;
> - case INTEL_PIPE_CRC_SOURCE_DP_B:
> - if (!IS_G4X(dev_priv))
> - return -EINVAL;
> - *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
> - need_stable_symbols = true;
> - break;
> - case INTEL_PIPE_CRC_SOURCE_DP_C:
> - if (!IS_G4X(dev_priv))
> - return -EINVAL;
> - *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
> - need_stable_symbols = true;
> - break;
> - case INTEL_PIPE_CRC_SOURCE_DP_D:
> - if (!IS_G4X(dev_priv))
> - return -EINVAL;
> - *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
> - need_stable_symbols = true;
> - break;
> case INTEL_PIPE_CRC_SOURCE_NONE:
> *val = 0;
> break;
> default:
> + /*
> + * The DP CRC source doesn't work on g4x.
> + * It can be made to work to some degree by selecting
> + * the correct CRC source before the port is enabled,
> + * and not touching the CRC source bits again until
> + * the port is disabled. But even then the bits
> + * eventually get stuck and a reboot is needed to get
> + * working CRCs on the pipe again. Let's simply
> + * refuse to use DP CRCs on g4x.
> + */
> return -EINVAL;
is this the right return now? maybe ENOENT?
(just brainstorming without looking to igt tests)
But I know how terrible unreliable crcs are and this patch
looks the right way, so:
Reviewed-by: Rodrigo Vivi
> }
>
> - /*
> - * When the pipe CRC tap point is after the transcoders we need
> - * to tweak symbol-level features to produce a deterministic series of
> - * symbols for a given frame. We need to reset those features only once
> - * a frame (instead of every nth symbol):
> - * - DC-balance: used to ensure a better clock recovery from the data
> - * link (SDVO)
> - * - DisplayPort scrambling: used for EMI reduction
> - */
> - if (need_stable_symbols) {
> - u32 tmp = I915_READ(PORT_DFT2_G4X);
> -
> - WARN_ON(!IS_G4X(dev_priv));
> -
> - I915_WRITE(PORT_DFT_I9XX,
> -I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
> -
> - if (pipe == PIPE_A)
> - tmp |= PIPE_A_SCRAMBLE_RESET;
> - else
> - tmp |= PIPE_B_SCRAMBLE_RESET;
> -
> - I915_WRITE(PORT_DFT2_G4X, tmp);
> - }
> -
> return 0;
> }
>
> @@ -282,24 +247,6 @@ static void vlv_undo_pipe_scramble_reset(struct
> drm_i915_private *dev_priv,
> if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
> tmp &= ~DC_BALANCE_RESET_VLV;
> I915_WRITE(PORT_DFT2_G4X, tmp);
> -
> -}
> -
> -stat
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Use named initializers for the crc source name array
On Thu, Feb 14, 2019 at 09:22:17PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We assume that the index of the string in the crc source names
> array matches the enum value for the crc source. Let's use named
> initializers to make sure that is indeed the case even if someone
> rearranges either the enum or the array.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_pipe_crc.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index a3a3ad760158..fe0ff89b980b 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -31,15 +31,15 @@
> #include "intel_drv.h"
>
> static const char * const pipe_crc_sources[] = {
> - "none",
> - "plane1",
> - "plane2",
> - "pipe",
> - "TV",
> - "DP-B",
> - "DP-C",
> - "DP-D",
> - "auto",
> + [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
> + [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
> + [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
> + [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
> + [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
> + [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
> + [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
> + [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
> + [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
> };
>
> static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
> --
> 2.19.2
>
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Remove the "pf" crc source
On Thu, Feb 14, 2019 at 09:22:16PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The "pipe" and "pf" crc sources are in fact the same thing.
> Remove the "pf" one.
>
> Signed-off-by: Ville Syrjälä
I wonder where this came from
Anyway, just by looking the current code:
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/intel_pipe_crc.c | 6 ++
> 2 files changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 17fe942eaafa..4e11d970cbcf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1196,7 +1196,6 @@ enum intel_pipe_crc_source {
> INTEL_PIPE_CRC_SOURCE_NONE,
> INTEL_PIPE_CRC_SOURCE_PLANE1,
> INTEL_PIPE_CRC_SOURCE_PLANE2,
> - INTEL_PIPE_CRC_SOURCE_PF,
> INTEL_PIPE_CRC_SOURCE_PIPE,
> /* TV/DP on pre-gen5/vlv can't use the pipe source. */
> INTEL_PIPE_CRC_SOURCE_TV,
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index a8554dc4f196..a3a3ad760158 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -34,7 +34,6 @@ static const char * const pipe_crc_sources[] = {
> "none",
> "plane1",
> "plane2",
> - "pf",
> "pipe",
> "TV",
> "DP-B",
> @@ -396,7 +395,7 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
> *dev_priv,
> bool set_wa)
> {
> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> - *source = INTEL_PIPE_CRC_SOURCE_PF;
> + *source = INTEL_PIPE_CRC_SOURCE_PIPE;
>
> switch (*source) {
> case INTEL_PIPE_CRC_SOURCE_PLANE1:
> @@ -405,7 +404,7 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
> *dev_priv,
> case INTEL_PIPE_CRC_SOURCE_PLANE2:
> *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
> break;
> - case INTEL_PIPE_CRC_SOURCE_PF:
> + case INTEL_PIPE_CRC_SOURCE_PIPE:
> if (set_wa && (IS_HASWELL(dev_priv) ||
>IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
> hsw_pipe_A_crc_wa(dev_priv, true);
> @@ -532,7 +531,6 @@ static int ivb_crc_source_valid(struct drm_i915_private
> *dev_priv,
> case INTEL_PIPE_CRC_SOURCE_PIPE:
> case INTEL_PIPE_CRC_SOURCE_PLANE1:
> case INTEL_PIPE_CRC_SOURCE_PLANE2:
> - case INTEL_PIPE_CRC_SOURCE_PF:
> case INTEL_PIPE_CRC_SOURCE_NONE:
> return 0;
> default:
> --
> 2.19.2
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Remove the "pf" crc source
== Series Details ==
Series: series starting with [1/4] drm/i915: Remove the "pf" crc source
URL : https://patchwork.freedesktop.org/series/56692/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5602 -> Patchwork_12224
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56692/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12224 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709]
* igt@i915_selftest@live_hangcheck:
- fi-kbl-7560u: PASS -> INCOMPLETE [fdo#108044] / [fdo#108744]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@i915_selftest@live_workarounds:
- {fi-icl-u3}:INCOMPLETE [fdo#109626] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: FAIL [fdo#108800] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109226]: https://bugs.freedesktop.org/show_bug.cgi?id=109226
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109528]: https://bugs.freedesktop.org/show_bug.cgi?id=109528
[fdo#109530]: https://bugs.freedesktop.org/show_bug.cgi?id=109530
[fdo#109626]: https://bugs.freedesktop.org/show_bug.cgi?id=109626
Participating hosts (48 -> 42)
--
Additional (1): fi-icl-y
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-glk-j4005 fi-skl-6700hq fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5602 -> Patchwork_12224
CI_DRM_5602: 570d4d9a80d29c77155979e5fdfb2e1ba76057c7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4827: 395eaffd7e1390c9d6043c2980dc14ce3e08b154 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12224: 0434615d44ce8f4dc908e836f6981eceb17903dc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0434615d44ce drm/i915: Extend skl+ crc sources with more planes
647cd3d3a7e8 drm/i915: Remove the broken DP CRC support for g4x
4c9ccf4ebd34 drm/i915: Use named initializers for the crc source name array
1d7270fc22b4 drm/i915: Remove the "pf" crc source
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12224/
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915: Remove the "pf" crc source
== Series Details == Series: series starting with [1/4] drm/i915: Remove the "pf" crc source URL : https://patchwork.freedesktop.org/series/56692/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Remove the "pf" crc source -drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3565:16: warning: expression using sizeof(void) Commit: drm/i915: Use named initializers for the crc source name array Okay! Commit: drm/i915: Remove the broken DP CRC support for g4x Okay! Commit: drm/i915: Extend skl+ crc sources with more planes -drivers/gpu/drm/i915/selftests/../i915_drv.h:3565:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Remove the "pf" crc source
== Series Details == Series: series starting with [1/4] drm/i915: Remove the "pf" crc source URL : https://patchwork.freedesktop.org/series/56692/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1d7270fc22b4 drm/i915: Remove the "pf" crc source 4c9ccf4ebd34 drm/i915: Use named initializers for the crc source name array 647cd3d3a7e8 drm/i915: Remove the broken DP CRC support for g4x 0434615d44ce drm/i915: Extend skl+ crc sources with more planes -:78: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t' #78: FILE: drivers/gpu/drm/i915/intel_pipe_crc.c:379: + uint32_t *val, total: 0 errors, 0 warnings, 1 checks, 134 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915: Remove the broken DP CRC support for g4x
From: Ville Syrjälä
DP CRCs don't really work on g4x. If you want any CRCs on DP you must
select the CRC source before the port is enabled, otherwise the CRC
source select bits simply ignore any writes to them. And once the port
is enabled we mustn't change the CRC source select until the port is
disabled. That almost works, but not quite :( Eventually the CRC source
select bits get permanently stuck one way or the other, and after that
a reboot (or possibly a display reset) is needed to get working CRCs
on that pipe (not matter which CRC source we try to use).
Additionally the DFT scrambler reset bits we're trying to use don't
seem to exist on g4x. There are some potentially relevant looking bits
in the pipe registers, but when I tried it I got stable looking CRCs
without setting any bits for this.
If there is a way to make DP CRCs work reliably on g4x, I wasn't
able to find it. So let's just remove the broken code we have.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pipe_crc.c | 80 ---
1 file changed, 11 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index fe0ff89b980b..66bb7b031537 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -191,8 +191,6 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv,
enum intel_pipe_crc_source *source,
u32 *val)
{
- bool need_stable_symbols = false;
-
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
if (ret)
@@ -208,56 +206,23 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv,
return -EINVAL;
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
break;
- case INTEL_PIPE_CRC_SOURCE_DP_B:
- if (!IS_G4X(dev_priv))
- return -EINVAL;
- *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
- need_stable_symbols = true;
- break;
- case INTEL_PIPE_CRC_SOURCE_DP_C:
- if (!IS_G4X(dev_priv))
- return -EINVAL;
- *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
- need_stable_symbols = true;
- break;
- case INTEL_PIPE_CRC_SOURCE_DP_D:
- if (!IS_G4X(dev_priv))
- return -EINVAL;
- *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
- need_stable_symbols = true;
- break;
case INTEL_PIPE_CRC_SOURCE_NONE:
*val = 0;
break;
default:
+ /*
+* The DP CRC source doesn't work on g4x.
+* It can be made to work to some degree by selecting
+* the correct CRC source before the port is enabled,
+* and not touching the CRC source bits again until
+* the port is disabled. But even then the bits
+* eventually get stuck and a reboot is needed to get
+* working CRCs on the pipe again. Let's simply
+* refuse to use DP CRCs on g4x.
+*/
return -EINVAL;
}
- /*
-* When the pipe CRC tap point is after the transcoders we need
-* to tweak symbol-level features to produce a deterministic series of
-* symbols for a given frame. We need to reset those features only once
-* a frame (instead of every nth symbol):
-* - DC-balance: used to ensure a better clock recovery from the data
-* link (SDVO)
-* - DisplayPort scrambling: used for EMI reduction
-*/
- if (need_stable_symbols) {
- u32 tmp = I915_READ(PORT_DFT2_G4X);
-
- WARN_ON(!IS_G4X(dev_priv));
-
- I915_WRITE(PORT_DFT_I9XX,
- I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
-
- if (pipe == PIPE_A)
- tmp |= PIPE_A_SCRAMBLE_RESET;
- else
- tmp |= PIPE_B_SCRAMBLE_RESET;
-
- I915_WRITE(PORT_DFT2_G4X, tmp);
- }
-
return 0;
}
@@ -282,24 +247,6 @@ static void vlv_undo_pipe_scramble_reset(struct
drm_i915_private *dev_priv,
if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
tmp &= ~DC_BALANCE_RESET_VLV;
I915_WRITE(PORT_DFT2_G4X, tmp);
-
-}
-
-static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
-enum pipe pipe)
-{
- u32 tmp = I915_READ(PORT_DFT2_G4X);
-
- if (pipe == PIPE_A)
- tmp &= ~PIPE_A_SCRAMBLE_RESET;
- else
- tmp &= ~PIPE_B_SCRAMBLE_RESET;
- I915_WRITE(PORT_DFT2_G4X, tmp);
-
- if (!(tmp
[Intel-gfx] [PATCH 1/4] drm/i915: Remove the "pf" crc source
From: Ville Syrjälä
The "pipe" and "pf" crc sources are in fact the same thing.
Remove the "pf" one.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pipe_crc.c | 6 ++
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 17fe942eaafa..4e11d970cbcf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1196,7 +1196,6 @@ enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_NONE,
INTEL_PIPE_CRC_SOURCE_PLANE1,
INTEL_PIPE_CRC_SOURCE_PLANE2,
- INTEL_PIPE_CRC_SOURCE_PF,
INTEL_PIPE_CRC_SOURCE_PIPE,
/* TV/DP on pre-gen5/vlv can't use the pipe source. */
INTEL_PIPE_CRC_SOURCE_TV,
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index a8554dc4f196..a3a3ad760158 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -34,7 +34,6 @@ static const char * const pipe_crc_sources[] = {
"none",
"plane1",
"plane2",
- "pf",
"pipe",
"TV",
"DP-B",
@@ -396,7 +395,7 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv,
bool set_wa)
{
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
- *source = INTEL_PIPE_CRC_SOURCE_PF;
+ *source = INTEL_PIPE_CRC_SOURCE_PIPE;
switch (*source) {
case INTEL_PIPE_CRC_SOURCE_PLANE1:
@@ -405,7 +404,7 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv,
case INTEL_PIPE_CRC_SOURCE_PLANE2:
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
break;
- case INTEL_PIPE_CRC_SOURCE_PF:
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
if (set_wa && (IS_HASWELL(dev_priv) ||
IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
hsw_pipe_A_crc_wa(dev_priv, true);
@@ -532,7 +531,6 @@ static int ivb_crc_source_valid(struct drm_i915_private
*dev_priv,
case INTEL_PIPE_CRC_SOURCE_PIPE:
case INTEL_PIPE_CRC_SOURCE_PLANE1:
case INTEL_PIPE_CRC_SOURCE_PLANE2:
- case INTEL_PIPE_CRC_SOURCE_PF:
case INTEL_PIPE_CRC_SOURCE_NONE:
return 0;
default:
--
2.19.2
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915: Use named initializers for the crc source name array
From: Ville Syrjälä
We assume that the index of the string in the crc source names
array matches the enum value for the crc source. Let's use named
initializers to make sure that is indeed the case even if someone
rearranges either the enum or the array.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pipe_crc.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index a3a3ad760158..fe0ff89b980b 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -31,15 +31,15 @@
#include "intel_drv.h"
static const char * const pipe_crc_sources[] = {
- "none",
- "plane1",
- "plane2",
- "pipe",
- "TV",
- "DP-B",
- "DP-C",
- "DP-D",
- "auto",
+ [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
+ [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
+ [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
+ [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
+ [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
+ [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
+ [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
+ [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
+ [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
};
static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
--
2.19.2
___
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[Intel-gfx] [PATCH 4/4] drm/i915: Extend skl+ crc sources with more planes
From: Ville Syrjälä
On skl the crc registers were extended to provide plane crcs
for up to 7 planes. Add the new crc sources.
The current code uses the ivb+ register definitions for skl+
which does happen to work as the plane1, plane2, and dmux/pf
bits happen the match what ivb+ had. So no bug in the current
code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_reg.h | 9
drivers/gpu/drm/i915/intel_pipe_crc.c | 76 ++-
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e11d970cbcf..8607c1e9ed02 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1196,6 +1196,11 @@ enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_NONE,
INTEL_PIPE_CRC_SOURCE_PLANE1,
INTEL_PIPE_CRC_SOURCE_PLANE2,
+ INTEL_PIPE_CRC_SOURCE_PLANE3,
+ INTEL_PIPE_CRC_SOURCE_PLANE4,
+ INTEL_PIPE_CRC_SOURCE_PLANE5,
+ INTEL_PIPE_CRC_SOURCE_PLANE6,
+ INTEL_PIPE_CRC_SOURCE_PLANE7,
INTEL_PIPE_CRC_SOURCE_PIPE,
/* TV/DP on pre-gen5/vlv can't use the pipe source. */
INTEL_PIPE_CRC_SOURCE_TV,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0df8c6e76da7..5286536e9cb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4017,6 +4017,15 @@ enum {
/* Pipe A CRC regs */
#define _PIPE_CRC_CTL_A0x60050
#define PIPE_CRC_ENABLE (1 << 31)
+/* skl+ source selection */
+#define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28)
+#define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28)
+#define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
+#define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28)
+#define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28)
+#define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28)
+#define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28)
+#define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28)
/* ivb+ source selection */
#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 66bb7b031537..e521f82ba5d9 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -34,6 +34,11 @@ static const char * const pipe_crc_sources[] = {
[INTEL_PIPE_CRC_SOURCE_NONE] = "none",
[INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
[INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
+ [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
+ [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
+ [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
+ [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
+ [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
[INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
[INTEL_PIPE_CRC_SOURCE_TV] = "TV",
[INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
@@ -368,6 +373,50 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv,
return 0;
}
+static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
+ enum pipe pipe,
+ enum intel_pipe_crc_source *source,
+ uint32_t *val,
+ bool set_wa)
+{
+ if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
+ *source = INTEL_PIPE_CRC_SOURCE_PIPE;
+
+ switch (*source) {
+ case INTEL_PIPE_CRC_SOURCE_PLANE1:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PLANE2:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PLANE3:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PLANE4:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PLANE5:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PLANE6:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PLANE7:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_PIPE:
+ *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
+ break;
+ case INTEL_PIPE_CRC_SOURCE_NONE:
+ *val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source *source, u32 *val,
@@ -381,8 +430,10 @@ static i
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Disable PSR2 while getting pipe CRC
On Wed, 2019-02-13 at 18:02 -0800, José Roberto de Souza wrote:
> As stated in CRC_CTL spec, after PSR entry state CRC will not be
> calculated anymore what is not a problem as IGT tests do some screen
> change and then request the pipe CRC right after the change so PSR
> will go to idle state and only will entry again after at least 6
> idles frames.
>
> But for PSR2 it is more problematic as any change to the screen could
> trigger a selective/partial update causing the CRC value not to be
> calculated over the full frame.
Okay, that reasoning runs counter to my understanding. My understanding
is that the whole frame is fetched and processed at the pipe level but
the DDI sends selective blocks of pixels. So, if the CRC's are
calculated at the pipe level, the CRC should be for the full frame with
PSR2 having no effect? Checking bspec, I see there are DDI CRCs as
well, which should reflect the partial frame that PSR2 sends.
To get a better understanding, I'd like to know what the source for
mismatching CRCs is?
> So here it disables PSR2 and keep it disabled while user is
> requesting pipe CRC.
>
> BSpec: 7536
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pipe_crc.c | 10 ++
> drivers/gpu/drm/i915/intel_psr.c | 23 +++
> 4 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 17fe942eaafa..609e9c5bd453 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -520,6 +520,7 @@ struct i915_psr {
> bool sink_not_reliable;
> bool irq_aux_error;
> u16 su_x_granularity;
> + bool pipe_crc_enabled;
> };
>
> enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 3398b28c053b..40ce7a600585 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2103,6 +2103,7 @@ void intel_psr_short_pulse(struct intel_dp
> *intel_dp);
> int intel_psr_wait_for_idle(const struct intel_crtc_state
> *new_crtc_state,
> u32 *out_value);
> bool intel_psr_enabled(struct intel_dp *intel_dp);
> +void intel_psr_crc_prepare_or_finish(struct drm_i915_private
> *dev_priv, enum pipe pipe, bool prepare);
>
> /* intel_quirks.c */
> void intel_init_quirks(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index a8554dc4f196..5d8772399f60 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -583,6 +583,14 @@ int intel_crtc_verify_crc_source(struct drm_crtc
> *crtc, const char *source_name,
> return -EINVAL;
> }
>
> +static inline void intel_crtc_crc_prepare_or_finish(struct drm_crtc
> *crtc, bool prepare)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + intel_psr_crc_prepare_or_finish(dev_priv, intel_crtc->pipe,
> prepare);
> +}
> +
> int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char
> *source_name)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> @@ -609,6 +617,8 @@ int intel_crtc_set_crc_source(struct drm_crtc
> *crtc, const char *source_name)
> if (ret != 0)
> goto out;
>
> + intel_crtc_crc_prepare_or_finish(crtc, source !=
> INTEL_PIPE_CRC_SOURCE_NONE);
> +
> pipe_crc->source = source;
> I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
> POSTING_READ(PIPE_CRC_CTL(crtc->index));
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 08967836b48e..9c93138988aa 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -577,6 +577,9 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> + if (dev_priv->psr.pipe_crc_enabled)
> + return false;
> +
> return true;
> }
>
> @@ -1291,3 +1294,23 @@ bool intel_psr_enabled(struct intel_dp
> *intel_dp)
>
> return ret;
> }
> +
> +void intel_psr_crc_prepare_or_finish(struct drm_i915_private
> *dev_priv, enum pipe pipe, bool prepare)
> +{
> + bool fastset = false;
> +
> + if (!CAN_PSR(dev_priv))
> + return;
> +
> + mutex_lock(&dev_priv->psr.lock);
> +
> + if (dev_priv->psr.pipe == pipe) {
> + dev_priv->psr.pipe_crc_enabled = prepare;
> + fastset = !prepare || dev_priv->psr.psr2_enabled;
> + }
> +
> + mutex_unlock(&dev_priv->psr.lock);
> +
> + if (fastset)
> + intel_psr_fastset_force(dev_priv);
> +}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https:/
[Intel-gfx] [PATCH i-g-t] i915/gem_create: Verify that all new objects are clear
The kernel must not return stale information back to userspace when they
create a new object. For that purpose, we always clear objects on
creation, so verify that this is so.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
tests/i915/gem_create.c | 71 +
1 file changed, 71 insertions(+)
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index 25c5e8088..9de2263d5 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -44,6 +44,7 @@
#include
#include
#include
+#include
#include
@@ -141,6 +142,73 @@ static void invalid_nonaligned_size(int fd)
gem_close(fd, handle);
}
+static uint64_t get_npages(uint64_t *global, uint64_t npages)
+{
+ uint64_t try, old, max;
+
+ max = *global;
+ do {
+ old = max;
+ try = npages % (max / 2);
+ max -= try;
+ } while ((max = __sync_val_compare_and_swap(global, old, max)) != old);
+
+ return try;
+}
+
+struct thread_clear {
+ uint64_t max;
+ int timeout;
+ int i915;
+};
+
+static void *thread_clear(void *data)
+{
+ struct thread_clear *arg = data;
+ int i915 = arg->i915;
+
+ igt_until_timeout(arg->timeout) {
+ uint32_t handle;
+ uint64_t npages;
+
+ npages = random();
+ npages <<= 32;
+ npages |= random();
+ npages = get_npages(&arg->max, npages);
+
+ handle = gem_create(i915, npages << 12);
+ for (uint64_t page = 0; page < npages; page++) {
+ uint64_t x;
+
+ gem_read(i915, handle,
+ page % (4096 - sizeof(x)),
+ &x, sizeof(x));
+ igt_assert_eq_u64(x, 0);
+ }
+ gem_close(i915, handle);
+
+ __sync_add_and_fetch(&arg->max, npages);
+ }
+
+ return NULL;
+}
+
+static void always_clear(int i915, int timeout)
+{
+ struct thread_clear arg = {
+ .i915 = i915,
+ .timeout = timeout,
+ .max = intel_get_avail_ram_mb() << (20 - 12), /* in pages */
+ };
+ const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
+ pthread_t thread[ncpus];
+
+ for (int i = 0; i < ncpus; i++)
+ pthread_create(&thread[i], NULL, thread_clear, &arg);
+ for (int i = 0; i < ncpus; i++)
+ pthread_join(thread[i], NULL);
+}
+
igt_main
{
int fd = -1;
@@ -162,4 +230,7 @@ igt_main
igt_subtest("create-invalid-nonaligned")
invalid_nonaligned_size(fd);
+
+ igt_subtest("create-clear")
+ always_clear(fd, 30);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce memory region concept (including device local memory)
== Series Details == Series: Introduce memory region concept (including device local memory) URL : https://patchwork.freedesktop.org/series/56683/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: support 1G pages for the 48b PPGTT Okay! Commit: drm/i915: enable platform support for 1G pages Okay! Commit: drm/i915: buddy allocator +./include/linux/slab.h:664:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:664:13: warning: call with no type! Commit: drm/i915: introduce intel_memory_region -drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/region: support basic eviction -drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) Commit: drm/i915/region: support continuous allocations Okay! Commit: drm/i915/region: support volatile objects Okay! Commit: drm/i915: Add memory region information to device_info -drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3571:16: warning: expression using sizeof(void) Commit: drm/i915: support creating LMEM objects -drivers/gpu/drm/i915/selftests/../i915_drv.h:3571:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3576:16: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/lmem: add helper to get CPU visible pfn Okay! Commit: drm/i915/selftests: exercise writes to LMEM +drivers/gpu/drm/i915/selftests/intel_memory_region.c:507:22:expected unsigned int [noderef] [usertype] *base +drivers/gpu/drm/i915/selftests/intel_memory_region.c:507:22:got void * +drivers/gpu/drm/i915/selftests/intel_memory_region.c:507:22: warning: incorrect type in assignment (different address spaces) Commit: drm/i915/selftests: exercise huge-pages for LMEM +drivers/gpu/drm/i915/selftests/huge_pages.c:1147:22:expected unsigned int [noderef] [usertype] *base +drivers/gpu/drm/i915/selftests/huge_pages.c:1147:22:got void * +drivers/gpu/drm/i915/selftests/huge_pages.c:1147:22: warning: incorrect type in assignment (different address spaces) Commit: drm/i915: support object clearing via blitter engine -drivers/gpu/drm/i915/selftests/../i915_drv.h:3576:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3578:16: warning: expression using sizeof(void) Commit: drm/i915: introduce kernel blitter_context -drivers/gpu/drm/i915/selftests/../i915_drv.h:3578:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3580:16: warning: expression using sizeof(void) Commit: drm/i915: support copying objects via blitter engine -drivers/gpu/drm/i915/selftests/../i915_drv.h:3580:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3583:16: warning: expression using sizeof(void) Commit: drm/i915: support basic object migration -drivers/gpu/drm/i915/selftests/../i915_drv.h:3583:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3588:16: warning: expression using sizeof(void) Commit: drm/i915/lmem: support kernel mapping +drivers/gpu/drm/i915/i915_gem.c:2261:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/i915_gem.c:2261:42:got void *[assigned] ptr +drivers/gpu/drm/i915/i915_gem.c:2261:42: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/i915_gem.c:2645:51:expected void * +drivers/gpu/drm/i915/i915_gem.c:2645:51:got void [noderef] * +drivers/gpu/drm/i915/i915_gem.c:2645:51: warning: incorrect type in return expression (different address spaces) +drivers/gpu/drm/i915/i915_gem.c:2727:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/i915_gem.c:2727:42:got void *[assigned] ptr +drivers/gpu/drm/i915/i915_gem.c:2727:42: warning: incorrect type in argument 1 (different address spaces) -O:drivers/gpu/drm/i915/selftests/huge_pages.c:1147:22:expected unsigned int [noderef] [usertype] *base -O:drivers/gpu/drm/i915/selftests/huge_pages.c:1147:22:got void * -O:drivers/gpu/drm/i915/selftests/huge_pages.c:1147:22: warning: incorrect type in assignment (different address spaces) -O:drivers/gpu/drm/i915/selftests/intel_memory_region.c:507:22:expected unsigned int [noderef] [usertype] *base -O:drivers/gpu/drm/i915/selftests/intel_memory_region.c:507:22:got void * -O:drivers/gpu/drm/i915/selftests/intel_memory_region.c:5
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce memory region concept (including device local memory)
== Series Details ==
Series: Introduce memory region concept (including device local memory)
URL : https://patchwork.freedesktop.org/series/56683/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3a398101dfda drm/i915: support 1G pages for the 48b PPGTT
e99e4b7bc632 drm/i915: enable platform support for 1G pages
ee6706cbf465 drm/i915: buddy allocator
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#25:
new file mode 100644
-:30: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#30: FILE: drivers/gpu/drm/i915/i915_gem_buddy.c:1:
+/*
-:242: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#242: FILE: drivers/gpu/drm/i915/i915_gem_buddy.h:1:
+/*
-:336: ERROR:CODE_INDENT: code indent should use tabs where possible
#336: FILE: drivers/gpu/drm/i915/i915_gem_buddy.h:95:
+^I^I struct i915_gem_buddy_block *block)$
-:336: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#336: FILE: drivers/gpu/drm/i915/i915_gem_buddy.h:95:
+i915_gem_buddy_block_size(struct i915_gem_buddy_mm *mm,
+ struct i915_gem_buddy_block *block)
-:366: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#366: FILE: drivers/gpu/drm/i915/selftests/i915_gem_buddy.c:1:
+/*
-:511: ERROR:CODE_INDENT: code indent should use tabs where possible
#511: FILE: drivers/gpu/drm/i915/selftests/i915_gem_buddy.c:146:
+^I^I^I^I^Iorder);$
-:533: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#533: FILE: drivers/gpu/drm/i915/selftests/i915_gem_buddy.c:168:
+ pr_err("buddy_alloc offset misaligned,
offset=%llx, block_size=%llu\n",
+ offset, block_size);
total: 2 errors, 4 warnings, 2 checks, 544 lines checked
f88fcf2002da drm/i915: introduce intel_memory_region
-:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#68:
new file mode 100644
-:73: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#73: FILE: drivers/gpu/drm/i915/intel_memory_region.c:1:
+/*
-:104: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#104: FILE: drivers/gpu/drm/i915/intel_memory_region.c:32:
+{
+
-:311: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#311: FILE: drivers/gpu/drm/i915/intel_memory_region.h:1:
+/*
-:362: WARNING:TYPO_SPELLING: 'UKNOWN' may be misspelled - perhaps 'UNKNOWN'?
#362: FILE: drivers/gpu/drm/i915/intel_memory_region.h:52:
+ INTEL_MEMORY_UKNOWN, /* Should be last */
-:371: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'r' may be better as '(r)' to
avoid precedence issues
#371: FILE: drivers/gpu/drm/i915/intel_memory_region.h:61:
+#define MEMORY_TYPE_FROM_REGION(r) (ilog2(r >> INTEL_MEMORY_TYPE_SHIFT))
-:372: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'r' may be better as '(r)' to
avoid precedence issues
#372: FILE: drivers/gpu/drm/i915/intel_memory_region.h:62:
+#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2(r & 0x))
-:386: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#386: FILE: drivers/gpu/drm/i915/intel_memory_region.h:76:
+ int (*init)(struct intel_memory_region *);
-:387: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#387: FILE: drivers/gpu/drm/i915/intel_memory_region.h:77:
+ void (*release)(struct intel_memory_region *);
-:389: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#389: FILE: drivers/gpu/drm/i915/intel_memory_region.h:79:
+ struct drm_i915_gem_object *
-:389: WARNING:FUNCTION_ARGUMENTS: function definition argument
'resource_size_t' should also have an identifier name
#389: FILE: drivers/gpu/drm/i915/intel_memory_region.h:79:
+ struct drm_i915_gem_object *
-:389: WARNING:FUNCTION_ARGUMENTS: function definition argument 'unsigned int'
should also have an identifier name
#389: FILE: drivers/gpu/drm/i915/intel_memory_region.h:79:
+ struct drm_i915_gem_object *
-:404: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#404: FILE: drivers/gpu/drm/i915/intel_memory_region.h:94:
+ struct mutex mm_lock;
-:445: CHECK:LINE_SPACING: Please don't use multiple blank lines
#445: FILE: drivers/gpu/drm/i915/selftests/huge_pages.c:461:
+
-:475: ERROR:CODE_INDENT: code indent should use tabs where possible
#475: FILE: drivers/gpu/drm/i915/selftests/huge_pages.c:491:
+^I^I&obj->memory_region->region.start);$
-:551: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#551: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:1:
+/*
-:634: WARNI
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Replace the fixed vblank evasion with a ewma of past update times
== Series Details ==
Series: drm/i915: Replace the fixed vblank evasion with a ewma of past update
times
URL : https://patchwork.freedesktop.org/series/56680/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5601 -> Patchwork_1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56680/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_1 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6700k2: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@gem_exec_suspend@basic-s3:
- {fi-icl-u3}:FAIL [fdo#103375] -> PASS
* igt@gem_mmap_gtt@basic-small-bo:
- {fi-icl-u3}:DMESG-WARN [fdo#107724] -> PASS
* igt@i915_selftest@live_workarounds:
- {fi-icl-u2}:INCOMPLETE [fdo#109626] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-ivb-3520m: FAIL [fdo#103375] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: FAIL [fdo#108800] -> PASS
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]
-> DMESG-FAIL [fdo#105079]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109226]: https://bugs.freedesktop.org/show_bug.cgi?id=109226
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109626]: https://bugs.freedesktop.org/show_bug.cgi?id=109626
Participating hosts (50 -> 42)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-gdg-551 fi-pnv-d510 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5601 -> Patchwork_1
CI_DRM_5601: 7977cc73f17770b9b1ed8baff66a8c9fd681d6a8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4827: 395eaffd7e1390c9d6043c2980dc14ce3e08b154 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_1: f0b46f774f5ee1a411b9b2e769abb712343c995b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f0b46f774f5e drm/i915: Replace the fixed vblank evasion with a ewma of past
update times
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Defer application of request banning to submission (rev2)
== Series Details ==
Series: drm/i915: Defer application of request banning to submission (rev2)
URL : https://patchwork.freedesktop.org/series/56626/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5599_full -> Patchwork_12217_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_12217_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12217_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12217_full:
### IGT changes ###
Warnings
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-iclb: FAIL [fdo#108948] -> INCOMPLETE
* igt@prime_nv_api@i915_self_import_to_different_fd:
- shard-iclb: {SKIP} [fdo#109291] -> INCOMPLETE
Known issues
Here are the changes found in Patchwork_12217_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_linear_blits@interruptible:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +2
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-apl: PASS -> FAIL [fdo#109350]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-iclb: PASS -> FAIL [fdo#105363]
* igt@kms_flip@flip-vs-wf_vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#100368]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +1
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-glk: PASS -> FAIL [fdo#108948]
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +5
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724]
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> FAIL [fdo#100047]
- shard-kbl: NOTRUN -> FAIL [fdo#100047]
* igt@pm_rpm@gem-pread:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] +1
Possible fixes
* igt@gem_eio@reset-stress:
- shard-snb: FAIL [fdo#107799] -> PASS
* igt@i915_selftest@live_workarounds:
- shard-iclb: DMESG-FAIL [fdo#108954] -> PASS
* igt@kms_color@pipe-a-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-iclb: FAIL [fdo#103167] -> PASS
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-iclb: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Replace the fixed vblank evasion with a ewma of past update times
== Series Details == Series: drm/i915: Replace the fixed vblank evasion with a ewma of past update times URL : https://patchwork.freedesktop.org/series/56680/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Replace the fixed vblank evasion with a ewma of past update times +drivers/gpu/drm/i915/intel_sprite.c:88:19: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Gen8+ GPU Watchdog Reset Support (rev2)
== Series Details == Series: Gen8+ GPU Watchdog Reset Support (rev2) URL : https://patchwork.freedesktop.org/series/56587/ State : failure == Summary == Applying: drm/i915: Add engine reset count in get-reset-stats ioctl Applying: drm/i915: Watchdog timeout: IRQ handler for gen8+ Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_drv.h M drivers/gpu/drm/i915/i915_gpu_error.h M drivers/gpu/drm/i915/i915_irq.c M drivers/gpu/drm/i915/i915_reg.h M drivers/gpu/drm/i915/intel_engine_cs.c M drivers/gpu/drm/i915/intel_hangcheck.c M drivers/gpu/drm/i915/intel_lrc.c M drivers/gpu/drm/i915/intel_ringbuffer.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_ringbuffer.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_ringbuffer.h Auto-merging drivers/gpu/drm/i915/intel_lrc.c Auto-merging drivers/gpu/drm/i915/intel_hangcheck.c Auto-merging drivers/gpu/drm/i915/intel_engine_cs.c Auto-merging drivers/gpu/drm/i915/i915_reg.h Auto-merging drivers/gpu/drm/i915/i915_irq.c Auto-merging drivers/gpu/drm/i915/i915_gpu_error.h Auto-merging drivers/gpu/drm/i915/i915_drv.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915: Watchdog timeout: IRQ handler for gen8+ When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset
== Series Details ==
Series: series starting with [1/4] drm/i915/psr: Only lookup for enabled CRTCs
when forcing a fastset
URL : https://patchwork.freedesktop.org/series/56647/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5601 -> Patchwork_12220
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56647/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12220 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@gem_exec_suspend@basic-s3:
- {fi-icl-u3}:FAIL [fdo#103375] -> PASS
* igt@gem_mmap_gtt@basic-small-bo:
- {fi-icl-u3}:DMESG-WARN [fdo#107724] -> PASS
* igt@i915_module_load@reload:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6700hq: DMESG-WARN [fdo#105998] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-ivb-3520m: FAIL [fdo#103375] -> PASS
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]
-> DMESG-FAIL [fdo#105079]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (50 -> 42)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-glk-j4005 fi-gdg-551 fi-icl-y fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5601 -> Patchwork_12220
CI_DRM_5601: 7977cc73f17770b9b1ed8baff66a8c9fd681d6a8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4827: 395eaffd7e1390c9d6043c2980dc14ce3e08b154 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12220: b912f44f1bf4d36de451e198a419b937f0637cde @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b912f44f1bf4 drm/i915: Enable PSR2 by default
727cc543561b drm/i915/psr: Remove PSR2 FIXME
441f8b87c393 drm/i915: Disable PSR2 while getting pipe CRC
e53ec9ed5dc6 drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12220/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_create: Verify that all new objects are clear
The kernel must not return stale information back to userspace when they
create a new object. For that purpose, we always clear objects on
creation, so verify that this is so.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
tests/i915/gem_create.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index 25c5e8088..9d1a4af4f 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -141,6 +141,32 @@ static void invalid_nonaligned_size(int fd)
gem_close(fd, handle);
}
+static void always_clear(int i915, int timeout)
+{
+ uint64_t max = intel_get_avail_ram_mb() << (20 - 12); /* in pages */
+
+ igt_until_timeout(timeout) {
+ uint64_t npages;
+ uint32_t handle;
+
+ npages = random();
+ npages <<= 32;
+ npages |= random();
+ npages %= max;
+
+ handle = gem_create(i915, npages << 12);
+ for (uint64_t page = 0; page < npages; page++) {
+ uint64_t x;
+
+ gem_read(i915, handle,
+page % (4096 - sizeof(x)),
+&x, sizeof(x));
+ igt_assert_eq_u64(x, 0);
+ }
+ gem_close(i915, handle);
+ }
+}
+
igt_main
{
int fd = -1;
@@ -162,4 +188,7 @@ igt_main
igt_subtest("create-invalid-nonaligned")
invalid_nonaligned_size(fd);
+
+ igt_subtest("create-clear")
+ always_clear(fd, 30);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] Revert "drm/i915: W/A for underruns with WM1+ disabled on icl"
== Series Details ==
Series: series starting with [1/3] Revert "drm/i915: W/A for underruns with
WM1+ disabled on icl"
URL : https://patchwork.freedesktop.org/series/56621/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5599_full -> Patchwork_12216_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12216_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl: PASS -> FAIL [fdo#103232] +2
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: PASS -> FAIL [fdo#105767] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724]
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> FAIL [fdo#100047]
- shard-kbl: NOTRUN -> FAIL [fdo#100047]
* igt@perf@short-reads:
- shard-kbl: PASS -> FAIL [fdo#103183]
* igt@pm_rpm@sysfs-read:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724]
Possible fixes
* igt@gem_eio@reset-stress:
- shard-snb: FAIL [fdo#107799] -> PASS
* igt@i915_selftest@live_workarounds:
- shard-iclb: DMESG-FAIL [fdo#108954] -> PASS
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +3
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-iclb: FAIL [fdo#103167] -> PASS
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-iclb: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@pm_rpm@gem-evict-pwrite:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS +5
* igt@pm_rpm@legacy-planes:
- shard-iclb: DMESG-WARN [fdo#107732] -> PASS
* igt@tools_test@tools_test:
- shard-iclb: {SKIP} [fdo#109352] -> PASS
Warnings
* igt@i915_selftest@live_contexts:
- shard-iclb: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108569] /
[fdo#109226]
* igt@i915_suspend@shrink:
- shard-apl: INCOMPLETE [fdo#103927] / [fdo#106886] -> DMESG-WARN
[fdo#107886] / [fdo#109244]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103232]: https://bugs.free
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset
== Series Details == Series: series starting with [1/4] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset URL : https://patchwork.freedesktop.org/series/56647/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset Okay! Commit: drm/i915: Disable PSR2 while getting pipe CRC -drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) Commit: drm/i915/psr: Remove PSR2 FIXME Okay! Commit: drm/i915: Enable PSR2 by default Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset
== Series Details == Series: series starting with [1/4] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset URL : https://patchwork.freedesktop.org/series/56647/ State : warning == Summary == $ dim checkpatch origin/drm-tip e53ec9ed5dc6 drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset 441f8b87c393 drm/i915: Disable PSR2 while getting pipe CRC -:48: WARNING:LONG_LINE: line over 100 characters #48: FILE: drivers/gpu/drm/i915/intel_drv.h:2106: +void intel_psr_crc_prepare_or_finish(struct drm_i915_private *dev_priv, enum pipe pipe, bool prepare); -:99: WARNING:LONG_LINE: line over 100 characters #99: FILE: drivers/gpu/drm/i915/intel_psr.c:1298: +void intel_psr_crc_prepare_or_finish(struct drm_i915_private *dev_priv, enum pipe pipe, bool prepare) total: 0 errors, 2 warnings, 0 checks, 68 lines checked 727cc543561b drm/i915/psr: Remove PSR2 FIXME b912f44f1bf4 drm/i915: Enable PSR2 by default ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Only try to stop engines after a failed reset
== Series Details ==
Series: drm/i915: Only try to stop engines after a failed reset
URL : https://patchwork.freedesktop.org/series/56636/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5601 -> Patchwork_12219
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56636/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12219:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_hangcheck:
- {fi-whl-u}: PASS -> INCOMPLETE
Known issues
Here are the changes found in Patchwork_12219 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@i915_selftest@live_hangcheck:
- fi-kbl-r: PASS -> INCOMPLETE [fdo#108744]
- fi-kbl-8809g: NOTRUN -> INCOMPLETE [fdo#108744]
Possible fixes
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@gem_exec_suspend@basic-s3:
- {fi-icl-u3}:FAIL [fdo#103375] -> PASS
* igt@gem_mmap_gtt@basic-small-bo:
- {fi-icl-u3}:DMESG-WARN [fdo#107724] -> PASS
* igt@i915_module_load@reload:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_selftest@live_workarounds:
- {fi-icl-u2}:INCOMPLETE [fdo#109626] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-ivb-3520m: FAIL [fdo#103375] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: FAIL [fdo#108800] -> PASS
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]
-> DMESG-FAIL [fdo#105079]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109226]: https://bugs.freedesktop.org/show_bug.cgi?id=109226
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109567]: https://bugs.freedesktop.org/show_bug.cgi?id=109567
[fdo#109626]: https://bugs.freedesktop.org/show_bug.cgi?id=109626
Participating hosts (50 -> 38)
--
Missing(12): fi-kbl-soraka fi-ilk-m540 fi-byt-j1900 fi-skl-guc
fi-byt-squawks fi-bsw-cyan fi-glk-j4005 fi-gdg-551 fi-pnv-d510 fi-byt-clapper
fi-skl-6700hq fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5601 -> Patchwork_12219
CI_DRM_5601: 7977cc73f17770b9b1ed8baff66a8c9fd681d6a8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4827: 395eaffd7e1390c9d6043c2980dc14ce3e08b154 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12219: f537750f58d12fe4314390125c387126630a89c7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f537750f58d1 drm/i915: Only try to stop engines after a failed reset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12219/
___
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Re: [Intel-gfx] [RFC PATCH 34/42] drm/i915/query: Expose memory regions through the query uAPI
Quoting Chris Wilson (2019-02-14 16:31:13)
> Quoting Matthew Auld (2019-02-14 14:57:32)
> > int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file
> > *file)
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 26d2274b5d2b..5a102a5cb415 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1744,6 +1744,7 @@ struct drm_i915_perf_oa_config {
> > struct drm_i915_query_item {
> > __u64 query_id;
> > #define DRM_I915_QUERY_TOPOLOGY_INFO1
> > +#define DRM_I915_QUERY_MEMREGION_INFO 3
>
> Ahem.
>
> > /*
> > * When set to zero by userspace, this is filled with the size of
> > the
> > @@ -1832,7 +1833,6 @@ struct drm_i915_query_topology_info {
> > * Offset in data[] at which the EU masks are stored.
> > */
> > __u16 eu_offset;
> > -
> > /*
> > * Stride at which each of the EU masks for each subslice are
> > stored.
> > */
> > @@ -1841,6 +1841,44 @@ struct drm_i915_query_topology_info {
> > __u8 data[];
> > };
> >
> > +struct drm_i915_memory_region_info {
> > +
> > + /** Base type of a region
> > +*/
> > +#define I915_SYSTEM_MEMORY 0
> > +#define I915_DEVICE_MEMORY 1
> > +
> > + /** The region id is encoded in a layout which makes it possible to
> > +* retrieve the following information:
> > +*
> > +* Base type: log2(ID >> 16)
> > +* Instance: log2(ID & 0x)
> > +*/
> > + __u32 id;
> > +
> > + /** Reserved field. MBZ */
> > + __u32 rsvd0;
> > +
> > + /** Unused for now. MBZ */
> > + __u64 flags;
> > +
> > + __u64 size;
> > +
> > + /** Reserved fields must be cleared to zero. */
> > + __u64 rsvd1[4];
> > +};
>
> If you were to apply this to stolen memory as an example, can you spot
> how much information is missing?
>
> Userspace would need to know total size, largest allocation chunk (i.e
> largest object), rough estimate of availability, and most importantly a
> list of API that is not allowed (such as CPU mmap, fencing). There's
> without a doubt more that would be needed to actually wire it up to Vk.
Cross-process/ppgtt and cross-device sharing for example...
-Chris
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Re: [Intel-gfx] [RFC PATCH 34/42] drm/i915/query: Expose memory regions through the query uAPI
Quoting Matthew Auld (2019-02-14 14:57:32)
> int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file
> *file)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 26d2274b5d2b..5a102a5cb415 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1744,6 +1744,7 @@ struct drm_i915_perf_oa_config {
> struct drm_i915_query_item {
> __u64 query_id;
> #define DRM_I915_QUERY_TOPOLOGY_INFO1
> +#define DRM_I915_QUERY_MEMREGION_INFO 3
Ahem.
> /*
> * When set to zero by userspace, this is filled with the size of the
> @@ -1832,7 +1833,6 @@ struct drm_i915_query_topology_info {
> * Offset in data[] at which the EU masks are stored.
> */
> __u16 eu_offset;
> -
> /*
> * Stride at which each of the EU masks for each subslice are stored.
> */
> @@ -1841,6 +1841,44 @@ struct drm_i915_query_topology_info {
> __u8 data[];
> };
>
> +struct drm_i915_memory_region_info {
> +
> + /** Base type of a region
> +*/
> +#define I915_SYSTEM_MEMORY 0
> +#define I915_DEVICE_MEMORY 1
> +
> + /** The region id is encoded in a layout which makes it possible to
> +* retrieve the following information:
> +*
> +* Base type: log2(ID >> 16)
> +* Instance: log2(ID & 0x)
> +*/
> + __u32 id;
> +
> + /** Reserved field. MBZ */
> + __u32 rsvd0;
> +
> + /** Unused for now. MBZ */
> + __u64 flags;
> +
> + __u64 size;
> +
> + /** Reserved fields must be cleared to zero. */
> + __u64 rsvd1[4];
> +};
If you were to apply this to stolen memory as an example, can you spot
how much information is missing?
Userspace would need to know total size, largest allocation chunk (i.e
largest object), rough estimate of availability, and most importantly a
list of API that is not allowed (such as CPU mmap, fencing). There's
without a doubt more that would be needed to actually wire it up to Vk.
-Chris
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Re: [Intel-gfx] [RFC PATCH 42/42] HAX drm/i915/lmem: default userspace allocations to LMEM
Quoting Matthew Auld (2019-02-14 14:57:40) > Hack patch to default all userspace allocations to LMEM. Useful for > testing purposes. One caveat to note is that userspace assumes objects start idle in .write=CPU. That assumption may very well be put to the test, and go unnoticed for quite a while... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 35/42] drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION
Quoting Matthew Auld (2019-02-14 14:57:33) > From: Abdiel Janulgue > > This call will specify which memory region an object should be placed. > > Note that changing the object's backing storage should be immediately > done after an object is created or if it's not yet in use, otherwise > this will fail on a busy object. We already have a generic object SETPARAM, GETPARAM. The idea was to extend CONTEXT_SETPARAM/GETPARAM into OBJECT_SETPARAM/GETPARAM by splitting u64 parameter into (u32 object_class, u32 parameter). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 42/42] HAX drm/i915/lmem: default userspace allocations to LMEM
Quoting Matthew Auld (2019-02-14 14:57:40)
> Hack patch to default all userspace allocations to LMEM. Useful for
> testing purposes.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> drivers/gpu/drm/i915/i915_gem.c | 45 +++--
> 1 file changed, 43 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 3c86909d55b9..bd857f477ef9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -641,7 +641,8 @@ i915_gem_create(struct drm_file *file,
> u32 *handle_p)
> {
> struct drm_i915_gem_object *obj;
> - int ret;
> + intel_wakeref_t wakeref;
> + int ret = 0;
> u32 handle;
>
> size = roundup(size, PAGE_SIZE);
> @@ -649,10 +650,50 @@ i915_gem_create(struct drm_file *file,
> return -EINVAL;
>
> /* Allocate the new object */
> - obj = i915_gem_object_create(dev_priv, size);
> + if (HAS_LMEM(dev_priv))
> + obj = i915_gem_object_create_lmem(dev_priv, size, 0);
> + else
> + obj = i915_gem_object_create(dev_priv, size);
> if (IS_ERR(obj))
> return PTR_ERR(obj);
>
> + if (i915_gem_object_is_lmem(obj)) {
> + struct i915_gem_context *ctx;
> +
> + /* XXX: we should prob use the blitter context for this? */
Or the kernel_context which is setup for emitting without taking
struct_mutex...
-Chris
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Re: [Intel-gfx] [RFC PATCH 29/42] drm/i915: Set correct vmf source pages for gem objects
Quoting Matthew Auld (2019-02-14 14:57:27)
> +int i915_gem_vmf_fill_pages_cpu(struct drm_i915_gem_object *obj,
> +struct vm_fault *vmf,
> +pgoff_t page_offset)
> +{
> + struct vm_area_struct *area = vmf->vma;
> + struct drm_device *dev = obj->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct page *page;
> + unsigned long pfn;
> + vm_fault_t vmf_ret;
> + pgoff_t pg_off = (vmf->address - area->vm_start) >> PAGE_SHIFT;
> +
> + if (HAS_MAPPABLE_APERTURE(dev_priv))
> + return __vmf_fill_pages_gtt(obj, vmf, page_offset);
> +
> + page = i915_gem_object_get_page(obj, pg_off);
> + pfn = page_to_pfn(page);
> +
> + vmf_ret = vmf_insert_mixed(area, vmf->address,
> + __pfn_to_pfn_t(pfn, PFN_DEV));
> + if (vmf_ret & VM_FAULT_ERROR)
> + return vm_fault_to_errno(vmf_ret, 0);
> +
> + if (!obj->userfault_count++)
> + list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
> +
> + GEM_BUG_ON(!obj->userfault_count);
What are you using the GGTT fence tracking for?
-Chris
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Re: [Intel-gfx] [RFC PATCH 31/42] drm/i915: cpu-map based dumb buffers
Quoting Matthew Auld (2019-02-14 14:57:29) > From: Abdiel Janulgue > > If there is no aperture we can't use map_gtt to map dumb buffers, so we > need a cpu-map based path to do it. We prefer map_gtt on platforms that > do have aperture. This is very hard as a standalone patch to see if you the semantics for dumb buffers correct. Is is coherent for starters? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 30/42] drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET
Quoting Matthew Auld (2019-02-14 14:57:28)
> @@ -157,6 +163,10 @@ struct drm_i915_gem_object {
> unsigned int userfault_count;
> struct list_head userfault_link;
>
> + enum i915_cpu_mmap_origin_type mmap_origin;
> + atomic_t mmap_count;
> + u64 mmap_flags;
These flags must be per-mmap instance, userspace does try to keep
several different types of mmaps active.
-Chris
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Re: [Intel-gfx] [RFC PATCH 28/42] drm/i915: Split out GTT fault handler to make it generic
Quoting Matthew Auld (2019-02-14 14:57:26)
> From: Abdiel Janulgue
>
> In preparation for using multiple page-fault handlers depending
> on the object's backing storage.
>
> Signed-off-by: Abdiel Janulgue
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_gem.c | 112 +++-
> 1 file changed, 66 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e59f38e00f0d..95e31529a738 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1782,11 +1782,7 @@ compute_partial_view(const struct drm_i915_gem_object
> *obj,
> }
>
> /**
> - * i915_gem_fault - fault a page into the GTT
> - * @vmf: fault info
> - *
> - * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
> - * from userspace. The fault handler takes care of binding the object to
> + * The GTT fill pages handler takes care of binding the object to
> * the GTT (if needed), allocating and programming a fence register (again,
> * only if needed based on whether the old reg is still valid or the object
> * is tiled) and inserting a new PTE into the faulting process.
> @@ -1799,57 +1795,20 @@ compute_partial_view(const struct drm_i915_gem_object
> *obj,
> * The current feature set supported by i915_gem_fault() and thus GTT mmaps
> * is exposed via I915_PARAM_MMAP_GTT_VERSION (see
> i915_gem_mmap_gtt_version).
> */
> -vm_fault_t i915_gem_fault(struct vm_fault *vmf)
> +static int __vmf_fill_pages_gtt(struct drm_i915_gem_object *obj,
> + struct vm_fault *vmf,
> + pgoff_t page_offset)
> {
> #define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
> struct vm_area_struct *area = vmf->vma;
> - struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
> struct drm_device *dev = obj->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct i915_ggtt *ggtt = &dev_priv->ggtt;
> bool write = area->vm_flags & VM_WRITE;
> - intel_wakeref_t wakeref;
> struct i915_vma *vma;
> - pgoff_t page_offset;
> int srcu;
> int ret;
>
> - /* Sanity check that we allow writing into this object */
> - if (i915_gem_object_is_readonly(obj) && write)
> - return VM_FAULT_SIGBUS;
> -
> - /* We don't use vmf->pgoff since that has the fake offset */
> - page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
> -
> - trace_i915_gem_object_fault(obj, page_offset, true, write);
> -
> - /* Try to flush the object off the GPU first without holding the lock.
> -* Upon acquiring the lock, we will perform our sanity checks and then
> -* repeat the flush holding the lock in the normal manner to catch
> cases
> -* where we are gazumped.
> -*/
> - ret = i915_gem_object_wait(obj,
> - I915_WAIT_INTERRUPTIBLE,
> - MAX_SCHEDULE_TIMEOUT);
> - if (ret)
> - goto err;
> -
> - ret = i915_gem_object_pin_pages(obj);
> - if (ret)
> - goto err;
> -
> - wakeref = intel_runtime_pm_get(dev_priv);
> -
> - ret = i915_mutex_lock_interruptible(dev);
> - if (ret)
> - goto err_rpm;
> -
> - /* Access to snoopable pages through the GTT is incoherent. */
> - if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
> - ret = -EFAULT;
> - goto err_unlock;
> - }
> -
> /* Now pin it into the GTT as needed */
> vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
>PIN_MAPPABLE |
> @@ -1880,7 +1839,7 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
> }
> if (IS_ERR(vma)) {
> ret = PTR_ERR(vma);
> - goto err_unlock;
> + return ret;
> }
>
> ret = i915_gem_object_set_to_gtt_domain(obj, write);
> @@ -1920,6 +1879,67 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
> i915_vma_unpin_fence(vma);
> err_unpin:
> __i915_vma_unpin(vma);
> +
> + return ret;
> +}
> +
> +/**
> + * i915_gem_fault - fault a page into the memory
> + * @vmf: fault info
> + *
> + * The fault handler is set up by drm_gem_mmap() when mmap_offset is called
> on
> + * an object from userspace. The missing pages are setup by an object's
> + * vmf_fill_pages pages handler, depending on it's backing storage.
> + */
> +vm_fault_t i915_gem_fault(struct vm_fault *vmf)
> +{
> + struct vm_area_struct *area = vmf->vma;
> + struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
> + struct drm_device *dev = obj->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + intel_wakeref_t wakeref;
> + bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
> +
Re: [Intel-gfx] [RFC PATCH 26/42] drm/i915: error capture with no ggtt slot
Quoting Matthew Auld (2019-02-14 14:57:24)
> + void *s;
> + struct page *page;
> +
> + for_each_sgt_page(page, iter, vma->pages) {
> + s = kmap_atomic(page);
These pages are not coherent, so missing the point of using UC/WC access
to get what the GPU saw and not what the CPU last speculated.
Typically, and historically, we would use clflush before after.
Just be careful not to use drm_clflush as that invokes wbinvd via
on_each_cpu and is therefore illegal.
Alternatively would be to kmap them as WC.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Always use an active engine while resetting
== Series Details ==
Series: drm/i915/selftests: Always use an active engine while resetting
URL : https://patchwork.freedesktop.org/series/56633/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5601 -> Patchwork_12218
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56633/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12218 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
Possible fixes
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@gem_exec_suspend@basic-s3:
- {fi-icl-u3}:FAIL [fdo#103375] -> PASS
* igt@gem_mmap_gtt@basic-small-bo:
- {fi-icl-u3}:DMESG-WARN [fdo#107724] -> PASS
* igt@i915_module_load@reload:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_selftest@live_workarounds:
- {fi-icl-u2}:INCOMPLETE [fdo#109626] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-ivb-3520m: FAIL [fdo#103375] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: FAIL [fdo#108800] -> PASS
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]
-> DMESG-FAIL [fdo#105079]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109626]: https://bugs.freedesktop.org/show_bug.cgi?id=109626
Participating hosts (50 -> 42)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-ilk-650 fi-icl-y fi-bdw-samus fi-snb-2600
Build changes
-
* Linux: CI_DRM_5601 -> Patchwork_12218
CI_DRM_5601: 7977cc73f17770b9b1ed8baff66a8c9fd681d6a8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4827: 395eaffd7e1390c9d6043c2980dc14ce3e08b154 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12218: 716e071ecb2e9396d92231555761968be282621d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
716e071ecb2e drm/i915/selftests: Always use an active engine while resetting
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12218/
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Re: [Intel-gfx] [RFC PATCH 20/42] drm/i915/lmem: support pread
Quoting Matthew Auld (2019-02-14 14:57:18) > + ret = mutex_lock_interruptible(&i915->drm.struct_mutex); > + if (ret) > + goto out_unpin; > + > + wakeref = intel_runtime_pm_get(i915); But why wakeref in the middle? > + > + ret = i915_gem_object_set_to_wc_domain(obj, false); > + mutex_unlock(&i915->drm.struct_mutex); Anyway, this is a disaster that needs fixing before we make it worse. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 18/42] drm/i915/lmem: support CPU relocations
Quoting Matthew Auld (2019-02-14 14:57:16) > We need to support doing relocations from the CPU when dealing with LMEM > objects. Why not just use the GPU reloc? Please do explain the relative merits. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Bump vblank evasion time for seamless updates
== Series Details ==
Series: drm/i915/psr: Bump vblank evasion time for seamless updates
URL : https://patchwork.freedesktop.org/series/56618/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5599_full -> Patchwork_12215_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12215_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@runner@aborted}:
- shard-iclb: ( 17 FAIL ) [fdo#108654] / [fdo#108756] /
[fdo#109624] -> ( 16 FAIL ) [fdo#109624]
Known issues
Here are the changes found in Patchwork_12215_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@unwedge-stress:
- shard-snb: PASS -> FAIL [fdo#107799]
* igt@i915_selftest@live_hangcheck:
- shard-iclb: PASS -> INCOMPLETE [fdo#108569]
* igt@i915_suspend@debugfs-reader:
- shard-iclb: NOTRUN -> FAIL [fdo#103375] +2
* igt@i915_suspend@forcewake:
- shard-iclb: PASS -> FAIL [fdo#103375] +3
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled:
- shard-glk: PASS -> FAIL [fdo#103184]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167]
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166]
- shard-apl: PASS -> FAIL [fdo#103166]
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724]
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> FAIL [fdo#100047]
- shard-kbl: NOTRUN -> FAIL [fdo#100047]
* igt@pm_rpm@gem-pread:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724]
Possible fixes
* igt@gem_eio@reset-stress:
- shard-snb: FAIL [fdo#107799] -> PASS
* igt@i915_selftest@live_workarounds:
- shard-iclb: DMESG-FAIL [fdo#108954] -> PASS
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-iclb: FAIL [fdo#103167] -> PASS
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-glk: FAIL [fdo#108948] -> PASS
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-iclb: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@pm_rpm@gem-evict-pwrite:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS +5
* igt@pm_rpm@legacy-planes:
- shard-iclb: DMESG-WARN [fdo#107732] -> PASS
* igt@tools_test@tools_test:
- shard-iclb: {SKIP} [fdo#109352] -> PASS
Warnings
* igt@i915_suspend@shrink:
- shard-apl: INCOMPLE
Re: [Intel-gfx] [RFC PATCH 14/42] drm/i915: introduce kernel blitter_context
Quoting Matthew Auld (2019-02-14 14:57:12) > We may be without a context to perform various internal blitter > operations, for example when performing object migration. Piggybacking > off the kernel_context is probably a bad idea, since it has other uses. Explain why it is a worse idea than creating yet another kernel context to manage. The fact that we may use it for blitting makes the kernel context even more viable for its other jobs (such as knowing we've flushed off user contexts). Convince me that we really need more than one internal context; and that blitting especially needs its own. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 13/42] drm/i915: support object clearing via blitter engine
Quoting Matthew Auld (2019-02-14 14:57:11)
> +static int i915_gem_object_fill_blt(struct i915_gem_context *ctx,
> + struct drm_i915_gem_object *obj,
> + u32 value)
> +{
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> + struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->vm :
> &i915->ggtt.vm;
> + struct i915_vma *vma;
> + int err;
> +
> + lockdep_assert_held(&i915->drm.struct_mutex);
> +
> + vma = i915_vma_instance(obj, vm, NULL);
> + if (IS_ERR(vma))
> + return PTR_ERR(vma);
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_USER);
> + if (err) {
> + i915_vma_close(vma);
> + return err;
> + }
> +
> + err = i915_gem_fill_blt(ctx, vma, value);
> + i915_vma_unpin(vma);
> + if (err)
> + return err;
> +
> + return i915_gem_object_wait(obj,
> + I915_WAIT_LOCKED |
> + I915_WAIT_ALL,
> + MAX_SCHEDULE_TIMEOUT);
Oh no, don't even start by making this synchronous.
-Chris
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Re: [Intel-gfx] [RFC PATCH 13/42] drm/i915: support object clearing via blitter engine
Quoting Matthew Auld (2019-02-14 14:57:11)
> +static struct i915_vma *
> +__i915_gem_fill_blt(struct i915_vma *vma, u32 value)
> +{
> + struct drm_i915_private *i915 = to_i915(vma->obj->base.dev);
> + const int gen = INTEL_GEN(i915);
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *batch;
> + u32 *cmd;
> + int err;
> +
> + obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
> + if (IS_ERR(obj))
> + return ERR_CAST(obj);
> +
> + cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + if (IS_ERR(cmd)) {
> + err = PTR_ERR(cmd);
> + goto err;
> + }
> +
> + if (gen >= 8) {
> + *cmd++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA;
> + *cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
> + *cmd++ = 0;
> + *cmd++ = vma->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE
> / 4;
> + *cmd++ = lower_32_bits(vma->node.start);
> + *cmd++ = upper_32_bits(vma->node.start);
> + *cmd++ = value;
> + *cmd++ = MI_NOOP;
> + } else {
> + *cmd++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
> + *cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
> + *cmd++ = vma->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE;
> + *cmd++ = vma->node.start;
> + *cmd++ = value;
> + *cmd++ = MI_NOOP;
> + }
> +
> + *cmd = MI_BATCH_BUFFER_END;
Why did you create a batch? Just issue the command from inside the
request.
-Chris
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Re: [Intel-gfx] [RFC PATCH 13/42] drm/i915: support object clearing via blitter engine
Quoting Matthew Auld (2019-02-14 14:57:11) > diff --git a/drivers/gpu/drm/i915/intel_gpu_commands.h > b/drivers/gpu/drm/i915/intel_gpu_commands.h > index b96a31bc1080..f74ff1d095c2 100644 > --- a/drivers/gpu/drm/i915/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/intel_gpu_commands.h > @@ -175,6 +175,7 @@ > #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) > > #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) > +#define XY_COLOR_BLT_CMD (2<<29 | 0x50<<22 | (7-2)) Remove the dword lengths here. The XY commands are not gen8 specific, and construction is much neater if we just add the pktlen on writing the cmd. > #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) > #define XY_SRC_COPY_BLT_CMD((2<<29)|(0x53<<22)|6) > #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 10/42] drm/i915/lmem: add helper to get CPU visible pfn
Quoting Matthew Auld (2019-02-14 14:57:08)
> From: Abdiel Janulgue
Why?
So can something without a CPU visible struct page even have a pfn?
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/intel_region_lmem.c | 11 +++
> drivers/gpu/drm/i915/intel_region_lmem.h | 3 +++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
> b/drivers/gpu/drm/i915/intel_region_lmem.c
> index 4a205639cbb6..b398becb2733 100644
> --- a/drivers/gpu/drm/i915/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/intel_region_lmem.c
> @@ -65,6 +65,17 @@ static const struct intel_memory_region_ops
> region_lmem_ops = {
> .object_create = region_lmem_object_create,
> };
>
> +unsigned long i915_gem_object_lmem_io_pfn(struct drm_i915_gem_object *obj,
> + unsigned long n)
> +{
> + struct intel_memory_region *mem = obj->memory_region;
> + resource_size_t offset;
> +
> + offset = i915_gem_object_get_dma_address(obj, n);
Magic of type convenience?
We definitely do not want to be returning a dma_address as a CPU
address. The semantics here needs to be cleaned up.
-Chris
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Re: [Intel-gfx] [RFC PATCH 09/42] drm/i915: support creating LMEM objects
Quoting Matthew Auld (2019-02-14 14:57:07)
> +int intel_memory_region_live_selftests(struct drm_i915_private *i915)
> +{
> + static const struct i915_subtest tests[] = {
> + SUBTEST(igt_lmem_create),
> + };
> + struct i915_gem_context *ctx;
> + struct drm_file *file;
> + intel_wakeref_t wakeref;
> + int err;
> +
> + if (!HAS_LMEM(i915)) {
> + pr_info("device lacks LMEM support, skipping\n");
> + return 0;
> + }
> +
> + if (i915_terminally_wedged(&i915->gpu_error))
> + return 0;
> +
> + file = mock_file(i915);
> + if (IS_ERR(file))
> + return PTR_ERR(file);
> +
> + mutex_lock(&i915->drm.struct_mutex);
> + wakeref = intel_runtime_pm_get(i915);
Is taking a global mutex and wakeref wise? Unless I see otherwise, it
means I assume you haven't tested without struct_mutex or rpm very well.
-Chris
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Re: [Intel-gfx] [RFC PATCH 05/42] drm/i915/region: support basic eviction
Quoting Matthew Auld (2019-02-14 14:57:03)
> Support basic eviction for regions.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_gem.c | 16
> drivers/gpu/drm/i915/i915_gem_object.h| 7 ++
> drivers/gpu/drm/i915/i915_gem_shrinker.c | 59 ++
> drivers/gpu/drm/i915/intel_memory_region.c| 40 +-
> drivers/gpu/drm/i915/intel_memory_region.h| 7 ++
> .../drm/i915/selftests/intel_memory_region.c | 76 +++
> drivers/gpu/drm/i915/selftests/mock_region.c | 1 +
> 8 files changed, 204 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0bea7d889284..3df27769b978 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3196,6 +3196,8 @@ void i915_gem_shrinker_register(struct drm_i915_private
> *i915);
> void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
> void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
> struct mutex *mutex);
> +int i915_gem_shrink_memory_region(struct intel_memory_region *mem,
> + resource_size_t target);
>
> /* i915_gem_tiling.c */
> static inline bool i915_gem_object_needs_bit17_swizzle(struct
> drm_i915_gem_object *obj)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 92768ab294a4..7f044b643a75 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4095,6 +4095,22 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void
> *data,
> !i915_gem_object_has_pages(obj))
> i915_gem_object_truncate(obj);
>
> + if (obj->memory_region) {
> + mutex_lock(&obj->memory_region->obj_lock);
> +
> + switch (obj->mm.madv) {
> + case I915_MADV_WILLNEED:
> + list_move(&obj->region_link,
> &obj->memory_region->objects);
> + break;
> + default:
> + list_move(&obj->region_link,
> + &obj->memory_region->purgeable);
> + break;
> + }
> +
> + mutex_unlock(&obj->memory_region->obj_lock);
> + }
> +
> args->retained = obj->mm.madv != __I915_MADV_PURGED;
> mutex_unlock(&obj->mm.lock);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
> b/drivers/gpu/drm/i915/i915_gem_object.h
> index ac52f61e8ad1..76947a6f49f1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/i915_gem_object.h
> @@ -95,6 +95,13 @@ struct drm_i915_gem_object {
> * List of memory region blocks allocated for this object.
> */
> struct list_head blocks;
> + /**
> +* Element within memory_region->objects or memory_region->purgeable
> if
> +* the object is marked as DONTNEED. Access is protected by
> +* memory_region->obj_lock.
Lies. ;-p
> +*/
> + struct list_head region_link;
> + struct list_head tmp_link;
>
> struct {
> /**
> diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c
> b/drivers/gpu/drm/i915/i915_gem_shrinker.c
> index 6da795c7e62e..713c6c93cf30 100644
> --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
> +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
> @@ -308,6 +308,65 @@ unsigned long i915_gem_shrink_all(struct
> drm_i915_private *i915)
> return freed;
> }
>
> +int i915_gem_shrink_memory_region(struct intel_memory_region *mem,
> + resource_size_t target)
If it's not going to be coupled into the mm.shrinker callback, do not put
it here! And there's no reason why we would ever couple local memory to
the generic mm shrinker!
> +{
> + struct drm_i915_private *i915 = mem->i915;
> + struct drm_i915_gem_object *obj, *on;
> + resource_size_t found;
> + LIST_HEAD(purgeable);
> + bool unlock;
> + int err;
> +
> + if (!shrinker_lock(i915, 0, &unlock))
> + return 0;
Don't...
> +
> + i915_retire_requests(i915);
And this, don't do this.
> + err = 0;
> + found = 0;
> +
> + mutex_lock(&mem->obj_lock);
That's all the top-level locking we should ever need.
> + list_for_each_entry(obj, &mem->purgeable, region_link) {
> + if (!i915_gem_object_has_pages(obj))
> + continue;
> +
> + if (READ_ONCE(obj->pin_global))
> + continue;
> +
> + if (atomic_read(&obj->mm.pages_pin_count) > obj->bind_count)
> + continue;
> +
> + list_add(&obj->tmp_link, &purgeable);
Oh crikey.
> +
> + found += obj->base.size;
> +
Re: [Intel-gfx] [RFC PATCH 04/42] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-02-14 14:57:02)
> +int
> +i915_memory_region_get_pages_buddy(struct drm_i915_gem_object *obj)
> +{
> + struct intel_memory_region *mem = obj->memory_region;
> + resource_size_t size = obj->base.size;
> + struct sg_table *st;
> + struct scatterlist *sg;
> + unsigned int sg_page_sizes;
> + unsigned long n_pages;
> +
> + GEM_BUG_ON(!IS_ALIGNED(size, mem->mm.min_size));
> + GEM_BUG_ON(!list_empty(&obj->blocks));
> +
> + st = kmalloc(sizeof(*st), GFP_KERNEL);
> + if (!st)
> + return -ENOMEM;
> +
> + n_pages = div64_u64(size, mem->mm.min_size);
min_size is a power of two.
n_pages = size >> ilog2(min_size);
would suffice. Keeping min_order would come in handy later.
> +
> + if (sg_alloc_table(st, n_pages, GFP_KERNEL)) {
> + kfree(st);
> + return -ENOMEM;
> + }
> +
> + sg = st->sgl;
> + st->nents = 0;
> + sg_page_sizes = 0;
> +
> + mutex_lock(&mem->mm_lock);
> +
> + do {
> + struct i915_gem_buddy_block *block;
> + unsigned int order;
> + u64 block_size;
> + u64 offset;
> +
> + order = fls(n_pages) - 1;
> + GEM_BUG_ON(order > mem->mm.max_order);
> +
> + do {
> + block = i915_gem_buddy_alloc(&mem->mm, order);
> + if (!IS_ERR(block))
> + break;
> +
> + /* XXX: some kind of eviction pass, local to the
> device */
> + if (!order--)
> + goto err_free_blocks;
> + } while (1);
> +
> + n_pages -= 1 << order;
BIT(order) so you don't have sign extension fun. Need to fix
i915_gem_internal.c!
> +struct intel_memory_region_ops {
> + unsigned int flags;
> +
> + int (*init)(struct intel_memory_region *);
> + void (*release)(struct intel_memory_region *);
> +
> + struct drm_i915_gem_object *
> + (*object_create)(struct intel_memory_region *,
> +resource_size_t,
> +unsigned int);
create_object()
ops is acting as a factory here; and we are not operating on the object
itself.
> +static int igt_mock_fill(void *arg)
> +{
> + struct intel_memory_region *mem = arg;
> + resource_size_t total = resource_size(&mem->region);
> + resource_size_t page_size;
> + resource_size_t rem;
> + unsigned long max_pages;
> + unsigned long page_num;
> + LIST_HEAD(objects);
> + int err = 0;
> +
> + page_size = mem->mm.min_size;
> + max_pages = total / page_size;
Hmm, 32b? Can resource_size_t be 64b on a 32b system?
It must be to accommodate PAE.
> +static struct drm_i915_gem_object *
> +mock_object_create(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_private *i915 = mem->i915;
> + struct drm_i915_gem_object *obj;
> +
> + if (size > BIT(mem->mm.max_order) * mem->mm.min_size)
A mix of 64b and 32b types.
if (size >> mem->mm.max_order + mem->mm.min_order)
> + return ERR_PTR(-E2BIG);
GEM_BUG_ON(overflows_type(size, obj->base.size);
> + obj = i915_gem_object_alloc(i915);
> + if (!obj)
> + return ERR_PTR(-ENOMEM);
> +
> + drm_gem_private_object_init(&i915->drm, &obj->base, size);
> + i915_gem_object_init(obj, &mock_region_obj_ops);
> +
> + obj->read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
> + obj->cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
i915_gem_object_set_cache_coherency() ?
-Chris
___
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[Intel-gfx] [RFC PATCH 34/42] drm/i915/query: Expose memory regions through the query uAPI
From: Abdiel Janulgue
Returns the available memory region areas supported by the HW.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_query.c | 57 +++
include/uapi/drm/i915_drm.h | 40 +-
2 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index b4f26605f617..e03958c7a384 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -95,9 +95,66 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
return total_length;
}
+static int query_memregion_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+ struct drm_i915_query_memory_region_info __user *query_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_memory_region_info __user *info_ptr =
+ &query_ptr->regions[0];
+ struct drm_i915_memory_region_info info = { };
+ struct drm_i915_query_memory_region_info query;
+ u32 total_length;
+ int ret, i;
+
+ if (query_item->flags != 0)
+ return -EINVAL;
+
+ total_length = sizeof(struct drm_i915_query_memory_region_info);
+ for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) {
+ struct intel_memory_region *region = dev_priv->regions[i];
+
+ if (!region)
+ continue;
+
+ total_length += sizeof(struct drm_i915_memory_region_info);
+ }
+
+ ret = init_query_item_check(&query, sizeof(query), total_length,
+ query_item);
+ if (ret != 0)
+ return ret;
+
+ if (query.num_regions || query.rsvd[0] || query.rsvd[1] ||
+ query.rsvd[2])
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) {
+ struct intel_memory_region *region = dev_priv->regions[i];
+
+ if (!region)
+ continue;
+
+ info.id = region->id;
+ info.size = resource_size(®ion->region);
+
+ if (__copy_to_user(info_ptr, &info, sizeof(info)))
+ return -EFAULT;
+
+ query.num_regions++;
+ info_ptr++;
+ }
+
+ if (__copy_to_user(query_ptr, &query, sizeof(query)))
+ return -EFAULT;
+
+ return total_length;
+}
+
static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item)
= {
query_topology_info,
+ query_memregion_info,
};
int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 26d2274b5d2b..5a102a5cb415 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1744,6 +1744,7 @@ struct drm_i915_perf_oa_config {
struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO1
+#define DRM_I915_QUERY_MEMREGION_INFO 3
/*
* When set to zero by userspace, this is filled with the size of the
@@ -1832,7 +1833,6 @@ struct drm_i915_query_topology_info {
* Offset in data[] at which the EU masks are stored.
*/
__u16 eu_offset;
-
/*
* Stride at which each of the EU masks for each subslice are stored.
*/
@@ -1841,6 +1841,44 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+struct drm_i915_memory_region_info {
+
+ /** Base type of a region
+*/
+#define I915_SYSTEM_MEMORY 0
+#define I915_DEVICE_MEMORY 1
+
+ /** The region id is encoded in a layout which makes it possible to
+* retrieve the following information:
+*
+* Base type: log2(ID >> 16)
+* Instance: log2(ID & 0x)
+*/
+ __u32 id;
+
+ /** Reserved field. MBZ */
+ __u32 rsvd0;
+
+ /** Unused for now. MBZ */
+ __u64 flags;
+
+ __u64 size;
+
+ /** Reserved fields must be cleared to zero. */
+ __u64 rsvd1[4];
+};
+
+struct drm_i915_query_memory_region_info {
+
+ /** Number of struct drm_i915_memory_region_info structs */
+ __u32 num_regions;
+
+ /** MBZ */
+ __u32 rsvd[3];
+
+ struct drm_i915_memory_region_info regions[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.20.1
___
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[Intel-gfx] [RFC PATCH 40/42] drm/i915: setup io-mapping for LMEM
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index b8b6b8248737..10dfcf961c4b 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -233,9 +233,33 @@ region_lmem_object_create(struct intel_memory_region *mem,
return obj;
}
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(&mem->iomap);
+ i915_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(&mem->iomap,
+ mem->io_start,
+ resource_size(&mem->region)))
+ return -EIO;
+
+ ret = i915_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(&mem->iomap);
+
+ return ret;
+}
+
static const struct intel_memory_region_ops region_lmem_ops = {
- .init = i915_memory_region_init_buddy,
- .release = i915_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.object_create = region_lmem_object_create,
};
--
2.20.1
___
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[Intel-gfx] [RFC PATCH 41/42] HAX drm/i915: add the fake lmem region
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the aperture and 1:1 it map to the stolen region.
To enable simply set i915_fake_lmem_start= on the kernel cmdline with the
start of reserved region(see memmap=). The size of the region we can
use is determined by the size of the mappable aperture, so the size of
reserved region should be >= mappable_end.
eg. memmap=2G$16G i915_fake_lmem_start=0x4
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
arch/x86/kernel/early-quirks.c | 26
drivers/gpu/drm/i915/i915_drv.c| 7 +++
drivers/gpu/drm/i915/i915_gem_gtt.c| 3 +
drivers/gpu/drm/i915/intel_memory_region.h | 4 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 73 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 3 +
include/drm/i915_drm.h | 3 +
7 files changed, 119 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 50d5848bf22e..bdc99d6bfa26 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -600,6 +600,32 @@ static void __init intel_graphics_quirks(int num, int
slot, int func)
}
}
+struct resource intel_graphics_fake_lmem_res __ro_after_init =
DEFINE_RES_MEM(0, 0);
+EXPORT_SYMBOL(intel_graphics_fake_lmem_res);
+
+static int __init early_i915_fake_lmem_init(char *s)
+{
+ u64 start;
+ int ret;
+
+ if (*s == '=')
+ s++;
+
+ ret = kstrtoull(s, 16, &start);
+ if (ret)
+ return ret;
+
+ intel_graphics_fake_lmem_res.start = start;
+ intel_graphics_fake_lmem_res.end = SZ_2G; /* Placeholder; depends on
aperture size */
+
+ printk(KERN_INFO "Intel graphics fake LMEM starts at %pa\n",
+ &intel_graphics_fake_lmem_res.start);
+
+ return 0;
+}
+
+early_param("i915_fake_lmem_start", early_i915_fake_lmem_init);
+
static void __init force_disable_hpet(int num, int slot, int func)
{
#ifdef CONFIG_HPET_TIMER
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 08a4286b70c6..54e24fa075c9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1732,6 +1732,13 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
+ /* Check if we need fake LMEM */
+ if (INTEL_GEN(dev_priv) >= 9 && intel_graphics_fake_lmem_res.start) {
+ mkwrite_device_info(dev_priv)->memory_regions =
+ REGION_SMEM | REGION_LMEM;
+ GEM_BUG_ON(!HAS_LMEM(dev_priv));
+ }
+
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f5d595c700f4..4101992b65f3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2832,6 +2832,9 @@ static int i915_gem_init_memory_regions(struct
drm_i915_private *i915)
case INTEL_STOLEN:
mem = i915_gem_setup_stolen(i915);
break;
+ case INTEL_LMEM:
+ mem = i915_gem_setup_fake_lmem(i915);
+ break;
}
if (IS_ERR(mem)) {
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h
b/drivers/gpu/drm/i915/intel_memory_region.h
index 7754989ad165..ebc46024a376 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "i915_gem_buddy.h"
@@ -90,6 +91,9 @@ struct intel_memory_region {
struct io_mapping iomap;
struct resource region;
+ /* For faking for lmem */
+ struct drm_mm_node fake_mappable;
+
struct i915_gem_buddy_mm mm;
struct mutex mm_lock;
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 10dfcf961c4b..a5a7386ff255 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -233,9 +233,41 @@ region_lmem_object_create(struct intel_memory_region *mem,
return obj;
}
+static int i915_gem_init_fake_lmem_bar(struct intel_memory_region *mem)
+{
+ struct drm_i915_private *i915 = mem->i915;
+ struct i915_ggtt *ggtt = &i915->ggtt;
+ unsigned long n;
+ int ret;
+
+ mem->fake_mappable.start = 0;
+ mem->fake_mappable.size = resource_size(&mem->region);
+ mem->fake_mappable.color = I915_COLOR_UNEVIC
[Intel-gfx] [RFC PATCH 23/42] drm/i915: do not map aperture if it is not available.
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ++---
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index de67a2f1ccfe..3732f21148d3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2831,8 +2831,10 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
mutex_unlock(&dev_priv->drm.struct_mutex);
- arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(&ggtt->iomap);
+ if (HAS_MAPPABLE_APERTURE(dev_priv)) {
+ arch_phys_wc_del(ggtt->mtrr);
+ io_mapping_fini(&ggtt->iomap);
+ }
i915_gem_cleanup_stolen(dev_priv);
}
@@ -3214,10 +3216,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- ggtt->gmadr =
- (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
-pci_resource_len(pdev, 2));
- ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ /* FIXME: We probably need to add do device_info or runtime_info */
+ if (!HAS_LMEM(dev_priv)) {
+ ggtt->gmadr =
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
+pci_resource_len(pdev,
2));
+ ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ }
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
if (!err)
@@ -3454,14 +3459,17 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
mutex_unlock(&dev_priv->drm.struct_mutex);
- if (!io_mapping_init_wc(&dev_priv->ggtt.iomap,
- dev_priv->ggtt.gmadr.start,
- dev_priv->ggtt.mappable_end)) {
- ret = -EIO;
- goto out_gtt_cleanup;
- }
+ if (HAS_MAPPABLE_APERTURE(dev_priv)) {
+ if (!io_mapping_init_wc(&dev_priv->ggtt.iomap,
+ dev_priv->ggtt.gmadr.start,
+ dev_priv->ggtt.mappable_end)) {
+ ret = -EIO;
+ goto out_gtt_cleanup;
+ }
- ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
+ ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
+ ggtt->mappable_end);
+ }
/*
* Initialise stolen early so that we may reserve preallocated
--
2.20.1
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[Intel-gfx] [RFC PATCH 42/42] HAX drm/i915/lmem: default userspace allocations to LMEM
Hack patch to default all userspace allocations to LMEM. Useful for
testing purposes.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem.c | 45 +++--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3c86909d55b9..bd857f477ef9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -641,7 +641,8 @@ i915_gem_create(struct drm_file *file,
u32 *handle_p)
{
struct drm_i915_gem_object *obj;
- int ret;
+ intel_wakeref_t wakeref;
+ int ret = 0;
u32 handle;
size = roundup(size, PAGE_SIZE);
@@ -649,10 +650,50 @@ i915_gem_create(struct drm_file *file,
return -EINVAL;
/* Allocate the new object */
- obj = i915_gem_object_create(dev_priv, size);
+ if (HAS_LMEM(dev_priv))
+ obj = i915_gem_object_create_lmem(dev_priv, size, 0);
+ else
+ obj = i915_gem_object_create(dev_priv, size);
if (IS_ERR(obj))
return PTR_ERR(obj);
+ if (i915_gem_object_is_lmem(obj)) {
+ struct i915_gem_context *ctx;
+
+ /* XXX: we should prob use the blitter context for this? */
+ ctx = i915_gem_context_lookup(file->driver_priv,
+ DEFAULT_CONTEXT_HANDLE);
+ if (!ctx) {
+ i915_gem_object_put(obj);
+ return -ENOENT;
+ }
+
+ /*
+* XXX: We really want to move this to get_pages(), but we
+* require grabbing the BKL for the blitting operation which is
+* annoying. In the pipeline is support for async get_pages()
+* which should fit nicely for this. Also note that the actual
+* clear should be done async(we currently do an object_wait
+* in clear_blt which is pure garbage), we just need to take
+* care if userspace opts of implicit sync for the execbuf, to
+* avoid any potential info leak.
+*/
+
+ mutex_lock(&dev_priv->drm.struct_mutex);
+
+ with_intel_runtime_pm(dev_priv, wakeref)
+ ret = i915_gem_object_clear_blt(ctx, obj);
+
+ i915_gem_context_put(ctx);
+ if (ret) {
+ __i915_gem_object_release_unless_active(obj);
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+ return ret;
+ }
+
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+ }
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
--
2.20.1
___
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[Intel-gfx] [RFC PATCH 21/42] drm/i915/lmem: support pwrite
We need to add support for pwrite'ing an LMEM object.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/intel_region_lmem.c | 73
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 67dc50be2e6b..d549242a3578 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -98,11 +98,84 @@ static int region_lmem_pread(struct drm_i915_gem_object
*obj,
return ret;
}
+static int region_lmem_pwrite(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *args)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ intel_wakeref_t wakeref;
+ char __user *user_data;
+ unsigned int offset;
+ unsigned long idx;
+ u64 remain;
+ int ret;
+
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ return ret;
+
+ ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
+ if (ret)
+ goto out_unpin;
+
+ wakeref = intel_runtime_pm_get(i915);
+
+ ret = i915_gem_object_set_to_wc_domain(obj, true);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (ret)
+ goto out_put;
+
+ remain = args->size;
+ user_data = u64_to_user_ptr(args->data_ptr);
+ offset = offset_in_page(args->offset);
+ for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
+ unsigned long unwritten;
+ void __iomem *vaddr;
+ int length;
+
+ length = remain;
+ if (offset + length > PAGE_SIZE)
+ length = PAGE_SIZE - offset;
+
+ vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
+ if (!vaddr) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
+
+ unwritten = copy_from_user((void __force*)vaddr + offset,
+ user_data,
+ length);
+ io_mapping_unmap_atomic(vaddr);
+ if (unwritten) {
+ ret = -EFAULT;
+ goto out_put;
+ }
+
+ remain -= length;
+ user_data += length;
+ offset = 0;
+ }
+
+out_put:
+ intel_runtime_pm_put(i915, wakeref);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+
+ return ret;
+}
+
static const struct drm_i915_gem_object_ops region_lmem_obj_ops = {
.get_pages = i915_memory_region_get_pages_buddy,
.put_pages = i915_memory_region_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
.pread = region_lmem_pread,
+ .pwrite = region_lmem_pwrite,
};
static struct drm_i915_gem_object *
--
2.20.1
___
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[Intel-gfx] [RFC PATCH 15/42] drm/i915: support copying objects via blitter engine
We need to support copying from one object backing store to another for
object migration.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem.c | 187 ++
drivers/gpu/drm/i915/intel_gpu_commands.h | 2 +
.../gpu/drm/i915/selftests/i915_gem_object.c | 80
4 files changed, 272 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b39af57c36c..b9d01caa3430 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2811,6 +2811,9 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_object_ops *ops);
int i915_gem_object_clear_blt(struct i915_gem_context *ctx,
struct drm_i915_gem_object *obj);
+int i915_gem_object_copy_blt(struct i915_gem_context *ctx,
+struct drm_i915_gem_object *src,
+struct drm_i915_gem_object *dst);
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 032d4334c0f1..501714fbf92f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4288,6 +4288,193 @@ static bool discard_backing_storage(struct
drm_i915_gem_object *obj)
return atomic_long_read(&obj->base.filp->f_count) == 1;
}
+static struct i915_vma *
+__i915_gem_copy_blt(struct i915_vma *src, struct i915_vma *dst)
+{
+ struct drm_i915_private *i915 = to_i915(src->obj->base.dev);
+ const int gen = INTEL_GEN(i915);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *batch;
+ u32 *cmd;
+ int err;
+
+ GEM_BUG_ON(src->vm != dst->vm);
+ GEM_BUG_ON(src->obj->base.size != dst->obj->base.size);
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto err;
+ }
+
+ if (gen >= 9) {
+ *cmd++ = GEN9_XY_FAST_COPY_BLT_CMD;
+ *cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = src->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE /
4;
+ *cmd++ = lower_32_bits(dst->node.start);
+ *cmd++ = upper_32_bits(dst->node.start);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src->node.start);
+ *cmd++ = upper_32_bits(src->node.start);
+ } else if (gen >= 8) {
+ *cmd++ = GEN8_XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = src->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE /
4;
+ *cmd++ = lower_32_bits(dst->node.start);
+ *cmd++ = upper_32_bits(dst->node.start);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src->node.start);
+ *cmd++ = upper_32_bits(src->node.start);
+ } else {
+ *cmd++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = src->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE /
4;
+ *cmd++ = dst->node.start;
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = src->node.start;
+ }
+
+ *cmd = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_unpin_map(obj);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ goto err;
+
+ batch = i915_vma_instance(obj, src->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err;
+
+ return batch;
+
+err:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static int i915_gem_copy_blt(struct i915_gem_context *ctx,
+struct i915_vma *src,
+struct i915_vma *dst)
+{
+ struct drm_i915_private *i915 = to_i915(src->obj->base.dev);
+ struct intel_engine_cs *engine = i915->engine[BCS];
+ struct i915_request *rq;
+ struct i915_vma *batch;
+ int flags = 0;
+ int err;
+
+ err = i915_gem_object_set_to_gtt_domain(src->obj, false);
+ if (err)
+ return err;
+
+ err = i915_gem_object_set_to_gtt_domain(dst->obj, true);
+ if (err)
+ return err;
+
+ rq =
[Intel-gfx] [RFC PATCH 31/42] drm/i915: cpu-map based dumb buffers
From: Abdiel Janulgue
If there is no aperture we can't use map_gtt to map dumb buffers, so we
need a cpu-map based path to do it. We prefer map_gtt on platforms that
do have aperture.
Signed-off-by: Abdiel Janulgue
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_gem.c| 8 ++--
drivers/gpu/drm/i915/i915_gem_object.h | 1 +
4 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90785030a0dd..90ce9973ce46 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3040,7 +3040,7 @@ static struct drm_driver driver = {
.gem_prime_import = i915_gem_prime_import,
.dumb_create = i915_gem_dumb_create,
- .dumb_map_offset = i915_gem_mmap_gtt,
+ .dumb_map_offset = i915_gem_mmap_dumb,
.ioctls = i915_ioctls,
.num_ioctls = ARRAY_SIZE(i915_ioctls),
.fops = &i915_driver_fops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c6ae157d0ede..f0e8567f18f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3030,7 +3030,7 @@ i915_mutex_lock_interruptible(struct drm_device *dev)
int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
-int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
+int i915_gem_mmap_dumb(struct drm_file *file_priv, struct drm_device *dev,
u32 handle, u64 *offset);
int i915_gem_mmap_gtt_version(void);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cc6c88ec749d..b426a1ee8d0f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2157,12 +2157,16 @@ __assign_gem_object_mmap_data(struct drm_file *file,
}
int
-i915_gem_mmap_gtt(struct drm_file *file,
+i915_gem_mmap_dumb(struct drm_file *file,
struct drm_device *dev,
u32 handle,
u64 *offset)
{
- return __assign_gem_object_mmap_data(file, handle, I915_MMAP_ORIGIN_GTT,
+ struct drm_i915_private *i915 = dev->dev_private;
+ enum i915_cpu_mmap_origin_type mmap_type = HAS_MAPPABLE_APERTURE(i915) ?
+ I915_MMAP_ORIGIN_GTT : I915_MMAP_ORIGIN_DUMB;
+
+ return __assign_gem_object_mmap_data(file, handle, mmap_type,
0, offset);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index b37ffe2e17b6..82f9068f8aed 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -90,6 +90,7 @@ enum i915_cpu_mmap_origin_type {
I915_MMAP_ORIGIN_NONE = 0,
I915_MMAP_ORIGIN_GTT,
I915_MMAP_ORIGIN_OFFSET,
+ I915_MMAP_ORIGIN_DUMB,
};
struct drm_i915_gem_object {
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 25/42] drm/i915: set num_fence_regs to 0 if there is no aperture
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 43e813d0e647..e59f38e00f0d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5666,8 +5666,10 @@ i915_gem_load_init_fences(struct drm_i915_private
*dev_priv)
{
int i;
- if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
- !IS_CHERRYVIEW(dev_priv))
+ if (!HAS_MAPPABLE_APERTURE(dev_priv))
+ dev_priv->num_fence_regs = 0;
+ else if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
+!IS_CHERRYVIEW(dev_priv))
dev_priv->num_fence_regs = 32;
else if (INTEL_GEN(dev_priv) >= 4 ||
IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
--
2.20.1
___
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[Intel-gfx] [RFC PATCH 12/42] drm/i915/selftests: exercise huge-pages for LMEM
We already exercise huge-pages for our other object types, so add LMEM
objects to the list. Also try our luck with 1G pages.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 121 +++-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index b0c8b4955f14..f4283d41c13f 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1095,7 +1095,7 @@ static int gpu_write(struct i915_vma *vma,
return err;
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1127,6 +1127,52 @@ static int cpu_check(struct drm_i915_gem_object *obj,
u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
+{
+ unsigned long n;
+ int err;
+
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = (void __force
*)io_mapping_map_atomic_wc(&obj->memory_region->iomap,
+
i915_gem_object_get_dma_address(obj, n));
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (HAS_LMEM(i915) && obj->memory_region)
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
struct drm_i915_gem_object *obj,
@@ -1510,6 +1556,78 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ SZ_1G, /* Try our luck! */
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+* Sanity check that the HW uses huge pages correctly through LMEM
+* -- ensure that our writes land in the right place.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size, 0);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys == I915_GTT_PAGE_SIZE_1G) {
+ pr_info("long live 1G pages!\n");
+ } else if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with
size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ return err;
+}
+
static
[Intel-gfx] [RFC PATCH 19/42] drm/i915: add vfunc for pread
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem.c| 6 ++
drivers/gpu/drm/i915/i915_gem_object.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3f319524beed..43e813d0e647 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1116,6 +1116,12 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
trace_i915_gem_object_pread(obj, args->offset, args->size);
+ ret = -ENODEV;
+ if (obj->ops->pread)
+ ret = obj->ops->pread(obj, args);
+ if (ret != -ENODEV)
+ goto out;
+
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE,
MAX_SCHEDULE_TIMEOUT);
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index 0dfe9603e3cc..f5b8bca33fe3 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -75,6 +75,8 @@ struct drm_i915_gem_object_ops {
int (*get_pages)(struct drm_i915_gem_object *);
void (*put_pages)(struct drm_i915_gem_object *, struct sg_table *);
+ int (*pread)(struct drm_i915_gem_object *,
+const struct drm_i915_gem_pread *);
int (*pwrite)(struct drm_i915_gem_object *,
const struct drm_i915_gem_pwrite *);
--
2.20.1
___
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[Intel-gfx] [RFC PATCH 07/42] drm/i915/region: support volatile objects
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem_object.h| 3 +-
drivers/gpu/drm/i915/intel_memory_region.c| 10 +++-
.../drm/i915/selftests/intel_memory_region.c | 54 +++
3 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index efc23fc2b1df..0dfe9603e3cc 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -164,7 +164,8 @@ struct drm_i915_gem_object {
*/
#define I915_BO_ACTIVE_REF 0
#define I915_BO_ALLOC_CONTIGUOUS (1<<1)
-#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+#define I915_BO_ALLOC_VOLATILE (1<<2)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)
/*
* Is the object to be mapped as read-only to the GPU
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index ed37599c7784..5531ed94bdab 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -148,6 +148,9 @@ i915_memory_region_get_pages_buddy(struct
drm_i915_gem_object *obj)
i915_sg_trim(st);
+ if (flags & I915_BO_ALLOC_VOLATILE)
+ obj->mm.madv = I915_MADV_DONTNEED;
+
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
@@ -209,7 +212,12 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
obj->flags = flags;
mutex_lock(&mem->obj_lock);
- list_add(&obj->region_link, &mem->objects);
+
+ if (flags & I915_BO_ALLOC_VOLATILE)
+ list_add(&obj->region_link, &mem->purgeable);
+ else
+ list_add(&obj->region_link, &mem->objects);
+
mutex_unlock(&mem->obj_lock);
i915_gem_object_set_cache_coherency(obj, obj->cache_level);
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index fbb1497d0f82..0f6432a2a4c4 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -309,12 +309,66 @@ static int igt_mock_continuous(void *arg)
return err;
}
+static int igt_mock_volatile(void *arg)
+{
+ struct intel_memory_region *mem = arg;
+ struct drm_i915_gem_object *obj;
+ int err;
+
+ obj = i915_gem_object_create_region(mem, PAGE_SIZE, 0);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto err_put;
+
+ i915_gem_object_unpin_pages(obj);
+
+ err = i915_gem_shrink_memory_region(mem, PAGE_SIZE);
+ if (err != -ENOSPC) {
+ pr_err("shrink memory region\n");
+ goto err_put;
+ }
+
+ obj = i915_gem_object_create_region(mem, PAGE_SIZE,
I915_BO_ALLOC_VOLATILE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ if (!(obj->flags & I915_BO_ALLOC_VOLATILE)) {
+ pr_err("missing flags\n");
+ goto err_put;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto err_put;
+
+ i915_gem_object_unpin_pages(obj);
+
+ err = i915_gem_shrink_memory_region(mem, PAGE_SIZE);
+ if (err) {
+ pr_err("failed to shrink memory\n");
+ goto err_put;
+ }
+
+ if (i915_gem_object_has_pages(obj)) {
+ pr_err("object pages not discarded\n");
+ err = -EINVAL;
+ }
+
+err_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
int intel_memory_region_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_mock_fill),
SUBTEST(igt_mock_shrink),
SUBTEST(igt_mock_continuous),
+ SUBTEST(igt_mock_volatile),
};
struct intel_memory_region *mem;
struct drm_i915_private *i915;
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 27/42] drm/i915: Don't try to place HWS in non-existing mappable region
From: Michal Wajdeczko HWS placement restrictions can't just rely on HAS_LLC flag. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 2547e2e51db8..3384cdf7edab 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -502,7 +502,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && HAS_MAPPABLE_APERTURE(engine->i915)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 20/42] drm/i915/lmem: support pread
We need to add support for pread'ing an LMEM object.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/intel_region_lmem.c | 73
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index c8bee0c18c88..67dc50be2e6b 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -26,10 +26,83 @@
#include "intel_memory_region.h"
#include "intel_region_lmem.h"
+static int region_lmem_pread(struct drm_i915_gem_object *obj,
+const struct drm_i915_gem_pread *args)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ intel_wakeref_t wakeref;
+ char __user *user_data;
+ unsigned int offset;
+ unsigned long idx;
+ u64 remain;
+ int ret;
+
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ return ret;
+
+ ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
+ if (ret)
+ goto out_unpin;
+
+ wakeref = intel_runtime_pm_get(i915);
+
+ ret = i915_gem_object_set_to_wc_domain(obj, false);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (ret)
+ goto out_put;
+
+ remain = args->size;
+ user_data = u64_to_user_ptr(args->data_ptr);
+ offset = offset_in_page(args->offset);
+ for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
+ unsigned long unwritten;
+ void __iomem *vaddr;
+ int length;
+
+ length = remain;
+ if (offset + length > PAGE_SIZE)
+ length = PAGE_SIZE - offset;
+
+ vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
+ if (!vaddr) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
+
+ unwritten = copy_to_user(user_data,
+(void __force *)vaddr + offset,
+length);
+ io_mapping_unmap_atomic(vaddr);
+ if (unwritten) {
+ ret = -EFAULT;
+ goto out_put;
+ }
+
+ remain -= length;
+ user_data += length;
+ offset = 0;
+ }
+
+out_put:
+ intel_runtime_pm_put(i915, wakeref);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+
+ return ret;
+}
+
static const struct drm_i915_gem_object_ops region_lmem_obj_ops = {
.get_pages = i915_memory_region_get_pages_buddy,
.put_pages = i915_memory_region_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
+ .pread = region_lmem_pread,
};
static struct drm_i915_gem_object *
--
2.20.1
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[Intel-gfx] [RFC PATCH 33/42] UPSTREAM: drm/i915/query: Split out query item checks
From: Abdiel Janulgue
This simplifies adding new query item objects.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_query.c | 40 ---
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index cbcb957b7141..b4f26605f617 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -10,12 +10,33 @@
#include "i915_query.h"
#include
+static int init_query_item_check(void* data_ptr, size_t data_sz,
+u32 total_length,
+struct drm_i915_query_item *query_item)
+{
+ if (query_item->length == 0)
+ return total_length;
+
+ if (query_item->length < total_length)
+ return -EINVAL;
+
+ if (copy_from_user(data_ptr, u64_to_user_ptr(query_item->data_ptr),
+ data_sz))
+ return -EFAULT;
+
+ if (!access_ok(u64_to_user_ptr(query_item->data_ptr),
+ total_length))
+ return -EFAULT;
+
+ return 0;
+}
+
static int query_topology_info(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item)
{
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
- u32 slice_length, subslice_length, eu_length, total_length;
+ u32 ret, slice_length, subslice_length, eu_length, total_length;
if (query_item->flags != 0)
return -EINVAL;
@@ -33,23 +54,14 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
- if (query_item->length == 0)
- return total_length;
-
- if (query_item->length < total_length)
- return -EINVAL;
-
- if (copy_from_user(&topo, u64_to_user_ptr(query_item->data_ptr),
- sizeof(topo)))
- return -EFAULT;
+ ret = init_query_item_check(&topo, sizeof(topo), total_length,
+ query_item);
+ if (ret != 0)
+ return ret;
if (topo.flags != 0)
return -EINVAL;
- if (!access_ok(u64_to_user_ptr(query_item->data_ptr),
- total_length))
- return -EFAULT;
-
memset(&topo, 0, sizeof(topo));
topo.max_slices = sseu->max_slices;
topo.max_subslices = sseu->max_subslices;
--
2.20.1
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[Intel-gfx] [RFC PATCH 30/42] drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET
From: Abdiel Janulgue
CPU mmap implementation depending on the object's backing pages.
At the moment we introduce shmem and local-memory BAR fault handlers
Note that the mmap type is done one at a time to circumvent the DRM
offset manager limitation. Note that we multiplex mmap_gtt and
mmap_offset through the same ioctl, and use the zero extending behaviour
of drm to differentiate between them, when we inspect the flags.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c| 5 +-
drivers/gpu/drm/i915/i915_drv.h| 3 +
drivers/gpu/drm/i915/i915_gem.c| 94 ++
drivers/gpu/drm/i915/i915_gem_object.h | 10 +++
include/uapi/drm/i915_drm.h| 30
5 files changed, 126 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b1200d7ebd13..90785030a0dd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -423,6 +423,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
case I915_PARAM_HAS_EXEC_CAPTURE:
case I915_PARAM_HAS_EXEC_BATCH_FIRST:
case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
+ case I915_PARAM_MMAP_OFFSET_VERSION:
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
@@ -2936,7 +2937,7 @@ const struct dev_pm_ops i915_pm_ops = {
static const struct vm_operations_struct i915_gem_vm_ops = {
.fault = i915_gem_fault,
.open = drm_gem_vm_open,
- .close = drm_gem_vm_close,
+ .close = i915_gem_close,
};
static const struct file_operations i915_driver_fops = {
@@ -2991,7 +2992,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
- DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_gtt_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl,
DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 065953a9264f..c6ae157d0ede 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2770,6 +2770,8 @@ int i915_gem_mmap_ioctl(struct drm_device *dev, void
*data,
struct drm_file *file_priv);
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
@@ -3073,6 +3075,7 @@ void i915_gem_suspend_late(struct drm_i915_private
*dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma);
vm_fault_t i915_gem_fault(struct vm_fault *vmf);
+void i915_gem_close(struct vm_area_struct *vma);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
unsigned int flags,
long timeout);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 48dbb57fbc6d..cc6c88ec749d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2123,11 +2123,12 @@ static void i915_gem_object_free_mmap_offset(struct
drm_i915_gem_object *obj)
drm_gem_free_mmap_offset(&obj->base);
}
-int
-i915_gem_mmap_gtt(struct drm_file *file,
- struct drm_device *dev,
- u32 handle,
- u64 *offset)
+static int
+__assign_gem_object_mmap_data(struct drm_file *file,
+ u32 handle,
+ enum i915_cpu_mmap_origin_type mmap_type,
+ u64 mmap_flags,
+ u64 *offset)
{
struct drm_i915_gem_object *obj;
int ret;
@@ -2136,14 +2137,35 @@ i915_gem_mmap_gtt(struct drm_file *file,
if (!obj)
return -ENOENT;
+ if (atomic_read(&obj->mmap_count) &&
+ obj->mmap_origin != mmap_type) {
+ /* Re-map object with existing different map-type */
+ ret = -EINVAL;
+ goto e
[Intel-gfx] [RFC PATCH 28/42] drm/i915: Split out GTT fault handler to make it generic
From: Abdiel Janulgue
In preparation for using multiple page-fault handlers depending
on the object's backing storage.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c | 112 +++-
1 file changed, 66 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e59f38e00f0d..95e31529a738 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1782,11 +1782,7 @@ compute_partial_view(const struct drm_i915_gem_object
*obj,
}
/**
- * i915_gem_fault - fault a page into the GTT
- * @vmf: fault info
- *
- * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
- * from userspace. The fault handler takes care of binding the object to
+ * The GTT fill pages handler takes care of binding the object to
* the GTT (if needed), allocating and programming a fence register (again,
* only if needed based on whether the old reg is still valid or the object
* is tiled) and inserting a new PTE into the faulting process.
@@ -1799,57 +1795,20 @@ compute_partial_view(const struct drm_i915_gem_object
*obj,
* The current feature set supported by i915_gem_fault() and thus GTT mmaps
* is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
*/
-vm_fault_t i915_gem_fault(struct vm_fault *vmf)
+static int __vmf_fill_pages_gtt(struct drm_i915_gem_object *obj,
+ struct vm_fault *vmf,
+ pgoff_t page_offset)
{
#define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
struct vm_area_struct *area = vmf->vma;
- struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = &dev_priv->ggtt;
bool write = area->vm_flags & VM_WRITE;
- intel_wakeref_t wakeref;
struct i915_vma *vma;
- pgoff_t page_offset;
int srcu;
int ret;
- /* Sanity check that we allow writing into this object */
- if (i915_gem_object_is_readonly(obj) && write)
- return VM_FAULT_SIGBUS;
-
- /* We don't use vmf->pgoff since that has the fake offset */
- page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
-
- trace_i915_gem_object_fault(obj, page_offset, true, write);
-
- /* Try to flush the object off the GPU first without holding the lock.
-* Upon acquiring the lock, we will perform our sanity checks and then
-* repeat the flush holding the lock in the normal manner to catch cases
-* where we are gazumped.
-*/
- ret = i915_gem_object_wait(obj,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT);
- if (ret)
- goto err;
-
- ret = i915_gem_object_pin_pages(obj);
- if (ret)
- goto err;
-
- wakeref = intel_runtime_pm_get(dev_priv);
-
- ret = i915_mutex_lock_interruptible(dev);
- if (ret)
- goto err_rpm;
-
- /* Access to snoopable pages through the GTT is incoherent. */
- if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
- ret = -EFAULT;
- goto err_unlock;
- }
-
/* Now pin it into the GTT as needed */
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
PIN_MAPPABLE |
@@ -1880,7 +1839,7 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
}
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
- goto err_unlock;
+ return ret;
}
ret = i915_gem_object_set_to_gtt_domain(obj, write);
@@ -1920,6 +1879,67 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
i915_vma_unpin_fence(vma);
err_unpin:
__i915_vma_unpin(vma);
+
+ return ret;
+}
+
+/**
+ * i915_gem_fault - fault a page into the memory
+ * @vmf: fault info
+ *
+ * The fault handler is set up by drm_gem_mmap() when mmap_offset is called on
+ * an object from userspace. The missing pages are setup by an object's
+ * vmf_fill_pages pages handler, depending on it's backing storage.
+ */
+vm_fault_t i915_gem_fault(struct vm_fault *vmf)
+{
+ struct vm_area_struct *area = vmf->vma;
+ struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ intel_wakeref_t wakeref;
+ bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
+ pgoff_t page_offset;
+ int ret;
+
+ /* Sanity check that we allow writing into this object */
+ if (i915_gem_object_is_readonly(obj) && write)
+ return VM_FAULT_SIGBUS;
+
+ /* We don't use vmf->pgoff since that has the fake offset */
+ page_offset = (v
[Intel-gfx] [RFC PATCH 32/42] drm/i915: Add fill_pages handler for dma_buf imported objects
From: Abdiel Janulgue
Use the plumbing from the new mmap_offset infrastructure to
implement gtt-mmaps.
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c| 8
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 14 ++
drivers/gpu/drm/i915/i915_gem_object.h | 5 +
3 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b426a1ee8d0f..a9e119d8d1f1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1797,9 +1797,9 @@ compute_partial_view(const struct drm_i915_gem_object
*obj,
* The current feature set supported by i915_gem_fault() and thus GTT mmaps
* is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
*/
-static int __vmf_fill_pages_gtt(struct drm_i915_gem_object *obj,
- struct vm_fault *vmf,
- pgoff_t page_offset)
+int i915_vmf_fill_pages_gtt(struct drm_i915_gem_object *obj,
+ struct vm_fault *vmf,
+ pgoff_t page_offset)
{
#define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
struct vm_area_struct *area = vmf->vma;
@@ -4299,7 +4299,7 @@ int i915_gem_vmf_fill_pages_cpu(struct
drm_i915_gem_object *obj,
if (HAS_MAPPABLE_APERTURE(dev_priv) &&
obj->mmap_origin == I915_MMAP_ORIGIN_GTT)
- return __vmf_fill_pages_gtt(obj, vmf, page_offset);
+ return i915_vmf_fill_pages_gtt(obj, vmf, page_offset);
page = i915_gem_object_get_page(obj, pg_off);
pfn = page_to_pfn(page);
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 02f7298bfe57..b5a8d01e41cc 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -268,9 +268,23 @@ static void i915_gem_object_put_pages_dmabuf(struct
drm_i915_gem_object *obj,
DMA_BIDIRECTIONAL);
}
+static int i915_gem_vmf_fill_pages_dmabuf(struct drm_i915_gem_object *obj,
+ struct vm_fault *vmf,
+ pgoff_t page_offset)
+{
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ if (!HAS_MAPPABLE_APERTURE(dev_priv))
+ return -EFAULT;
+
+ return i915_vmf_fill_pages_gtt(obj, vmf, page_offset);
+}
+
static const struct drm_i915_gem_object_ops i915_gem_object_dmabuf_ops = {
.get_pages = i915_gem_object_get_pages_dmabuf,
.put_pages = i915_gem_object_put_pages_dmabuf,
+ .vmf_fill_pages = i915_gem_vmf_fill_pages_dmabuf,
};
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index 82f9068f8aed..078d5550a1c8 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -536,4 +536,9 @@ void i915_gem_object_flush_if_display(struct
drm_i915_gem_object *obj);
int i915_gem_vmf_fill_pages_cpu(struct drm_i915_gem_object *obj,
struct vm_fault *vmf,
pgoff_t page_offset);
+
+int i915_vmf_fill_pages_gtt(struct drm_i915_gem_object *obj,
+ struct vm_fault *vmf,
+ pgoff_t page_offset);
+
#endif
--
2.20.1
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[Intel-gfx] [RFC PATCH 37/42] drm/i915: enumerate and init each supported region
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 73 ++---
1 file changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 045c6715d5a6..e0a8e90b1480 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2798,6 +2798,71 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
return ret;
}
+static void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915)
+{
+ int i;
+
+ i915_gem_cleanup_stolen(i915);
+
+ for (i = 0; i < ARRAY_SIZE(i915->regions); ++i) {
+ struct intel_memory_region *region = i915->regions[i];
+
+ if (region)
+ intel_memory_region_destroy(region);
+ }
+}
+
+static int i915_gem_init_memory_regions(struct drm_i915_private *i915)
+{
+ int err, i;
+
+ /* All platforms currently have system memory */
+ GEM_BUG_ON(!HAS_REGION(i915, REGION_SMEM));
+
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ /* XXX: stolen will become a region at some point */
+ err = i915_gem_init_stolen(i915);
+ if (err)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(intel_region_map); i++) {
+ struct intel_memory_region *mem = NULL;
+ u32 type;
+
+ if (!HAS_REGION(i915, BIT(i)))
+ continue;
+
+ type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
+ switch (type) {
+ default:
+ break;
+ }
+
+ if (IS_ERR(mem)) {
+ err = PTR_ERR(mem);
+ DRM_ERROR("Failed to setup region(%d) type=%d\n", err,
type);
+ goto out_cleanup;
+ }
+
+ if (mem) {
+ mem->id = intel_region_map[i];
+ mem->type = type;
+ mem->instance =
MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
+ }
+
+ i915->regions[i] = mem;
+ }
+
+ return 0;
+
+out_cleanup:
+ i915_gem_cleanup_memory_regions(i915);
+ return err;
+}
+
/**
* i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
* @dev_priv: i915 device
@@ -2839,7 +2904,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
io_mapping_fini(&ggtt->iomap);
}
- i915_gem_cleanup_stolen(dev_priv);
+ i915_gem_cleanup_memory_regions(dev_priv);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3474,11 +3539,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
ggtt->mappable_end);
}
- /*
-* Initialise stolen early so that we may reserve preallocated
-* objects for the BIOS to KMS transition.
-*/
- ret = i915_gem_init_stolen(dev_priv);
+ ret = i915_gem_init_memory_regions(dev_priv);
if (ret)
goto out_gtt_cleanup;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 35/42] drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION
From: Abdiel Janulgue
This call will specify which memory region an object should be placed.
Note that changing the object's backing storage should be immediately
done after an object is created or if it's not yet in use, otherwise
this will fail on a busy object.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 111
include/uapi/drm/i915_drm.h | 24 +++
4 files changed, 138 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90ce9973ce46..08a4286b70c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3016,6 +3016,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG,
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_OBJECT_SETPARAM,
i915_gem_object_setparam_ioctl, DRM_RENDER_ALLOW),
};
static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f0e8567f18f5..8185ea126752 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2762,6 +2762,8 @@ ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv, u32 bits)
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+int i915_gem_object_setparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a9e119d8d1f1..387eae998fbf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2257,6 +2257,117 @@ int i915_gem_mmap(struct file *filp, struct
vm_area_struct *vma)
return ret;
}
+static enum intel_region_id
+__region_id(u32 region)
+{
+ enum intel_region_id id;
+
+ for (id = 0; id < ARRAY_SIZE(intel_region_map); ++id) {
+ if (intel_region_map[id] == region)
+ return id;
+ }
+
+ return INTEL_MEMORY_UKNOWN;
+}
+
+static int i915_gem_object_region_select(struct drm_i915_private *dev_priv,
+struct drm_i915_gem_object_param *args,
+struct drm_file *file,
+struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_context *ctx = 0;
+ intel_wakeref_t wakeref;
+ u32 __user *uregions = u64_to_user_ptr(args->data);
+ int i, ret;
+
+ ctx = i915_gem_context_lookup(file->driver_priv,
+ DEFAULT_CONTEXT_HANDLE);
+ if (!ctx)
+ return -ENOENT;
+
+ mutex_lock(&dev_priv->drm.struct_mutex);
+ ret = i915_gem_object_prepare_move(obj);
+ if (ret) {
+ DRM_ERROR("Cannot set memory region, object in use\n");
+ goto err;
+ }
+
+ if (args->size > ARRAY_SIZE(intel_region_map))
+ return -EINVAL;
+
+ for (i = 0; i < args->size; i++) {
+ u32 region;
+ enum intel_region_id id;
+
+ ret = get_user(region, uregions);
+ if (ret)
+ goto err;
+
+ id = __region_id(region);
+ if (id == INTEL_MEMORY_UKNOWN) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = i915_gem_object_migrate(ctx, obj, id);
+ if (!ret) {
+ if (MEMORY_TYPE_FROM_REGION(region) ==
+ INTEL_LMEM) {
+ /*
+* TODO: this should be part of get_pages(),
+* when async get_pages arrives
+*/
+ with_intel_runtime_pm(dev_priv, wakeref)
+ ret = i915_gem_object_clear_blt(ctx,
obj);
+
+ if (ret) {
+
__i915_gem_object_release_unless_active(obj);
+ DRM_ERROR("Failed clearing the
object\n");
+ goto err;
+ }
+ }
+ break;
+ }
+ ++uregions;
+ }
+err:
+ mutex_unlock
[Intel-gfx] [RFC PATCH 04/42] drm/i915: introduce intel_memory_region
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_object.h| 9 +
drivers/gpu/drm/i915/intel_memory_region.c| 232 ++
drivers/gpu/drm/i915/intel_memory_region.h| 126 ++
drivers/gpu/drm/i915/selftests/huge_pages.c | 81 ++
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 128 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
drivers/gpu/drm/i915/selftests/mock_region.c | 71 ++
drivers/gpu/drm/i915/selftests/mock_region.h | 35 +++
12 files changed, 687 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h
create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5ce813d1936..96be264fa382 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -88,6 +88,7 @@ i915-y += \
intel_engine_cs.o \
intel_hangcheck.o \
intel_lrc.o \
+ intel_memory_region.o \
intel_mocs.o \
intel_ringbuffer.o \
intel_uncore.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 17fe942eaafa..0bea7d889284 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -72,6 +72,7 @@
#include "intel_wopcm.h"
#include "intel_workarounds.h"
#include "intel_uc.h"
+#include "intel_memory_region.h"
#include "i915_gem.h"
#include "i915_gem_context.h"
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b421bc7a2e26..92768ab294a4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5706,4 +5706,5 @@ int i915_gem_object_attach_phys(struct
drm_i915_gem_object *obj, int align)
#include "selftests/i915_gem_object.c"
#include "selftests/i915_gem_coherency.c"
#include "selftests/i915_gem.c"
+#include "selftests/intel_memory_region.c"
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index fab040331cdb..ac52f61e8ad1 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -87,6 +87,15 @@ struct drm_i915_gem_object {
const struct drm_i915_gem_object_ops *ops;
+ /**
+* Memory region for this object.
+*/
+ struct intel_memory_region *memory_region;
+ /**
+* List of memory region blocks allocated for this object.
+*/
+ struct list_head blocks;
+
struct {
/**
* @vma.lock: protect the list/tree of vmas
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
new file mode 100644
index ..405d6d51194f
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_memory_region.h"
+#include "i915_drv.h"
+
+static void
+memory_region_free_pages(struct drm_i915_gem_object *obj,
+struct sg_table *pages)
+{
+
+ struct i915_gem_buddy_block *block, *on;
+
+ lockdep_assert_held(&obj->memory_region->mm_lock);
+
+ list_for_each_entry_safe(block, on, &obj->blocks, link) {
[Intel-gfx] [RFC PATCH 01/42] drm/i915: support 1G pages for the 48b PPGTT
Support inserting 1G gtt pages into the 48b PPGTT.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +---
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +++-
drivers/gpu/drm/i915/selftests/huge_pages.c | 3 ++-
4 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2aeea977283f..fed46fe19c03 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -118,10 +118,14 @@ stringify_page_sizes(unsigned int page_sizes, char *buf,
size_t len)
return "64K";
case I915_GTT_PAGE_SIZE_2M:
return "2M";
+ case I915_GTT_PAGE_SIZE_1G:
+ return "1G";
default:
if (!buf)
return "M";
+ if (page_sizes & I915_GTT_PAGE_SIZE_1G)
+ x += snprintf(buf + x, len - x, "1G, ");
if (page_sizes & I915_GTT_PAGE_SIZE_2M)
x += snprintf(buf + x, len - x, "2M, ");
if (page_sizes & I915_GTT_PAGE_SIZE_64K)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d646d37eec2f..de67a2f1ccfe 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1069,9 +1069,19 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
gen8_pte_t *vaddr;
u16 index, max;
- if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
- IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
- rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) {
+ if (unlikely(vma->page_sizes.sg & I915_GTT_PAGE_SIZE_1G) &&
+ IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_1G) &&
+ rem >= I915_GTT_PAGE_SIZE_1G && !(idx.pte | idx.pde)) {
+ index = idx.pdpe;
+ max = GEN8_PML4ES_PER_PML4;
+ page_size = I915_GTT_PAGE_SIZE_1G;
+
+ encode |= GEN8_PDPE_PS_1G;
+
+ vaddr = kmap_atomic_px(pdp);
+ } else if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
+ IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
+ rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) {
index = idx.pde;
max = I915_PDES;
page_size = I915_GTT_PAGE_SIZE_2M;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 03ade71b8d9a..9a8066779f47 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -46,9 +46,10 @@
#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
+#define I915_GTT_PAGE_SIZE_1G BIT_ULL(30)
#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
-#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
+#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_1G
#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
@@ -160,6 +161,7 @@ typedef u64 gen8_ppgtt_pml4e_t;
#define GEN8_PDE_IPS_64K BIT(11)
#define GEN8_PDE_PS_2M BIT(7)
+#define GEN8_PDPE_PS_1G BIT(7)
struct sg_table;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index a9a2fa35876f..b6d84939592b 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -30,6 +30,7 @@
#include "i915_random.h"
static const unsigned int page_sizes[] = {
+ I915_GTT_PAGE_SIZE_1G,
I915_GTT_PAGE_SIZE_2M,
I915_GTT_PAGE_SIZE_64K,
I915_GTT_PAGE_SIZE_4K,
@@ -1220,7 +1221,7 @@ static int igt_ppgtt_exhaust_huge(void *arg)
*/
n = 0;
- for_each_set_bit(i, &supported, ilog2(I915_GTT_MAX_PAGE_SIZE) + 1)
+ for_each_set_bit(i, &supported, ilog2(I915_GTT_PAGE_SIZE_2M) + 1)
pages[n++] = BIT(i);
for (size_mask = 2; size_mask < BIT(n); size_mask++) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 10/42] drm/i915/lmem: add helper to get CPU visible pfn
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_region_lmem.c | 11 +++
drivers/gpu/drm/i915/intel_region_lmem.h | 3 +++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 4a205639cbb6..b398becb2733 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -65,6 +65,17 @@ static const struct intel_memory_region_ops region_lmem_ops
= {
.object_create = region_lmem_object_create,
};
+unsigned long i915_gem_object_lmem_io_pfn(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ struct intel_memory_region *mem = obj->memory_region;
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return (mem->io_start + offset) >> PAGE_SHIFT;
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *region = obj->memory_region;
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.h
b/drivers/gpu/drm/i915/intel_region_lmem.h
index 7204f61aab44..1aa24bd28690 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.h
+++ b/drivers/gpu/drm/i915/intel_region_lmem.h
@@ -25,6 +25,9 @@
#ifndef __INTEL_REGION_LMEM_H
#define __INTEL_REGION_LMEM_H
+unsigned long i915_gem_object_lmem_io_pfn(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 00/42] Introduce memory region concept (including device local memory)
In preparation for upcoming devices with device local memory, introduce the concept of different memory regions, and a simple buddy allocator to manage them. At the end of the series are a couple of HAX patches which introduce a fake local memory region for testing purposes. Currently smoke tested on a Skull Canyon device. Abdiel Janulgue (13): drm/i915: Add memory region information to device_info drm/i915/lmem: add helper to get CPU visible pfn drm/i915/lmem: support kernel mapping drm/i915: Split out GTT fault handler to make it generic drm/i915: Set correct vmf source pages for gem objects drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET drm/i915: cpu-map based dumb buffers drm/i915: Add fill_pages handler for dma_buf imported objects UPSTREAM: drm/i915/query: Split out query item checks drm/i915/query: Expose memory regions through the query uAPI drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION drm/i915: enumerate and init each supported region drm/i915: setup io-mapping for LMEM Daniele Ceraolo Spurio (5): drm/i915: define HAS_MAPPABLE_APERTURE drm/i915: do not map aperture if it is not available. drm/i915: expose missing map_gtt support to users drm/i915: set num_fence_regs to 0 if there is no aperture drm/i915: error capture with no ggtt slot Matthew Auld (23): drm/i915: support 1G pages for the 48b PPGTT drm/i915: enable platform support for 1G pages drm/i915: buddy allocator drm/i915: introduce intel_memory_region drm/i915/region: support basic eviction drm/i915/region: support continuous allocations drm/i915/region: support volatile objects drm/i915: support creating LMEM objects drm/i915/selftests: exercise writes to LMEM drm/i915/selftests: exercise huge-pages for LMEM drm/i915: support object clearing via blitter engine drm/i915: introduce kernel blitter_context drm/i915: support copying objects via blitter engine drm/i915: support basic object migration drm/i915/lmem: support CPU relocations drm/i915: add vfunc for pread drm/i915/lmem: support pread drm/i915/lmem: support pwrite drm/i915/lmem: include debugfs metrics drm/i915: treat shmem as a region drm/i915: treat stolen as a region HAX drm/i915: add the fake lmem region HAX drm/i915/lmem: default userspace allocations to LMEM Michal Wajdeczko (1): drm/i915: Don't try to place HWS in non-existing mappable region arch/x86/kernel/early-quirks.c| 26 + drivers/gpu/drm/i915/Makefile |3 + drivers/gpu/drm/i915/i915_debugfs.c | 31 + drivers/gpu/drm/i915/i915_drv.c | 19 +- drivers/gpu/drm/i915/i915_drv.h | 37 +- drivers/gpu/drm/i915/i915_gem.c | 1005 +++-- drivers/gpu/drm/i915/i915_gem_buddy.c | 206 drivers/gpu/drm/i915/i915_gem_buddy.h | 118 ++ drivers/gpu/drm/i915/i915_gem_context.c | 13 + drivers/gpu/drm/i915/i915_gem_dmabuf.c| 14 + drivers/gpu/drm/i915/i915_gem_execbuffer.c| 67 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 136 ++- drivers/gpu/drm/i915/i915_gem_gtt.h |4 +- drivers/gpu/drm/i915/i915_gem_object.c|1 + drivers/gpu/drm/i915/i915_gem_object.h| 43 +- drivers/gpu/drm/i915/i915_gem_shrinker.c | 59 + drivers/gpu/drm/i915/i915_gem_stolen.c| 66 +- drivers/gpu/drm/i915/i915_gpu_error.c | 63 +- drivers/gpu/drm/i915/i915_pci.c | 18 +- drivers/gpu/drm/i915/i915_query.c | 97 +- drivers/gpu/drm/i915/intel_device_info.h |1 + drivers/gpu/drm/i915/intel_engine_cs.c|2 +- drivers/gpu/drm/i915/intel_gpu_commands.h |3 + drivers/gpu/drm/i915/intel_memory_region.c| 286 + drivers/gpu/drm/i915/intel_memory_region.h| 140 +++ drivers/gpu/drm/i915/intel_region_lmem.c | 388 +++ drivers/gpu/drm/i915/intel_region_lmem.h | 46 + drivers/gpu/drm/i915/selftests/huge_pages.c | 204 +++- .../gpu/drm/i915/selftests/i915_gem_buddy.c | 209 .../gpu/drm/i915/selftests/i915_gem_object.c | 150 +++ .../drm/i915/selftests/i915_live_selftests.h |1 + .../drm/i915/selftests/i915_mock_selftests.h |2 + .../drm/i915/selftests/intel_memory_region.c | 911 +++ .../gpu/drm/i915/selftests/mock_gem_device.c |8 +- drivers/gpu/drm/i915/selftests/mock_region.c | 75 ++ drivers/gpu/drm/i915/selftests/mock_region.h | 35 + include/drm/i915_drm.h|3 + include/uapi/drm/i915_drm.h | 94 +- 38 files changed, 4396 insertions(+), 188 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gem_buddy.c create mode 100644 drivers/gpu/drm/i915/i915_gem_buddy.h create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c create mode 100
[Intel-gfx] [RFC PATCH 38/42] drm/i915: treat shmem as a region
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_drv.h| 2 +
drivers/gpu/drm/i915/i915_gem.c| 89 ++
drivers/gpu/drm/i915/i915_gem_gtt.c| 11 ++-
drivers/gpu/drm/i915/intel_memory_region.c | 9 +++
4 files changed, 74 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8185ea126752..23f04e5a4b76 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2833,6 +2833,8 @@ int i915_gem_object_migrate(struct i915_gem_context *ctx,
struct drm_i915_gem_object *obj,
enum intel_region_id id);
+struct intel_memory_region *i915_gem_setup_smem(struct drm_i915_private *i915);
+
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
if (!atomic_read(&i915->mm.free_count))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 387eae998fbf..3c86909d55b9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2576,6 +2576,7 @@ bool i915_sg_trim(struct sg_table *orig_st)
static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+ struct intel_memory_region *mem = obj->memory_region;
const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned long i;
struct address_space *mapping;
@@ -2602,7 +2603,7 @@ static int i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (page_count > totalram_pages())
+ if (obj->base.size > resource_size(&mem->region))
return -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
@@ -4437,11 +4438,13 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_ops = {
.pwrite = i915_gem_object_pwrite_gtt,
.vmf_fill_pages = i915_gem_vmf_fill_pages_cpu,
+
+ .release = i915_gem_object_release_memory_region,
};
-static int i915_gem_object_create_shmem(struct drm_device *dev,
- struct drm_gem_object *obj,
- size_t size)
+static int __i915_gem_object_create_shmem(struct drm_device *dev,
+ struct drm_gem_object *obj,
+ resource_size_t size)
{
struct drm_i915_private *i915 = to_i915(dev);
unsigned long flags = VM_NORESERVE;
@@ -4463,31 +4466,22 @@ static int i915_gem_object_create_shmem(struct
drm_device *dev,
return 0;
}
-struct drm_i915_gem_object *
-i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
+static struct drm_i915_gem_object *
+i915_gem_object_create_shmem(struct intel_memory_region *mem,
+resource_size_t size,
+unsigned flags)
{
+ struct drm_i915_private *dev_priv = mem->i915;
struct drm_i915_gem_object *obj;
struct address_space *mapping;
- unsigned int cache_level;
gfp_t mask;
int ret;
- /* There is a prevalence of the assumption that we fit the object's
-* page count inside a 32bit _signed_ variable. Let's document this and
-* catch if we ever need to fix it. In the meantime, if you do spot
-* such a local variable, please consider fixing!
-*/
- if (size >> PAGE_SHIFT > INT_MAX)
- return ERR_PTR(-E2BIG);
-
- if (overflows_type(size, obj->base.size))
- return ERR_PTR(-E2BIG);
-
obj = i915_gem_object_alloc(dev_priv);
if (obj == NULL)
return ERR_PTR(-ENOMEM);
- ret = i915_gem_object_create_shmem(&dev_priv->drm, &obj->base, size);
+ ret = __i915_gem_object_create_shmem(&dev_priv->drm, &obj->base, size);
if (ret)
goto fail;
@@ -4520,13 +4514,9 @@ i915_gem_object_create(struct drm_i915_private
*dev_priv, u64 size)
* However, we maintain the display planes as UC, and so
* need to rebind when first used as such.
*/
- cache_level = I915_CACHE_LLC;
+ obj->cache_level = I915_CACHE_LLC;
else
- cache_level = I915_CACHE_NONE;
-
- i915_gem_object_set_cache_coherency(obj, cache_level);
-
- trace_i915_gem_object_create(obj);
+ obj->cache_level = I915_CACHE_NONE;
return obj;
@@ -4535,6 +4525,49 @@ i915_gem_object_create(struct drm_i915_private
*dev_priv, u64 size)
return ERR_PTR(ret);
}
+struct drm_i915_gem_object *
+i915_gem_object_create(struct drm_i915_private *i915, u64 size)
+{
+ return i915_gem_object_create_region(i915->regions[INTE
[Intel-gfx] [RFC PATCH 39/42] drm/i915: treat stolen as a region
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_drv.h| 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 14 +
drivers/gpu/drm/i915/i915_gem_stolen.c | 66 +++---
drivers/gpu/drm/i915/intel_memory_region.c | 2 +-
4 files changed, 62 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 23f04e5a4b76..46fd5fd64231 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3194,8 +3194,7 @@ int i915_gem_stolen_insert_node_in_range(struct
drm_i915_private *dev_priv,
u64 end);
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
struct drm_mm_node *node);
-int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
-void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
+struct intel_memory_region *i915_gem_setup_stolen(struct drm_i915_private
*i915);
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
resource_size_t size);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 84b2fa5608fb..f5d595c700f4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2802,8 +2802,6 @@ static void i915_gem_cleanup_memory_regions(struct
drm_i915_private *i915)
{
int i;
- i915_gem_cleanup_stolen(i915);
-
for (i = 0; i < ARRAY_SIZE(i915->regions); ++i) {
struct intel_memory_region *region = i915->regions[i];
@@ -2819,15 +2817,6 @@ static int i915_gem_init_memory_regions(struct
drm_i915_private *i915)
/* All platforms currently have system memory */
GEM_BUG_ON(!HAS_REGION(i915, REGION_SMEM));
- /*
-* Initialise stolen early so that we may reserve preallocated
-* objects for the BIOS to KMS transition.
-*/
- /* XXX: stolen will become a region at some point */
- err = i915_gem_init_stolen(i915);
- if (err)
- return err;
-
for (i = 0; i < ARRAY_SIZE(intel_region_map); i++) {
struct intel_memory_region *mem = NULL;
u32 type;
@@ -2840,6 +2829,9 @@ static int i915_gem_init_memory_regions(struct
drm_i915_private *i915)
case INTEL_SMEM:
mem = i915_gem_setup_smem(i915);
break;
+ case INTEL_STOLEN:
+ mem = i915_gem_setup_stolen(i915);
+ break;
}
if (IS_ERR(mem)) {
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 74a9661479ca..6ef94a32edf9 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -166,7 +166,7 @@ static int i915_adjust_stolen(struct drm_i915_private
*dev_priv,
return 0;
}
-void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
+static void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
{
if (!drm_mm_initialized(&dev_priv->mm.stolen))
return;
@@ -371,7 +371,7 @@ static void icl_get_stolen_reserved(struct drm_i915_private
*dev_priv,
}
}
-int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
+static int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
{
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
@@ -550,6 +550,9 @@ i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj)
i915_gem_stolen_remove_node(dev_priv, stolen);
kfree(stolen);
+
+ if (obj->memory_region)
+ i915_gem_object_release_memory_region(obj);
}
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
@@ -559,8 +562,8 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_stolen_ops = {
};
static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- struct drm_mm_node *stolen)
+__i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ struct drm_mm_node *stolen)
{
struct drm_i915_gem_object *obj;
unsigned int cache_level;
@@ -587,10 +590,12 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- resource_size_t size)
+static struct drm_i915_gem_object *
+_i915_gem_object_create_stolen(struct intel_memory_region *mem,
+ resource_size_t size,
+
[Intel-gfx] [RFC PATCH 36/42] drm/i915/lmem: include debugfs metrics
Useful for debugging.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_debugfs.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fed46fe19c03..2178c13213ef 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -435,6 +435,8 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
struct i915_ggtt *ggtt = &dev_priv->ggtt;
u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
+ u32 lmem_count, lmem_dpy_count;
+ u64 lmem_size, lmem_dpy_size;
struct drm_i915_gem_object *obj;
unsigned int page_sizes = 0;
char buf[80];
@@ -448,6 +450,7 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
mapped_size = mapped_count = 0;
purgeable_size = purgeable_count = 0;
huge_size = huge_count = 0;
+ lmem_size = lmem_count = lmem_dpy_size = lmem_dpy_count = 0;
spin_lock(&dev_priv->mm.obj_lock);
list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
@@ -469,6 +472,15 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
huge_size += obj->base.size;
page_sizes |= obj->mm.page_sizes.sg;
}
+
+ if (i915_gem_object_is_lmem(obj)) {
+ if (obj->pin_global) {
+ lmem_dpy_count++;
+ lmem_dpy_size += obj->base.size;
+ }
+ lmem_count++;
+ lmem_size += obj->base.size;
+ }
}
seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
@@ -497,6 +509,15 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
huge_size += obj->base.size;
page_sizes |= obj->mm.page_sizes.sg;
}
+
+ if (i915_gem_object_is_lmem(obj)) {
+ if (obj->pin_global) {
+ lmem_dpy_count++;
+ lmem_dpy_size += obj->base.size;
+ }
+ lmem_count++;
+ lmem_size += obj->base.size;
+ }
}
spin_unlock(&dev_priv->mm.obj_lock);
@@ -513,6 +534,12 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
dpy_count, dpy_size);
+ if (HAS_LMEM(dev_priv)) {
+ seq_printf(m, "%u LMEM objects, %llu bytes\n", lmem_count,
lmem_size);
+ seq_printf(m, "%u LMEM display objects (globally pinned), %llu
bytes\n",
+ lmem_dpy_count, lmem_dpy_size);
+ }
+
seq_printf(m, "%llu [%pa] gtt total\n",
ggtt->vm.total, &ggtt->mappable_end);
seq_printf(m, "Supported page sizes: %s\n",
--
2.20.1
___
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[Intel-gfx] [RFC PATCH 26/42] drm/i915: error capture with no ggtt slot
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fal back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
drivers/gpu/drm/i915/i915_gpu_error.c | 63 ---
2 files changed, 59 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3732f21148d3..045c6715d5a6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2763,13 +2763,15 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
if (ret)
return ret;
- /* Reserve a mappable slot for our lockless error capture */
- ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
- PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
- 0, ggtt->mappable_end,
- DRM_MM_INSERT_LOW);
- if (ret)
- return ret;
+ if (HAS_MAPPABLE_APERTURE(dev_priv)) {
+ /* Reserve a mappable slot for our lockless error capture */
+ ret = drm_mm_insert_node_in_range(&ggtt->vm.mm,
&ggtt->error_capture,
+ PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
+ 0, ggtt->mappable_end,
+ DRM_MM_INSERT_LOW);
+ if (ret)
+ return ret;
+ }
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
@@ -2791,7 +2793,8 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
return 0;
err:
- drm_mm_remove_node(&ggtt->error_capture);
+ if (drm_mm_node_allocated(&ggtt->error_capture))
+ drm_mm_remove_node(&ggtt->error_capture);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9a65341fec09..9ccd6cfa6c25 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -211,7 +211,7 @@ struct compress {
void *tmp;
};
-static bool compress_init(struct compress *c)
+static bool compress_init(struct compress *c, bool wc)
{
struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
@@ -227,7 +227,7 @@ static bool compress_init(struct compress *c)
}
c->tmp = NULL;
- if (i915_has_memcpy_from_wc())
+ if (wc && i915_has_memcpy_from_wc())
c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
return true;
@@ -328,10 +328,12 @@ static void err_compression_marker(struct
drm_i915_error_state_buf *m)
#else
struct compress {
+ bool wc;
};
-static bool compress_init(struct compress *c)
+static bool compress_init(struct compress *c, bool wc)
{
+ c->wc = wc;
return true;
}
@@ -347,7 +349,7 @@ static int compress_page(struct compress *c,
return -ENOMEM;
ptr = (void *)page;
- if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
+ if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
memcpy(ptr, src, PAGE_SIZE);
dst->pages[dst->page_count++] = ptr;
@@ -1013,7 +1015,6 @@ i915_error_object_create(struct drm_i915_private *i915,
struct compress compress;
unsigned long num_pages;
struct sgt_iter iter;
- dma_addr_t dma;
int ret;
if (!vma || !vma->pages)
@@ -1032,22 +1033,52 @@ i915_error_object_create(struct drm_i915_private *i915,
dst->page_count = 0;
dst->unused = 0;
- if (!compress_init(&compress)) {
+ if (!compress_init(&compress,
drm_mm_node_allocated(&ggtt->error_capture))) {
kfree(dst);
return NULL;
}
ret = -EINVAL;
- for_each_sgt_dma(dma, iter, vma->pages) {
+ if (drm_mm_node_allocated(&ggtt->error_capture)) {
void __iomem *s;
+ dma_addr_t dma;
- ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
+ for_each_sgt_dma(dma, iter, vma->pages) {
+ ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
- s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
- ret = compress_page(&compress, (void __force *)s, dst);
- io_mapping_unmap_atomic(s);
- if (ret)
- break;
+ s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
+ ret = compress_page(&compress, (void __force *)s, dst);
+ io_mapping_unmap_atomic(s);
+
+ if (ret)
+
[Intel-gfx] [RFC PATCH 24/42] drm/i915: expose missing map_gtt support to users
From: Daniele Ceraolo Spurio Done by returning -ENODEV from the map_gtt version ioctl. Cc: Antonio Argenziano Cc: Matthew Auld Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6630212f2faf..dc446430a340 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -390,6 +390,8 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, return value; break; case I915_PARAM_MMAP_GTT_VERSION: + if (!HAS_MAPPABLE_APERTURE(dev_priv)) + return -ENODEV; /* Though we've started our numbering from 1, and so class all * earlier versions as 0, in effect their value is undefined as * the ioctl will report EINVAL for the unknown param! -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 29/42] drm/i915: Set correct vmf source pages for gem objects
From: Abdiel Janulgue
This allows page-faults from objects with different backing stores
from a single interface.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 58 +++-
drivers/gpu/drm/i915/i915_gem_object.h | 6 ++-
drivers/gpu/drm/i915/intel_region_lmem.c | 28
5 files changed, 92 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dc446430a340..b1200d7ebd13 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2944,7 +2944,7 @@ static const struct file_operations i915_driver_fops = {
.open = drm_open,
.release = drm_release,
.unlocked_ioctl = drm_ioctl,
- .mmap = drm_gem_mmap,
+ .mmap = i915_gem_mmap,
.poll = drm_poll,
.read = drm_read,
.compat_ioctl = i915_compat_ioctl,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 772fffa87545..065953a9264f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3071,6 +3071,7 @@ int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv,
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
+int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma);
vm_fault_t i915_gem_fault(struct vm_fault *vmf);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
unsigned int flags,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 95e31529a738..48dbb57fbc6d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
#include "i915_drv.h"
#include "i915_gem_clflush.h"
@@ -377,6 +378,7 @@ static const struct drm_i915_gem_object_ops
i915_gem_phys_ops = {
.get_pages = i915_gem_object_get_pages_phys,
.put_pages = i915_gem_object_put_pages_phys,
.release = i915_gem_object_release_phys,
+ .vmf_fill_pages = i915_gem_vmf_fill_pages_cpu,
};
static const struct drm_i915_gem_object_ops i915_gem_object_ops;
@@ -1938,7 +1940,7 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
goto err_unlock;
}
- ret = __vmf_fill_pages_gtt(obj, vmf, page_offset);
+ ret = obj->ops->vmf_fill_pages(obj, vmf, page_offset);
err_unlock:
mutex_unlock(&dev->struct_mutex);
@@ -2166,6 +2168,26 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void
*data,
return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
}
+int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ int ret;
+ struct drm_i915_gem_object *obj;
+
+ ret = drm_gem_mmap(filp, vma);
+ if (ret < 0)
+ return ret;
+
+ obj = to_intel_bo(vma->vm_private_data);
+ if (obj->memory_region) {
+ if (obj->mmap_origin == I915_MMAP_ORIGIN_OFFSET) {
+ vma->vm_flags &= ~VM_PFNMAP;
+ vma->vm_flags |= VM_MIXEDMAP;
+ }
+ }
+
+ return ret;
+}
+
/* Immediately discard the backing storage */
static void
i915_gem_object_truncate(struct drm_i915_gem_object *obj)
@@ -4194,6 +4216,37 @@ void i915_gem_object_init(struct drm_i915_gem_object
*obj,
i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
}
+int i915_gem_vmf_fill_pages_cpu(struct drm_i915_gem_object *obj,
+struct vm_fault *vmf,
+pgoff_t page_offset)
+{
+ struct vm_area_struct *area = vmf->vma;
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct page *page;
+ unsigned long pfn;
+ vm_fault_t vmf_ret;
+ pgoff_t pg_off = (vmf->address - area->vm_start) >> PAGE_SHIFT;
+
+ if (HAS_MAPPABLE_APERTURE(dev_priv))
+ return __vmf_fill_pages_gtt(obj, vmf, page_offset);
+
+ page = i915_gem_object_get_page(obj, pg_off);
+ pfn = page_to_pfn(page);
+
+ vmf_ret = vmf_insert_mixed(area, vmf->address,
+ __pfn_to_pfn_t(pfn, PFN_DEV));
+ if (vmf_ret & VM_FAULT_ERROR)
+ return vm_fault_to_errno(vmf_ret, 0);
+
+ if (!obj->userfault_count++)
+ list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
+
+ GEM_BUG_ON(!obj->userfault_count);
+
+ return 0;
+}
+
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
I915_GEM_OBJECT_IS_SHRINKABLE,
@@ -4202,6 +4255,7
[Intel-gfx] [RFC PATCH 17/42] drm/i915/lmem: support kernel mapping
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c | 18 ++-
drivers/gpu/drm/i915/intel_memory_region.h| 3 +
drivers/gpu/drm/i915/intel_region_lmem.c | 24
drivers/gpu/drm/i915/intel_region_lmem.h | 5 +
drivers/gpu/drm/i915/selftests/huge_pages.c | 3 +-
.../drm/i915/selftests/intel_memory_region.c | 107 +-
6 files changed, 148 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 33699b3dc395..3f319524beed 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2257,7 +2257,9 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
void *ptr;
ptr = page_mask_bits(obj->mm.mapping);
- if (is_vmalloc_addr(ptr))
+ if (i915_gem_object_is_lmem(obj))
+ io_mapping_unmap(ptr);
+ else if (is_vmalloc_addr(ptr))
vunmap(ptr);
else
kunmap(kmap_to_page(ptr));
@@ -2625,7 +2627,7 @@ int __i915_gem_object_get_pages(struct
drm_i915_gem_object *obj)
}
/* The 'mapping' part of i915_gem_object_pin_map() below */
-static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
+static void *i915_gem_object_map(struct drm_i915_gem_object *obj,
enum i915_map_type type)
{
unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
@@ -2638,6 +2640,11 @@ static void *i915_gem_object_map(const struct
drm_i915_gem_object *obj,
pgprot_t pgprot;
void *addr;
+ if (i915_gem_object_is_lmem(obj)) {
+ /* XXX: we are ignoring the type here -- this is simply wc */
+ return i915_gem_object_lmem_io_map(obj, 0, obj->base.size);
+ }
+
/* A single page can always be kmapped */
if (n_pages == 1 && type == I915_MAP_WB)
return kmap(sg_page(sgt->sgl));
@@ -2683,7 +2690,8 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
void *ptr;
int ret;
- if (unlikely(!i915_gem_object_has_struct_page(obj)))
+ if (unlikely(!i915_gem_object_has_struct_page(obj) &&
+!i915_gem_object_is_lmem(obj)))
return ERR_PTR(-ENXIO);
ret = mutex_lock_interruptible(&obj->mm.lock);
@@ -2715,7 +2723,9 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
goto err_unpin;
}
- if (is_vmalloc_addr(ptr))
+ if (i915_gem_object_is_lmem(obj))
+ io_mapping_unmap(ptr);
+ else if (is_vmalloc_addr(ptr))
vunmap(ptr);
else
kunmap(kmap_to_page(ptr));
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h
b/drivers/gpu/drm/i915/intel_memory_region.h
index b1546afb0b6e..7754989ad165 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -115,6 +115,9 @@ void i915_memory_region_put_pages_buddy(struct
drm_i915_gem_object *obj,
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
+unsigned long i915_gem_object_lmem_io_pfn(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
struct intel_memory_region *
intel_memory_region_create(struct drm_i915_private *i915,
resource_size_t start,
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index b398becb2733..c8bee0c18c88 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -65,6 +65,30 @@ static const struct intel_memory_region_ops region_lmem_ops
= {
.object_create = region_lmem_object_create,
};
+/* XXX: Time to vfunc your life up? */
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_atomic_wc(&obj->memory_region->iomap, offset);
+}
+
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->memory_region->iomap, offset, size);
+}
+
unsigned long i915_gem_object_lmem_io_pfn(struct drm_i915_gem_object *obj,
[Intel-gfx] [RFC PATCH 22/42] drm/i915: define HAS_MAPPABLE_APERTURE
From: Daniele Ceraolo Spurio The following patches in the series will use it to avoid certain operations when aperture is not available in HW. Signed-off-by: Daniele Ceraolo Spurio Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index bdf85e901268..772fffa87545 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2481,6 +2481,8 @@ static inline unsigned int i915_sg_segment_size(void) #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ (INTEL_INFO(dev_priv)->display.overlay_needs_physical) +#define HAS_MAPPABLE_APERTURE(dev_priv) (dev_priv->ggtt.mappable_end > 0) + /* Early gen2 have a totally busted CS tlb and require pinned batches. */ #define HAS_BROKEN_CS_TLB(dev_priv)(IS_I830(dev_priv) || IS_I845G(dev_priv)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 16/42] drm/i915: support basic object migration
We are going want to able to move objects between different regions
like system memory and local memory. In the future everything should
be just another region.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_gem.c | 121 +
.../drm/i915/selftests/intel_memory_region.c | 127 ++
3 files changed, 253 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b9d01caa3430..bdf85e901268 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2822,6 +2822,11 @@ i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv,
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
void i915_gem_free_object(struct drm_gem_object *obj);
+int i915_gem_object_prepare_move(struct drm_i915_gem_object *obj);
+int i915_gem_object_migrate(struct i915_gem_context *ctx,
+ struct drm_i915_gem_object *obj,
+ enum intel_region_id id);
+
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
if (!atomic_read(&i915->mm.free_count))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 501714fbf92f..33699b3dc395 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4626,6 +4626,127 @@ int i915_gem_object_clear_blt(struct i915_gem_context
*ctx,
return i915_gem_object_fill_blt(ctx, obj, 0);
}
+int i915_gem_object_prepare_move(struct drm_i915_gem_object *obj)
+{
+ int err;
+
+ lockdep_assert_held(&obj->base.dev->struct_mutex);
+
+ if (obj->mm.madv != I915_MADV_WILLNEED)
+ return -EINVAL;
+
+ if (i915_gem_object_needs_bit17_swizzle(obj))
+ return -EINVAL;
+
+ if (atomic_read(&obj->mm.pages_pin_count) > obj->bind_count)
+ return -EBUSY;
+
+ if (obj->pin_global)
+ return -EBUSY;
+
+ i915_gem_release_mmap(obj);
+
+ GEM_BUG_ON(obj->mm.mapping);
+ GEM_BUG_ON(obj->base.filp && mapping_mapped(obj->base.filp->f_mapping));
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_LOCKED |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ if (err)
+ return err;
+
+ return i915_gem_object_unbind(obj);
+}
+
+int i915_gem_object_migrate(struct i915_gem_context *ctx,
+ struct drm_i915_gem_object *obj,
+ enum intel_region_id id)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct drm_i915_gem_object *donor;
+ struct intel_memory_region *mem;
+ int err = 0;
+
+ lockdep_assert_held(&i915->drm.struct_mutex);
+
+ GEM_BUG_ON(id >= INTEL_MEMORY_UKNOWN);
+ GEM_BUG_ON(obj->memory_region->id == id);
+ GEM_BUG_ON(obj->mm.madv != I915_MADV_WILLNEED);
+
+ mem = i915->regions[id];
+
+ donor = i915_gem_object_create_region(mem, obj->base.size, 0);
+ if (IS_ERR(donor))
+ return PTR_ERR(donor);
+
+ /* Copy backing-pages if we have to */
+ if (i915_gem_object_has_pages(obj)) {
+ struct sg_table *pages;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto err_put_donor;
+
+ err = i915_gem_object_copy_blt(ctx, obj, donor);
+ if (err)
+ goto err_put_donor;
+
+ i915_retire_requests(i915);
+
+ i915_gem_object_unbind(donor);
+ err = i915_gem_object_unbind(obj);
+ if (err)
+ goto err_put_donor;
+
+ mutex_lock(&obj->mm.lock);
+
+ pages = fetch_and_zero(&obj->mm.pages);
+ obj->ops->put_pages(obj, pages);
+
+ obj->mm.pages = __i915_gem_object_unset_pages(donor);
+ memcpy(&obj->mm.page_sizes, &donor->mm.page_sizes,
+ sizeof(struct i915_page_sizes));
+
+ obj->mm.get_page.sg_pos = obj->mm.pages->sgl;
+ obj->mm.get_page.sg_idx = 0;
+ __i915_gem_object_reset_page_iter(obj);
+
+ mutex_unlock(&obj->mm.lock);
+ }
+
+ if (obj->ops->release)
+ obj->ops->release(obj);
+
+ /* We need still need a little special casing for shmem */
+ if (obj->base.filp)
+ fput(fetch_and_zero(&obj->base.filp));
+ else
+ obj->base.filp = fetch_and_zero(&donor->base.filp);
+
+ obj->base.size = donor->base.size;
+ obj->memory_region = mem;
+ obj->flags = donor->flags;
+ obj->ops = donor-
[Intel-gfx] [RFC PATCH 18/42] drm/i915/lmem: support CPU relocations
We need to support doing relocations from the CPU when dealing with LMEM
objects.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 67 ++
1 file changed, 56 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 02adcaf6ebea..390691128c1d 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -265,6 +265,7 @@ struct i915_execbuffer {
bool has_llc : 1;
bool has_fence : 1;
bool needs_unfenced : 1;
+ bool is_lmem : 1;
struct i915_request *rq;
u32 *rq_cmd;
@@ -973,6 +974,7 @@ static void reloc_cache_init(struct reloc_cache *cache,
cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
cache->has_fence = cache->gen < 4;
cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
+ cache->is_lmem = false;
cache->node.allocated = false;
cache->rq = NULL;
cache->rq_size = 0;
@@ -1027,16 +1029,23 @@ static void reloc_cache_reset(struct reloc_cache *cache)
i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object
*)cache->node.mm);
} else {
wmb();
- io_mapping_unmap_atomic((void __iomem *)vaddr);
- if (cache->node.allocated) {
- struct i915_ggtt *ggtt = cache_to_ggtt(cache);
-
- ggtt->vm.clear_range(&ggtt->vm,
-cache->node.start,
-cache->node.size);
- drm_mm_remove_node(&cache->node);
+
+ if (cache->is_lmem) {
+ io_mapping_unmap_atomic((void __iomem *)vaddr);
+ i915_gem_object_unpin_pages((struct drm_i915_gem_object
*)cache->node.mm);
+ cache->is_lmem = false;
} else {
- i915_vma_unpin((struct i915_vma *)cache->node.mm);
+ io_mapping_unmap_atomic((void __iomem *)vaddr);
+ if (cache->node.allocated) {
+ struct i915_ggtt *ggtt = cache_to_ggtt(cache);
+
+ ggtt->vm.clear_range(&ggtt->vm,
+cache->node.start,
+cache->node.size);
+ drm_mm_remove_node(&cache->node);
+ } else {
+ i915_vma_unpin((struct i915_vma
*)cache->node.mm);
+ }
}
}
@@ -1076,6 +1085,38 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,
return vaddr;
}
+static void *reloc_lmem(struct drm_i915_gem_object *obj,
+ struct reloc_cache *cache,
+ unsigned long page)
+{
+ void *vaddr;
+ int err;
+
+ GEM_BUG_ON(use_cpu_reloc(cache, obj));
+
+ if (cache->vaddr) {
+ io_mapping_unmap_atomic((void __force __iomem *)
unmask_page(cache->vaddr));
+ } else {
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ if (err)
+ return ERR_PTR(err);
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return ERR_PTR(err);
+
+ cache->node.mm = (void *)obj;
+ cache->is_lmem = true;
+ }
+
+ vaddr = i915_gem_object_lmem_io_map_page(obj, page);
+
+ cache->vaddr = (unsigned long)vaddr;
+ cache->page = page;
+
+ return vaddr;
+}
+
static void *reloc_iomap(struct drm_i915_gem_object *obj,
struct reloc_cache *cache,
unsigned long page)
@@ -1150,8 +1191,12 @@ static void *reloc_vaddr(struct drm_i915_gem_object *obj,
vaddr = unmask_page(cache->vaddr);
} else {
vaddr = NULL;
- if ((cache->vaddr & KMAP) == 0)
- vaddr = reloc_iomap(obj, cache, page);
+ if ((cache->vaddr & KMAP) == 0) {
+ if (i915_gem_object_is_lmem(obj))
+ vaddr = reloc_lmem(obj, cache, page);
+ else
+ vaddr = reloc_iomap(obj, cache, page);
+ }
if (!vaddr)
vaddr = reloc_kmap(obj, cache, page);
}
--
2.20.1
___
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[Intel-gfx] [RFC PATCH 14/42] drm/i915: introduce kernel blitter_context
We may be without a context to perform various internal blitter
operations, for example when performing object migration. Piggybacking
off the kernel_context is probably a bad idea, since it has other uses.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_context.c | 13 +
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 4
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index feec3bab0f5f..5b39af57c36c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1544,6 +1544,8 @@ struct drm_i915_private {
struct intel_engine_cs *engine[I915_NUM_ENGINES];
/* Context used internally to idle the GPU and setup initial state */
struct i915_gem_context *kernel_context;
+ /* Context used internally for various blitting operations */
+ struct i915_gem_context *blitter_context;
/* Context only to be used for injecting preemption commands */
struct i915_gem_context *preempt_context;
struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 280813a4bf82..e814030dd89a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -583,6 +583,18 @@ int i915_gem_contexts_init(struct drm_i915_private
*dev_priv)
GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
dev_priv->kernel_context = ctx;
+ ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_NORMAL);
+ if (IS_ERR(ctx)) {
+ DRM_ERROR("Failed to create blitter global context\n");
+ return PTR_ERR(ctx);
+ }
+
+ /*
+* XXX: one idea here is do s/kernel_context/idle_context/, then use the
+* kernel_context for doing things like blitting...
+*/
+ dev_priv->blitter_context = ctx;
+
/* highest priority; preempting task */
if (needs_preempt_context(dev_priv)) {
ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
@@ -615,6 +627,7 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
if (i915->preempt_context)
destroy_kernel_context(&i915->preempt_context);
+ destroy_kernel_context(&i915->blitter_context);
destroy_kernel_context(&i915->kernel_context);
/* Must free all deferred contexts (via flush_workqueue) first */
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index f8901cd12180..0b59246c99c8 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -248,6 +248,10 @@ struct drm_i915_private *mock_gem_device(void)
if (!i915->engine[RCS])
goto err_context;
+ i915->blitter_context = mock_context(i915, NULL);
+ if (!i915->blitter_context)
+ goto err_context;
+
mutex_unlock(&i915->drm.struct_mutex);
WARN_ON(i915_gemfs_init(i915));
--
2.20.1
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[Intel-gfx] [RFC PATCH 13/42] drm/i915: support object clearing via blitter engine
Support clearing objects via the blitter engine. This is needed for LMEM
where we need to clear the backing store before handing the object to
userspace.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 151 ++
drivers/gpu/drm/i915/intel_gpu_commands.h | 1 +
.../gpu/drm/i915/selftests/i915_gem_object.c | 70
4 files changed, 224 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0ed000d52aa..feec3bab0f5f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2807,6 +2807,8 @@ void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
void i915_gem_object_init(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_object_ops *ops);
+int i915_gem_object_clear_blt(struct i915_gem_context *ctx,
+ struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7f044b643a75..032d4334c0f1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4288,6 +4288,157 @@ static bool discard_backing_storage(struct
drm_i915_gem_object *obj)
return atomic_long_read(&obj->base.filp->f_count) == 1;
}
+static struct i915_vma *
+__i915_gem_fill_blt(struct i915_vma *vma, u32 value)
+{
+ struct drm_i915_private *i915 = to_i915(vma->obj->base.dev);
+ const int gen = INTEL_GEN(i915);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *batch;
+ u32 *cmd;
+ int err;
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto err;
+ }
+
+ if (gen >= 8) {
+ *cmd++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA;
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = vma->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE /
4;
+ *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = value;
+ *cmd++ = MI_NOOP;
+ } else {
+ *cmd++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
+ *cmd++ = vma->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE;
+ *cmd++ = vma->node.start;
+ *cmd++ = value;
+ *cmd++ = MI_NOOP;
+ }
+
+ *cmd = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_unpin_map(obj);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ goto err;
+
+ batch = i915_vma_instance(obj, vma->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err;
+
+ return batch;
+
+err:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static int i915_gem_fill_blt(struct i915_gem_context *ctx,
+struct i915_vma *vma,
+u32 value)
+{
+ struct drm_i915_private *i915 = to_i915(vma->obj->base.dev);
+ struct intel_engine_cs *engine = i915->engine[BCS];
+ struct i915_request *rq;
+ struct i915_vma *batch;
+ int flags = 0;
+ int err;
+
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ if (err)
+ return err;
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ batch = __i915_gem_fill_blt(vma, value);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_request;
+ }
+
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unpin(batch);
+ i915_vma_close(batch);
+ if (err) {
+ i915_gem_object_put(batch->obj);
+ goto err_request;
+ }
+
+ i915_gem_object_set_active_reference(batch->obj);
+
+ err = engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ flags);
+ if (err)
+ goto err_request;
+
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ if (err)
+ i915_request_skip(rq, err);
+
+err_request:
+ i915_request_add(rq);
+ return err;
+}
+
+static int
[Intel-gfx] [RFC PATCH 02/42] drm/i915: enable platform support for 1G pages
For gen8+ platforms which support the 48b PPGTT, enable support for 1G
pages. Also enable for mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c4d6b8da9b03..4a7b587e9a92 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -431,7 +431,8 @@ static const struct intel_device_info
intel_haswell_gt3_info = {
GEN(8), \
BDW_COLORS, \
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_2M, \
+ I915_GTT_PAGE_SIZE_2M | \
+ I915_GTT_PAGE_SIZE_1G, \
.has_logical_ring_contexts = 1, \
.ppgtt = INTEL_PPGTT_FULL_4LVL, \
.has_64bit_reloc = 1, \
@@ -491,7 +492,8 @@ static const struct intel_device_info intel_cherryview_info
= {
#define GEN9_DEFAULT_PAGE_SIZES \
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_64K | \
- I915_GTT_PAGE_SIZE_2M
+ I915_GTT_PAGE_SIZE_2M | \
+ I915_GTT_PAGE_SIZE_1G
#define GEN9_FEATURES \
GEN8_FEATURES, \
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index fc516a2970f4..876f4e6dadac 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -182,7 +182,8 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->page_sizes =
I915_GTT_PAGE_SIZE_4K |
I915_GTT_PAGE_SIZE_64K |
- I915_GTT_PAGE_SIZE_2M;
+ I915_GTT_PAGE_SIZE_2M |
+ I915_GTT_PAGE_SIZE_1G;
mock_uncore_init(i915);
i915_gem_init__mm(i915);
--
2.20.1
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[Intel-gfx] [RFC PATCH 05/42] drm/i915/region: support basic eviction
Support basic eviction for regions.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 16
drivers/gpu/drm/i915/i915_gem_object.h| 7 ++
drivers/gpu/drm/i915/i915_gem_shrinker.c | 59 ++
drivers/gpu/drm/i915/intel_memory_region.c| 40 +-
drivers/gpu/drm/i915/intel_memory_region.h| 7 ++
.../drm/i915/selftests/intel_memory_region.c | 76 +++
drivers/gpu/drm/i915/selftests/mock_region.c | 1 +
8 files changed, 204 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0bea7d889284..3df27769b978 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3196,6 +3196,8 @@ void i915_gem_shrinker_register(struct drm_i915_private
*i915);
void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
struct mutex *mutex);
+int i915_gem_shrink_memory_region(struct intel_memory_region *mem,
+ resource_size_t target);
/* i915_gem_tiling.c */
static inline bool i915_gem_object_needs_bit17_swizzle(struct
drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 92768ab294a4..7f044b643a75 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4095,6 +4095,22 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void
*data,
!i915_gem_object_has_pages(obj))
i915_gem_object_truncate(obj);
+ if (obj->memory_region) {
+ mutex_lock(&obj->memory_region->obj_lock);
+
+ switch (obj->mm.madv) {
+ case I915_MADV_WILLNEED:
+ list_move(&obj->region_link,
&obj->memory_region->objects);
+ break;
+ default:
+ list_move(&obj->region_link,
+ &obj->memory_region->purgeable);
+ break;
+ }
+
+ mutex_unlock(&obj->memory_region->obj_lock);
+ }
+
args->retained = obj->mm.madv != __I915_MADV_PURGED;
mutex_unlock(&obj->mm.lock);
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index ac52f61e8ad1..76947a6f49f1 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -95,6 +95,13 @@ struct drm_i915_gem_object {
* List of memory region blocks allocated for this object.
*/
struct list_head blocks;
+ /**
+* Element within memory_region->objects or memory_region->purgeable if
+* the object is marked as DONTNEED. Access is protected by
+* memory_region->obj_lock.
+*/
+ struct list_head region_link;
+ struct list_head tmp_link;
struct {
/**
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 6da795c7e62e..713c6c93cf30 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -308,6 +308,65 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private
*i915)
return freed;
}
+int i915_gem_shrink_memory_region(struct intel_memory_region *mem,
+ resource_size_t target)
+{
+ struct drm_i915_private *i915 = mem->i915;
+ struct drm_i915_gem_object *obj, *on;
+ resource_size_t found;
+ LIST_HEAD(purgeable);
+ bool unlock;
+ int err;
+
+ if (!shrinker_lock(i915, 0, &unlock))
+ return 0;
+
+ i915_retire_requests(i915);
+
+ err = 0;
+ found = 0;
+
+ mutex_lock(&mem->obj_lock);
+
+ list_for_each_entry(obj, &mem->purgeable, region_link) {
+ if (!i915_gem_object_has_pages(obj))
+ continue;
+
+ if (READ_ONCE(obj->pin_global))
+ continue;
+
+ if (atomic_read(&obj->mm.pages_pin_count) > obj->bind_count)
+ continue;
+
+ list_add(&obj->tmp_link, &purgeable);
+
+ found += obj->base.size;
+ if (found >= target)
+ goto found;
+ }
+
+ err = -ENOSPC;
+found:
+ mutex_unlock(&mem->obj_lock);
+
+ list_for_each_entry_safe(obj, on, &purgeable, tmp_link) {
+ if (!err)
+ err = i915_gem_object_unbind(obj);
+ if (!err) {
+ __i915_gem_object_put_pages(obj,
+ I915_MM_SHRINKER);
+ if (!i915_gem_object_has_pages(obj))
+ obj->mm.madv = __I915_MADV_PURGED;
+
[Intel-gfx] [RFC PATCH 11/42] drm/i915/selftests: exercise writes to LMEM
Quick and dirty test to exercise writing through LMEM from the GPU/CPU.
We currently don't have an LMEM region so these tests should just skip
for now.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../drm/i915/selftests/intel_memory_region.c | 225 ++
1 file changed, 225 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 08fe6e064361..210ec6fec19a 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -362,6 +362,201 @@ static int igt_mock_volatile(void *arg)
return err;
}
+static struct i915_vma *
+igt_gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
+{
+ struct drm_i915_private *i915 = to_i915(vma->obj->base.dev);
+ const int gen = INTEL_GEN(vma->vm->i915);
+ unsigned int count = vma->size >> PAGE_SHIFT;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *batch;
+ unsigned int size;
+ u32 *cmd;
+ int n;
+ int err;
+
+ size = (1 + 4 * count) * sizeof(u32);
+ size = round_up(size, PAGE_SIZE);
+ obj = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto err;
+ }
+
+ offset += vma->node.start;
+
+ for (n = 0; n < count; n++) {
+ if (gen >= 8) {
+ *cmd++ = MI_STORE_DWORD_IMM_GEN4;
+ *cmd++ = lower_32_bits(offset);
+ *cmd++ = upper_32_bits(offset);
+ *cmd++ = val;
+ } else if (gen >= 4) {
+ *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
+ (gen < 6 ? 1 << 22 : 0);
+ *cmd++ = 0;
+ *cmd++ = offset;
+ *cmd++ = val;
+ } else {
+ *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
+ *cmd++ = offset;
+ *cmd++ = val;
+ }
+
+ offset += PAGE_SIZE;
+ }
+
+ *cmd = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_unpin_map(obj);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ goto err;
+
+ batch = i915_vma_instance(obj, vma->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err;
+
+ return batch;
+
+err:
+ i915_gem_object_put(obj);
+
+ return ERR_PTR(err);
+}
+
+static int igt_gpu_write(struct i915_vma *vma,
+struct i915_gem_context *ctx,
+struct intel_engine_cs *engine,
+u32 dword,
+u32 value)
+{
+ struct i915_request *rq;
+ struct i915_vma *batch;
+ int flags = 0;
+ int err;
+
+ GEM_BUG_ON(!intel_engine_can_store_dword(engine));
+
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ if (err)
+ return err;
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ batch = igt_gpu_write_dw(vma, dword * sizeof(u32), value);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_request;
+ }
+
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unpin(batch);
+ i915_vma_close(batch);
+ if (err)
+ goto err_request;
+
+ i915_gem_object_set_active_reference(batch->obj);
+
+ err = engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ flags);
+ if (err)
+ goto err_request;
+
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ if (err)
+ i915_request_skip(rq, err);
+
+err_request:
+ i915_request_add(rq);
+
+ return err;
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = (void __force *)
io_mapping_map_atomic_wc(&obj->memory_region->iomap,
+
i915_gem_object_get_dma_address(obj, n));
+
+ read_val = ioread32(base + dword
[Intel-gfx] [RFC PATCH 08/42] drm/i915: Add memory region information to device_info
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 12
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3df27769b978..3093a8814f8e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2520,6 +2520,8 @@ static inline unsigned int i915_sg_segment_size(void)
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+
/*
* For now, anything with a GuC requires uCode loading, and then supports
* command submission once loaded. But these are logically independent
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4a7b587e9a92..19c98215791e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -85,6 +85,9 @@
#define GEN_DEFAULT_PAGE_SIZES \
.page_sizes = I915_GTT_PAGE_SIZE_4K
+#define GEN_DEFAULT_REGIONS \
+ .memory_regions = REGION_SMEM | REGION_STOLEN
+
#define GEN2_FEATURES \
GEN(2), \
.num_pipes = 1, \
@@ -97,6 +100,7 @@
.ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
+ GEN_DEFAULT_REGIONS, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -136,6 +140,7 @@ static const struct intel_device_info intel_i865g_info = {
.ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
+ GEN_DEFAULT_REGIONS, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -213,6 +218,7 @@ static const struct intel_device_info intel_pineview_info =
{
.ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
+ GEN_DEFAULT_REGIONS, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -262,6 +268,7 @@ static const struct intel_device_info intel_gm45_info = {
.has_coherent_ggtt = true, \
/* ilk does support rc6, but we do not implement [power] contexts */ \
.has_rc6 = 0, \
+ GEN_DEFAULT_REGIONS, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -289,6 +296,7 @@ static const struct intel_device_info intel_ironlake_m_info
= {
.has_rc6 = 1, \
.has_rc6p = 1, \
.ppgtt = INTEL_PPGTT_ALIASING, \
+ GEN_DEFAULT_REGIONS, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -334,6 +342,7 @@ static const struct intel_device_info
intel_sandybridge_m_gt2_info = {
.has_rc6 = 1, \
.has_rc6p = 1, \
.ppgtt = INTEL_PPGTT_FULL, \
+ GEN_DEFAULT_REGIONS, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
@@ -391,6 +400,7 @@ static const struct intel_device_info intel_valleyview_info
= {
.has_coherent_ggtt = false,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
.display_mmio_offset = VLV_DISPLAY_BASE,
+ GEN_DEFAULT_REGIONS,
GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_PIPEOFFSETS,
CURSOR_OFFSETS
@@ -483,6 +493,7 @@ static const struct intel_device_info intel_cherryview_info
= {
.has_snoop = true,
.has_coherent_ggtt = false,
.display_mmio_offset = VLV_DISPLAY_BASE,
+ GEN_DEFAULT_REGIONS,
GEN_DEFAULT_PAGE_SIZES,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -559,6 +570,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.has_snoop = true, \
.has_coherent_ggtt = false, \
.display.has_ipc = 1, \
+ GEN_DEFAULT_REGIONS, \
GEN9_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index e8b8661df746..4179f6a66443 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ struct intel_device_info {
} display;
u16 ddb_size; /* in blocks */
+ u32 memory_regions;
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 03/42] drm/i915: buddy allocator
Really simply buddy allocator.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_gem_buddy.c | 206 +
drivers/gpu/drm/i915/i915_gem_buddy.h | 118 ++
.../gpu/drm/i915/selftests/i915_gem_buddy.c | 209 ++
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
5 files changed, 535 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_gem_buddy.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_buddy.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_buddy.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1787e1299b1b..e5ce813d1936 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -61,6 +61,7 @@ i915-y += \
i915_active.o \
i915_cmd_parser.o \
i915_gem_batch_pool.o \
+ i915_gem_buddy.o \
i915_gem_clflush.o \
i915_gem_context.o \
i915_gem_dmabuf.o \
diff --git a/drivers/gpu/drm/i915/i915_gem_buddy.c
b/drivers/gpu/drm/i915/i915_gem_buddy.c
new file mode 100644
index ..4dc688c091a2
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_buddy.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+
+#include "i915_gem_buddy.h"
+#include "i915_gem.h"
+
+int i915_gem_buddy_init(struct i915_gem_buddy_mm *mm, u64 size, u64 min_size)
+{
+ unsigned int i;
+
+ /*
+* XXX: if not a power of 2, maybe split into power of 2 blocks,
+* effectively having multiple roots, similar to if we had a global
+* MAX_ORDER.
+*/
+ size = rounddown_pow_of_two(size);
+ min_size = roundup_pow_of_two(min_size);
+
+ if (size < min_size)
+ return -EINVAL;
+
+ if (min_size < PAGE_SIZE)
+ return -EINVAL;
+
+ mm->max_order = ilog2(size) - ilog2(min_size);
+ mm->min_size = min_size;
+
+ mm->free_list = kmalloc_array(mm->max_order + 1,
+ sizeof(struct list_head),
+ GFP_KERNEL);
+ if (!mm->free_list)
+ return -ENOMEM;
+
+ for (i = 0; i <= mm->max_order; ++i)
+ INIT_LIST_HEAD(&mm->free_list[i]);
+
+ mm->blocks = KMEM_CACHE(i915_gem_buddy_block, SLAB_HWCACHE_ALIGN);
+ if (!mm->blocks)
+ goto out_free_list;
+
+ mm->root = kmem_cache_zalloc(mm->blocks, GFP_KERNEL);
+ if (!mm->root)
+ goto out_free_blocks;
+
+ mm->root->header = mm->max_order;
+
+ list_add(&mm->root->link, &mm->free_list[mm->max_order]);
+
+ return 0;
+
+out_free_blocks:
+ kmem_cache_destroy(mm->blocks);
+out_free_list:
+ kfree(mm->free_list);
+
+ return -ENOMEM;
+}
+
+void i915_gem_buddy_fini(struct i915_gem_buddy_mm *mm)
+{
+ if (WARN_ON(i915_gem_buddy_block_allocated(mm->root)))
+ return;
+
+ kfree(mm->free_list);
+ kmem_cache_free(mm->blocks, mm->root);
+ kmem_cache_destroy(mm->blocks);
+}
+
+/*
+ * The 'order' here means:
+ *
+ * 0 = 2^0 * mm->min_size
+ * 1 = 2^1 * mm->min_size
+ * 2 = 2^2 * mm->min_size
+ * ...
+ */
+struct i915_gem_buddy_block *
+i915_gem_buddy_alloc(struct i915_gem_buddy_mm *mm, unsigned int order)
+{
+ struct i915_gem_buddy_block *block = NULL;
+ struct i915_gem_buddy_block *root;
+ unsigned int i;
+
+ for (i = order; i <= mm->max_order; ++i) {
+ block = list_first_entry_or_null(&mm->free_list[i],
+struct i915_gem_buddy_block,
+link);
+ if (block)
+ break;
+ }
+
+ if (!bl
