Re: [Intel-gfx] [PATCH 2/7] drm/i915: Remove (pipe == crtc->index) assumption
On 2020-02-04 at 16:36:17 +0200, Ville Syrjälä wrote:
> On Tue, Feb 04, 2020 at 04:59:22PM +0530, Anshuman Gupta wrote:
> > we can't have (pipe == crtc->index) assumption in
> > driver in order to support 3 non-contiguous
> > display pipe system.
> >
> > FIXME: Remove the WARN_ON(drm_crtc_index(&crtc->base) != crtc->pipe)
> > till we won't fix all such assumption.
> >
> > changes since RFC:
> > - Added again removed (pipe == crtc->index) WARN_ON.
> > - Pass drm_crtc_index instead of intel pipe in order to
> > call drm_handle_vblank() from gen8_de_irq_handler(),
> > other legacy irq handlers also calls drm_handle_vblank()
> > with intel pipe but those doesn't require this change.
> >
> > Cc: Ville Syrjälä
> > Cc: Cc: Jani Nikula
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 8
> > drivers/gpu/drm/i915/display/intel_display_types.h | 4 +++-
> > drivers/gpu/drm/i915/i915_irq.c| 8 ++--
> > 3 files changed, 13 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 878d331b9e8c..5709e672151a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14070,11 +14070,11 @@ verify_single_dpll_state(struct drm_i915_private
> > *dev_priv,
> > if (new_crtc_state->hw.active)
> > I915_STATE_WARN(!(pll->active_mask & crtc_mask),
> > "pll active mismatch (expected pipe %c in
> > active mask 0x%02x)\n",
> > - pipe_name(drm_crtc_index(&crtc->base)),
> > pll->active_mask);
> > + pipe_name(crtc->pipe), pll->active_mask);
> > else
> > I915_STATE_WARN(pll->active_mask & crtc_mask,
> > "pll active mismatch (didn't expect pipe %c in
> > active mask 0x%02x)\n",
> > - pipe_name(drm_crtc_index(&crtc->base)),
> > pll->active_mask);
> > + pipe_name(crtc->pipe), pll->active_mask);
> >
> > I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
> > "pll enabled crtcs mismatch (expected 0x%x in
> > 0x%02x)\n",
> > @@ -14103,10 +14103,10 @@ verify_shared_dpll_state(struct intel_crtc *crtc,
> >
> > I915_STATE_WARN(pll->active_mask & crtc_mask,
> > "pll active mismatch (didn't expect pipe %c in
> > active mask)\n",
> > - pipe_name(drm_crtc_index(&crtc->base)));
> > + pipe_name(crtc->pipe));
> > I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
> > "pll enabled crtcs mismatch (found %x in
> > enabled mask)\n",
> > - pipe_name(drm_crtc_index(&crtc->base)));
> > + pipe_name(crtc->pipe));
> > }
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 33ba93863488..80a6460da852 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1618,7 +1618,9 @@ intel_crtc_has_dp_encoder(const struct
> > intel_crtc_state *crtc_state)
> > static inline void
> > intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
> > {
> > - drm_wait_one_vblank(&dev_priv->drm, pipe);
> > + const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > +
> > + drm_wait_one_vblank(&dev_priv->drm, drm_crtc_index(&crtc->base));
> > }
> > static inline void
> > intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum
> > pipe pipe)
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 22ecd5bc407e..9f8b2566166a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2311,6 +2311,8 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> >
> > for_each_pipe(dev_priv, pipe) {
> > u32 fault_errors;
> > + struct intel_crtc *crtc =
> > + intel_get_crtc_for_pipe(dev_priv, pipe);
> >
> > if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
> > continue;
> > @@ -2324,8 +2326,10 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> > ret = IRQ_HANDLED;
> > I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
> >
> > - if (iir & GEN8_PIPE_VBLANK)
> > - drm_handle_vblank(&dev_priv->drm, pipe);
> > + if (iir & GEN8_PIPE_VBLANK) {
> > + drm_handle_vblank(&dev_priv->drm,
> > + drm_crtc_index(&crtc->base));
>
> Missed all the other places.
All other places were legcay handlers so i
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/vgem: Close use-after-free race in vgem_gem_create
== Series Details == Series: drm/vgem: Close use-after-free race in vgem_gem_create URL : https://patchwork.freedesktop.org/series/72873/ State : success == Summary == CI Bug Log - changes from CI_DRM_7856_full -> Patchwork_16379_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16379_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_import_export@import-close-race-prime: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] ([i915#472]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-tglb1/igt@drm_import_exp...@import-close-race-prime.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-tglb6/igt@drm_import_exp...@import-close-race-prime.html * igt@gem_busy@extended-parallel-vcs1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-iclb2/igt@gem_b...@extended-parallel-vcs1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-iclb8/igt@gem_b...@extended-parallel-vcs1.html * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@pi-userfault-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-iclb6/igt@gem_exec_sched...@pi-userfault-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-iclb1/igt@gem_exec_sched...@pi-userfault-bsd.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_partial_pwrite_pread@write-snoop: - shard-hsw: [PASS][11] -> [FAIL][12] ([i915#694]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-hsw8/igt@gem_partial_pwrite_pr...@write-snoop.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-hsw1/igt@gem_partial_pwrite_pr...@write-snoop.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][13] -> [TIMEOUT][14] ([i915#716]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl7/igt@gen9_exec_pa...@allowed-single.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-skl5/igt@gen9_exec_pa...@allowed-single.html * igt@i915_pm_rpm@gem-mmap-cpu: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([i915#189]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-iclb7/igt@i915_pm_...@gem-mmap-cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-iclb2/igt@i915_pm_...@gem-mmap-cpu.html * igt@i915_selftest@live_blt: - shard-hsw: [PASS][17] -> [DMESG-FAIL][18] ([i915#725]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-hsw1/igt@i915_selftest@live_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-hsw6/igt@i915_selftest@live_blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-apl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16379/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb:
[Intel-gfx] [PATCH] drm/i915/mst: fix pipe and vblank enable
Commit 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to
encoders on DDI platforms") pushed pipe and vblank enable to encoders on
DDI platforms, however it missed the DP MST encoder. Fix it.
Fixes: 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to encoders on
DDI platforms")
Cc: Vandita Kulkarni
Cc: Ville Syrjala
Reported-by: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b8aee506d595..9cd59141953d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -491,6 +491,12 @@ static void intel_mst_enable_dp(struct intel_encoder
*encoder,
struct intel_dp *intel_dp = &intel_dig_port->dp;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
+
+ intel_enable_pipe(pipe_config);
+
+ intel_crtc_vblank_on(pipe_config);
+
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915/display: Defer application of initial chv_phy_control
Hi, On 2/3/20 2:12 PM, Ville Syrjälä wrote: On Sat, Feb 01, 2020 at 10:31:59AM +, Chris Wilson wrote: To write to the DISPLAY_PHY_CONTROL requires holding the powerwells, which during early resume we have not yet acquired until later in intel_display_power_init_hw(). So compute the initial chv_phy_control, but leave the HW unset until we first acquire the powerwell. <7> [120.055984] i915 :00:02.0: [drm:intel_power_domains_init_hw [i915]] rawclk rate: 20 kHz <4> [120.056381] [ cut here ] <4> [120.056621] i915 :00:02.0: Unclaimed write to register 0x1e0100 <4> [120.056924] WARNING: CPU: 1 PID: 164 at drivers/gpu/drm/i915/intel_uncore.c:1166 __unclaimed_reg_debug+0x69/0x80 [i915] <4> [120.056935] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic btusb btrtl btbcm btintel i915 bluetooth coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg snd_hda_codec ghash_clmulni_intel snd_hwdep ecdh_generic ecc snd_hda_core r8169 snd_pcm lpc_ich realtek pinctrl_cherryview i2c_designware_pci prime_numbers <4> [120.057027] CPU: 1 PID: 164 Comm: kworker/u4:3 Tainted: G U 5.5.0-CI-CI_DRM_7854+ #1 <4> [120.057038] Hardware name: /NUC5CPYB, BIOS PYBSWCEL.86A.0055.2016.0812.1130 08/12/2016 <4> [120.057058] Workqueue: events_unbound async_run_entry_fn <4> [120.057275] RIP: 0010:__unclaimed_reg_debug+0x69/0x80 [i915] <4> [120.057289] Code: 48 8b 78 18 48 8b 5f 50 48 85 db 74 2d e8 1f a0 3f e1 45 89 e8 48 89 e9 48 89 da 48 89 c6 48 c7 c7 00 8c 48 a0 e8 67 82 df e0 <0f> 0b 83 2d ce e2 2b 00 01 5b 5d 41 5c 41 5d c3 48 8b 1f eb ce 66 <4> [120.057301] RSP: 0018:c9bcfd08 EFLAGS: 00010082 <4> [120.057315] RAX: RBX: 888079919b60 RCX: 0003 <4> [120.057326] RDX: 8003 RSI: RDI: <4> [120.057336] RBP: a04c9f4e R08: R09: 0001 <4> [120.057348] R10: 25c3d560 R11: 6815f798 R12: <4> [120.057359] R13: 001e0100 R14: 0286 R15: 8234a76b <4> [120.057371] FS: () GS:888074b0() knlGS: <4> [120.057382] CS: 0010 DS: ES: CR0: 80050033 <4> [120.057393] CR2: 55f4197df0d8 CR3: 6f326000 CR4: 001006e0 <4> [120.057404] Call Trace: <4> [120.057635] fwtable_write32+0x114/0x1d0 [i915] <4> [120.057892] intel_power_domains_init_hw+0x4ff/0x650 [i915] <4> [120.058150] intel_power_domains_resume+0x3d/0x70 [i915] <4> [120.058363] i915_drm_resume_early+0x97/0xd0 [i915] <4> [120.058575] ? i915_resume_switcheroo+0x30/0x30 [i915] <4> [120.058594] dpm_run_callback+0x64/0x280 <4> [120.058626] device_resume_early+0xa7/0xe0 <4> [120.058652] async_resume_early+0x14/0x40 Closes: https://gitlab.freedesktop.org/drm/intel/issues/1089 Signed-off-by: Chris Wilson Cc: Imre Deak --- drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 64943179c05e..492668d5a193 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5163,11 +5163,10 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) dev_priv->chv_phy_assert[DPIO_PHY1] = true; } - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, - dev_priv->chv_phy_control); - drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n", dev_priv->chv_phy_control); + + /* Defer application of initial phy_control to enabling the powerwell */ Can't recall if there was a specific reason for wanting to write this immediately. Maybe not. At least all the asserts are after we write the register elsewhere so should trip that stuff. I suppose the other option would be to check that the display power well is enabled before we write this. But this is probably OK. Reviewed-by: Ville Syrjälä What I don't undestand is what actually changed to cause this? Did we reorganize something in the init/resume sequence that previously forced the display power well on before this point, or did we simply not check for the unclaimed reg access? I have been seeing this happen occasionally for quite a while now, but it was not always reproducible (IIRC), so I guess that we were racing with some other code-path which did grab the power-well ? I might be completely wrong here, but the WARN triggered by this has been on my radar for quite a while now. Anyways, thank you for fixing this Chris. Regards, Hans ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Remove PageReserved manipulation from drm_pci_alloc
== Series Details == Series: drm: Remove PageReserved manipulation from drm_pci_alloc URL : https://patchwork.freedesktop.org/series/72882/ State : success == Summary == CI Bug Log - changes from CI_DRM_7856_full -> Patchwork_16384_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16384_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112146]) +6 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#644]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl2/igt@gem_pp...@flink-and-close-vma-leak.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-skl5/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-apl4/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-apl4/igt@gem_soft...@noreloc-s3.html * igt@gem_wait@busy-bcs0: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#109]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl6/igt@gem_w...@busy-bcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-skl4/igt@gem_w...@busy-bcs0.html * igt@i915_pm_rps@waitboost: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#413]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-iclb8/igt@i915_pm_...@waitboost.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-iclb4/igt@i915_pm_...@waitboost.html * igt@kms_draw_crc@draw-method-xrgb-blt-ytiled: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#52] / [i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl2/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-skl1/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#221]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl6/igt@kms_f...@flip-vs-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-skl6/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: - shard-tglb: [PASS][15] -> [SKIP][16] ([i915#668]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-tglb5/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#49]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl2/igt@kms_frontbuffer_track...@psr-1p-primscrn-shrfb-plflip-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-skl1/igt@kms_frontbuffer_track...@psr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-kbl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-kbl4/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#69]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl9/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-skl2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7856/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16384/shard-skl1/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blen
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mst: fix pipe and vblank enable
== Series Details == Series: drm/i915/mst: fix pipe and vblank enable URL : https://patchwork.freedesktop.org/series/73006/ State : success == Summary == CI Bug Log - changes from CI_DRM_7867 -> Patchwork_16427 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/index.html Known issues Here are the changes found in Patchwork_16427 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([i915#392]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7867/fi-bsw-nick/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/fi-bsw-nick/igt@i915_selftest@live_blt.html - fi-hsw-4770:[PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7867/fi-hsw-4770/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [PASS][5] -> [DMESG-FAIL][6] ([i915#1052]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7867/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][7] -> [FAIL][8] ([i915#217]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7867/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [INCOMPLETE][9] ([i915#45]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7867/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][11] ([i915#725]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7867/fi-hsw-4770r/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/fi-hsw-4770r/igt@i915_selftest@live_blt.html Warnings * igt@gem_exec_parallel@fds: - fi-byt-n2820: [TIMEOUT][13] ([fdo#112271]) -> [FAIL][14] ([i915#694]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7867/fi-byt-n2820/igt@gem_exec_paral...@fds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/fi-byt-n2820/igt@gem_exec_paral...@fds.html [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1052]: https://gitlab.freedesktop.org/drm/intel/issues/1052 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (42 -> 39) -- Additional (4): fi-hsw-peppy fi-bdw-5557u fi-kbl-r fi-kbl-7500u Missing(7): fi-hsw-4200u fi-byt-squawks fi-bwr-2160 fi-ctg-p8600 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7867 -> Patchwork_16427 CI-20190529: 20190529 CI_DRM_7867: a4c409e48c6281538b1e375545dfb5989fa02063 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5418: 4028bd390b41925f6e26f6f11b31e05054652527 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16427: 96040803c6cafbdec7efb41d208e63340c1e410d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 96040803c6ca drm/i915/mst: fix pipe and vblank enable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16427/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Check require bandwidth did not exceed LSPCON limitation
On Wed, 05 Feb 2020, Lee Shawn C wrote:
>While mode setting, driver would calculate mode rate based on resolution and
>bpp. And choose the best bpp that did not exceed DP bandwidtd.
>
>But LSPCON had more restriction due to it convert DP to HDMI.
>Driver should respect HDMI's bandwidth limitation if LSPCON was active. This
>change would ignore the bpp when its required output bandwidth already over
>HDMI 2.0 or 1.4 spec.
>
>Cc: Imre Deak
>Cc: Ville Syrjälä
>Cc: Maarten Lankhorst
>Cc: Jani Nikula
>Cc: Cooper Chiou
>Cc: Sam McNally
>Signed-off-by: Lee Shawn C
>---
> drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
> drivers/gpu/drm/i915/display/intel_lspcon.c | 10 ++
> drivers/gpu/drm/i915/display/intel_lspcon.h | 1 +
> 3 files changed, 29 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>b/drivers/gpu/drm/i915/display/intel_dp.c
>index 2057f63e32f0..64969ae1c285 100644
>--- a/drivers/gpu/drm/i915/display/intel_dp.c
>+++ b/drivers/gpu/drm/i915/display/intel_dp.c
>@@ -1992,6 +1992,9 @@ intel_dp_compute_link_config_wide(struct intel_dp
>*intel_dp,
> const struct link_config_limits *limits) {
> struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>+ struct intel_connector *connector = intel_dp->attached_connector;
>+ const struct drm_display_info *info = &connector->base.display_info;
>+ struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
> int bpp, clock, lane_count;
> int mode_rate, link_clock, link_avail;
>
>@@ -2001,6 +2004,21 @@ intel_dp_compute_link_config_wide(struct intel_dp
>*intel_dp,
> mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> output_bpp);
>
>+ /*
>+ * Bypass this mode if require bandwidth over downstream
>+ * limitation or HDMI spec when LSPCON active.
>+ */
>+ if (lspcon->active) {
>+ int max_clock_rate = lspcon_max_rate(lspcon);
>+
>+ if (info->max_tmds_clock)
>+ max_clock_rate = min(max_clock_rate,
>+ info->max_tmds_clock);
>+
>+ if (mode_rate > max_clock_rate)
>+ continue;
>+ }
>+
> for (clock = limits->min_clock; clock <= limits->max_clock;
> clock++) {
> for (lane_count = limits->min_lane_count;
>lane_count <= limits->max_lane_count; diff --git
> a/drivers/gpu/drm/i915/display/intel_lspcon.c
> b/drivers/gpu/drm/i915/display/intel_lspcon.c
>index d807c5648c87..3b0438356a88 100644
>--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
>+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
>@@ -518,6 +518,16 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
> buf, ret);
> }
>
>+int lspcon_max_rate(struct intel_lspcon *lspcon) {
>+ enum drm_lspcon_mode current_mode = lspcon_get_current_mode(lspcon);
>+
>+ if (current_mode == DRM_LSPCON_MODE_LS)
>+ return DIV_ROUND_UP(34 * 24, 8);
>+
>+ return DIV_ROUND_UP(60 * 24, 8);
>+}
>+
> u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config) {
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
> b/drivers/gpu/drm/i915/display/intel_lspcon.h
>index 37cfddf8a9c5..b584c02ab33b 100644
>--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
>+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
>@@ -18,6 +18,7 @@ struct intel_lspcon;
> bool lspcon_init(struct intel_digital_port *intel_dig_port); void
> lspcon_resume(struct intel_lspcon *lspcon); void
> lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
>+int lspcon_max_rate(struct intel_lspcon *lspcon);
> void lspcon_write_infoframe(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> unsigned int type,
>--
>2.17.1
>
>
This patch version info is not accurate.
I will submit a new one instead of this patch. Thanks!
___
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Re: [Intel-gfx] [PATCH] drm/i915/mst: fix pipe and vblank enable
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, February 5, 2020 2:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Kulkarni, Vandita
> ; Ville Syrjala ;
> Lisovskiy, Stanislav
> Subject: [PATCH] drm/i915/mst: fix pipe and vblank enable
>
> Commit 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to
> encoders on DDI platforms") pushed pipe and vblank enable to encoders on DDI
> platforms, however it missed the DP MST encoder. Fix it.
>
> Fixes: 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to encoders
> on DDI platforms")
> Cc: Vandita Kulkarni
> Cc: Ville Syrjala
> Reported-by: Stanislav Lisovskiy
> Signed-off-by: Jani Nikula
Looks good to me.
Reviewed-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index b8aee506d595..9cd59141953d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -491,6 +491,12 @@ static void intel_mst_enable_dp(struct intel_encoder
> *encoder,
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> + drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
> +
> + intel_enable_pipe(pipe_config);
> +
> + intel_crtc_vblank_on(pipe_config);
> +
> DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>
> if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
> --
> 2.20.1
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[Intel-gfx] [PATCH] drm/i915/lspcon: Make sure link rate did not exceed downstream and lspcon limitation
While mode setting, driver would calculate mode rate based on
resolution and bpp. And choose the best bpp that did not exceed
DP bandwidtd.
But LSPCON had more restriction due to it convert DP to HDMI.
Driver should respect HDMI's bandwidth limitation if LSPCON
was active. This change would ignore the bpp when its required
output bandwidth already over HDMI 2.0 or 1.4 spec.
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Sam McNally
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
drivers/gpu/drm/i915/display/intel_lspcon.c | 10 ++
drivers/gpu/drm/i915/display/intel_lspcon.h | 1 +
3 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2057f63e32f0..64969ae1c285 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1992,6 +1992,9 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
const struct link_config_limits *limits)
{
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct intel_connector *connector = intel_dp->attached_connector;
+ const struct drm_display_info *info = &connector->base.display_info;
+ struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
int bpp, clock, lane_count;
int mode_rate, link_clock, link_avail;
@@ -2001,6 +2004,21 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
output_bpp);
+ /*
+* Bypass this mode if require bandwidth over downstream
+* limitation or HDMI spec when LSPCON active.
+*/
+ if (lspcon->active) {
+ int max_clock_rate = lspcon_max_rate(lspcon);
+
+ if (info->max_tmds_clock)
+ max_clock_rate = min(max_clock_rate,
+info->max_tmds_clock);
+
+ if (mode_rate > max_clock_rate)
+ continue;
+ }
+
for (clock = limits->min_clock; clock <= limits->max_clock;
clock++) {
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d807c5648c87..3b0438356a88 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -518,6 +518,16 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
buf, ret);
}
+int lspcon_max_rate(struct intel_lspcon *lspcon)
+{
+ enum drm_lspcon_mode current_mode = lspcon_get_current_mode(lspcon);
+
+ if (current_mode == DRM_LSPCON_MODE_LS)
+ return DIV_ROUND_UP(34 * 24, 8);
+
+ return DIV_ROUND_UP(60 * 24, 8);
+}
+
u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 37cfddf8a9c5..b584c02ab33b 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -18,6 +18,7 @@ struct intel_lspcon;
bool lspcon_init(struct intel_digital_port *intel_dig_port);
void lspcon_resume(struct intel_lspcon *lspcon);
void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
+int lspcon_max_rate(struct intel_lspcon *lspcon);
void lspcon_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
--
2.17.1
___
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[Intel-gfx] [PATCH] drm/i915: Disable use of hwsp_cacheline for kernel_context
Currently on execlists, we use a local hwsp for the kernel_context,
rather than the engine's HWSP, as this is the default for execlists.
However, seqno rollover requires allocating a new HWSP cachline, and may
require pinning a new HWSP page in the GTT. This operation requiring
pinning in the GGTT is not allowed within the kernel_context timeline,
as doing so may require re-entering the kernel_context in order to evict
from the GGTT. As we want to avoid requiring a new HWSP for the
kernel_context, we can use the permanently pinned engine's HWSP instead.
However to do so we must prevent the use of semaphores reading the
kernel_context's HWSP, as the use of semaphores do not support rollover
onto the same cacheline. Fortunately, the kernel_context is mostly
isolated, so unlikely to give benefit to semaphores.
Reported-by: Maarten Lankhorst
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 10 --
drivers/gpu/drm/i915/gt/selftest_lrc.c | 12 +---
drivers/gpu/drm/i915/i915_request.c| 25 -
3 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c196fb90c59f..bc47afcc801f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2970,7 +2970,8 @@ static int gen8_emit_init_breadcrumb(struct i915_request
*rq)
{
u32 *cs;
- GEM_BUG_ON(!i915_request_timeline(rq)->has_initial_breadcrumb);
+ if (!i915_request_timeline(rq)->has_initial_breadcrumb)
+ return 0;
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
@@ -4622,8 +4623,13 @@ static int __execlists_context_alloc(struct
intel_context *ce,
if (!ce->timeline) {
struct intel_timeline *tl;
+ struct i915_vma *hwsp;
+
+ hwsp = NULL;
+ if (unlikely(test_bit(CONTEXT_BARRIER_BIT, &ce->flags)))
+ hwsp = engine->status_page.vma;
- tl = intel_timeline_create(engine->gt, NULL);
+ tl = intel_timeline_create(engine->gt, hwsp);
if (IS_ERR(tl)) {
ret = PTR_ERR(tl);
goto error_deref_obj;
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 79b9f7d092e4..f38738978e57 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3409,15 +3409,21 @@ static int bond_virtual_engine(struct intel_gt *gt,
rq[0] = ERR_PTR(-ENOMEM);
for_each_engine(master, gt, id) {
struct i915_sw_fence fence = {};
+ struct intel_context *ce;
if (master->class == class)
continue;
+ ce = intel_context_create(master);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out;
+ }
+
memset_p((void *)rq, ERR_PTR(-EINVAL), ARRAY_SIZE(rq));
- rq[0] = igt_spinner_create_request(&spin,
- master->kernel_context,
- MI_NOOP);
+ rq[0] = igt_spinner_create_request(&spin, ce, MI_NOOP);
+ intel_context_put(ce);
if (IS_ERR(rq[0])) {
err = PTR_ERR(rq[0]);
goto out;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f56b046a32de..370100cf56a4 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -881,11 +881,28 @@ __emit_semaphore_wait(struct i915_request *to,
return 0;
}
+static bool can_use_semaphore(const struct i915_request *rq)
+{
+ bool ok;
+
+ rcu_read_lock();
+ ok = rcu_dereference(rq->timeline)->hwsp_cacheline;
+ rcu_read_unlock();
+
+ return ok;
+}
+
static int
emit_semaphore_wait(struct i915_request *to,
struct i915_request *from,
gfp_t gfp)
{
+ if (!intel_context_use_semaphores(to->context))
+ goto await_fence;
+
+ if (!can_use_semaphore(from))
+ goto await_fence;
+
/* Just emit the first semaphore we see as request space is limited. */
if (already_busywaiting(to) & from->engine->mask)
goto await_fence;
@@ -931,12 +948,8 @@ i915_request_await_request(struct i915_request *to, struct
i915_request *from)
ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
&from->submit,
I915_FENCE_GFP);
- else if (intel_context_use_semaphores(to->context))
- ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
e
Re: [Intel-gfx] [PATCH] drm/i915/mst: fix pipe and vblank enable
On Wed, 2020-02-05 at 10:29 +0200, Jani Nikula wrote:
> Commit 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to
> encoders on DDI platforms") pushed pipe and vblank enable to encoders
> on
> DDI platforms, however it missed the DP MST encoder. Fix it.
>
> Fixes: 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to
> encoders on DDI platforms")
> Cc: Vandita Kulkarni
> Cc: Ville Syrjala
> Reported-by: Stanislav Lisovskiy
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++
> 1 file changed, 6 insertions(+)
Checked, seems to fix my displays, so
Reviewed-by: Stanislav Lisovskiy
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index b8aee506d595..9cd59141953d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -491,6 +491,12 @@ static void intel_mst_enable_dp(struct
> intel_encoder *encoder,
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> + drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
> +
> + intel_enable_pipe(pipe_config);
> +
> + intel_crtc_vblank_on(pipe_config);
> +
> DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>
> if (intel_de_wait_for_set(dev_priv, intel_dp-
> >regs.dp_tp_status,
___
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[Intel-gfx] [PATCH 2/2] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
If we find ourselves waiting on a MI_SEMAPHORE_WAIT, either within the
user batch or in our own preamble, the engine raises a
GT_WAIT_ON_SEMAPHORE interrupt. We can unmask that interrupt and so
respond to a semaphore wait by yielding the timeslice, if we have
another context to yield to!
The only real complication is that the interrupt is only generated for
the start of the semaphore wait, and is asynchronous to our
process_csb() -- that is, we may not have registered the timeslice before
we see the interrupt. To ensure we don't miss a potential semaphore
blocking forward progress (e.g. selftests/live_timeslice_preempt) we mark
the interrupt and apply it to the next timeslice regardless of whether it
was active at the time.
v2: We use semaphores in preempt-to-busy, within the timeslicing
implementation itself! Ergo, when we do insert a preemption due to an
expired timeslice, the new context may start with the missed semaphore
flagged by the retired context and be yielded, ad infinitum. To avoid
this, read the context id at the time of the semaphore interrupt and
only yield if that context is still active.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 40 +---
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b1c7b1ed6149..ef2f4ce1a86d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1297,6 +1297,12 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
+ if (HAS_EXECLISTS(dev_priv)) {
+ drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
+ drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
+ }
drm_printf(m, "\tRING_START: 0x%08x\n",
ENGINE_READ(engine, RING_START));
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 45e36d963ea7..8eb7365b4230 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -157,6 +157,15 @@ struct intel_engine_execlists {
*/
struct i915_priolist default_priolist;
+ /**
+* @yield: CCID at the time of the last semaphore-wait interrupt.
+*
+* Instead of leaving a semaphore busy-spinning on an engine, we would
+* like to switch to another ready context, i.e. yielding the semaphore
+* timeslice.
+*/
+ u32 yield;
+
/**
* @error_interrupt: CS Master EIR
*
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..875bd0392ffc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -39,6 +39,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
}
}
+ if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+ WRITE_ONCE(engine->execlists.yield,
+ ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
+ if (del_timer(&engine->execlists.timer))
+ tasklet = true;
+ }
+
if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
tasklet = true;
@@ -228,7 +235,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
@@ -366,7 +374,8 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
const u32 gt_interrupts[] = {
irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c196fb90c59f..dd21066d6987 100644
---
[Intel-gfx] [PATCH 1/2] drm/i915: Flush execution tasklets before checking request status
Rather than flushing the submission tasklets just before we sleep, flush
before we check the request status. Ideally this gives us a moment to
process the tasklets after sleeping just before we timeout.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f56b046a32de..5c2bb0b9478b 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1564,6 +1564,7 @@ long i915_request_wait(struct i915_request *rq,
goto out;
for (;;) {
+ intel_engine_flush_submission(rq->engine);
set_current_state(state);
if (i915_request_completed(rq)) {
@@ -1581,7 +1582,6 @@ long i915_request_wait(struct i915_request *rq,
break;
}
- intel_engine_flush_submission(rq->engine);
timeout = io_schedule_timeout(timeout);
}
__set_current_state(TASK_RUNNING);
--
2.25.0
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/lspcon: Make sure link rate did not exceed downstream and lspcon limitation
== Series Details == Series: drm/i915/lspcon: Make sure link rate did not exceed downstream and lspcon limitation URL : https://patchwork.freedesktop.org/series/73012/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7868 -> Patchwork_16428 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16428 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16428, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16428/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16428: ### IGT changes ### Possible regressions * igt@kms_flip@basic-flip-vs-dpms: - fi-skl-6770hq: NOTRUN -> [FAIL][1] +15 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16428/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html Known issues Here are the changes found in Patchwork_16428 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][2] ([i915#553] / [i915#725]) -> [PASS][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7868/fi-hsw-4770r/igt@i915_selftest@live_blt.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16428/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][4] ([fdo#108569]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7868/fi-icl-y/igt@i915_selftest@live_execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16428/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [DMESG-FAIL][6] ([i915#722]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7868/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16428/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_hangcheck: - fi-icl-guc: [INCOMPLETE][8] ([fdo#108569]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7868/fi-icl-guc/igt@i915_selftest@live_hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16428/fi-icl-guc/igt@i915_selftest@live_hangcheck.html Warnings * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][10] ([i915#725]) -> [DMESG-FAIL][11] ([i915#553] / [i915#725]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7868/fi-hsw-4770/igt@i915_selftest@live_blt.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16428/fi-hsw-4770/igt@i915_selftest@live_blt.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (48 -> 41) -- Additional (5): fi-bdw-5557u fi-skl-6770hq fi-snb-2520m fi-cfl-8109u fi-byt-n2820 Missing(12): fi-kbl-soraka fi-icl-1065g7 fi-ilk-m540 fi-bsw-n3050 fi-byt-j1900 fi-glk-dsi fi-byt-squawks fi-kbl-7500u fi-ctg-p8600 fi-ivb-3770 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7868 -> Patchwork_16428 CI-20190529: 20190529 CI_DRM_7868: 2a4eeb761e833082eed9cb82fb775a862b7a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5419: 44913a91e77434b03001bb9ea53216cd03c476e6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16428: ecce0d80a8a519aedaa0dff37a48198ec03ee348 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ecce0d80a8a5 drm/i915/lspcon: Make sure link rate did not exceed downstream and lspcon limitation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16428/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: add basic selftests for rc6
From: Andi Shyti
Add three basic tests for rc6 power status:
1. live_rc6_basic - simply checks if rc6 works when it's enabled
or stops when it's disabled.
2. live_rc6_threshold - rc6 should not work when the evaluation
interval is less than the threshold and should work otherwise.
3. live_rc6_busy - keeps the gpu busy and then goes in idle;
checks that we don't fall in rc6 when busy and that we do fall
in rc6 when idling.
The three tests are added as sutest of the bigger live_late_gt_pm
selftest.
The basic rc6 functionality is tested by checking the reference
counter within the evaluation interval.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 173 +++
drivers/gpu/drm/i915/gt/selftest_rc6.h | 2 +
3 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 09ff8e4f88af..5c7b92301a14 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -52,6 +52,8 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rc6_threshold),
+ SUBTEST(live_rc6_busy),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 5f7e2dcf5686..92375f458845 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -11,6 +11,7 @@
#include "selftest_rc6.h"
#include "selftests/i915_random.h"
+#include "selftests/igt_spinner.h"
int live_rc6_manual(void *arg)
{
@@ -202,3 +203,175 @@ int live_rc6_ctx_wa(void *arg)
kfree(engines);
return err;
}
+
+static bool test_rc6(struct intel_rc6 *rc6, bool enabled)
+{
+ struct intel_uncore *uncore = rc6_to_uncore(rc6);
+ intel_wakeref_t wakeref;
+ u32 ec1, ec2;
+ u32 interval;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ interval = intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL);
+
+ /*
+* the interval is stored in steps of 1.28us
+*/
+ interval = div_u64(mul_u32_u32(interval, 128),
+ 100 * 1000); /* => miliseconds */
+
+ ec1 = intel_uncore_read(uncore, GEN6_GT_GFX_RC6);
+
+ /*
+* It's not important to precisely wait the interval time.
+* I'll wait at least twice the time in order to be sure
+* that the counting happens in the reference counter.
+*/
+ msleep(2 * interval);
+
+ ec2 = intel_uncore_read(uncore, GEN6_GT_GFX_RC6);
+
+ pr_info("interval:%x [%dms], threshold:%x, rc6:%x, enabled?:%s\n",
+ intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL),
+ interval,
+ intel_uncore_read(uncore, GEN6_RC6_THRESHOLD),
+ ec2 - ec1,
+ yesno(enabled));
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
+
+ return enabled != (ec1 >= ec2);
+}
+
+int live_rc6_threshold(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_rc6 *rc6 = >->rc6;
+ intel_wakeref_t wakeref;
+ u32 threshold, interval;
+ u32 t_orig, i_orig;
+ int err = 0;
+
+ if (!rc6->manual) /* No interferring PCU! */
+ return 0;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ __intel_rc6_disable(rc6); /* stop before adjusting thresholds */
+
+ t_orig = intel_uncore_read(uncore, GEN6_RC6_THRESHOLD);
+ i_orig = intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL);
+
+ /*
+* set the threshold to 50ms
+*
+* 50ms * 1000 = 5us
+* 5 / (1.28 * 100) / 100 (we don't have floating point)
+*/
+ threshold = 50 * 1000 / 128 * 100;
+ intel_uncore_write(uncore, GEN6_RC6_THRESHOLD, threshold);
+
+ /* set interval indicatively to half the threshold */
+ interval = threshold / 2;
+ intel_uncore_write(uncore, GEN6_RC_EVALUATION_INTERVAL, interval);
+
+ intel_rc6_unpark(rc6);
+
+ /* interval < threshold */
+ if (!test_rc6(rc6, false)) {
+ pr_err("i915 mismatch: rc6 with interval < threshold\n");
+ err = -EINVAL;
+ }
+
+ __intel_rc6_disable(rc6);
+
+ /* set interval indicatively to twice the threshold */
+ interval = threshold * 2;
+ intel_uncore_write(uncore, GEN6_RC_EVALUATION_INTERVAL, interval);
+
+ intel_rc6_unpark(rc6);
+
+ /* interval > threshold */
+ if (!test_rc6(rc6, true)) {
+ pr_err("i915 mismatch: not in rc6 with interval > threshold\n");
+ err = -EINVAL;
+ }
+
+ __intel_rc6_disable(rc6);
+
+
Re: [Intel-gfx] [PATCH 2/7] drm/i915: Remove (pipe == crtc->index) assumption
On Wed, Feb 05, 2020 at 01:32:54PM +0530, Anshuman Gupta wrote:
> On 2020-02-04 at 16:36:17 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 04, 2020 at 04:59:22PM +0530, Anshuman Gupta wrote:
> > > we can't have (pipe == crtc->index) assumption in
> > > driver in order to support 3 non-contiguous
> > > display pipe system.
> > >
> > > FIXME: Remove the WARN_ON(drm_crtc_index(&crtc->base) != crtc->pipe)
> > > till we won't fix all such assumption.
> > >
> > > changes since RFC:
> > > - Added again removed (pipe == crtc->index) WARN_ON.
> > > - Pass drm_crtc_index instead of intel pipe in order to
> > > call drm_handle_vblank() from gen8_de_irq_handler(),
> > > other legacy irq handlers also calls drm_handle_vblank()
> > > with intel pipe but those doesn't require this change.
> > >
> > > Cc: Ville Syrjälä
> > > Cc: Cc: Jani Nikula
> > > Signed-off-by: Anshuman Gupta
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 8
> > > drivers/gpu/drm/i915/display/intel_display_types.h | 4 +++-
> > > drivers/gpu/drm/i915/i915_irq.c| 8 ++--
> > > 3 files changed, 13 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 878d331b9e8c..5709e672151a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -14070,11 +14070,11 @@ verify_single_dpll_state(struct
> > > drm_i915_private *dev_priv,
> > > if (new_crtc_state->hw.active)
> > > I915_STATE_WARN(!(pll->active_mask & crtc_mask),
> > > "pll active mismatch (expected pipe %c in
> > > active mask 0x%02x)\n",
> > > - pipe_name(drm_crtc_index(&crtc->base)),
> > > pll->active_mask);
> > > + pipe_name(crtc->pipe), pll->active_mask);
> > > else
> > > I915_STATE_WARN(pll->active_mask & crtc_mask,
> > > "pll active mismatch (didn't expect pipe %c in
> > > active mask 0x%02x)\n",
> > > - pipe_name(drm_crtc_index(&crtc->base)),
> > > pll->active_mask);
> > > + pipe_name(crtc->pipe), pll->active_mask);
> > >
> > > I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
> > > "pll enabled crtcs mismatch (expected 0x%x in
> > > 0x%02x)\n",
> > > @@ -14103,10 +14103,10 @@ verify_shared_dpll_state(struct intel_crtc
> > > *crtc,
> > >
> > > I915_STATE_WARN(pll->active_mask & crtc_mask,
> > > "pll active mismatch (didn't expect pipe %c in
> > > active mask)\n",
> > > - pipe_name(drm_crtc_index(&crtc->base)));
> > > + pipe_name(crtc->pipe));
> > > I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
> > > "pll enabled crtcs mismatch (found %x in
> > > enabled mask)\n",
> > > - pipe_name(drm_crtc_index(&crtc->base)));
> > > + pipe_name(crtc->pipe));
> > > }
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 33ba93863488..80a6460da852 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1618,7 +1618,9 @@ intel_crtc_has_dp_encoder(const struct
> > > intel_crtc_state *crtc_state)
> > > static inline void
> > > intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
> > > {
> > > - drm_wait_one_vblank(&dev_priv->drm, pipe);
> > > + const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > +
> > > + drm_wait_one_vblank(&dev_priv->drm, drm_crtc_index(&crtc->base));
> > > }
> > > static inline void
> > > intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum
> > > pipe pipe)
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 22ecd5bc407e..9f8b2566166a 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -2311,6 +2311,8 @@ gen8_de_irq_handler(struct drm_i915_private
> > > *dev_priv, u32 master_ctl)
> > >
> > > for_each_pipe(dev_priv, pipe) {
> > > u32 fault_errors;
> > > + struct intel_crtc *crtc =
> > > + intel_get_crtc_for_pipe(dev_priv, pipe);
> > >
> > > if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
> > > continue;
> > > @@ -2324,8 +2326,10 @@ gen8_de_irq_handler(struct drm_i915_private
> > > *dev_priv, u32 master_ctl)
> > > ret = IRQ_HANDLED;
> > > I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
> > >
> > > - if (iir & GEN8_PIPE_VBLANK)
> > > - drm_handle_vblank(&dev_priv->drm, pipe);
> > > + if (iir & GEN8_PIPE_VBLA
[Intel-gfx] [PATCH 0/1] Adding YUV444 packed format support for skl+
Adding YUV444 packed format support for skl+ Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com Stanislav Lisovskiy (1): drm/i915: Adding YUV444 packed format support for skl+ (V13) drivers/gpu/drm/i915/display/intel_display.c | 5 + drivers/gpu/drm/i915/display/intel_sprite.c | 5 + drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-) -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V13)
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
v14: Rebase.
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 368e481d45ee..cb7d5dbfc3ad 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3331,6 +3331,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4570,6 +4572,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -6186,6 +6190,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7abeefe8dce5..1540eab7ba79 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2483,6 +2483,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2501,6 +2502,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2572,6 +2574,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2603,6 +2606,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2770,6 +2774,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..a6204e9bc36e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6769,7 +6769,7 @@ enum {
#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016(7 << 24)
-#define PLANE_CTL_FORMAT_AYUV(8 << 24)
+#define PLANE_CTL_FORMAT_XYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
htt
[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
== Series Details == Series: Enable second DBuf slice for ICL and TGL (rev23) URL : https://patchwork.freedesktop.org/series/70059/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16386_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16386_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16386_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16386_full: ### IGT changes ### Possible regressions * igt@kms_plane_cursor@pipe-a-viewport-size-128: - shard-tglb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_plane_cur...@pipe-a-viewport-size-128.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_plane_cur...@pipe-a-viewport-size-128.html Known issues Here are the changes found in Patchwork_16386_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_eio@in-flight-suspend: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@gem_...@in-flight-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@gem_...@in-flight-suspend.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +18 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_sched...@out-order-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb7/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@gem_exec_sched...@wide-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html * igt@gem_exec_store@pages-vcs1: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_exec_st...@pages-vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@gem_exec_st...@pages-vcs1.html * igt@gem_exec_suspend@basic-s4-devices: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@gem_exec_susp...@basic-s4-devices.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@i915_pm...@dc6-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +15 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl3/igt@kms_b...@extended-pageflip-hang-oldfb-render-pipe-b.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@kms_b...@extended-pageflip-hang-oldfb-render-pipe-b.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen: - shard-tglb: [PASS][21] -> [FAIL][22] ([fdo#111703]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb5/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html * igt@kms_draw_crc@draw-method-rg
[Intel-gfx] [PATCH] drm/i915: align dumb buffer stride to page_sz of the region
If stride of the dumb buffer requested is greater than the primary
plane's max stride, then we align the stride to the page size. But the
page size was hard coded for 4096.
With the lmem addition, lets align the stride to the page size of the
memory region that will be used for dumb buffer.
Signed-off-by: Ramalingam C
cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a712e60b016a..0f01396ca24e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -239,8 +239,9 @@ i915_gem_dumb_create(struct drm_file *file,
struct drm_device *dev,
struct drm_mode_create_dumb *args)
{
- enum intel_memory_type mem_type;
int cpp = DIV_ROUND_UP(args->bpp, 8);
+ enum intel_memory_type mem_type;
+ struct intel_memory_region *mr;
u32 format;
switch (cpp) {
@@ -260,24 +261,21 @@ i915_gem_dumb_create(struct drm_file *file,
/* have to work out size/pitch and return them */
args->pitch = ALIGN(args->width * cpp, 64);
+ mem_type = INTEL_MEMORY_SYSTEM;
+ if (HAS_LMEM(to_i915(dev)))
+ mem_type = INTEL_MEMORY_LOCAL;
+ mr = intel_memory_region_by_type(to_i915(dev), mem_type);
+
/* align stride to page size so that we can remap */
if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
DRM_FORMAT_MOD_LINEAR))
- args->pitch = ALIGN(args->pitch, 4096);
+ args->pitch = ALIGN(args->pitch, mr->min_page_size);
if (args->pitch < args->width)
return -EINVAL;
args->size = mul_u32_u32(args->pitch, args->height);
-
- mem_type = INTEL_MEMORY_SYSTEM;
- if (HAS_LMEM(to_i915(dev)))
- mem_type = INTEL_MEMORY_LOCAL;
-
- return i915_gem_create(file,
- intel_memory_region_by_type(to_i915(dev),
- mem_type),
- &args->size, &args->handle);
+ return i915_gem_create(file, mr, &args->size, &args->handle);
}
/**
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915: align dumb buffer stride to page_sz of the region
Quoting Ramalingam C (2020-02-05 11:40:19)
> If stride of the dumb buffer requested is greater than the primary
> plane's max stride, then we align the stride to the page size. But the
> page size was hard coded for 4096.
>
> With the lmem addition, lets align the stride to the page size of the
> memory region that will be used for dumb buffer.
>
> Signed-off-by: Ramalingam C
> cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem.c | 20 +---
> 1 file changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a712e60b016a..0f01396ca24e 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -239,8 +239,9 @@ i915_gem_dumb_create(struct drm_file *file,
> struct drm_device *dev,
> struct drm_mode_create_dumb *args)
> {
> - enum intel_memory_type mem_type;
> int cpp = DIV_ROUND_UP(args->bpp, 8);
> + enum intel_memory_type mem_type;
> + struct intel_memory_region *mr;
> u32 format;
>
> switch (cpp) {
> @@ -260,24 +261,21 @@ i915_gem_dumb_create(struct drm_file *file,
> /* have to work out size/pitch and return them */
> args->pitch = ALIGN(args->width * cpp, 64);
>
> + mem_type = INTEL_MEMORY_SYSTEM;
> + if (HAS_LMEM(to_i915(dev)))
> + mem_type = INTEL_MEMORY_LOCAL;
> + mr = intel_memory_region_by_type(to_i915(dev), mem_type);
> +
> /* align stride to page size so that we can remap */
> if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
> DRM_FORMAT_MOD_LINEAR))
> - args->pitch = ALIGN(args->pitch, 4096);
> + args->pitch = ALIGN(args->pitch, mr->min_page_size);
That should be ggtt-page size, different semantics, right?
-Chris
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Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_exec: Cover all engines for nohangcheck
On 04/02/2020 16:19, Chris Wilson wrote:
No engine can be missed when verifying that a rogue user cannot cause a
denial-of-service with nohangcheck.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
__for_each_physical_engine, keep the leaks
---
tests/i915/gem_ctx_exec.c | 38 --
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index b1ae65774..aeb8d2976 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -42,6 +42,7 @@
#include "igt_dummyload.h"
#include "igt_sysfs.h"
+#include "sw_sync.h"
IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
@@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
static void nohangcheck_hostile(int i915)
{
- int64_t timeout = NSEC_PER_SEC / 2;
- igt_spin_t *spin;
+ const struct intel_execution_engine2 *e;
igt_hang_t hang;
+ int fence = -1;
uint32_t ctx;
int err = 0;
int dir;
@@ -215,6 +216,8 @@ static void nohangcheck_hostile(int i915)
* we forcibly terminate that context.
*/
+ i915 = gem_reopen_driver(i915);
+
dir = igt_sysfs_open_parameters(i915);
igt_require(dir != -1);
@@ -223,16 +226,35 @@ static void nohangcheck_hostile(int i915)
igt_require(__enable_hangcheck(dir, false));
- spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
+ __for_each_physical_engine(i915, e) {
+ igt_spin_t *spin;
+
+ spin = igt_spin_new(i915, ctx,
+ .engine = e->flags,
Ouch, I missed a mismatch between ctx and e->flags here. Thanks to
Sreedhar for reporting it.
We either need gem_context_set_all_engines back or to rethink a cleaner
strategy.
Regards,
Tvrtko
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_FENCE_OUT));
+
+ igt_assert(spin->out_fence != -1);
+ if (fence < 0) {
+ fence = spin->out_fence;
+ spin->out_fence = -1;
+ } else {
+ int new;
+
+ new = sync_fence_merge(fence, spin->out_fence);
+ close(fence);
+
+ fence = new;
+ }
+ }
gem_context_destroy(i915, ctx);
+ igt_assert(fence != -1);
- if (gem_wait(i915, spin->handle, &timeout)) {
+ if (sync_fence_wait(fence, MSEC_PER_SEC / 2)) {
igt_debugfs_dump(i915, "i915_engine_info");
err = -ETIME;
}
- igt_spin_free(i915, spin);
-
__enable_hangcheck(dir, true);
gem_quiescent_gpu(i915);
igt_disallow_hang(i915, hang);
@@ -240,7 +262,11 @@ static void nohangcheck_hostile(int i915)
igt_assert_f(err == 0,
"Hostile unpreemptable context was not cancelled immediately
upon closure\n");
+ igt_assert_eq(sync_fence_status(fence), -EIO);
+ close(fence);
+
close(dir);
+ close(i915);
}
igt_main
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Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_exec: Cover all engines for nohangcheck
Quoting Tvrtko Ursulin (2020-02-05 11:48:42)
>
> On 04/02/2020 16:19, Chris Wilson wrote:
> > No engine can be missed when verifying that a rogue user cannot cause a
> > denial-of-service with nohangcheck.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > __for_each_physical_engine, keep the leaks
> > ---
> > tests/i915/gem_ctx_exec.c | 38 --
> > 1 file changed, 32 insertions(+), 6 deletions(-)
> >
> > diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> > index b1ae65774..aeb8d2976 100644
> > --- a/tests/i915/gem_ctx_exec.c
> > +++ b/tests/i915/gem_ctx_exec.c
> > @@ -42,6 +42,7 @@
> >
> > #include "igt_dummyload.h"
> > #include "igt_sysfs.h"
> > +#include "sw_sync.h"
> >
> > IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
> >
> > @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
> >
> > static void nohangcheck_hostile(int i915)
> > {
> > - int64_t timeout = NSEC_PER_SEC / 2;
> > - igt_spin_t *spin;
> > + const struct intel_execution_engine2 *e;
> > igt_hang_t hang;
> > + int fence = -1;
> > uint32_t ctx;
> > int err = 0;
> > int dir;
> > @@ -215,6 +216,8 @@ static void nohangcheck_hostile(int i915)
> >* we forcibly terminate that context.
> >*/
> >
> > + i915 = gem_reopen_driver(i915);
> > +
> > dir = igt_sysfs_open_parameters(i915);
> > igt_require(dir != -1);
> >
> > @@ -223,16 +226,35 @@ static void nohangcheck_hostile(int i915)
> >
> > igt_require(__enable_hangcheck(dir, false));
> >
> > - spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> > + __for_each_physical_engine(i915, e) {
> > + igt_spin_t *spin;
> > +
> > + spin = igt_spin_new(i915, ctx,
> > + .engine = e->flags,
>
> Ouch, I missed a mismatch between ctx and e->flags here. Thanks to
> Sreedhar for reporting it.
>
> We either need gem_context_set_all_engines back or to rethink a cleaner
> strategy.
Copy engines, or pass the ctx into __for_each_physical_engine.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_exec: Cover all engines for nohangcheck
Quoting Chris Wilson (2020-02-05 11:52:11)
> Quoting Tvrtko Ursulin (2020-02-05 11:48:42)
> >
> > On 04/02/2020 16:19, Chris Wilson wrote:
> > > No engine can be missed when verifying that a rogue user cannot cause a
> > > denial-of-service with nohangcheck.
> > >
> > > Signed-off-by: Chris Wilson
> > > Cc: Tvrtko Ursulin
> > > ---
> > > __for_each_physical_engine, keep the leaks
> > > ---
> > > tests/i915/gem_ctx_exec.c | 38 --
> > > 1 file changed, 32 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
> > > index b1ae65774..aeb8d2976 100644
> > > --- a/tests/i915/gem_ctx_exec.c
> > > +++ b/tests/i915/gem_ctx_exec.c
> > > @@ -42,6 +42,7 @@
> > >
> > > #include "igt_dummyload.h"
> > > #include "igt_sysfs.h"
> > > +#include "sw_sync.h"
> > >
> > > IGT_TEST_DESCRIPTION("Test context batch buffer execution.");
> > >
> > > @@ -203,9 +204,9 @@ static bool __enable_hangcheck(int dir, bool state)
> > >
> > > static void nohangcheck_hostile(int i915)
> > > {
> > > - int64_t timeout = NSEC_PER_SEC / 2;
> > > - igt_spin_t *spin;
> > > + const struct intel_execution_engine2 *e;
> > > igt_hang_t hang;
> > > + int fence = -1;
> > > uint32_t ctx;
> > > int err = 0;
> > > int dir;
> > > @@ -215,6 +216,8 @@ static void nohangcheck_hostile(int i915)
> > >* we forcibly terminate that context.
> > >*/
> > >
> > > + i915 = gem_reopen_driver(i915);
> > > +
> > > dir = igt_sysfs_open_parameters(i915);
> > > igt_require(dir != -1);
> > >
> > > @@ -223,16 +226,35 @@ static void nohangcheck_hostile(int i915)
> > >
> > > igt_require(__enable_hangcheck(dir, false));
> > >
> > > - spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_NO_PREEMPTION);
> > > + __for_each_physical_engine(i915, e) {
> > > + igt_spin_t *spin;
> > > +
> > > + spin = igt_spin_new(i915, ctx,
> > > + .engine = e->flags,
> >
> > Ouch, I missed a mismatch between ctx and e->flags here. Thanks to
> > Sreedhar for reporting it.
> >
> > We either need gem_context_set_all_engines back or to rethink a cleaner
> > strategy.
>
> Copy engines, or pass the ctx into __for_each_physical_engine.
Which [copy engines] reveals a bug... More missing tests in
gem_ctx_persistence.
-Chris
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[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Update the list of engines on the actual context
We want to iterate the set of physical engines on this context, so
update the iterators to act on a particular context.
This tunnel keeps on getting longer.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
lib/i915/gem_engine_topology.h | 7 +--
tests/i915/gem_ctx_exec.c | 2 +-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index e40d7ec83..027d86be2 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -67,9 +67,12 @@ struct intel_execution_engine2
gem_eb_flags_to_engine(unsigned int flags);
intel_next_engine(&i__))
/* needs to replace "for_each_physical_engine" when conflicts are fixed */
-#define __for_each_physical_engine(fd__, e__) \
- for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
+#define for_each_physical_engine(fd__, ctx__, e__) \
+ for (struct intel_engine_data i__ = intel_init_engine_list(fd__,
ctx__); \
((e__) = intel_get_current_physical_engine(&i__)); \
intel_next_engine(&i__))
+#define __for_each_physical_engine(fd__, e__) \
+ for_each_physical_engine(fd__, 0, e__)
+
#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index aeb8d2976..5b4e4b3db 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -226,7 +226,7 @@ static void nohangcheck_hostile(int i915)
igt_require(__enable_hangcheck(dir, false));
- __for_each_physical_engine(i915, e) {
+ for_each_physical_engine(i915, ctx, e) {
igt_spin_t *spin;
spin = igt_spin_new(i915, ctx,
--
2.25.0
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Re: [Intel-gfx] [PATCH] drm/i915: align dumb buffer stride to page_sz of the region
On 2020-02-05 at 11:43:35 +, Chris Wilson wrote:
> Quoting Ramalingam C (2020-02-05 11:40:19)
> > If stride of the dumb buffer requested is greater than the primary
> > plane's max stride, then we align the stride to the page size. But the
> > page size was hard coded for 4096.
> >
> > With the lmem addition, lets align the stride to the page size of the
> > memory region that will be used for dumb buffer.
> >
> > Signed-off-by: Ramalingam C
> > cc: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 20 +---
> > 1 file changed, 9 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index a712e60b016a..0f01396ca24e 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -239,8 +239,9 @@ i915_gem_dumb_create(struct drm_file *file,
> > struct drm_device *dev,
> > struct drm_mode_create_dumb *args)
> > {
> > - enum intel_memory_type mem_type;
> > int cpp = DIV_ROUND_UP(args->bpp, 8);
> > + enum intel_memory_type mem_type;
> > + struct intel_memory_region *mr;
> > u32 format;
> >
> > switch (cpp) {
> > @@ -260,24 +261,21 @@ i915_gem_dumb_create(struct drm_file *file,
> > /* have to work out size/pitch and return them */
> > args->pitch = ALIGN(args->width * cpp, 64);
> >
> > + mem_type = INTEL_MEMORY_SYSTEM;
> > + if (HAS_LMEM(to_i915(dev)))
> > + mem_type = INTEL_MEMORY_LOCAL;
> > + mr = intel_memory_region_by_type(to_i915(dev), mem_type);
> > +
> > /* align stride to page size so that we can remap */
> > if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
> > DRM_FORMAT_MOD_LINEAR))
> > - args->pitch = ALIGN(args->pitch, 4096);
> > + args->pitch = ALIGN(args->pitch, mr->min_page_size);
>
> That should be ggtt-page size, different semantics, right?
Chris,
Sicne the purpose(remapping stride) is not clear, couldn't understand
which page size this is. I assumed this is of hw page size.
Btw, there is no issues found with 4096 on lmem too. May be this is
unwanted change, unless they meant hw page size here and luckily we are
not hitting the issue. I am not sure though.
-Ram
> -Chris
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Re: [Intel-gfx] [PATCH] drm/i915: align dumb buffer stride to page_sz of the region
Quoting Ramalingam C (2020-02-05 12:02:50)
> On 2020-02-05 at 11:43:35 +, Chris Wilson wrote:
> > Quoting Ramalingam C (2020-02-05 11:40:19)
> > > If stride of the dumb buffer requested is greater than the primary
> > > plane's max stride, then we align the stride to the page size. But the
> > > page size was hard coded for 4096.
> > >
> > > With the lmem addition, lets align the stride to the page size of the
> > > memory region that will be used for dumb buffer.
> > >
> > > Signed-off-by: Ramalingam C
> > > cc: Chris Wilson
> > > ---
> > > drivers/gpu/drm/i915/i915_gem.c | 20 +---
> > > 1 file changed, 9 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > > b/drivers/gpu/drm/i915/i915_gem.c
> > > index a712e60b016a..0f01396ca24e 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -239,8 +239,9 @@ i915_gem_dumb_create(struct drm_file *file,
> > > struct drm_device *dev,
> > > struct drm_mode_create_dumb *args)
> > > {
> > > - enum intel_memory_type mem_type;
> > > int cpp = DIV_ROUND_UP(args->bpp, 8);
> > > + enum intel_memory_type mem_type;
> > > + struct intel_memory_region *mr;
> > > u32 format;
> > >
> > > switch (cpp) {
> > > @@ -260,24 +261,21 @@ i915_gem_dumb_create(struct drm_file *file,
> > > /* have to work out size/pitch and return them */
> > > args->pitch = ALIGN(args->width * cpp, 64);
> > >
> > > + mem_type = INTEL_MEMORY_SYSTEM;
> > > + if (HAS_LMEM(to_i915(dev)))
> > > + mem_type = INTEL_MEMORY_LOCAL;
> > > + mr = intel_memory_region_by_type(to_i915(dev), mem_type);
> > > +
> > > /* align stride to page size so that we can remap */
> > > if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
> > >
> > > DRM_FORMAT_MOD_LINEAR))
> > > - args->pitch = ALIGN(args->pitch, 4096);
> > > + args->pitch = ALIGN(args->pitch, mr->min_page_size);
> >
> > That should be ggtt-page size, different semantics, right?
> Chris,
>
> Sicne the purpose(remapping stride) is not clear, couldn't understand
> which page size this is. I assumed this is of hw page size.
>
> Btw, there is no issues found with 4096 on lmem too. May be this is
> unwanted change, unless they meant hw page size here and luckily we are
> not hitting the issue. I am not sure though.
It for doing tricks with I915_GGTT_VIEW_REMAPPED (intel_remap_pages) so
that a large framebuffer can be cut into CRTC-sized chunks and not go
over the HW limits.
-Chris
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[Intel-gfx] [PATCH] drm/i915/gem: Don't leak non-persistent requests on changing engines
If we have a set of active engines marked as being non-persistent, we
lose track of those if the user replaces those engines with
I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
non-persistent requests are terminated if they are no longer being
tracked by the user's context (in order to prevent a lost request
causing an untracked and so unstoppable GPU hang), we need to apply the
same context cancellation upon changing engines.
Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
Testcase: XXX
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 52a749691a8d..5d4093266103 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1623,6 +1623,11 @@ set_engines(struct i915_gem_context *ctx,
}
replace:
+ /* Flush stale requests off the old engines if required */
+ if (!i915_gem_context_is_persistent(ctx) ||
+ !i915_modparams.enable_hangcheck)
+ kill_context(ctx);
+
mutex_lock(&ctx->engines_mutex);
if (args->size)
i915_gem_context_set_user_engines(ctx);
--
2.25.0
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[Intel-gfx] [PATCH v2] drm/i915/gem: Don't leak non-persistent requests on changing engines
If we have a set of active engines marked as being non-persistent, we
lose track of those if the user replaces those engines with
I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
non-persistent requests are terminated if they are no longer being
tracked by the user's context (in order to prevent a lost request
causing an untracked and so unstoppable GPU hang), we need to apply the
same context cancellation upon changing engines.
Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
Testcase: XXX
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 52a749691a8d..20f1d3e0221f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1624,11 +1624,18 @@ set_engines(struct i915_gem_context *ctx,
replace:
mutex_lock(&ctx->engines_mutex);
+
+ /* Flush stale requests off the old engines if required */
+ if (!i915_gem_context_is_persistent(ctx) ||
+ !i915_modparams.enable_hangcheck)
+ kill_context(ctx);
+
if (args->size)
i915_gem_context_set_user_engines(ctx);
else
i915_gem_context_clear_user_engines(ctx);
set.engines = rcu_replace_pointer(ctx->engines, set.engines, 1);
+
mutex_unlock(&ctx->engines_mutex);
call_rcu(&set.engines->rcu, free_engines_rcu);
--
2.25.0
___
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Update the list of engines on the actual context
On 05/02/2020 11:59, Chris Wilson wrote:
We want to iterate the set of physical engines on this context, so
update the iterators to act on a particular context.
This tunnel keeps on getting longer.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
lib/i915/gem_engine_topology.h | 7 +--
tests/i915/gem_ctx_exec.c | 2 +-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index e40d7ec83..027d86be2 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -67,9 +67,12 @@ struct intel_execution_engine2
gem_eb_flags_to_engine(unsigned int flags);
intel_next_engine(&i__))
/* needs to replace "for_each_physical_engine" when conflicts are fixed */
-#define __for_each_physical_engine(fd__, e__) \
- for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
+#define for_each_physical_engine(fd__, ctx__, e__) \
+ for (struct intel_engine_data i__ = intel_init_engine_list(fd__,
ctx__); \
((e__) = intel_get_current_physical_engine(&i__)); \
intel_next_engine(&i__))
+#define __for_each_physical_engine(fd__, e__) \
+ for_each_physical_engine(fd__, 0, e__)
+
#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index aeb8d2976..5b4e4b3db 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -226,7 +226,7 @@ static void nohangcheck_hostile(int i915)
igt_require(__enable_hangcheck(dir, false));
- __for_each_physical_engine(i915, e) {
+ for_each_physical_engine(i915, ctx, e) {
igt_spin_t *spin;
spin = igt_spin_new(i915, ctx,
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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[Intel-gfx] [PATCH] drm/i915: Mark i915.reset as unsigned
We have been using '-1' to mean the maximum i915.reset level in the belief that it was unsigned... This turns out to have been a grave error, and instead of setting the default reset mechanism in igt, we have been disabling reset! Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index cb16410c2ada..45323732f099 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -63,7 +63,7 @@ struct drm_printer; param(char *, dmc_firmware_path, NULL, 0400) \ param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \ param(int, edp_vswing, 0, 0400) \ - param(int, reset, 3, 0600) \ + param(unsigned int, reset, 3, 0600) \ param(unsigned int, inject_probe_failure, 0, 0600) \ param(int, fastboot, -1, 0600) \ param(int, enable_dpcd_backlight, -1, 0600) \ -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
That is a crc mismatch which has nothing to do with DBuf: Starting subtest: pipe-A-viewport-size-128 (kms_plane_cursor:1056) igt_debugfs-CRITICAL: Test assertion failure function igt_assert_crc_equal, file ../lib/igt_debugfs.c:423: (kms_plane_cursor:1056) igt_debugfs-CRITICAL: Failed assertion: !mismatch || igt_skip_crc_compare Subtest pipe-A-viewport-size-128 failed. I guess we really need to push that already. Best Regards, Lisovskiy Stanislav Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo From: Patchwork Sent: Wednesday, February 5, 2020 1:33:28 PM To: Lisovskiy, Stanislav Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23) == Series Details == Series: Enable second DBuf slice for ICL and TGL (rev23) URL : https://patchwork.freedesktop.org/series/70059/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16386_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16386_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16386_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16386_full: ### IGT changes ### Possible regressions * igt@kms_plane_cursor@pipe-a-viewport-size-128: - shard-tglb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_plane_cur...@pipe-a-viewport-size-128.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_plane_cur...@pipe-a-viewport-size-128.html Known issues Here are the changes found in Patchwork_16386_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_eio@in-flight-suspend: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@gem_...@in-flight-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@gem_...@in-flight-suspend.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +18 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_sched...@out-order-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb7/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@gem_exec_sched...@wide-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html * igt@gem_exec_store@pages-vcs1: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_exec_st...@pages-vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@gem_exec_st...@pages-vcs1.html * igt@gem_exec_suspend@basic-s4-devices: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@gem_exec_susp...@basic-s4-devices.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@i915_pm...@dc6-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b: - shard-kbl:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
Added Lakshmi to cc, I guess we should have a bug somewhere about crc mismatch, as it can't be caused by changes in DBuf in absence of underruns and especially for single pipe. Best Regards, Lisovskiy Stanislav Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo From: Lisovskiy, Stanislav Sent: Wednesday, February 5, 2020 2:57:23 PM To: intel-gfx@lists.freedesktop.org Subject: Re: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23) That is a crc mismatch which has nothing to do with DBuf: Starting subtest: pipe-A-viewport-size-128 (kms_plane_cursor:1056) igt_debugfs-CRITICAL: Test assertion failure function igt_assert_crc_equal, file ../lib/igt_debugfs.c:423: (kms_plane_cursor:1056) igt_debugfs-CRITICAL: Failed assertion: !mismatch || igt_skip_crc_compare Subtest pipe-A-viewport-size-128 failed. I guess we really need to push that already. Best Regards, Lisovskiy Stanislav Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo From: Patchwork Sent: Wednesday, February 5, 2020 1:33:28 PM To: Lisovskiy, Stanislav Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23) == Series Details == Series: Enable second DBuf slice for ICL and TGL (rev23) URL : https://patchwork.freedesktop.org/series/70059/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16386_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16386_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16386_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16386_full: ### IGT changes ### Possible regressions * igt@kms_plane_cursor@pipe-a-viewport-size-128: - shard-tglb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_plane_cur...@pipe-a-viewport-size-128.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_plane_cur...@pipe-a-viewport-size-128.html Known issues Here are the changes found in Patchwork_16386_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_eio@in-flight-suspend: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@gem_...@in-flight-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@gem_...@in-flight-suspend.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +18 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_sched...@out-order-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb7/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@gem_exec_sched...@wide-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html * igt@gem_exec_store@pages-vcs1: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_exec_st...@pages-vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@gem_exec_st...@pages-vcs1.html * igt@gem_exec_suspend@basic-s4-devices: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@gem_exec_susp...@basic
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable use of hwsp_cacheline for kernel_context (rev2)
== Series Details == Series: drm/i915: Disable use of hwsp_cacheline for kernel_context (rev2) URL : https://patchwork.freedesktop.org/series/72992/ State : success == Summary == CI Bug Log - changes from CI_DRM_7869 -> Patchwork_16429 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/index.html Known issues Here are the changes found in Patchwork_16429 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] ([fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-y/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-kbl-x1275: [PASS][5] -> [DMESG-FAIL][6] ([i915#943]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bxt-dsi: [PASS][7] -> [TIMEOUT][8] ([fdo#112271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bxt-dsi/igt@i915_selftest@live_gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-bxt-dsi/igt@i915_selftest@live_gtt.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([i915#44]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@prime_self_import@basic-llseek-bad: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([CI#94] / [i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@prime_self_imp...@basic-llseek-bad.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-tgl-y/igt@prime_self_imp...@basic-llseek-bad.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][13] ([i915#45]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_parallel@fds: - fi-icl-u3: [INCOMPLETE][15] -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-u3/igt@gem_exec_paral...@fds.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-icl-u3/igt@gem_exec_paral...@fds.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][17] ([CI#94] / [i915#402]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_selftest@live_blt: - fi-bsw-nick:[INCOMPLETE][19] ([i915#392]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bsw-nick/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-bsw-nick/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][21] ([fdo#109635] / [i915#217]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#111096] / [i915#323]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16429/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][25] ([i915#553]) -> [DMESG-FAIL][26] ([i915#725]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-4770/igt@i915_selftest@live_blt.html [26]: https://intel-gf
[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_persistence: Check that we cannot hide hangs on old engines
As the kernel loses track of the context's old engines, if we request
that the context is non-persistent then any request on the untracked
engines must be cancelled.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_ctx_persistence.c | 62 +++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index c54797e9b..0db5c31c2 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -761,6 +761,51 @@ static void smoketest(int i915)
gem_quiescent_gpu(i915);
}
+static void replace_engines_hostile(int i915,
+ const struct intel_execution_engine2 *e)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ .engines = {{ e->class, e->instance }}
+ };
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ .size = sizeof(engines),
+ };
+ igt_spin_t *spin[2];
+ int64_t timeout;
+
+ /*
+* Suppose the user tries to hide a hanging batch by replacing
+* the set of engines on the context so that it's not visible
+* at the time of closure? Then we must act when they replace
+* the engines!
+*/
+
+ gem_context_set_persistence(i915, param.ctx_id, false);
+
+ gem_context_set_param(i915, ¶m);
+ spin[0] = igt_spin_new(i915, param.ctx_id,
+ .flags = IGT_SPIN_NO_PREEMPTION);
+
+ gem_context_set_param(i915, ¶m);
+ spin[1] = igt_spin_new(i915, param.ctx_id,
+ .flags = IGT_SPIN_NO_PREEMPTION);
+
+ gem_context_destroy(i915, param.ctx_id);
+
+ timeout = reset_timeout_ms * NSEC_PER_MSEC;
+ igt_assert_eq(gem_wait(i915, spin[1]->handle, &timeout), 0);
+
+ timeout = reset_timeout_ms * NSEC_PER_MSEC;
+ igt_assert_eq(gem_wait(i915, spin[0]->handle, &timeout), 0);
+
+ igt_spin_free(i915, spin[1]);
+ igt_spin_free(i915, spin[0]);
+ gem_quiescent_gpu(i915);
+}
+
int i915;
static void exit_handler(int sig)
@@ -793,10 +838,10 @@ igt_main
igt_assert(igt_sysfs_set_parameter
(i915, "reset", "%d", -1 /* any [default] reset */));
- igt_require(has_persistence(i915));
enable_hangcheck(i915);
igt_install_exit_handler(exit_handler);
+ igt_require(has_persistence(i915));
igt_allow_hang(i915, 0, 0);
}
@@ -861,6 +906,21 @@ igt_main
smoketest(i915);
}
+ /* Check interactions with set-engines */
+ igt_subtest_group {
+ const struct intel_execution_engine2 *e;
+
+ igt_fixture
+ gem_require_contexts(i915);
+
+ igt_subtest_with_dynamic("replace-hostile") {
+ __for_each_physical_engine(i915, e) {
+ igt_dynamic_f("%s", e->name)
+ replace_engines_hostile(i915, e);
+ }
+ }
+ }
+
igt_fixture {
close(i915);
}
--
2.25.0
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Re: [Intel-gfx] [PATCH] drm/i915: align dumb buffer stride to page_sz of the region
On 2020-02-05 at 12:05:11 +, Chris Wilson wrote:
> Quoting Ramalingam C (2020-02-05 12:02:50)
> > On 2020-02-05 at 11:43:35 +, Chris Wilson wrote:
> > > Quoting Ramalingam C (2020-02-05 11:40:19)
> > > > If stride of the dumb buffer requested is greater than the primary
> > > > plane's max stride, then we align the stride to the page size. But the
> > > > page size was hard coded for 4096.
> > > >
> > > > With the lmem addition, lets align the stride to the page size of the
> > > > memory region that will be used for dumb buffer.
> > > >
> > > > Signed-off-by: Ramalingam C
> > > > cc: Chris Wilson
> > > > ---
> > > > drivers/gpu/drm/i915/i915_gem.c | 20 +---
> > > > 1 file changed, 9 insertions(+), 11 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > > > b/drivers/gpu/drm/i915/i915_gem.c
> > > > index a712e60b016a..0f01396ca24e 100644
> > > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > > @@ -239,8 +239,9 @@ i915_gem_dumb_create(struct drm_file *file,
> > > > struct drm_device *dev,
> > > > struct drm_mode_create_dumb *args)
> > > > {
> > > > - enum intel_memory_type mem_type;
> > > > int cpp = DIV_ROUND_UP(args->bpp, 8);
> > > > + enum intel_memory_type mem_type;
> > > > + struct intel_memory_region *mr;
> > > > u32 format;
> > > >
> > > > switch (cpp) {
> > > > @@ -260,24 +261,21 @@ i915_gem_dumb_create(struct drm_file *file,
> > > > /* have to work out size/pitch and return them */
> > > > args->pitch = ALIGN(args->width * cpp, 64);
> > > >
> > > > + mem_type = INTEL_MEMORY_SYSTEM;
> > > > + if (HAS_LMEM(to_i915(dev)))
> > > > + mem_type = INTEL_MEMORY_LOCAL;
> > > > + mr = intel_memory_region_by_type(to_i915(dev), mem_type);
> > > > +
> > > > /* align stride to page size so that we can remap */
> > > > if (args->pitch > intel_plane_fb_max_stride(to_i915(dev),
> > > > format,
> > > >
> > > > DRM_FORMAT_MOD_LINEAR))
> > > > - args->pitch = ALIGN(args->pitch, 4096);
> > > > + args->pitch = ALIGN(args->pitch, mr->min_page_size);
> > >
> > > That should be ggtt-page size, different semantics, right?
> > Chris,
> >
> > Sicne the purpose(remapping stride) is not clear, couldn't understand
> > which page size this is. I assumed this is of hw page size.
> >
> > Btw, there is no issues found with 4096 on lmem too. May be this is
> > unwanted change, unless they meant hw page size here and luckily we are
> > not hitting the issue. I am not sure though.
>
> It for doing tricks with I915_GGTT_VIEW_REMAPPED (intel_remap_pages) so
> that a large framebuffer can be cut into CRTC-sized chunks and not go
> over the HW limits.
Sure. I will discard this change. Thanks for explaining that to me.
-Ram.
> -Chris
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[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_persistence: Check that we cannot hide hangs on old engines
As the kernel loses track of the context's old engines, if we request
that the context is non-persistent then any request on the untracked
engines must be cancelled.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_ctx_persistence.c | 60 +++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index c54797e9b..04a6c179e 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -761,6 +761,49 @@ static void smoketest(int i915)
gem_quiescent_gpu(i915);
}
+static void replace_engines_hostile(int i915,
+ const struct intel_execution_engine2 *e)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ .engines = {{ e->class, e->instance }}
+ };
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ .size = sizeof(engines),
+ };
+ igt_spin_t *spin[2];
+ int64_t timeout;
+
+ /*
+* Suppose the user tries to hide a hanging batch by replacing
+* the set of engines on the context so that it's not visible
+* at the time of closure? Then we must act when they replace
+* the engines!
+*/
+
+ gem_context_set_persistence(i915, param.ctx_id, false);
+
+ gem_context_set_param(i915, ¶m);
+ spin[0] = igt_spin_new(i915, param.ctx_id);
+
+ gem_context_set_param(i915, ¶m);
+ spin[1] = igt_spin_new(i915, param.ctx_id);
+
+ gem_context_destroy(i915, param.ctx_id);
+
+ timeout = reset_timeout_ms * NSEC_PER_MSEC;
+ igt_assert_eq(gem_wait(i915, spin[1]->handle, &timeout), 0);
+
+ timeout = reset_timeout_ms * NSEC_PER_MSEC;
+ igt_assert_eq(gem_wait(i915, spin[0]->handle, &timeout), 0);
+
+ igt_spin_free(i915, spin[1]);
+ igt_spin_free(i915, spin[0]);
+ gem_quiescent_gpu(i915);
+}
+
int i915;
static void exit_handler(int sig)
@@ -793,10 +836,10 @@ igt_main
igt_assert(igt_sysfs_set_parameter
(i915, "reset", "%d", -1 /* any [default] reset */));
- igt_require(has_persistence(i915));
enable_hangcheck(i915);
igt_install_exit_handler(exit_handler);
+ igt_require(has_persistence(i915));
igt_allow_hang(i915, 0, 0);
}
@@ -861,6 +904,21 @@ igt_main
smoketest(i915);
}
+ /* Check interactions with set-engines */
+ igt_subtest_group {
+ const struct intel_execution_engine2 *e;
+
+ igt_fixture
+ gem_require_contexts(i915);
+
+ igt_subtest_with_dynamic("replace-hostile") {
+ __for_each_physical_engine(i915, e) {
+ igt_dynamic_f("%s", e->name)
+ replace_engines_hostile(i915, e);
+ }
+ }
+ }
+
igt_fixture {
close(i915);
}
--
2.25.0
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Re: [Intel-gfx] [PATCH] drm/i915: Mark i915.reset as unsigned
Chris Wilson writes: > We have been using '-1' to mean the maximum i915.reset level in the > belief that it was unsigned... This turns out to have been a grave > error, and instead of setting the default reset mechanism in igt, > we have been disabling reset! Disabling engine reset? -Mika > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/i915_params.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_params.h > b/drivers/gpu/drm/i915/i915_params.h > index cb16410c2ada..45323732f099 100644 > --- a/drivers/gpu/drm/i915/i915_params.h > +++ b/drivers/gpu/drm/i915/i915_params.h > @@ -63,7 +63,7 @@ struct drm_printer; > param(char *, dmc_firmware_path, NULL, 0400) \ > param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \ > param(int, edp_vswing, 0, 0400) \ > - param(int, reset, 3, 0600) \ > + param(unsigned int, reset, 3, 0600) \ > param(unsigned int, inject_probe_failure, 0, 0600) \ > param(int, fastboot, -1, 0600) \ > param(int, enable_dpcd_backlight, -1, 0600) \ > -- > 2.25.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Flush execution tasklets before checking request status
== Series Details == Series: series starting with [1/2] drm/i915: Flush execution tasklets before checking request status URL : https://patchwork.freedesktop.org/series/73013/ State : success == Summary == CI Bug Log - changes from CI_DRM_7869 -> Patchwork_16430 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/index.html Known issues Here are the changes found in Patchwork_16430 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] ([fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-y/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gtt: - fi-hsw-4770:[PASS][5] -> [TIMEOUT][6] ([fdo#112271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-4770/igt@i915_selftest@live_gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-hsw-4770/igt@i915_selftest@live_gtt.html * igt@kms_addfb_basic@addfb25-x-tiled: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@kms_addfb_ba...@addfb25-x-tiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-tgl-y/igt@kms_addfb_ba...@addfb25-x-tiled.html Possible fixes * igt@gem_exec_parallel@fds: - fi-icl-u3: [INCOMPLETE][9] -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-u3/igt@gem_exec_paral...@fds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-icl-u3/igt@gem_exec_paral...@fds.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_module_load@reload: - fi-skl-6770hq: [DMESG-WARN][13] ([i915#92]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-6770hq/igt@i915_module_l...@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-bsw-nick:[INCOMPLETE][15] ([i915#392]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bsw-nick/igt@i915_selftest@live_blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-bsw-nick/igt@i915_selftest@live_blt.html - fi-ivb-3770:[DMESG-FAIL][17] ([i915#725]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-ivb-3770/igt@i915_selftest@live_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-ivb-3770/igt@i915_selftest@live_blt.html - fi-hsw-4770:[DMESG-FAIL][19] ([i915#553]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-4770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][21] ([fdo#109635] / [i915#217]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#111096] / [i915#323]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [SKIP][25] ([fdo#109271]) -> [PASS][26] +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16430/fi-skl-6770hq/igt@kms_pi
Re: [Intel-gfx] [PATCH] drm/i915: Mark i915.reset as unsigned
Quoting Mika Kuoppala (2020-02-05 14:03:14)
> Chris Wilson writes:
>
> > We have been using '-1' to mean the maximum i915.reset level in the
> > belief that it was unsigned... This turns out to have been a grave
> > error, and instead of setting the default reset mechanism in igt,
> > we have been disabling reset!
>
> Disabling engine reset?
Hmm, Right,
bool intel_has_gpu_reset(const struct intel_gt *gt)
{
if (!i915_modparams.reset)
return NULL;
return intel_get_gpu_reset(gt);
}
bool intel_has_reset_engine(const struct intel_gt *gt)
{
if (i915_modparams.reset < 2)
return false;
return INTEL_INFO(gt->i915)->has_reset_engine;
}
just engine-reset. Still that wasn't the intention when setting -1.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Mark i915.reset as unsigned
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-02-05 14:03:14)
>> Chris Wilson writes:
>>
>> > We have been using '-1' to mean the maximum i915.reset level in the
>> > belief that it was unsigned... This turns out to have been a grave
>> > error, and instead of setting the default reset mechanism in igt,
>> > we have been disabling reset!
>>
>> Disabling engine reset?
>
> Hmm, Right,
>
> bool intel_has_gpu_reset(const struct intel_gt *gt)
> {
> if (!i915_modparams.reset)
> return NULL;
>
> return intel_get_gpu_reset(gt);
> }
>
> bool intel_has_reset_engine(const struct intel_gt *gt)
> {
> if (i915_modparams.reset < 2)
> return false;
>
> return INTEL_INFO(gt->i915)->has_reset_engine;
> }
>
> just engine-reset. Still that wasn't the intention when setting -1.
I was trying to correlate the graveness to the code.
Glad that we agree. With commit message pointing to per engine
reset,
Reviewed-by: Mika Kuoppala
> -Chris
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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/dp: Compute port sync crtc states post compute_config()
On Sun, Feb 02, 2020 at 11:47:55PM -0800, Manasi Navare wrote:
> This patch pushes out the computation of master and slave
> transcoders in crtc states after encoder's compute_config hook.
> This ensures that the assigned master slave crtcs have exact same
> mode and timings which is a requirement for Port sync mode
> to be enabled.
>
> v2:
> * Correct indentation
> * Rename to intel_ddi_port_sync_transcoders (Ville)
> * remove unwanted debug (Ville)
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 109 +
> drivers/gpu/drm/i915/display/intel_display.c | 159 +--
> 2 files changed, 110 insertions(+), 158 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index aa066fb9eb00..eb970797cd68 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4448,6 +4448,114 @@ static int intel_ddi_compute_config(struct
> intel_encoder *encoder,
> return 0;
> }
>
> +static bool mode_equal(const struct drm_display_mode *mode1,
> +const struct drm_display_mode *mode2)
> +{
> + return drm_mode_match(mode1, mode2,
> + DRM_MODE_MATCH_TIMINGS |
> + DRM_MODE_MATCH_FLAGS |
> + DRM_MODE_MATCH_3D_FLAGS) &&
> + mode1->clock == mode2->clock; /* we want an exact match */
> +}
> +
> +static bool m_n_equal(const struct intel_link_m_n *m_n_1,
> + const struct intel_link_m_n *m_n_2)
> +{
> + return m_n_1->tu == m_n_2->tu &&
> + m_n_1->gmch_m == m_n_2->gmch_m &&
> + m_n_1->gmch_n == m_n_2->gmch_n &&
> + m_n_1->link_m == m_n_2->link_m &&
> + m_n_1->link_n == m_n_2->link_n;
> +}
> +
> +static bool crtcs_port_sync_compatible(const struct intel_crtc_state
> *crtc_state1,
> +const struct intel_crtc_state
> *crtc_state2)
> +{
> + return crtc_state1->hw.active && crtc_state2->hw.active &&
> + crtc_state1->output_types == crtc_state2->output_types &&
> + crtc_state1->output_format == crtc_state2->output_format &&
> + crtc_state1->lane_count == crtc_state2->lane_count &&
> + crtc_state1->port_clock == crtc_state2->port_clock &&
> + mode_equal(&crtc_state1->hw.adjusted_mode,
> +&crtc_state2->hw.adjusted_mode) &&
> + m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
> +}
> +
> +static u8
> +intel_ddi_port_sync_transcoders(const struct intel_crtc_state
> *ref_crtc_state,
> + int tile_group_id)
> +{
> + struct drm_connector *connector;
> + struct drm_connector_state *conn_state;
Can be const
> + struct drm_i915_private *dev_priv =
> to_i915(ref_crtc_state->uapi.crtc->dev);
> + struct intel_atomic_state *state =
> + to_intel_atomic_state(ref_crtc_state->uapi.state);
> + u8 transcoders = 0;
> + int i;
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return 0;
> +
> + if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
> + return 0;
> +
> + for_each_new_connector_in_state(&state->base, connector, conn_state, i)
> {
> + struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
> + struct intel_crtc_state *crtc_state = NULL;
Can be const
Pointless NULL initialization.
> +
> + if (!crtc)
> + continue;
> +
> + if (!(connector->has_tile &&
> + connector->tile_group->id ==
> + tile_group_id))
I'd write that as
if (!has_tile || id != group_id)
Looks like some pointless newlines in there. Makes it look a bit ugly.
Otherwise lgtm
Reviewed-by: Ville Syrjälä
> + continue;
> +
> + crtc_state = intel_atomic_get_new_crtc_state(state,
> + crtc);
> + if (!crtcs_port_sync_compatible(ref_crtc_state,
> + crtc_state))
> + continue;
> +
> + transcoders |= BIT(crtc_state->cpu_transcoder);
> + }
> +
> + return transcoders;
> +}
> +
> +static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> +{
> + struct drm_connector *connector = conn_state->connector;
> + u8 port_sync_transcoders = 0;
> +
> + DRM_DEBUG_KMS("[ENCODER:%d:%s] [CRTC:%d:%s]",
> + encoder->base.base.id, encoder->base.name,
> + crtc_state->uapi.crtc->base.id,
> crtc_state->uapi.crtc->name);
> +
> + if (connector->has_tile)
>
Re: [Intel-gfx] [PATCH] drm/i915/selftests: add basic selftests for rc6
Chris Wilson writes:
> From: Andi Shyti
>
> Add three basic tests for rc6 power status:
>
> 1. live_rc6_basic - simply checks if rc6 works when it's enabled
>or stops when it's disabled.
>
> 2. live_rc6_threshold - rc6 should not work when the evaluation
>interval is less than the threshold and should work otherwise.
>
> 3. live_rc6_busy - keeps the gpu busy and then goes in idle;
>checks that we don't fall in rc6 when busy and that we do fall
>in rc6 when idling.
>
> The three tests are added as sutest of the bigger live_late_gt_pm
> selftest.
>
> The basic rc6 functionality is tested by checking the reference
> counter within the evaluation interval.
>
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 173 +++
> drivers/gpu/drm/i915/gt/selftest_rc6.h | 2 +
> 3 files changed, 177 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> index 09ff8e4f88af..5c7b92301a14 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> @@ -52,6 +52,8 @@ int intel_gt_pm_live_selftests(struct drm_i915_private
> *i915)
> {
> static const struct i915_subtest tests[] = {
> SUBTEST(live_rc6_manual),
> + SUBTEST(live_rc6_threshold),
> + SUBTEST(live_rc6_busy),
> SUBTEST(live_gt_resume),
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 5f7e2dcf5686..92375f458845 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -11,6 +11,7 @@
> #include "selftest_rc6.h"
>
> #include "selftests/i915_random.h"
> +#include "selftests/igt_spinner.h"
>
> int live_rc6_manual(void *arg)
> {
> @@ -202,3 +203,175 @@ int live_rc6_ctx_wa(void *arg)
> kfree(engines);
> return err;
> }
> +
> +static bool test_rc6(struct intel_rc6 *rc6, bool enabled)
> +{
> + struct intel_uncore *uncore = rc6_to_uncore(rc6);
> + intel_wakeref_t wakeref;
> + u32 ec1, ec2;
> + u32 interval;
> +
> + wakeref = intel_runtime_pm_get(uncore->rpm);
> +
> + interval = intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL);
> +
> + /*
> + * the interval is stored in steps of 1.28us
> + */
> + interval = div_u64(mul_u32_u32(interval, 128),
> +100 * 1000); /* => miliseconds */
> +
s/miliseconds/milliseconds.
I have a faint memory that the interval was not always 1.28us
but gen dependant.
> + ec1 = intel_uncore_read(uncore, GEN6_GT_GFX_RC6);
> +
> + /*
> + * It's not important to precisely wait the interval time.
> + * I'll wait at least twice the time in order to be sure
> + * that the counting happens in the reference counter.
> + */
> + msleep(2 * interval);
> +
> + ec2 = intel_uncore_read(uncore, GEN6_GT_GFX_RC6);
> +
> + pr_info("interval:%x [%dms], threshold:%x, rc6:%x, enabled?:%s\n",
> + intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL),
> + interval,
> + intel_uncore_read(uncore, GEN6_RC6_THRESHOLD),
> + ec2 - ec1,
> + yesno(enabled));
> +
> + intel_runtime_pm_put(uncore->rpm, wakeref);
> +
> + return enabled != (ec1 >= ec2);
Wrap?
> +}
> +
> +int live_rc6_threshold(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + struct intel_uncore *uncore = gt->uncore;
> + struct intel_rc6 *rc6 = >->rc6;
> + intel_wakeref_t wakeref;
> + u32 threshold, interval;
> + u32 t_orig, i_orig;
> + int err = 0;
> +
> + if (!rc6->manual) /* No interferring PCU! */
> + return 0;
> +
> + wakeref = intel_runtime_pm_get(uncore->rpm);
> +
> + __intel_rc6_disable(rc6); /* stop before adjusting thresholds */
> +
> + t_orig = intel_uncore_read(uncore, GEN6_RC6_THRESHOLD);
> + i_orig = intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL);
> +
> + /*
> + * set the threshold to 50ms
> + *
> + * 50ms * 1000 = 5us
> + * 5 / (1.28 * 100) / 100 (we don't have floating point)
> + */
> + threshold = 50 * 1000 / 128 * 100;
> + intel_uncore_write(uncore, GEN6_RC6_THRESHOLD, threshold);
> +
> + /* set interval indicatively to half the threshold */
> + interval = threshold / 2;
> + intel_uncore_write(uncore, GEN6_RC_EVALUATION_INTERVAL, interval);
> +
> + intel_rc6_unpark(rc6);
> +
> + /* interval < threshold */
> + if (!test_rc6(rc6, false)) {
consider removing the assertion of 'activeness' in parameter
and just if (!rc6_active(rc6)). Or am I missing something in here?
-Mika
> + pr_err("i915 mismatch: rc6 with interval < threshold\n");
> + err = -EINVAL;
> + }
> +
> + __intel_rc6_disable(rc6);
> +
> + /* set in
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/dp: Add all tiled and port sync conns to modeset
On Sun, Feb 02, 2020 at 11:47:56PM -0800, Manasi Navare wrote:
> If one of the synced crtcs needs a full modeset, we need
> to make sure all the synced crtcs are forced a full
> modeset.
>
> v2:
> * Add tiles based on cpu_trans check (Ville)
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 85 ---
> drivers/gpu/drm/i915/display/intel_dp.c | 142 ++-
> 2 files changed, 141 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a943787167de..6383d1287472 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14669,76 +14669,6 @@ static bool
> intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
> return false;
> }
>
> -static int
> -intel_modeset_all_tiles(struct intel_atomic_state *state, int tile_grp_id)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct drm_connector *connector;
> - struct drm_connector_list_iter conn_iter;
> - int ret = 0;
> -
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> - drm_for_each_connector_iter(connector, &conn_iter) {
> - struct drm_connector_state *conn_state;
> - struct drm_crtc_state *crtc_state;
> -
> - if (!connector->has_tile ||
> - connector->tile_group->id != tile_grp_id)
> - continue;
> - conn_state = drm_atomic_get_connector_state(&state->base,
> - connector);
> - if (IS_ERR(conn_state)) {
> - ret = PTR_ERR(conn_state);
> - break;
> - }
> -
> - if (!conn_state->crtc)
> - continue;
> -
> - crtc_state = drm_atomic_get_crtc_state(&state->base,
> -conn_state->crtc);
> - if (IS_ERR(crtc_state)) {
> - ret = PTR_ERR(crtc_state);
> - break;
> - }
> - crtc_state->mode_changed = true;
> - ret = drm_atomic_add_affected_connectors(&state->base,
> - conn_state->crtc);
> - if (ret)
> - break;
> - }
> - drm_connector_list_iter_end(&conn_iter);
> -
> - return ret;
> -}
> -
> -static int
> -intel_atomic_check_tiled_conns(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct drm_connector *connector;
> - struct drm_connector_state *old_conn_state, *new_conn_state;
> - int i, ret;
> -
> - if (INTEL_GEN(dev_priv) < 11)
> - return 0;
> -
> - /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> - for_each_oldnew_connector_in_state(&state->base, connector,
> -old_conn_state, new_conn_state, i) {
> - if (!connector->has_tile)
> - continue;
> - if (!intel_connector_needs_modeset(state, connector))
> - continue;
> -
> - ret = intel_modeset_all_tiles(state, connector->tile_group->id);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> /**
> * intel_atomic_check - validate state object
> * @dev: drm device
> @@ -14767,21 +14697,6 @@ static int intel_atomic_check(struct drm_device *dev,
> if (ret)
> goto fail;
>
> - /**
> - * This check adds all the connectors in current state that belong to
> - * the same tile group to a full modeset.
> - * This function directly sets the mode_changed to true and we also call
> - * drm_atomic_add_affected_connectors(). Hence we are not explicitly
> - * calling drm_atomic_helper_check_modeset() after this.
> - *
> - * Fixme: Handle some corner cases where one of the
> - * tiled connectors gets disconnected and tile info is lost but since it
> - * was previously synced to other conn, we need to add that to the
> modeset.
> - */
> - ret = intel_atomic_check_tiled_conns(state);
> - if (ret)
> - goto fail;
> -
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if (!needs_modeset(new_crtc_state)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f4dede6253f8..07f0374d4409 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6582,6 +6582,146 @@ void intel_dp_encoder_reset(struct drm_encoder
> *encoder)
> }
> }
>
Re: [Intel-gfx] [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a
> structure
%s/add/Add/
Also you can rephrase this as " Add DP1.4 VSC SDP Payload related Data
Structures"/
> It adds new enumeration definitions for VSC SDP Payload for Pixel
> Encoding/Colorimetry Format.
> And it adds a new drm data structure for DP VSC SDP.
>
> enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
> Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
> And enum dp_content_type corresponds "Content Type"
> All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
> DB16 through DB18].
>
> v3: Add a new drm data structure for DP VSC SDP
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> include/drm/drm_dp_helper.h | 57 +
> 1 file changed, 57 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> 262faf9e5e94..c098727681fa 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1209,6 +1209,63 @@ struct dp_sdp {
> #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
> #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
>
> +/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
> +DB18] */ enum dp_colorspace {
We should not call this colorspace, rather rename it to dp_pixelformat.
These are not colorspaces.
Also add these to kernel docs as they are standard definitions.
> + DP_COLORSPACE_RGB = 0,
Make this as DP_PIXELFORMAT_RGB and rename all the below ones as well.
> + DP_COLORSPACE_YUV444 = 0x1,
> + DP_COLORSPACE_YUV422 = 0x2,
> + DP_COLORSPACE_YUV420 = 0x3,
> + DP_COLORSPACE_Y_ONLY = 0x4,
> + DP_COLORSPACE_RAW = 0x5,
> + DP_COLORSPACE_RESERVED = 0x6,
> +};
> +
> +/**
> + * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
> +DB18]
> + * and a name of enum member followes DRM_MODE_COLORIMETRY definition.
Typo in follows
> + */
> +enum dp_colorimetry {
You can call this as dp_colorspace (this is actual colorspace), you can stick
with colorimetry as well.
Will leave that to you.
> + DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
> + DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
> + DP_COLORIMETRY_BT709_YCC = 0x1,
> + DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
> + DP_COLORIMETRY_XVYCC_601 = 0x2,
> + DP_COLORIMETRY_OPRGB = 0x3,
> + DP_COLORIMETRY_XVYCC_709 = 0x3,
> + DP_COLORIMETRY_DCI_P3_RGB = 0x4,
> + DP_COLORIMETRY_SYCC_601 = 0x4,
> + DP_COLORIMETRY_RGB_CUSTOM = 0x5,
> + DP_COLORIMETRY_OPYCC_601 = 0x5,
> + DP_COLORIMETRY_BT2020_RGB = 0x6,
> + DP_COLORIMETRY_BT2020_CYCC = 0x6,
> + DP_COLORIMETRY_BT2020_YCC = 0x7,
> +};
> +
> +enum dp_dynamic_range {
> + DP_DYNAMIC_RANGE_VESA = 0,
> + DP_DYNAMIC_RANGE_CTA = 1,
> +};
> +
> +enum dp_content_type {
> + DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
> + DP_CONTENT_TYPE_GRAPHICS = 0x01,
> + DP_CONTENT_TYPE_PHOTO = 0x02,
> + DP_CONTENT_TYPE_VIDEO = 0x03,
> + DP_CONTENT_TYPE_GAME = 0x04,
> +};
> +
> +/* DRM DP VSC SDP as per DP 1.4 spec */ struct drm_dp_vsc_sdp {
> + unsigned char sdp_type; /* Secondary-data Packet Type */
> + unsigned char revision; /* Revision Number */
These comments seems self-explanatory, you can probably drop them.
> + unsigned char length; /* Number of Valid Data Bytes */
> + enum dp_colorspace colorspace;
> + enum dp_colorimetry colorimetry;
> + int bpc; /* bit per color */
> + enum dp_dynamic_range dynamic_range;
> + enum dp_content_type content_type;
> +};
> +
> int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
>
> static inline int
> --
> 2.24.1
>
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Flush execution tasklets before checking request status
Chris Wilson writes:
> Rather than flushing the submission tasklets just before we sleep, flush
> before we check the request status. Ideally this gives us a moment to
> process the tasklets after sleeping just before we timeout.
Makes sense to check the possibly most recent state.
Reviewed-by: Mika Kuoppala
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c
> b/drivers/gpu/drm/i915/i915_request.c
> index f56b046a32de..5c2bb0b9478b 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1564,6 +1564,7 @@ long i915_request_wait(struct i915_request *rq,
> goto out;
>
> for (;;) {
> + intel_engine_flush_submission(rq->engine);
> set_current_state(state);
>
> if (i915_request_completed(rq)) {
> @@ -1581,7 +1582,6 @@ long i915_request_wait(struct i915_request *rq,
> break;
> }
>
> - intel_engine_flush_submission(rq->engine);
> timeout = io_schedule_timeout(timeout);
> }
> __set_current_state(TASK_RUNNING);
> --
> 2.25.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Wean off drm_pci_alloc/drm_pci_free
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: de09d31dd38a ("page-flags: define PG_reserved behavior on
compound pages").
The bot has tested the following trees: v5.5.1, v5.4.17, v4.19.101, v4.14.169,
v4.9.212.
v5.5.1: Build OK!
v5.4.17: Build OK!
v4.19.101: Failed to apply! Possible dependencies:
4a3d3f6785be ("drm/i915: Match code to comment and enforce ppgtt for
execlists")
4bdafb9ddfa4 ("drm/i915: Remove i915.enable_ppgtt override")
5771caf885ae ("drm/i915/skl+: Decode memory bandwidth and parameters")
6323113b7af6 ("drm/i915: Move SKL IPC WA to HAS_IPC()")
79556df293b2 ("drm/i915/gtt: Enable full-ppgtt by default everywhere")
86b592876cb6 ("drm/i915: Implement 16GB dimm wa for latency level-0")
8a6c5447635c ("drm/i915/kbl+: Enable IPC only for symmetric memory
configurations")
900ccf30f9e1 ("drm/i915: Only force GGTT coherency w/a on required
chipsets")
cbfa59d4b331 ("drm/i915/bxt: Decode memory bandwidth and parameters")
d53db442db36 ("drm/i915: Move display device info capabilities to its own
struct")
f361912aa9bf ("drm/i915/skl+: don't trust IPC value set by BIOS")
fd847b8e60e0 ("drm/i915: Do not modifiy reserved bit in gens that do not
have IPC")
v4.14.169: Failed to apply! Possible dependencies:
0d6fc92a73e0 ("drm/i915: Separate RPS and RC6 handling for VLV")
37d933fc1728 ("drm/i915: Introduce separate status variable for RC6 and LLC
ring frequency setup")
3e8ddd9e5071 ("drm/i915: Nuke some bogus tabs from the pcode defines")
562d9bae08a1 ("drm/i915: Name structure in dev_priv that contains RPS/RC6
state as "gt_pm"")
61843f0e6212 ("drm/i915: Name the IPS_PCODE_CONTROL bit")
771decb0b4d7 ("drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled")
960e54652cee ("drm/i915: Separate RPS and RC6 handling for gen6+")
9f817501bd7f ("drm/i915: Move rps.hw_lock to dev_priv and
s/hw_lock/pcu_lock")
c56b89f16dd0 ("drm/i915: Use INTEL_GEN everywhere")
d46b00dc38c8 ("drm/i915: Separate RPS and RC6 handling for CHV")
d53db442db36 ("drm/i915: Move display device info capabilities to its own
struct")
fb6db0f5bf1d ("drm/i915: Remove unsafe i915.enable_rc6")
v4.9.212: Failed to apply! Possible dependencies:
0031fb96859c ("drm/i915: Assorted dev_priv cleanups")
03cdc1d4f795 ("drm/i915: Store port enum in intel_encoder")
4f8036a28112 ("drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take
dev_priv")
50a0bc905416 ("drm/i915: Make INTEL_DEVID only take dev_priv")
6e266956a57f ("drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv")
8652744b647e ("drm/i915: Make IS_BROADWELL only take dev_priv")
d53db442db36 ("drm/i915: Move display device info capabilities to its own
struct")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks,
Sasha
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Re: [Intel-gfx] [PATCH] drm/i915: Disable use of hwsp_cacheline for kernel_context
Chris Wilson writes: > Currently on execlists, we use a local hwsp for the kernel_context, > rather than the engine's HWSP, as this is the default for execlists. > However, seqno rollover requires allocating a new HWSP cachline, and may s/cachline/cacheline -Mika ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP
>
> In order to support state readout for DP VSC SDP, we need to have a structure
> which
> holds DP VSC SDP payload data such as "union hdmi_infoframe drm" which is used
> for DRM infoframe.
> It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.
>
> And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
> While computing we'll also fill out the inforames.enable bitmask
> appropriately.
>
> The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
> DB16 through DB18].
>
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>
With the structure names updated, this looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 92 +++
> 2 files changed, 93 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 33ba93863488..6633c1061670 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1021,6 +1021,7 @@ struct intel_crtc_state {
> union hdmi_infoframe spd;
> union hdmi_infoframe hdmi;
> union hdmi_infoframe drm;
> + struct drm_dp_vsc_sdp vsc;
> } infoframes;
>
> /* HDMI scrambling status */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f4dede6253f8..2bdc43c80e03 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct
> drm_i915_private *dev_priv,
> return true;
> }
>
> +static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
> *crtc_state,
> + const struct drm_connector_state
> *conn_state,
> + struct drm_dp_vsc_sdp *vsc)
> +{
> + /*
> + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> + * Colorimetry Format indication.
> + */
> + vsc->revision = 0x5;
> + vsc->length = 0x13;
> +
> + /* DP 1.4a spec, Table 2-120 */
> + switch (crtc_state->output_format) {
> + case INTEL_OUTPUT_FORMAT_YCBCR444:
> + vsc->colorspace = DP_COLORSPACE_YUV444;
> + break;
> + case INTEL_OUTPUT_FORMAT_YCBCR420:
> + vsc->colorspace = DP_COLORSPACE_YUV420;
> + break;
> + case INTEL_OUTPUT_FORMAT_RGB:
> + default:
> + vsc->colorspace = DP_COLORSPACE_RGB;
> + }
> +
> + switch (conn_state->colorspace) {
> + case DRM_MODE_COLORIMETRY_BT709_YCC:
> + vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
> + break;
> + case DRM_MODE_COLORIMETRY_XVYCC_601:
> + vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
> + break;
> + case DRM_MODE_COLORIMETRY_XVYCC_709:
> + vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
> + break;
> + case DRM_MODE_COLORIMETRY_SYCC_601:
> + vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
> + break;
> + case DRM_MODE_COLORIMETRY_OPYCC_601:
> + vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
> + break;
> + case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> + vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
> + break;
> + case DRM_MODE_COLORIMETRY_BT2020_RGB:
> + vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
> + break;
> + case DRM_MODE_COLORIMETRY_BT2020_YCC:
> + vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
> + break;
> + case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> + case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> + vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
> + break;
> + default:
> + /*
> + * RGB->YCBCR color conversion uses the BT.709
> + * color space.
> + */
> + if (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> + vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
> + else
> + vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
> + break;
> + }
> +
> + vsc->bpc = crtc_state->pipe_bpp / 3;
> + /* all YCbCr are always limited range */
> + vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
> + vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
Re: [Intel-gfx] [PATCH] drm/i915: Disable use of hwsp_cacheline for kernel_context
Quoting Mika Kuoppala (2020-02-05 14:50:58) > Chris Wilson writes: > > > Currently on execlists, we use a local hwsp for the kernel_context, > > rather than the engine's HWSP, as this is the default for execlists. > > However, seqno rollover requires allocating a new HWSP cachline, and may > > s/cachline/cacheline That's the only thing stopping an r-b? :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Relax timeout for error-interrupt reset processing
We can not require that the system process a tasklet in reasonable time
(thanks be to ksoftirqd), but we can insist that having waited
sufficiently for the error interrupt to have been raised and having
kicked the tasklet, the reset has begun and the request will be marked
as in error (if not already completed).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 79b9f7d092e4..e3c360b6c4f1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -500,14 +500,21 @@ static int live_error_interrupt(void *arg)
}
for (i = 0; i < ARRAY_SIZE(client); i++) {
- if (i915_request_wait(client[i], 0, HZ / 5) <
0) {
- pr_err("%s: %s request still
executing!\n",
- engine->name,
- error_repr(p->error[i]));
+ if (i915_request_wait(client[i], 0, HZ / 5) < 0)
+ pr_debug("%s: %s request incomplete!\n",
+engine->name,
+error_repr(p->error[i]));
+
+ if (!i915_request_started(client[i])) {
+ pr_debug("%s: %s request not stated!\n",
+engine->name,
+error_repr(p->error[i]));
err = -ETIME;
goto out;
}
+ /* Kick the tasklet to process the error */
+ intel_engine_flush_submission(engine);
if (client[i]->fence.error != p->error[i]) {
pr_err("%s: %s request completed with
wrong error code: %d\n",
engine->name,
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: add basic selftests for rc6 (rev5)
== Series Details == Series: drm/i915/selftests: add basic selftests for rc6 (rev5) URL : https://patchwork.freedesktop.org/series/69825/ State : warning == Summary == $ dim checkpatch origin/drm-tip 342c89d084c1 drm/i915/selftests: add basic selftests for rc6 -:89: ERROR:CODE_INDENT: code indent should use tabs where possible #89: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:239: +^I ^Iec2 - ec1,$ -:89: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #89: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:239: +^I ^Iec2 - ec1,$ -:90: ERROR:CODE_INDENT: code indent should use tabs where possible #90: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:240: +^I ^Iyesno(enabled));$ -:90: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #90: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:240: +^I ^Iyesno(enabled));$ -:107: WARNING:TYPO_SPELLING: 'interferring' may be misspelled - perhaps 'interfering'? #107: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:257: + if (!rc6->manual) /* No interferring PCU! */ total: 2 errors, 3 warnings, 0 checks, 199 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata
> Infoframe SDP
>
> It stores computed dp hdr metadata infoframe sdp to infoframes.drm of crtc
> state.
> It referenced intel_hdmi_compute_drm_infoframe().
>
> While computing, we'll also fill out the inforames.enable bitmask
> appropriately.
Typo in infoframes
With the above fixed, this is
Reviewed-by: Uma Shankar
>
> v2: Wrap a long line.
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2bdc43c80e03..b265b5c599f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,27 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>&crtc_state->infoframes.vsc);
> }
>
> +static void
> +intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
> + const struct drm_connector_state
> *conn_state) {
> + int ret;
> + struct hdmi_drm_infoframe *drm_infoframe =
> +&crtc_state->infoframes.drm.drm;
> +
> + if (!conn_state->hdr_output_metadata)
> + return;
> +
> + ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
> +
> + if (ret) {
> + DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
> + return;
> + }
> +
> + crtc_state->infoframes.enable |=
> +
> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> +}
> +
> int
> intel_dp_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config, @@ -2569,6 +2590,7
> @@ intel_dp_compute_config(struct intel_encoder *encoder,
>
> intel_psr_compute_config(intel_dp, pipe_config);
> intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> + intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
>
> return 0;
> }
> --
> 2.24.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/3] drm/i915: Introduce encoder->compute_config_late()
== Series Details == Series: series starting with [v2,1/3] drm/i915: Introduce encoder->compute_config_late() URL : https://patchwork.freedesktop.org/series/72891/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16387_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16387_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16387_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16387_full: ### IGT changes ### Possible regressions * igt@gem_exec_await@wide-contexts: - shard-skl: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@gem_exec_aw...@wide-contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-skl4/igt@gem_exec_aw...@wide-contexts.html * igt@gem_exec_schedule@semaphore-codependency: - shard-kbl: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl4/igt@gem_exec_sched...@semaphore-codependency.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-kbl1/igt@gem_exec_sched...@semaphore-codependency.html * igt@runner@aborted: - shard-kbl: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-kbl1/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_16387_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#112080]) +9 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_b...@busy-vcs1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-iclb7/igt@gem_b...@busy-vcs1.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#109276]) +16 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_sched...@out-order-bsd2.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-iclb8/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][10] -> [SKIP][11] ([i915#677]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb7/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-iclb4/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#112146]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl3/igt@gem_soft...@noreloc-s3.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-apl4/igt@gem_soft...@noreloc-s3.html * igt@kms_color@pipe-a-ctm-0-5: - shard-skl: [PASS][16] -> [DMESG-WARN][17] ([i915#109]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl5/igt@kms_co...@pipe-a-ctm-0-5.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-skl9/igt@kms_co...@pipe-a-ctm-0-5.html * igt@kms_draw_crc@draw-method-xrgb-blt-ytiled: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#52] / [i915#54]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-skl5/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][20] -> [INCOMPLETE][21] ([i915#221]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl6/igt@kms_f...@flip-vs-suspend-interruptible.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16387/shard-skl10/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt: - shard-skl: [PASS][22] -> [FAIL][23] ([i915#49]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_frontbuffer_track...@psr-1p-primscrn-shrfb-plflip-blt.htm
[Intel-gfx] [PATCH v2] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
function which also includes pinning and map in cpu domain.
No change is dsb write/commit functions.
Now dsb get/put function is refactored and currently used only for
reference counting. Below dsb api added to do respective job
mentioned below.
intel_dsb_prepare - Allocate, pin and map the buffer.
intel_dsb_cleanup - Unpin and release the gem object.
RFC: Initial patch for design review.
v2: included _init() part in _prepare(). [Daniel, Ville]
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 13 ++
drivers/gpu/drm/i915/display/intel_dsb.c | 132 ---
drivers/gpu/drm/i915/display/intel_dsb.h | 2 +
4 files changed, 101 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 379c12f3b1d4..949272e60a04 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -290,7 +290,9 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ intel_dsb_cleanup(intel_crtc);
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 368e481d45ee..4e3b422f0a29 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15076,6 +15076,19 @@ static int intel_atomic_check(struct drm_device *dev,
static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
{
+ struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ bool mode_changed = needs_modeset(crtc_state);
+
+ if (mode_changed || crtc_state->update_pipe ||
+ crtc_state->uapi.color_mgmt_changed) {
+ intel_dsb_prepare(crtc);
+ }
+ }
+
return drm_atomic_helper_prepare_planes(state->base.dev,
&state->base);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 76ae01277fd6..fc9fc23b5fc1 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -34,6 +34,86 @@
#define DSB_BYTE_EN_SHIFT 20
#define DSB_REG_VALUE_MASK 0xf
+/**
+ * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function prepare the command buffer which is used to store dsb
+ * instructions with data.
+ */
+
+void intel_dsb_prepare(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_dsb *dsb = &crtc->dsb;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *buf;
+ intel_wakeref_t wakeref;
+
+ if (!HAS_DSB(i915) || dsb->cmd_buf)
+ return;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Gem object creation failed\n");
+ goto out;
+ }
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("Vma creation failed\n");
+ i915_gem_object_put(obj);
+ goto out;
+ }
+
+ buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(buf)) {
+ DRM_ERROR("Command buffer creation failed\n");
+ goto out;
+ }
+
+ dsb->id = DSB1;
+ dsb->vma = vma;
+ dsb->cmd_buf = buf;
+
+out:
+ /*
+* On error dsb->cmd_buf will continue to be NULL, making the writes
+* pass-through. Leave the dangling ref to be removed later by the
+* corresponding intel_dsb_put(): the important error message will
+* already be logged above.
+*/
+
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+}
+
+/**
+ * intel_dsb_cleanup() - To cleanup DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function cleanup the DSB context by unpinning and releasing
+ * the VMA object associated with it.
+ */
+
+void intel_dsb_cleanup(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = &
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Flush execution tasklets before checking request status
Quoting Mika Kuoppala (2020-02-05 14:42:16) > Chris Wilson writes: > > > Rather than flushing the submission tasklets just before we sleep, flush > > before we check the request status. Ideally this gives us a moment to > > process the tasklets after sleeping just before we timeout. > > Makes sense to check the possibly most recent state. > > Reviewed-by: Mika Kuoppala I suppose I should mention a small counter argument is that by kicking ksoftirqd before checking completed, we may add a small amount of latency to the ready client. A compromise is to kick before timeout? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: add basic selftests for rc6 (rev5)
== Series Details == Series: drm/i915/selftests: add basic selftests for rc6 (rev5) URL : https://patchwork.freedesktop.org/series/69825/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7869 -> Patchwork_16431 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16431 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16431, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16431: ### IGT changes ### Possible regressions * igt@i915_selftest@live_gt_pm: - fi-cfl-8700k: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-cfl-8700k/igt@i915_selftest@live_gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-cfl-8700k/igt@i915_selftest@live_gt_pm.html - fi-kbl-r: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-r/igt@i915_selftest@live_gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-kbl-r/igt@i915_selftest@live_gt_pm.html - fi-byt-j1900: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-j1900/igt@i915_selftest@live_gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-byt-j1900/igt@i915_selftest@live_gt_pm.html - fi-cfl-8109u: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-cfl-8109u/igt@i915_selftest@live_gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-cfl-8109u/igt@i915_selftest@live_gt_pm.html - fi-bsw-nick:[PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bsw-nick/igt@i915_selftest@live_gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-bsw-nick/igt@i915_selftest@live_gt_pm.html - fi-kbl-7500u: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@i915_selftest@live_gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-kbl-7500u/igt@i915_selftest@live_gt_pm.html - fi-kbl-x1275: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-x1275/igt@i915_selftest@live_gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-kbl-x1275/igt@i915_selftest@live_gt_pm.html - fi-kbl-guc: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-guc/igt@i915_selftest@live_gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-kbl-guc/igt@i915_selftest@live_gt_pm.html - fi-skl-guc: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-guc/igt@i915_selftest@live_gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-skl-guc/igt@i915_selftest@live_gt_pm.html - fi-icl-u3: NOTRUN -> [DMESG-FAIL][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-icl-u3/igt@i915_selftest@live_gt_pm.html - fi-snb-2600:[PASS][20] -> [DMESG-FAIL][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-snb-2600/igt@i915_selftest@live_gt_pm.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-snb-2600/igt@i915_selftest@live_gt_pm.html - fi-glk-dsi: [PASS][22] -> [DMESG-FAIL][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-glk-dsi/igt@i915_selftest@live_gt_pm.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-glk-dsi/igt@i915_selftest@live_gt_pm.html - fi-bsw-kefka: [PASS][24] -> [DMESG-FAIL][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bsw-kefka/igt@i915_selftest@live_gt_pm.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-bsw-kefka/igt@i915_selftest@live_gt_pm.html - fi-byt-n2820: NOTRUN -> [DMESG-FAIL][26] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-byt-n2820/igt@i915_selftest@live_gt_pm.html - fi-skl-6700k2: [PASS][27] -> [DMESG-FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-6700k2/igt@i915_selftest@live_gt_pm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16431/fi-skl-6700k2/igt@i915_selftest@live_gt_pm.html - fi-whl-u: [PASS][29] -> [DMESG-FAIL][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_78
[Intel-gfx] [PATCH v4 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
Dump out the DP VSC SDP in the normal crtc state dump
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Use drm core's DP VSC SDP logging function
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 440e2c1c855c..e3694e499b28 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13006,6 +13006,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
}
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
static const char * const output_type_str[] = {
@@ -13164,6 +13174,9 @@ static void intel_dump_pipe_config(const struct
intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC))
+ intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.24.1
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[Intel-gfx] [PATCH v4 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().
While computing, we'll also fill out the inforames.enable bitmask
appropriately.
v2: Wrap a long line.
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2bdc43c80e03..583a4a0d9114 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,29 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
&crtc_state->infoframes.vsc);
}
+static void
+intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ int ret;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct hdmi_drm_infoframe *drm_infoframe =
&crtc_state->infoframes.drm.drm;
+
+ if (!conn_state->hdr_output_metadata)
+ return;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
+
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in
infoframe\n");
+ return;
+ }
+
+ crtc_state->infoframes.enable |=
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2569,6 +2592,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+ intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config,
conn_state);
return 0;
}
--
2.24.1
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[Intel-gfx] [PATCH v4 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump. HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata Infoframe SDP use the same member variable in infoframes of crtc state. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 66dbaab5867e..440e2c1c855c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13161,6 +13161,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(&pipe_config->hw.mode); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure
It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
And it adds a new drm data structure for DP VSC SDP.
enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
v3: Add a new drm data structure for DP VSC SDP
Signed-off-by: Gwan-gyeong Mun
---
include/drm/drm_dp_helper.h | 57 +
1 file changed, 57 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..c098727681fa 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1209,6 +1209,63 @@ struct dp_sdp {
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
+/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18] */
+enum dp_colorspace {
+ DP_COLORSPACE_RGB = 0,
+ DP_COLORSPACE_YUV444 = 0x1,
+ DP_COLORSPACE_YUV422 = 0x2,
+ DP_COLORSPACE_YUV420 = 0x3,
+ DP_COLORSPACE_Y_ONLY = 0x4,
+ DP_COLORSPACE_RAW = 0x5,
+ DP_COLORSPACE_RESERVED = 0x6,
+};
+
+/**
+ * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18]
+ * and a name of enum member followes DRM_MODE_COLORIMETRY definition.
+ */
+enum dp_colorimetry {
+ DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
+ DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
+ DP_COLORIMETRY_BT709_YCC = 0x1,
+ DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
+ DP_COLORIMETRY_XVYCC_601 = 0x2,
+ DP_COLORIMETRY_OPRGB = 0x3,
+ DP_COLORIMETRY_XVYCC_709 = 0x3,
+ DP_COLORIMETRY_DCI_P3_RGB = 0x4,
+ DP_COLORIMETRY_SYCC_601 = 0x4,
+ DP_COLORIMETRY_RGB_CUSTOM = 0x5,
+ DP_COLORIMETRY_OPYCC_601 = 0x5,
+ DP_COLORIMETRY_BT2020_RGB = 0x6,
+ DP_COLORIMETRY_BT2020_CYCC = 0x6,
+ DP_COLORIMETRY_BT2020_YCC = 0x7,
+};
+
+enum dp_dynamic_range {
+ DP_DYNAMIC_RANGE_VESA = 0,
+ DP_DYNAMIC_RANGE_CTA = 1,
+};
+
+enum dp_content_type {
+ DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
+ DP_CONTENT_TYPE_GRAPHICS = 0x01,
+ DP_CONTENT_TYPE_PHOTO = 0x02,
+ DP_CONTENT_TYPE_VIDEO = 0x03,
+ DP_CONTENT_TYPE_GAME = 0x04,
+};
+
+/* DRM DP VSC SDP as per DP 1.4 spec */
+struct drm_dp_vsc_sdp {
+ unsigned char sdp_type; /* Secondary-data Packet Type */
+ unsigned char revision; /* Revision Number */
+ unsigned char length; /* Number of Valid Data Bytes */
+ enum dp_colorspace colorspace;
+ enum dp_colorimetry colorimetry;
+ int bpc; /* bit per color */
+ enum dp_dynamic_range dynamic_range;
+ enum dp_content_type content_type;
+};
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
--
2.24.1
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[Intel-gfx] [PATCH v4 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
Added state readout for DP HDR Metadata Infoframe SDP. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 857014fe5880..55eacc4d75bb 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4298,6 +4298,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, pipe_config->fec_enable); } + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); + break; case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ -4309,6 +4312,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); intel_dp_get_m_n(intel_crtc, pipe_config); + + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); break; default: break; @@ -4359,6 +4365,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_infoframe(encoder, pipe_config, HDMI_INFOFRAME_TYPE_DRM, &pipe_config->infoframes.drm); + + intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); } static enum intel_output_type -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 13/17] drm/i915: Add state readout for DP VSC SDP
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 43
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 55eacc4d75bb..7f29b08ea202 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4367,6 +4367,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
&pipe_config->infoframes.drm);
intel_read_dp_sdp(encoder, pipe_config,
HDMI_PACKET_TYPE_GAMUT_METADATA);
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e3694e499b28..c11898cc1b50 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13634,6 +13634,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
return memcmp(a, b, sizeof(*a)) == 0;
}
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+const struct drm_dp_vsc_sdp *b)
+{
+ return memcmp(a, b, sizeof(*a)) == 0;
+}
+
static void
pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
bool fastset, const char *name,
@@ -13659,6 +13666,31 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
}
}
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+ bool fastset, const char *name,
+ const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "fastset mismatch in %s dp sdp\n", name);
+ drm_dbg_kms(&dev_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+ drm_dbg_kms(&dev_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+ } else {
+ drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
+ drm_err(&dev_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+ drm_err(&dev_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+ }
+}
+
static void __printf(4, 5)
pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
const char *name, const char *format, ...)
@@ -13860,6 +13892,16 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
if (current_config->name1 != pipe_config->name1) { \
pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -14035,6 +14077,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_INFOFRAME(spd);
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
--
2.24.1
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[Intel-gfx] [PATCH v4 14/17] drm/i915: Program DP SDPs on pipe updates
Call intel_dp_set_infoframes() function on pipe updates to make sure that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 7f29b08ea202..99d3f011ed96 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4070,6 +4070,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state); + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); intel_edp_drrs_enable(intel_dp, crtc_state); intel_panel_update_backlight(encoder, crtc_state, conn_state); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 05/17] video/hdmi: Add Unpack only function for DRM infoframe
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.
It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.
Signed-off-by: Gwan-gyeong Mun
---
drivers/video/hdmi.c | 58 +++-
include/linux/hdmi.h | 2 ++
2 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 9c82e2a0a411..9818836d82b7 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
hdmi_vendor_any_infoframe *frame,
}
/**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI DRM
infoframe
* @frame: HDMI DRM infoframe
* @buffer: source buffer
* @size: size of buffer
*
- * Unpacks the information contained in binary @buffer into a structured
+ * Unpacks the information data block contained in binary @buffer into a
structured
* @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
*
* Returns 0 on success or a negative error code on failure.
*/
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
-const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
{
const u8 *ptr = buffer;
const u8 *temp;
@@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
int ret;
int i;
- if (size < HDMI_INFOFRAME_SIZE(DRM))
- return -EINVAL;
-
- if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
- ptr[1] != 1 ||
- ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
- return -EINVAL;
-
- if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ if (size < HDMI_DRM_INFOFRAME_SIZE)
return -EINVAL;
ret = hdmi_drm_infoframe_init(frame);
if (ret)
return ret;
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
frame->eotf = ptr[0] & 0x7;
frame->metadata_type = ptr[1] & 0x7;
@@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
return 0;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
HDMI_INFOFRAME_HEADER_SIZE,
+size - HDMI_INFOFRAME_HEADER_SIZE);
+ return ret;
+}
/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9918a6c910c5..afb43efc03e0 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
void *buffer, size_t size);
int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size);
enum hdmi_spd_sdi {
HDMI_S
[Intel-gfx] [PATCH v4 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A nameing rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 173
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 176 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f941bc261f6a..c30272e80dc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4928,6 +4928,179 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(vsc, 0, size);
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+ return -EINVAL;
+ vsc->sdp_type = sdp->sdp_header.HB1;
+
+ if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ } else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
+ vsc->colorimetry = sdp->db[16] & 0xf;
+ vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+ switch (sdp->db[17] & 0x7) {
+ case 0x1:
+ vsc->bpc = 8;
+ break;
+ case 0x2:
+ vsc->bpc = 10;
+ break;
+ case 0x3:
+ vsc->bpc = 12;
+ break;
+ case 0x4:
+ vsc->bpc = 16;
+ break;
+ default:
+ MISSING_CASE(sdp->db[17] & 0x7);
+ return -EINVAL;
+ }
+
+ vsc->content_type = sdp->db[18] & 0x7;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
*drm_infoframe,
+ const void *buffer, size_t size)
+{
+ int ret;
+
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+ return -EINVAL;
+
+ /*
+* Least Significant Eight Bits of (Data Byte Count – 1)
+* 1Dh (i.e., Data Byte Count = 30 bytes).
+*/
+ if (sdp->sdp_header.HB2 != 0x1D)
+ return -EINVAL;
+
+ /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+ if ((sdp->sdp_header.HB3 & 0x3) != 0)
+ return -EINVAL;
+
+ /* INFOFRAME SDP Version Number */
+ if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+ return -EINVAL;
+
+ /* CTA Header Byte 2 (INFOFRAME Version Number) */
+ if (sdp->db[0] != 1)
+ return -EINVAL;
+
+ /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+ if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
+HDMI_DRM_INFOFRAME_SIZE);
+
+ return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+ s
[Intel-gfx] [PATCH v4 07/17] drm: Add logging function for DP VSC SDP
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
v2: Minor style fix
v3: Move logging functions to drm core [Jani N]
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/drm_dp_helper.c | 174
include/drm/drm_dp_helper.h | 3 +
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..5e3aef8c32e0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+static const char *dp_colorspace_get_name(enum dp_colorspace colorspace)
+{
+ if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+ return "Invalid";
+
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "RGB";
+ case DP_COLORSPACE_YUV444:
+ return "YUV444";
+ case DP_COLORSPACE_YUV422:
+ return "YUV422";
+ case DP_COLORSPACE_YUV420:
+ return "YUV420";
+ case DP_COLORSPACE_Y_ONLY:
+ return "Y_ONLY";
+ case DP_COLORSPACE_RAW:
+ return "RAW";
+ default:
+ return "Reserved";
+ }
+}
+
+static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
+ enum dp_colorimetry colorimetry)
+{
+ if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+ return "Invalid";
+
+ switch (colorimetry) {
+ case DP_COLORIMETRY_DEFAULT:
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "sRGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.601";
+ case DP_COLORSPACE_Y_ONLY:
+ return "DICOM PS3.14";
+ case DP_COLORSPACE_RAW:
+ return "Custom Color Profile";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Wide Fixed";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Wide Float";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "xvYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "OpRGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "xvYCC 709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "DCI-P3";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "sYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Custom Profile";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "OpYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "BT.2020 RGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.2020 CYCC";
+ default:
+
[Intel-gfx] [PATCH v4 02/17] drm/i915/dp: Add compute routine for DP VSC SDP
In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.
And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.
The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Signed-off-by: Gwan-gyeong Mun
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 92 +++
2 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7ae0bc8b80d1..7997c307026d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -997,6 +997,7 @@ struct intel_crtc_state {
union hdmi_infoframe spd;
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
+ struct drm_dp_vsc_sdp vsc;
} infoframes;
/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..2bdc43c80e03 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct
drm_i915_private *dev_priv,
return true;
}
+static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
*crtc_state,
+const struct drm_connector_state
*conn_state,
+struct drm_dp_vsc_sdp *vsc)
+{
+ /*
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication.
+*/
+ vsc->revision = 0x5;
+ vsc->length = 0x13;
+
+ /* DP 1.4a spec, Table 2-120 */
+ switch (crtc_state->output_format) {
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ vsc->colorspace = DP_COLORSPACE_YUV444;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ vsc->colorspace = DP_COLORSPACE_YUV420;
+ break;
+ case INTEL_OUTPUT_FORMAT_RGB:
+ default:
+ vsc->colorspace = DP_COLORSPACE_RGB;
+ }
+
+ switch (conn_state->colorspace) {
+ case DRM_MODE_COLORIMETRY_BT709_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_709:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
+ break;
+ case DRM_MODE_COLORIMETRY_SYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_OPYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_RGB:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+ vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
+ break;
+ default:
+ /*
+* RGB->YCBCR color conversion uses the BT.709
+* color space.
+*/
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ else
+ vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
+ break;
+ }
+
+ vsc->bpc = crtc_state->pipe_bpp / 3;
+ /* all YCbCr are always limited range */
+ vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
+ vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
+}
+
+static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+struct intel_crtc_state *crtc_state,
+const struct drm_connector_state
*conn_state)
+{
+ struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
+
+ /* When PSR is enabled, VSC SDP is handled by PSR routine */
+ if (intel_psr_enabled(intel_dp))
+ return;
+
+ if (!intel_dp_needs_vsc_sdp(crtc_sta
[Intel-gfx] [PATCH v4 00/17] In order to readout DP SDPs, refactors the handling of DP SDPs
In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes. It adds new compute routines for DP HDR Metadata Infoframe SDP and DP VSC SDP. And new writing routines of DP SDPs (Secondary Data Packet) that uses computed configs. New reading routines of DP SDPs are added for readout. It adds a logging function for DP VSC SDP. When receiving video it is very useful to be able to log DP VSC SDP. This greatly simplifies debugging. In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a new psr vsc sdp compute routine. v2: Minor style fix v3: - Add a new drm data structure for DP VSC SDP - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp - Move logging functions to drm core [Jani N] And use drm core's DP VSC SDP logging function - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be used for HDMI), when intel_dp_set_infoframes() function will be called. v4: - Use struct drm_device logging macros - Rebased Gwan-gyeong Mun (17): drm: add DP 1.4 VSC SDP Payload related enums and a structure drm/i915/dp: Add compute routine for DP VSC SDP drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet) video/hdmi: Add Unpack only function for DRM infoframe drm/i915/dp: Read out DP SDPs (Secondary Data Packet) drm: Add logging function for DP VSC SDP drm/i915: Include HDMI DRM infoframe in the crtc state dump drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump drm/i915: Include DP VSC SDP in the crtc state dump drm/i915: Program DP SDPs with computed configs drm/i915: Add state readout for DP HDR Metadata Infoframe SDP drm/i915: Add state readout for DP VSC SDP drm/i915: Program DP SDPs on pipe updates drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp() drm/i915/dp: Add compute routine for DP PSR VSC SDP drm/i915/psr: Use new DP VSC SDP compute routine on PSR drivers/gpu/drm/drm_dp_helper.c | 174 + drivers/gpu/drm/i915/display/intel_ddi.c | 19 +- drivers/gpu/drm/i915/display/intel_display.c | 62 ++ .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 614 +- drivers/gpu/drm/i915/display/intel_dp.h | 18 +- drivers/gpu/drm/i915/display/intel_psr.c | 54 +- drivers/gpu/drm/i915/display/intel_psr.h | 6 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/video/hdmi.c | 58 +- include/drm/drm_dp_helper.h | 60 ++ include/linux/hdmi.h | 2 + 12 files changed, 851 insertions(+), 218 deletions(-) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 11/17] drm/i915: Program DP SDPs with computed configs
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
Before applying it, routines of program SDP always calculated configs when
they called. And it removes unused functions.
v3: Rebased
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 226 ---
drivers/gpu/drm/i915/display/intel_dp.h | 6 -
3 files changed, 1 insertion(+), 234 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1ab638e17046..857014fe5880 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3902,8 +3902,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
- intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c30272e80dc7..acf943b9e1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5101,232 +5101,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp vsc_sdp = {};
-
- /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
- vsc_sdp.sdp_header.HB0 = 0;
- vsc_sdp.sdp_header.HB1 = 0x7;
-
- /*
-* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-* Colorimetry Format indication.
-*/
- vsc_sdp.sdp_header.HB2 = 0x5;
-
- /*
-* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
-* Colorimetry Format indication (HB2 = 05h).
-*/
- vsc_sdp.sdp_header.HB3 = 0x13;
-
- /* DP 1.4a spec, Table 2-120 */
- switch (crtc_state->output_format) {
- case INTEL_OUTPUT_FORMAT_YCBCR444:
- vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
- break;
- case INTEL_OUTPUT_FORMAT_YCBCR420:
- vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
- break;
- case INTEL_OUTPUT_FORMAT_RGB:
- default:
- /* RGB: DB16[7:4] = 0h */
- break;
- }
-
- switch (conn_state->colorspace) {
- case DRM_MODE_COLORIMETRY_BT709_YCC:
- vsc_sdp.db[16] |= 0x1;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_601:
- vsc_sdp.db[16] |= 0x2;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_709:
- vsc_sdp.db[16] |= 0x3;
- break;
- case DRM_MODE_COLORIMETRY_SYCC_601:
- vsc_sdp.db[16] |= 0x4;
- break;
- case DRM_MODE_COLORIMETRY_OPYCC_601:
- vsc_sdp.db[16] |= 0x5;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_CYCC:
- case DRM_MODE_COLORIMETRY_BT2020_RGB:
- vsc_sdp.db[16] |= 0x6;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_YCC:
- vsc_sdp.db[16] |= 0x7;
- break;
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
- vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
- break;
- default:
- /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
- break;
- }
-
- /*
-* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
-* the following Component Bit Depth values are defined:
-* 001b = 8bpc.
-* 010b = 10bpc.
-* 011b = 12bpc.
-* 100b = 16bpc.
-*/
- switch (crtc_state->pipe_bpp) {
- case 24: /* 8bpc */
- vsc_sdp.db[17] = 0x1;
- break;
- case 30: /* 10bpc */
- vsc_sdp.db[17] = 0x2;
- break;
- case 36: /* 12bpc */
- vsc_sdp.db[17] = 0x3;
- break;
- case 48: /* 16bpc */
- vsc_
[Intel-gfx] [PATCH v4 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal crtc state dump. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 368e481d45ee..66dbaab5867e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13158,6 +13158,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(&pipe_config->hw.mode); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to pack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_pack() function.
And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A machanism and a naming rule of intel_dp_set_infoframes() function
references intel_encoder->set_infoframes() of intel_hdmi.c .
VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
Because PSR routine has its own routine of writing a VSC SDP, when the PSR
is enabled, intel_dp_set_infoframes() does not write a VSC SDP.
v3:
- Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
used for HDMI), when intel_dp_set_infoframes() function will be called.
- Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 195
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 198 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 583a4a0d9114..f941bc261f6a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4733,6 +4733,201 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
*crtc_state,
return false;
}
+static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /*
+* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+* VSC SDP Header Bytes
+*/
+ sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+ sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+ sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+ sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+ /* VSC SDP Payload for DB16 through DB18 */
+ /* Pixel Encoding and Colorimetry Formats */
+ sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
+ sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+ switch (vsc->bpc) {
+ case 8:
+ sdp->db[17] = 0x1; /* DB17[3:0] */
+ break;
+ case 10:
+ sdp->db[17] = 0x2;
+ break;
+ case 12:
+ sdp->db[17] = 0x3;
+ break;
+ case 16:
+ sdp->db[17] = 0x4;
+ break;
+ default:
+ MISSING_CASE(vsc->bpc);
+ break;
+ }
+ /* Dynamic Range and Component Bit Depth */
+ if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+ sdp->db[17] |= 0x80; /* DB17[7] */
+
+ /* Content Type */
+ sdp->db[18] = vsc->content_type & 0x7;
+
+ return length;
+}
+
+static ssize_t
+intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
*drm_infoframe,
+struct dp_sdp *sdp,
+size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+ const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
HDMI_DRM_INFOFRAME_SIZE;
+ unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+ ssize_t len;
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
+ if (len < 0) {
+ DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
infoframe\n");
+ return -ENOSPC;
+ }
+
+ if (len != infoframe_size) {
+ DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+ return -ENOSPC;
+ }
+
+ /*
+* Set up the infoframe sdp packet for HDR static metadata.
+* Prepare VSC Header for SU as per DP 1.4a spec,
+* Table 2-100 and Table 2-101
+*/
+
+ /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+ sdp->sdp_header.HB0 = 0;
+ /*
+* Packet Type 80h + Non-audio INFOFRAME Type value
+* HDMI_INFOFRAME_TYPE_DRM: 0x87
+* - 80h + Non-audio INFOFRAME Type value
+* - InfoFrame Type: 0x07
+*[CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
+*/
+ sdp->sdp_header.HB1 = drm_infoframe->type;
+ /*
+* Least Significant Eight Bits
[Intel-gfx] [PATCH v4 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Rebased
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 54 +++-
drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 22 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e21dfc0d926b..fd0e88566074 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3903,7 +3903,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(crtc_state, conn_state);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_enable(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
@@ -4071,7 +4071,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
*encoder,
intel_ddi_set_dp_msa(crtc_state, conn_state);
- intel_psr_update(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index db3d1561e9bf..953c0286307d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -335,39 +335,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct dp_sdp psr_vsc;
-
- if (dev_priv->psr.psr2_enabled) {
- /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support) {
- psr_vsc.sdp_header.HB2 = 0x5;
- psr_vsc.sdp_header.HB3 = 0x13;
- } else {
- psr_vsc.sdp_header.HB2 = 0x4;
- psr_vsc.sdp_header.HB3 = 0xe;
- }
- } else {
- /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x2;
- psr_vsc.sdp_header.HB3 = 0x8;
- }
-
- intel_dig_port->write_infoframe(&intel_dig_port->base,
- crtc_state,
- DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
-}
-
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -859,9 +826,12 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
u32 val;
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
@@ -900,7 +870,9 @@ static void intel_psr_enable_locked(struct drm_i915_private
*dev_priv,
drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
- intel_psr_setup_vsc(intel_dp, crtc_state);
+ intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+&dev_priv->psr.vsc);
+ intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
intel_psr_enable_sink(intel_dp);
[Intel-gfx] [PATCH v4 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make sure not to send VSC SDP and HDR Metadata Infoframe SDP. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 99d3f011ed96..e21dfc0d926b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3715,6 +3715,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, INTEL_OUTPUT_DP_MST); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); + /* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 +
drivers/gpu/drm/i915/display/intel_dp.h | 8
2 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index acf943b9e1ec..b544f08202dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
&crtc_state->infoframes.vsc);
}
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ vsc->sdp_type = DP_SDP_VSC;
+
+ if (dev_priv->psr.psr2_enabled) {
+ if (dev_priv->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [PSR2, +Colorimetry] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+vsc);
+ } else {
+ /*
+* [PSR2, -Colorimetry]
+* Prepare VSC Header for SU as per eDP 1.4 spec, Table
6-11
+* 3D stereo + PSR/PSR2 + Y-coordinate.
+*/
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
+ }
+ } else {
+ /*
+* [PSR1]
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+* higher).
+*/
+ vsc->revision = 0x2;
+ vsc->length = 0x8;
+ }
+}
+
static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
@@ -4892,6 +4928,24 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
}
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct dp_sdp sdp = {};
+ ssize_t len;
+
+ len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
+
+ if (drm_WARN_ON(&dev_priv->drm, len < 0))
+ return;
+
+ intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+ &sdp, len);
+}
+
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 6562bb8edeba..5074e52722c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -18,6 +18,7 @@ struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
@@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_persistence: Check that we cannot hide hangs on old engines
On 05/02/2020 13:48, Chris Wilson wrote:
As the kernel loses track of the context's old engines, if we request
that the context is non-persistent then any request on the untracked
engines must be cancelled.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_ctx_persistence.c | 60 +++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index c54797e9b..04a6c179e 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -761,6 +761,49 @@ static void smoketest(int i915)
gem_quiescent_gpu(i915);
}
+static void replace_engines_hostile(int i915,
+ const struct intel_execution_engine2 *e)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ .engines = {{ e->class, e->instance }}
+ };
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ .size = sizeof(engines),
+ };
+ igt_spin_t *spin[2];
+ int64_t timeout;
+
+ /*
+* Suppose the user tries to hide a hanging batch by replacing
+* the set of engines on the context so that it's not visible
+* at the time of closure? Then we must act when they replace
+* the engines!
+*/
+
+ gem_context_set_persistence(i915, param.ctx_id, false);
+
+ gem_context_set_param(i915, ¶m);
+ spin[0] = igt_spin_new(i915, param.ctx_id);
+
+ gem_context_set_param(i915, ¶m);
+ spin[1] = igt_spin_new(i915, param.ctx_id);
+
+ gem_context_destroy(i915, param.ctx_id);
At this point context_close() -> kill_context() but spin[0]
intel_context no longer in ctx->engines so hangs. spin[1] is terminated.
+
+ timeout = reset_timeout_ms * NSEC_PER_MSEC;
+ igt_assert_eq(gem_wait(i915, spin[1]->handle, &timeout), 0);
+
+ timeout = reset_timeout_ms * NSEC_PER_MSEC;
+ igt_assert_eq(gem_wait(i915, spin[0]->handle, &timeout), 0);
+
+ igt_spin_free(i915, spin[1]);
+ igt_spin_free(i915, spin[0]);
+ gem_quiescent_gpu(i915);
+}
+
int i915;
static void exit_handler(int sig)
@@ -793,10 +836,10 @@ igt_main
igt_assert(igt_sysfs_set_parameter
(i915, "reset", "%d", -1 /* any [default] reset */));
- igt_require(has_persistence(i915));
enable_hangcheck(i915);
igt_install_exit_handler(exit_handler);
+ igt_require(has_persistence(i915));
igt_allow_hang(i915, 0, 0);
}
@@ -861,6 +904,21 @@ igt_main
smoketest(i915);
}
+ /* Check interactions with set-engines */
+ igt_subtest_group {
+ const struct intel_execution_engine2 *e;
+
+ igt_fixture
+ gem_require_contexts(i915);
+
+ igt_subtest_with_dynamic("replace-hostile") {
+ __for_each_physical_engine(i915, e) {
+ igt_dynamic_f("%s", e->name)
+ replace_engines_hostile(i915, e);
+ }
+ }
+ }
+
igt_fixture {
close(i915);
}
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data
> Packet)
Drop things in (), not needed.
> It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
> In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
> It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table
> 2-117: VSC
> SDP Payload for DB16 through DB18]
>
> In order to pack DP HDR Metadata Infoframe SDP, it adds
> intel_dp_hdr_metadata_infoframe_sdp_pack() function.
> And it follows DP 1.4a spec.
> ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME
> SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42
> Dynamic Range and Mastering InfoFrame].
>
> A machanism and a naming rule of intel_dp_set_infoframes() function references
Typo in mechanism.
> intel_encoder->set_infoframes() of intel_hdmi.c .
> VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
> Because PSR routine has its own routine of writing a VSC SDP, when the PSR is
> enabled, intel_dp_set_infoframes() does not write a VSC SDP.
>
> v3:
> - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
> used for HDMI), when intel_dp_set_infoframes() function will be called.
> - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 194
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +
> 2 files changed, 197 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b265b5c599f2..dd7e5588001e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
> *crtc_state,
> return false;
> }
>
> +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
> + struct dp_sdp *sdp, size_t size) {
> + size_t length = sizeof(struct dp_sdp);
> +
> + if (size < length)
> + return -ENOSPC;
> +
> + memset(sdp, 0, size);
> +
> + /*
> + * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> + * VSC SDP Header Bytes
> + */
> + sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
> + sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
> + sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
> + sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> +
> + /* VSC SDP Payload for DB16 through DB18 */
> + /* Pixel Encoding and Colorimetry Formats */
> + sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
> + sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
> +
> + switch (vsc->bpc) {
> + case 8:
> + sdp->db[17] = 0x1; /* DB17[3:0] */
> + break;
> + case 10:
> + sdp->db[17] = 0x2;
> + break;
> + case 12:
> + sdp->db[17] = 0x3;
> + break;
> + case 16:
> + sdp->db[17] = 0x4;
> + break;
> + default:
> + MISSING_CASE(vsc->bpc);
6bpc is not handled here, add that as well.
> + break;
> + }
> + /* Dynamic Range and Component Bit Depth */
> + if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
> + sdp->db[17] |= 0x80; /* DB17[7] */
> +
> + /* Content Type */
> + sdp->db[18] = vsc->content_type & 0x7;
> +
> + return length;
> +}
> +
> +static ssize_t
> +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
> *drm_infoframe,
> + struct dp_sdp *sdp,
> + size_t size)
> +{
> + size_t length = sizeof(struct dp_sdp);
> + const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE;
> + unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE];
> + ssize_t len;
> +
> + if (size < length)
> + return -ENOSPC;
> +
> + memset(sdp, 0, size);
> +
> + len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
> + if (len < 0) {
> + DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> infoframe\n");
> + return -ENOSPC;
> + }
> +
> + if (len != infoframe_size) {
> + DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> + return -ENOSPC;
> + }
> +
> + /*
> + * Set up the infoframe sdp packet for HDR static metadata.
> + * Prepare VSC Header for SU as per DP 1.4a spec,
> + * Table 2-100 and Table 2-101
> +
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Defer application of initial chv_phy_control
== Series Details == Series: series starting with [1/3] drm/i915/display: Defer application of initial chv_phy_control URL : https://patchwork.freedesktop.org/series/72905/ State : success == Summary == CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16389_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16389_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +11 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-iclb6/igt@gem_b...@busy-vcs1.html * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +9 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +20 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-iclb7/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_partial_pwrite_pread@write: - shard-hsw: [PASS][9] -> [FAIL][10] ([i915#694]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw5/igt@gem_partial_pwrite_pr...@write.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-hsw2/igt@gem_partial_pwrite_pr...@write.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl3/igt@gem_soft...@noreloc-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-apl6/igt@gem_soft...@noreloc-s3.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][13] -> [TIMEOUT][14] ([i915#716]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl4/igt@gen9_exec_pa...@allowed-single.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-skl3/igt@gen9_exec_pa...@allowed-single.html * igt@kms_color@pipe-b-ctm-0-5: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#109]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_co...@pipe-b-ctm-0-5.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-skl5/igt@kms_co...@pipe-b-ctm-0-5.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#79]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-glk3/igt@kms_f...@2x-flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-glk8/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#34]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl6/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-skl10/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-tglb: [PASS][23] -> [SKIP][24] ([i915#668]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb8/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-tglb3/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-snb: [PASS][25] -> [SKIP][26] ([fdo#109271]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/sha
Re: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe
> -Original Message-
> From: Intel-gfx On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function
> for DRM
> infoframe
>
> It adds an unpack only function for DRM infoframe for dynamic range and
> mastering
> infoframe readout.
> It unpacks the information data block contained in the binary buffer into a
> structured
> frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
>
> In contrast to hdmi_drm_infoframe_unpack() function, it does not verify a
> checksum.
>
> It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
> DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
> (DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
> But DP SDP header and payload structure are different from HDMI DRM Infoframe.
> Therefore unpacking DRM infoframe for DP requires skipping of a verifying
> checksum.
Looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/video/hdmi.c | 58 +++-
> include/linux/hdmi.h | 2 ++
> 2 files changed, 43 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index
> 9c82e2a0a411..9818836d82b7 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
> hdmi_vendor_any_infoframe *frame, }
>
> /**
> - * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
> + * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI
> + DRM infoframe
> * @frame: HDMI DRM infoframe
> * @buffer: source buffer
> * @size: size of buffer
> *
> - * Unpacks the information contained in binary @buffer into a structured
> + * Unpacks the information data block contained in binary @buffer into
> + a structured
> * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> - * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
> - * specification.
> *
> * Returns 0 on success or a negative error code on failure.
> */
> -static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> - const void *buffer, size_t size)
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> +const void *buffer, size_t size)
> {
> const u8 *ptr = buffer;
> const u8 *temp;
> @@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> int ret;
> int i;
>
> - if (size < HDMI_INFOFRAME_SIZE(DRM))
> - return -EINVAL;
> -
> - if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> - ptr[1] != 1 ||
> - ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> - return -EINVAL;
> -
> - if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> + if (size < HDMI_DRM_INFOFRAME_SIZE)
> return -EINVAL;
>
> ret = hdmi_drm_infoframe_init(frame);
> if (ret)
> return ret;
>
> - ptr += HDMI_INFOFRAME_HEADER_SIZE;
> -
> frame->eotf = ptr[0] & 0x7;
> frame->metadata_type = ptr[1] & 0x7;
>
> @@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
>
> return 0;
> }
> +EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
> +
> +/**
> + * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> +infoframe
> + * @frame: HDMI DRM infoframe
> + * @buffer: source buffer
> + * @size: size of buffer
> + *
> + * Unpacks the information contained in binary @buffer into a
> +structured
> + * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> + * Also verifies the checksum as required by section 5.3.5 of the HDMI
> +1.4
> + * specification.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> + const void *buffer, size_t size) {
> + const u8 *ptr = buffer;
> + int ret;
> +
> + if (size < HDMI_INFOFRAME_SIZE(DRM))
> + return -EINVAL;
> +
> + if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> + ptr[1] != 1 ||
> + ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> + return -EINVAL;
> +
> + if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> + return -EINVAL;
> +
> + ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
> HDMI_INFOFRAME_HEADER_SIZE,
> + size - HDMI_INFOFRAME_HEADER_SIZE);
> + return ret;
> +}
>
> /**
> * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe diff
> --git
> a/include/linux/hdmi.h b/include/linux/hdmi.h index 9918a6c910c5..a
Re: [Intel-gfx] [PATCH v2] drm/i915/gem: Don't leak non-persistent requests on changing engines
On 05/02/2020 12:13, Chris Wilson wrote:
If we have a set of active engines marked as being non-persistent, we
lose track of those if the user replaces those engines with
I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
non-persistent requests are terminated if they are no longer being
tracked by the user's context (in order to prevent a lost request
causing an untracked and so unstoppable GPU hang), we need to apply the
same context cancellation upon changing engines.
Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
Testcase: XXX
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 52a749691a8d..20f1d3e0221f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1624,11 +1624,18 @@ set_engines(struct i915_gem_context *ctx,
replace:
mutex_lock(&ctx->engines_mutex);
+
+ /* Flush stale requests off the old engines if required */
+ if (!i915_gem_context_is_persistent(ctx) ||
+ !i915_modparams.enable_hangcheck)
+ kill_context(ctx);
Is the negative effect of this is legit contexts can't keep submitting
and changing the map? Only if PREEMPT_TIMEOUT is disabled I think but
still. Might break legitimate userspace. Not that I offer solutions.. :(
Banning changing engines once context went non-persistent? That too can
break someone.
Regards,
Tvrtko
+
if (args->size)
i915_gem_context_set_user_engines(ctx);
else
i915_gem_context_clear_user_engines(ctx);
set.engines = rcu_replace_pointer(ctx->engines, set.engines, 1);
+
mutex_unlock(&ctx->engines_mutex);
call_rcu(&set.engines->rcu, free_engines_rcu);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data
> Packet)
Drop the content in bracket.
> It adds code to read the DP SDPs from the video DIP and unpack them into the
> crtc
> state.
>
> It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP In
> order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
> It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table
> 2-117: VSC
> SDP Payload for DB16 through DB18]
>
> In order to unpack DP HDR Metadata Infoframe SDP, it adds
> intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
> ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME
> SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42
> Dynamic Range and Mastering InfoFrame].
>
> A nameing rule and style of intel_read_dp_sdp() function references
Typo in naming.
> intel_read_infoframe() function of intel_hdmi.c
>
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 170
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +
> 2 files changed, 173 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index dd7e5588001e..d4ece0a824c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct intel_encoder
> *encoder,
> intel_write_dp_sdp(encoder, crtc_state,
> HDMI_PACKET_TYPE_GAMUT_METADATA); }
>
> +static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
> +const void *buffer, size_t size) {
> + const struct dp_sdp *sdp = buffer;
> +
> + if (size < sizeof(struct dp_sdp))
> + return -EINVAL;
> +
> + memset(vsc, 0, size);
> +
> + if (sdp->sdp_header.HB0 != 0)
> + return -EINVAL;
> +
> + if (sdp->sdp_header.HB1 != DP_SDP_VSC)
> + return -EINVAL;
> + vsc->sdp_type = sdp->sdp_header.HB1;
> +
> + if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
> + vsc->revision = sdp->sdp_header.HB2;
> + vsc->length = sdp->sdp_header.HB3;
> + } else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
> + vsc->revision = sdp->sdp_header.HB2;
> + vsc->length = sdp->sdp_header.HB3;
> + } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
> + vsc->revision = sdp->sdp_header.HB2;
> + vsc->length = sdp->sdp_header.HB3;
The above 2 lines can be done unconditionally, may be combine the if checks.
> + vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
> + vsc->colorimetry = sdp->db[16] & 0xf;
> + vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
> +
> + switch (sdp->db[17] & 0x7) {
> + case 0x1:
> + vsc->bpc = 8;
> + break;
> + case 0x2:
> + vsc->bpc = 10;
> + break;
> + case 0x3:
> + vsc->bpc = 12;
> + break;
> + case 0x4:
> + vsc->bpc = 16;
> + break;
> + default:
> + MISSING_CASE(sdp->db[17] & 0x7);
Handle 6bpc case as well.
> + return -EINVAL;
> + }
> +
> + vsc->content_type = sdp->db[18] & 0x7;
> + } else {
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int
> +intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
> *drm_infoframe,
> +const void *buffer, size_t size) {
> + int ret;
> +
> + const struct dp_sdp *sdp = buffer;
> +
> + if (size < sizeof(struct dp_sdp))
> + return -EINVAL;
> +
> + if (sdp->sdp_header.HB0 != 0)
> + return -EINVAL;
> +
> + if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
> + return -EINVAL;
> +
> + /*
> + * Least Significant Eight Bits of (Data Byte Count – 1)
> + * 1Dh (i.e., Data Byte Count = 30 bytes).
> + */
> + if (sdp->sdp_header.HB2 != 0x1D)
> + return -EINVAL;
> +
> + /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
> + if ((sdp->sdp_header.HB3 & 0x3) != 0)
> + return -EINVAL;
> +
> + /* INFOFRAME SDP Version Number */
> + if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
> + return -EINVAL;
> +
> + /* CTA H
Re: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP
> -Original Message-
> From: Intel-gfx On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP
>
> When receiving video it is very useful to be able to log DP VSC SDP.
> This greatly simplifies debugging.
>
> v2: Minor style fix
> v3: Move logging functions to drm core [Jani N]
Looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/drm_dp_helper.c | 174
> include/drm/drm_dp_helper.h | 3 +
> 2 files changed, 177 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 5a103e9b3c86..5e3aef8c32e0 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> return num_bpc;
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +static const char *dp_colorspace_get_name(enum dp_colorspace
> +colorspace) {
> + if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> + return "Invalid";
> +
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "RGB";
> + case DP_COLORSPACE_YUV444:
> + return "YUV444";
> + case DP_COLORSPACE_YUV422:
> + return "YUV422";
> + case DP_COLORSPACE_YUV420:
> + return "YUV420";
> + case DP_COLORSPACE_Y_ONLY:
> + return "Y_ONLY";
> + case DP_COLORSPACE_RAW:
> + return "RAW";
> + default:
> + return "Reserved";
> + }
> +}
> +
> +static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
> +enum dp_colorimetry colorimetry) {
> + if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> + return "Invalid";
> +
> + switch (colorimetry) {
> + case DP_COLORIMETRY_DEFAULT:
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "sRGB";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "BT.601";
> + case DP_COLORSPACE_Y_ONLY:
> + return "DICOM PS3.14";
> + case DP_COLORSPACE_RAW:
> + return "Custom Color Profile";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and
> DP_COLORIMETRY_BT709_YCC */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "Wide Fixed";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "BT.709";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and
> DP_COLORIMETRY_XVYCC_601 */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "Wide Float";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "xvYCC 601";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "OpRGB";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "xvYCC 709";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601
> */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "DCI-P3";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "sYCC 601";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_RGB_CUSTOM: /* and
> DP_COLORIMETRY_OPYCC_601 */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "Custom Profile";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "OpYCC 601";
> + default:
> + return "Reserved";
> + }
>
Re: [Intel-gfx] [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump
> -Original Message- > From: dri-devel On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc > state > dump > > Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal > crtc state dump. Looks good to me. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index c0e5002ce64c..239861bcedba 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct > intel_crtc_state *pipe_config, > if (pipe_config->infoframes.enable & > intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) > intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); > + if (pipe_config->infoframes.enable & > + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) > + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); > > drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); > drm_mode_debug_printmodeline(&pipe_config->hw.mode); > -- > 2.24.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: align dumb buffer stride to page_sz of the region
== Series Details == Series: drm/i915: align dumb buffer stride to page_sz of the region URL : https://patchwork.freedesktop.org/series/73021/ State : success == Summary == CI Bug Log - changes from CI_DRM_7869 -> Patchwork_16433 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/index.html Known issues Here are the changes found in Patchwork_16433 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#563]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][5] -> [DMESG-FAIL][6] ([i915#722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][9] ([i915#45]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_parallel@fds: - fi-icl-u3: [INCOMPLETE][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-u3/igt@gem_exec_paral...@fds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-icl-u3/igt@gem_exec_paral...@fds.html * igt@gem_exec_suspend@basic-s3: - fi-cml-s: [INCOMPLETE][13] ([i915#1078] / [i915#283]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-cml-s/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-cml-s/igt@gem_exec_susp...@basic-s3.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_module_load@reload: - fi-skl-6770hq: [DMESG-WARN][17] ([i915#92]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-6770hq/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-bsw-nick:[INCOMPLETE][19] ([i915#392]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bsw-nick/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-bsw-nick/igt@i915_selftest@live_blt.html - fi-ivb-3770:[DMESG-FAIL][21] ([i915#725]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-ivb-3770/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#109635] / [i915#217]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][25] ([fdo#111096] / [i915#323]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html *
Re: [Intel-gfx] [PATCH v2] drm/i915/gem: Don't leak non-persistent requests on changing engines
Quoting Tvrtko Ursulin (2020-02-05 16:22:34)
>
>
> On 05/02/2020 12:13, Chris Wilson wrote:
> > If we have a set of active engines marked as being non-persistent, we
> > lose track of those if the user replaces those engines with
> > I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
> > non-persistent requests are terminated if they are no longer being
> > tracked by the user's context (in order to prevent a lost request
> > causing an untracked and so unstoppable GPU hang), we need to apply the
> > same context cancellation upon changing engines.
> >
> > Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
> > Testcase: XXX
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index 52a749691a8d..20f1d3e0221f 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1624,11 +1624,18 @@ set_engines(struct i915_gem_context *ctx,
> >
> > replace:
> > mutex_lock(&ctx->engines_mutex);
> > +
> > + /* Flush stale requests off the old engines if required */
> > + if (!i915_gem_context_is_persistent(ctx) ||
> > + !i915_modparams.enable_hangcheck)
> > + kill_context(ctx);
>
> Is the negative effect of this is legit contexts can't keep submitting
> and changing the map? Only if PREEMPT_TIMEOUT is disabled I think but
> still. Might break legitimate userspace. Not that I offer solutions.. :(
> Banning changing engines once context went non-persistent? That too can
> break someone.
It closes the hole we have. To do otherwise, we need to keep track of
the old engines. Not an impossible task, certainly inconvenient.
struct old_engines {
struct i915_active active;
struct list_head link;
struct i915_gem_context *ctx;
void *engines;
int num_engines;
};
With a list+spinlock in the ctx that we can work in kill_context.
The biggest catch there is actually worrying about attaching the active
to already executing request, and making sure the coupling doesn't bug
on a concurrent completion. Hmm, it's just a completion callback, but
more convenient to use a ready made one.
-Chris
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Re: [Intel-gfx] [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
> -Original Message- > From: dri-devel On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in > the > crtc state dump > > Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump. > > HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata > Infoframe SDP use the same member variable in infoframes of crtc state. Looks good to me. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 239861bcedba..593c63f51210 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct > intel_crtc_state *pipe_config, > if (pipe_config->infoframes.enable & > intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) > intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); > + if (pipe_config->infoframes.enable & > + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) > + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); > > drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); > drm_mode_debug_printmodeline(&pipe_config->hw.mode); > -- > 2.24.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
>
> Dump out the DP VSC SDP in the normal crtc state dump
>
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
> Use drm core's DP VSC SDP logging function
Looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 593c63f51210..4f187fd330e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private
> *dev_priv,
> hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); }
>
> +static void
> +intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
> + const struct drm_dp_vsc_sdp *vsc) {
> + if (!drm_debug_enabled(DRM_UT_KMS))
> + return;
> +
> + drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); }
> +
> #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
>
> static const char * const output_type_str[] = { @@ -13036,6 +13046,9 @@
> static
> void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> if (pipe_config->infoframes.enable &
> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> + if (pipe_config->infoframes.enable &
> + intel_hdmi_infoframe_enable(DP_SDP_VSC))
> + intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
>
> drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
> drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> --
> 2.24.1
>
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Re: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs
> -Original Message-
> From: Intel-gfx On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed
> configs
>
> In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
> Infoframe SDP), it replaces intel_dp_vsc_enable() function and
> intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes() function.
>
> Before applying it, routines of program SDP always calculated configs when
> they
> called. And it removes unused functions.
Fix the sentence, seems unclear.
With that fixed,
Reviewed-by: Uma Shankar
>
> v3: Rebased
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 226 ---
> drivers/gpu/drm/i915/display/intel_dp.h | 6 -
> 3 files changed, 1 insertion(+), 234 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c96f629cddc3..374ab6a3757c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
>
> intel_edp_backlight_on(crtc_state, conn_state);
> intel_psr_enable(intel_dp, crtc_state);
> - intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
> - intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
> + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> if (crtc_state->has_audio)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d4ece0a824c0..cffb77daec96 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
> }
> }
>
> -static void
> -intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> -const struct intel_crtc_state *crtc_state,
> -const struct drm_connector_state *conn_state)
> -{
> - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> - struct dp_sdp vsc_sdp = {};
> -
> - /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
> - vsc_sdp.sdp_header.HB0 = 0;
> - vsc_sdp.sdp_header.HB1 = 0x7;
> -
> - /*
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc_sdp.sdp_header.HB2 = 0x5;
> -
> - /*
> - * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> - * Colorimetry Format indication (HB2 = 05h).
> - */
> - vsc_sdp.sdp_header.HB3 = 0x13;
> -
> - /* DP 1.4a spec, Table 2-120 */
> - switch (crtc_state->output_format) {
> - case INTEL_OUTPUT_FORMAT_YCBCR444:
> - vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
> - break;
> - case INTEL_OUTPUT_FORMAT_YCBCR420:
> - vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
> - break;
> - case INTEL_OUTPUT_FORMAT_RGB:
> - default:
> - /* RGB: DB16[7:4] = 0h */
> - break;
> - }
> -
> - switch (conn_state->colorspace) {
> - case DRM_MODE_COLORIMETRY_BT709_YCC:
> - vsc_sdp.db[16] |= 0x1;
> - break;
> - case DRM_MODE_COLORIMETRY_XVYCC_601:
> - vsc_sdp.db[16] |= 0x2;
> - break;
> - case DRM_MODE_COLORIMETRY_XVYCC_709:
> - vsc_sdp.db[16] |= 0x3;
> - break;
> - case DRM_MODE_COLORIMETRY_SYCC_601:
> - vsc_sdp.db[16] |= 0x4;
> - break;
> - case DRM_MODE_COLORIMETRY_OPYCC_601:
> - vsc_sdp.db[16] |= 0x5;
> - break;
> - case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> - case DRM_MODE_COLORIMETRY_BT2020_RGB:
> - vsc_sdp.db[16] |= 0x6;
> - break;
> - case DRM_MODE_COLORIMETRY_BT2020_YCC:
> - vsc_sdp.db[16] |= 0x7;
> - break;
> - case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> - case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> - vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
> - break;
> - default:
> - /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
> -
> - /* RGB->YCBCR color conversion uses the BT.709 color space. */
> - if (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> - vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
> - break;
> - }
> -
> - /*
> - * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
> - * the following Component Bit Depth valu
Re: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
> -Original Message- > From: Intel-gfx On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR > Metadata Infoframe SDP > > Added state readout for DP HDR Metadata Infoframe SDP. Looks good. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 8 > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 374ab6a3757c..a9eaf7a6bc15 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > pipe_config->fec_enable); > } > > + pipe_config->infoframes.enable |= > + intel_hdmi_infoframes_enabled(encoder, pipe_config); > + > break; > case TRANS_DDI_MODE_SELECT_DP_MST: > pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ - > 4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); > > intel_dp_get_m_n(intel_crtc, pipe_config); > + > + pipe_config->infoframes.enable |= > + intel_hdmi_infoframes_enabled(encoder, pipe_config); > break; > default: > break; > @@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > intel_read_infoframe(encoder, pipe_config, >HDMI_INFOFRAME_TYPE_DRM, >&pipe_config->infoframes.drm); > + > + intel_read_dp_sdp(encoder, pipe_config, > +HDMI_PACKET_TYPE_GAMUT_METADATA); > } > > static enum intel_output_type > -- > 2.24.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP
>
> Added state readout for DP VSC SDP and enabled state validation for DP VSC
> SDP.
>
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Looks good.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 42
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a9eaf7a6bc15..64e4edefa998 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>&pipe_config->infoframes.drm);
>
> intel_read_dp_sdp(encoder, pipe_config,
> HDMI_PACKET_TYPE_GAMUT_METADATA);
> + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> static enum intel_output_type
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f187fd330e8..02471c7aa6e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union
> hdmi_infoframe *a,
> return memcmp(a, b, sizeof(*a)) == 0;
> }
>
> +static bool
> +intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
> + const struct drm_dp_vsc_sdp *b)
> +{
> + return memcmp(a, b, sizeof(*a)) == 0;
> +}
> +
> static void
> pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
> bool fastset, const char *name, @@ -13528,6
> +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
> *dev_priv,
> }
> }
>
> +static void
> +pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
> + bool fastset, const char *name,
> + const struct drm_dp_vsc_sdp *a,
> + const struct drm_dp_vsc_sdp *b)
> +{
> + if (fastset) {
> + if (!drm_debug_enabled(DRM_UT_KMS))
> + return;
> +
> + DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
> + DRM_DEBUG_KMS("expected:\n");
> + drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
> + DRM_DEBUG_KMS("found:\n");
> + drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
> + } else {
> + DRM_ERROR("mismatch in %s dp sdp\n", name);
> + DRM_ERROR("expected:\n");
> + drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
> + DRM_ERROR("found:\n");
> + drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
> + }
> +}
> +
> static void __printf(4, 5)
> pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
>const char *name, const char *format, ...) @@ -13729,6
> +13760,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> } \
> } while (0)
>
> +#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
> + if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
> + &pipe_config->infoframes.name)) { \
> + pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
> __stringify(name), \
> + ¤t_config-
> >infoframes.name, \
> + &pipe_config->infoframes.name);
> \
> + ret = false; \
> + } \
> +} while (0)
> +
> #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
> if (current_config->name1 != pipe_config->name1) { \
> pipe_config_mismatch(fastset, crtc, __stringify(name1), \ @@ -
> 13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> PIPE_CONF_CHECK_INFOFRAME(spd);
> PIPE_CONF_CHECK_INFOFRAME(hdmi);
> PIPE_CONF_CHECK_INFOFRAME(drm);
> + PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
>
> PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
> PIPE_CONF_CHECK_I(master_transcoder);
> --
> 2.24.1
>
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Re: [Intel-gfx] [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates
> -Original Message- > From: dri-devel On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates > > Call intel_dp_set_infoframes() function on pipe updates to make sure that we > send > VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets. Looks good to me. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 64e4edefa998..69073a15edb8 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct > intel_encoder > *encoder, > intel_ddi_set_dp_msa(crtc_state, conn_state); > > intel_psr_update(intel_dp, crtc_state); > + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); > intel_edp_drrs_enable(intel_dp, crtc_state); > > intel_panel_update_backlight(encoder, crtc_state, conn_state); > -- > 2.24.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
> -Original Message- > From: dri-devel On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on > intel_ddi_post_disable_dp() Just say " Stop sending DP SDPs on ddi disable" > Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() > to make > sure not to send VSC SDP and HDR Metadata Infoframe SDP. With the above fixed. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 69073a15edb8..8509cd33569e 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct > intel_encoder > *encoder, > INTEL_OUTPUT_DP_MST); > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > + intel_dp_set_infoframes(encoder, false, old_crtc_state, > +old_conn_state); > + > /* >* Power down sink before disabling the port, otherwise we end >* up getting interrupts from the sink on detecting link loss. > -- > 2.24.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
>
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it adds
> a
> compute routine for PSR VSC SDP.
> As PSR routine can not use infoframes.vsc of crtc state, it also adds new
> writing of
> DP SDPs (Secondary Data Packet) for PSR.
> PSR routine has its own scenario and timings of writing a VSC SDP.
>
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 53 +
> drivers/gpu/drm/i915/display/intel_dp.h | 8
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cffb77daec96..4d65ef36577f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>&crtc_state->infoframes.vsc);
> }
>
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state,
> + struct drm_dp_vsc_sdp *vsc)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + vsc->sdp_type = DP_SDP_VSC;
> +
> + if (dev_priv->psr.psr2_enabled) {
> + if (dev_priv->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [PSR2, +Colorimetry] */
> + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> + vsc);
> + } else {
> + /*
> + * [PSR2, -Colorimetry]
> + * Prepare VSC Header for SU as per eDP 1.4 spec, Table
> 6-
> 11
> + * 3D stereo + PSR/PSR2 + Y-coordinate.
> + */
> + vsc->revision = 0x4;
> + vsc->length = 0xe;
> + }
> + } else {
> + /*
> + * [PSR1]
> + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> + * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
> + * higher).
> + */
> + vsc->revision = 0x2;
> + vsc->length = 0x8;
> + }
> +}
> +
> static void
> intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state) @@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct
> intel_encoder *encoder,
> intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
> }
>
> +void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + struct drm_dp_vsc_sdp *vsc)
> +{
> + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> + struct dp_sdp sdp = {};
> + ssize_t len;
> +
> + len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
> +
> + if (WARN_ON(len < 0))
> + return;
> +
> + intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
> + &sdp, len);
> +}
> +
> void intel_dp_set_infoframes(struct intel_encoder *encoder,
>bool enable,
>const struct intel_crtc_state *crtc_state, diff
> --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 6562bb8edeba..5074e52722c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -18,6 +18,7 @@ struct drm_connector_state; struct drm_encoder; struct
> drm_i915_private; struct drm_modeset_acquire_ctx;
> +struct drm_dp_vsc_sdp;
> struct intel_connector;
> struct intel_crtc_state;
> struct intel_digital_port;
> @@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
> int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes); bool
> intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_sta
Re: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
> -Original Message-
> From: Intel-gfx On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute
> routine on PSR
>
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses
> a
> new psr vsc sdp compute routine.
> Because PSR routine has its own scenario and timings of writing a VSC SDP, the
> current PSR routine needs to have its own drm_dp_vsc_sdp structure member
> variable on struct i915_psr.
>
> In order to calculate colorimetry information, intel_psr_update() function and
> intel_psr_enable() function extend a drm_connector_state argument.
>
> There are no changes to PSR mechanism.
>
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Looks good.
Reviewed-by: Uma Shankar
Note: Please rebase, fix the comments and resend to trigger a full CI run.
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 54 +++-
> drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 4 files changed, 22 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8509cd33569e..00b46c45f6a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
> intel_dp_stop_link_train(intel_dp);
>
> intel_edp_backlight_on(crtc_state, conn_state);
> - intel_psr_enable(intel_dp, crtc_state);
> + intel_psr_enable(intel_dp, crtc_state, conn_state);
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> @@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct
> intel_encoder
> *encoder,
>
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
> - intel_psr_update(intel_dp, crtc_state);
> + intel_psr_update(intel_dp, crtc_state, conn_state);
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e41ed962aa80..a4564607b6c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> }
> }
>
> -static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct dp_sdp psr_vsc;
> -
> - if (dev_priv->psr.psr2_enabled) {
> - /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
> - memset(&psr_vsc, 0, sizeof(psr_vsc));
> - psr_vsc.sdp_header.HB0 = 0;
> - psr_vsc.sdp_header.HB1 = 0x7;
> - if (dev_priv->psr.colorimetry_support) {
> - psr_vsc.sdp_header.HB2 = 0x5;
> - psr_vsc.sdp_header.HB3 = 0x13;
> - } else {
> - psr_vsc.sdp_header.HB2 = 0x4;
> - psr_vsc.sdp_header.HB3 = 0xe;
> - }
> - } else {
> - /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
> - memset(&psr_vsc, 0, sizeof(psr_vsc));
> - psr_vsc.sdp_header.HB0 = 0;
> - psr_vsc.sdp_header.HB1 = 0x7;
> - psr_vsc.sdp_header.HB2 = 0x2;
> - psr_vsc.sdp_header.HB3 = 0x8;
> - }
> -
> - intel_dig_port->write_infoframe(&intel_dig_port->base,
> - crtc_state,
> - DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
> -}
> -
> static void hsw_psr_setup_aux(struct intel_dp *intel_dp) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -841,9
> +808,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, }
>
> static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *crtc_state)
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state
> *conn_state)
> {
> struct intel_dp *intel_dp = dev_priv->psr.dp;
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct intel_encoder *encoder = &intel_dig_port->base;
> u32 val;
>
> WARN_ON(dev_priv->psr.enabled)
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Don't leak non-persistent requests on changing engines (rev2)
== Series Details == Series: drm/i915/gem: Don't leak non-persistent requests on changing engines (rev2) URL : https://patchwork.freedesktop.org/series/73023/ State : success == Summary == CI Bug Log - changes from CI_DRM_7869 -> Patchwork_16434 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/index.html Known issues Here are the changes found in Patchwork_16434 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] ([fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-y/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-kbl-x1275: [PASS][5] -> [INCOMPLETE][6] ([i915#504]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [PASS][7] -> [TIMEOUT][8] ([fdo#112271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-bdw-5557u/igt@i915_selftest@live_gtt.html * igt@prime_self_import@basic-llseek-bad: - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([CI#94] / [i915#402]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@prime_self_imp...@basic-llseek-bad.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-tgl-y/igt@prime_self_imp...@basic-llseek-bad.html Possible fixes * igt@gem_exec_parallel@fds: - fi-icl-u3: [INCOMPLETE][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-u3/igt@gem_exec_paral...@fds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-icl-u3/igt@gem_exec_paral...@fds.html * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][13] ([CI#94]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_module_load@reload: - fi-skl-6770hq: [DMESG-WARN][17] ([i915#92]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-6770hq/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[DMESG-FAIL][19] ([i915#725]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-ivb-3770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][21] ([fdo#109635] / [i915#217]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#111096] / [i915#323]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [SKIP][25] ([fdo#109271]) -> [PASS][26] +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame
[Intel-gfx] [PATCH v6 00/10] Introduce CAP_PERFMON to secure system performance monitoring and observability
Currently access to perf_events, i915_perf and other performance monitoring and observability subsystems of the kernel is open only for a privileged process [1] with CAP_SYS_ADMIN capability enabled in the process effective set [2]. This patch set introduces CAP_PERFMON capability designed to secure system performance monitoring and observability operations so that CAP_PERFMON would assist CAP_SYS_ADMIN capability in its governing role for performance monitoring and observability subsystems of the kernel. CAP_PERFMON intends to harden system security and integrity during performance monitoring and observability operations by decreasing attack surface that is available to a CAP_SYS_ADMIN privileged process [2]. Providing the access to performance monitoring and observability operations under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes the operation more secure. Thus, CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e: 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) CAP_PERFMON intends to meet the demand to secure system performance monitoring and observability operations for adoption in security sensitive, restricted, multiuser production environments (e.g. HPC clusters, cloud and virtual compute environments), where root or CAP_SYS_ADMIN credentials are not available to mass users of a system, and securely unblock accessibility of system performance monitoring and observability operations beyond root and CAP_SYS_ADMIN use cases. CAP_PERFMON intends to take over CAP_SYS_ADMIN credentials related to system performance monitoring and observability operations and balance amount of CAP_SYS_ADMIN credentials following the recommendations in the capabilities man page [2] for CAP_SYS_ADMIN: "Note: this capability is overloaded; see Notes to kernel developers, below." For backward compatibility reasons access to system performance monitoring and observability subsystems of the kernel remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN capability usage for secure system performance monitoring and observability operations is discouraged with respect to the designed CAP_PERFMON capability. Possible alternative solution to this system security hardening, capabilities balancing task of making performance monitoring and observability operations more secure and accessible could be to use the existing CAP_SYS_PTRACE capability to govern system performance monitoring and observability subsystems. However CAP_SYS_PTRACE capability still provides users with more credentials than are required for secure performance monitoring and observability operations and this excess is avoided by the designed CAP_PERFMON capability. Although software running under CAP_PERFMON can not ensure avoidance of related hardware issues, the software can still mitigate those issues following the official hardware issues mitigation procedure [3]. The bugs in the software itself can be fixed following the standard kernel development process [4] to maintain and harden security of system performance monitoring and observability operations. Finally, the patch set is shaped in the way that simplifies backtracking procedure of possible induced issues [5] as much as possible. The patch set is for tip perf/core repository: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip perf/core sha1: 0cc4bd8f70d1ea2940295f1050508c663fe9eff9 --- Changes in v6: - avoided noaudit checks in perfmon_capable() to explicitly advertise CAP_PERFMON usage thru audit logs to secure system performance monitoring and observability Changes in v5: - renamed CAP_SYS_PERFMON to CAP_PERFMON - extended perfmon_capable() with noaudit checks Changes in v4: - converted perfmon_capable() into an inline function - made perf_events kprobes, uprobes, hw breakpoints and namespaces data available to CAP_SYS_PERFMON privileged processes - applied perfmon_capable() to drivers/perf and drivers/oprofile - extended __cmd_ftrace() with support of CAP_SYS_PERFMON Changes in v3: - implemented perfmon_capable() macros aggregating required capabilities checks Changes in v2: - made perf_events trace points available to CAP_SYS_PERFMON privileged processes - made perf_event_paranoid_check() treat CAP_SYS_PERFMON equally to CAP_SYS_ADMIN - applied CAP_SYS_PERFMON to i915_perf, bpf_trace, powerpc and parisc system performance monitoring and observability related subsystems --- Alexey Budankov (10): capabilities: introduce CAP_PERFMON to kernel and user space perf/core: open access to the core for CAP_PERFMON privileged process perf/core: open access to probes for CAP_P
[Intel-gfx] [PATCH v6 01/10] capabilities: introduce CAP_PERFMON to kernel and user space
Introduce CAP_PERFMON capability designed to secure system performance
monitoring and observability operations so that CAP_PERFMON would assist
CAP_SYS_ADMIN capability in its governing role for performance monitoring
and observability subsystems.
CAP_PERFMON hardens system security and integrity during performance
monitoring and observability operations by decreasing attack surface that
is available to a CAP_SYS_ADMIN privileged process [2]. Providing the access
to system performance monitoring and observability operations under CAP_PERFMON
capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes
chances to misuse the credentials and makes the operation more secure.
Thus, CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e: 2.2.2.39 principle
of least privilege: A security design principle that states that a process
or program be granted only those privileges (e.g., capabilities) necessary
to accomplish its legitimate function, and only for the time that such
privileges are actually required)
CAP_PERFMON meets the demand to secure system performance monitoring and
observability operations for adoption in security sensitive, restricted,
multiuser production environments (e.g. HPC clusters, cloud and virtual compute
environments), where root or CAP_SYS_ADMIN credentials are not available to
mass users of a system, and securely unblocks accessibility of system
performance monitoring and observability operations beyond root and
CAP_SYS_ADMIN use cases.
CAP_PERFMON takes over CAP_SYS_ADMIN credentials related to system performance
monitoring and observability operations and balances amount of CAP_SYS_ADMIN
credentials following the recommendations in the capabilities man page [1]
for CAP_SYS_ADMIN: "Note: this capability is overloaded; see Notes to kernel
developers, below." For backward compatibility reasons access to system
performance monitoring and observability subsystems of the kernel remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN capability
usage for secure system performance monitoring and observability operations
is discouraged with respect to the designed CAP_PERFMON capability.
Although the software running under CAP_PERFMON can not ensure avoidance
of related hardware issues, the software can still mitigate these issues
following the official hardware issues mitigation procedure [2]. The bugs
in the software itself can be fixed following the standard kernel development
process [3] to maintain and harden security of system performance monitoring
and observability operations.
[1] http://man7.org/linux/man-pages/man7/capabilities.7.html
[2]
https://www.kernel.org/doc/html/latest/process/embargoed-hardware-issues.html
[3] https://www.kernel.org/doc/html/latest/admin-guide/security-bugs.html
Signed-off-by: Alexey Budankov
---
include/linux/capability.h | 4
include/uapi/linux/capability.h | 8 +++-
security/selinux/include/classmap.h | 4 ++--
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/linux/capability.h b/include/linux/capability.h
index ecce0f43c73a..027d7e4a853b 100644
--- a/include/linux/capability.h
+++ b/include/linux/capability.h
@@ -251,6 +251,10 @@ extern bool privileged_wrt_inode_uidgid(struct
user_namespace *ns, const struct
extern bool capable_wrt_inode_uidgid(const struct inode *inode, int cap);
extern bool file_ns_capable(const struct file *file, struct user_namespace
*ns, int cap);
extern bool ptracer_capable(struct task_struct *tsk, struct user_namespace
*ns);
+static inline bool perfmon_capable(void)
+{
+ return capable(CAP_PERFMON) || capable(CAP_SYS_ADMIN);
+}
/* audit system wants to get cap info from files as well */
extern int get_vfs_caps_from_disk(const struct dentry *dentry, struct
cpu_vfs_cap_data *cpu_caps);
diff --git a/include/uapi/linux/capability.h b/include/uapi/linux/capability.h
index 240fdb9a60f6..8b416e5f3afa 100644
--- a/include/uapi/linux/capability.h
+++ b/include/uapi/linux/capability.h
@@ -366,8 +366,14 @@ struct vfs_ns_cap_data {
#define CAP_AUDIT_READ 37
+/*
+ * Allow system performance and observability privileged operations
+ * using perf_events, i915_perf and other kernel subsystems
+ */
+
+#define CAP_PERFMON38
-#define CAP_LAST_CAP CAP_AUDIT_READ
+#define CAP_LAST_CAP CAP_PERFMON
#define cap_valid(x) ((x) >= 0 && (x) <= CAP_LAST_CAP)
diff --git a/security/selinux/include/classmap.h
b/security/selinux/include/classmap.h
index 7db24855e12d..c599b0c2b0e7 100644
--- a/security/selinux/include/classmap.h
+++ b/security/selinux/include/classmap.h
@@ -27,9 +27,9 @@
"audit_control", "setfcap"
#define COMMON_CAP2_PERMS "mac_override", "mac_admin", "syslog", \
- "wake_alarm", "block_suspend", "audit_read"
+ "wake_alarm", "block_suspend", "audit_read", "perfmon"
-#if CAP_LAST
[Intel-gfx] [PATCH v6 02/10] perf/core: open access to the core for CAP_PERFMON privileged process
Open access to monitoring of kernel code, cpus, tracepoints and namespaces
data for a CAP_PERFMON privileged process. Providing the access under
CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials,
excludes chances to misuse the credentials and makes operation more secure.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle
of least privilege: A security design principle that states that a process or
program be granted only those privileges (e.g., capabilities) necessary to
accomplish its legitimate function, and only for the time that such privileges
are actually required)
For backward compatibility reasons access to perf_events subsystem remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure
perf_events monitoring is discouraged with respect to CAP_PERFMON capability.
Signed-off-by: Alexey Budankov
---
include/linux/perf_event.h | 6 +++---
kernel/events/core.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 6d4c22aee384..730469babcc2 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -1285,7 +1285,7 @@ static inline int perf_is_paranoid(void)
static inline int perf_allow_kernel(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > 1 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > 1 && !perfmon_capable())
return -EACCES;
return security_perf_event_open(attr, PERF_SECURITY_KERNEL);
@@ -1293,7 +1293,7 @@ static inline int perf_allow_kernel(struct
perf_event_attr *attr)
static inline int perf_allow_cpu(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > 0 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > 0 && !perfmon_capable())
return -EACCES;
return security_perf_event_open(attr, PERF_SECURITY_CPU);
@@ -1301,7 +1301,7 @@ static inline int perf_allow_cpu(struct perf_event_attr
*attr)
static inline int perf_allow_tracepoint(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > -1 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > -1 && !perfmon_capable())
return -EPERM;
return security_perf_event_open(attr, PERF_SECURITY_TRACEPOINT);
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 2173c23c25b4..d956c81bd310 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -11186,7 +11186,7 @@ SYSCALL_DEFINE5(perf_event_open,
}
if (attr.namespaces) {
- if (!capable(CAP_SYS_ADMIN))
+ if (!perfmon_capable())
return -EACCES;
}
--
2.20.1
___
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[Intel-gfx] [PATCH v6 03/10] perf/core: open access to probes for CAP_PERFMON privileged process
Open access to monitoring via kprobes and uprobes and eBPF tracing for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. perf kprobes and uprobes are used by ftrace and eBPF. perf probe uses ftrace to define new kprobe events, and those events are treated as tracepoint events. eBPF defines new probes via perf_event_open interface and then the probes are used in eBPF tracing. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to perf_events subsystem remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure perf_events monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- kernel/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index d956c81bd310..c6453320ffea 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -9088,7 +9088,7 @@ static int perf_kprobe_event_init(struct perf_event *event) if (event->attr.type != perf_kprobe.type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* @@ -9148,7 +9148,7 @@ static int perf_uprobe_event_init(struct perf_event *event) if (event->attr.type != perf_uprobe.type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 04/10] perf tool: extend Perf tool with CAP_PERFMON capability support
Extend error messages to mention CAP_PERFMON capability as an option
to substitute CAP_SYS_ADMIN capability for secure system performance
monitoring and observability operations. Make perf_event_paranoid_check()
and __cmd_ftrace() to be aware of CAP_PERFMON capability.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39
principle of least privilege: A security design principle that states
that a process or program be granted only those privileges (e.g.,
capabilities) necessary to accomplish its legitimate function, and only
for the time that such privileges are actually required)
For backward compatibility reasons access to perf_events subsystem remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for
secure perf_events monitoring is discouraged with respect to CAP_PERFMON
capability.
Signed-off-by: Alexey Budankov
---
tools/perf/builtin-ftrace.c | 5 +++--
tools/perf/design.txt | 3 ++-
tools/perf/util/cap.h | 4
tools/perf/util/evsel.c | 10 +-
tools/perf/util/util.c | 1 +
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c
index d5adc417a4ca..55eda54240fb 100644
--- a/tools/perf/builtin-ftrace.c
+++ b/tools/perf/builtin-ftrace.c
@@ -284,10 +284,11 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int
argc, const char **argv)
.events = POLLIN,
};
- if (!perf_cap__capable(CAP_SYS_ADMIN)) {
+ if (!(perf_cap__capable(CAP_PERFMON) ||
+ perf_cap__capable(CAP_SYS_ADMIN))) {
pr_err("ftrace only works for %s!\n",
#ifdef HAVE_LIBCAP_SUPPORT
- "users with the SYS_ADMIN capability"
+ "users with the CAP_PERFMON or CAP_SYS_ADMIN capability"
#else
"root"
#endif
diff --git a/tools/perf/design.txt b/tools/perf/design.txt
index 0453ba26cdbd..a42fab308ff6 100644
--- a/tools/perf/design.txt
+++ b/tools/perf/design.txt
@@ -258,7 +258,8 @@ gets schedule to. Per task counters can be created by any
user, for
their own tasks.
A 'pid == -1' and 'cpu == x' counter is a per CPU counter that counts
-all events on CPU-x. Per CPU counters need CAP_SYS_ADMIN privilege.
+all events on CPU-x. Per CPU counters need CAP_PERFMON or CAP_SYS_ADMIN
+privilege.
The 'flags' parameter is currently unused and must be zero.
diff --git a/tools/perf/util/cap.h b/tools/perf/util/cap.h
index 051dc590ceee..ae52878c0b2e 100644
--- a/tools/perf/util/cap.h
+++ b/tools/perf/util/cap.h
@@ -29,4 +29,8 @@ static inline bool perf_cap__capable(int cap __maybe_unused)
#define CAP_SYSLOG 34
#endif
+#ifndef CAP_PERFMON
+#define CAP_PERFMON38
+#endif
+
#endif /* __PERF_CAP_H */
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index a69e64236120..a35f17723dd3 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -2491,14 +2491,14 @@ int perf_evsel__open_strerror(struct evsel *evsel,
struct target *target,
"You may not have permission to collect %sstats.\n\n"
"Consider tweaking /proc/sys/kernel/perf_event_paranoid,\n"
"which controls use of the performance events system by\n"
-"unprivileged users (without CAP_SYS_ADMIN).\n\n"
+"unprivileged users (without CAP_PERFMON or
CAP_SYS_ADMIN).\n\n"
"The current value is %d:\n\n"
" -1: Allow use of (almost) all events by all users\n"
" Ignore mlock limit after perf_event_mlock_kb without
CAP_IPC_LOCK\n"
-">= 0: Disallow ftrace function tracepoint by users without
CAP_SYS_ADMIN\n"
-" Disallow raw tracepoint access by users without
CAP_SYS_ADMIN\n"
-">= 1: Disallow CPU event access by users without
CAP_SYS_ADMIN\n"
-">= 2: Disallow kernel profiling by users without
CAP_SYS_ADMIN\n\n"
+">= 0: Disallow ftrace function tracepoint by users without
CAP_PERFMON or CAP_SYS_ADMIN\n"
+" Disallow raw tracepoint access by users without
CAP_SYS_PERFMON or CAP_SYS_ADMIN\n"
+">= 1: Disallow CPU event access by users without CAP_PERFMON
or CAP_SYS_ADMIN\n"
+">= 2: Disallow kernel profiling by users without CAP_PERFMON
or CAP_SYS_ADMIN\n\n"
"To make this setting permanent, edit /etc/sysctl.conf too,
e.g.:\n\n"
" kernel.perf_event_paranoid = -1\n" ,
target->system_wide ? "system-wide " : "",
diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c
index 969ae560dad9..51cf3071db74 100644
--- a/tools/perf/util/util.c
+++ b/tools/perf/util/util.c
@@ -272,6 +272,7 @@ int perf_event_paranoid(void)
bool perf_event_paranoid_check(int max_level)
{
return perf_cap__capable(CAP_SYS_ADMIN)
