Re: [Intel-gfx] [i-g-t] dumb_buffer@clear_create triggers OOM since 0b0eaa353
On 4/23/20 5:38 PM, Li Zhijian wrote:
Hi guys
0Day noticed that dumb_buffer@clear_create triggers OOM since commit:
0b0eaa353 ("tests/dumb_buffer: Try to compute the largest possible
dumb buffer")
our platform is
- CPU: Intel(R) Xeon(R) CPU D-1541 @ 2.10GHz
- memory: 48G
- kernel: v5.5, v5.6, v5.7-rc2
i tried 2 other platforms
- i7-3770K + 16G
- AMD Opteron(TM) Processor 6276 + 128G
dumb_buffer@clear_create works well on both of them.
i have no enough knowledge in IGT and Kernel Graphic Driver, so if you
want to more debug info, please let me know.
Thanks
i tried to add some debug into the code as following
diff --git a/tests/dumb_buffer.c b/tests/dumb_buffer.c
index c1e7b4d3..22611f95 100644
--- a/tests/dumb_buffer.c
+++ b/tests/dumb_buffer.c
@@ -58,11 +58,13 @@ static int __dumb_create(int fd, struct
drm_mode_create_dumb *create)
{
int err = 0;
+ igt_info("start __dumb_create %ld\n", create->size);
if (igt_ioctl(fd, DRM_IOCTL_MODE_CREATE_DUMB, create)) {
err = -errno;
igt_assume(err);
}
+ igt_info("end __dumb_create %ld, err %d\n", create->size, err);
errno = 0;
return err;
}
@@ -80,10 +82,12 @@ static void *__dumb_map(int fd, uint32_t handle,
uint64_t size, unsigned prot)
if (igt_ioctl(fd, DRM_IOCTL_MODE_MAP_DUMB, ))
return NULL;
+ igt_info("size %ld, offset %x\n", size, arg.offset);
ptr = mmap(NULL, size, prot, MAP_SHARED, fd, arg.offset);
if (ptr == MAP_FAILED)
return NULL;
+ igt_info("mmap success, size %ld, offset %x\n", size,
arg.offset);
return ptr;
}
@@ -356,6 +360,7 @@ static uint64_t estimate_largest_dumb_buffer(int fd)
return largest / PAGE_SIZE;
}
+ sleep(1);
for (create.height = 1; create.height; create.height *= 2) {
if (__dumb_create(fd, ))
longjmp(sigjmp, SIGABRT);
@@ -368,7 +373,9 @@ static uint64_t estimate_largest_dumb_buffer(int fd)
if (!*ptr)
largest = create.size;
+ igt_info("mmap %ld\n", create.size);
munmap(ptr, create.size);
+ igt_info("unmmap %ld\n", create.size);
ptr = NULL;
}
then get below outputs:
Subtest map-invalid-size: SUCCESS (0.000s)
Starting subtest: create-clear
start __dumb_create 0
end __dumb_create 4194304, err 0
size 4194304, offset 1a48000
mmap success, size 4194304, offset 1a48000
mmap 4194304
unmmap 4194304
start __dumb_create 4194304
end __dumb_create 8388608, err 0
size 8388608, offset 1a48000
mmap success, size 8388608, offset 1a48000
mmap 8388608
unmmap 8388608
start __dumb_create 8388608
end __dumb_create 16777216, err 0
size 16777216, offset 1a48000
mmap success, size 16777216, offset 1a48000
mmap 16777216
unmmap 16777216
start __dumb_create 16777216
end __dumb_create 33554432, err 0
size 33554432, offset 1a48000
mmap success, size 33554432, offset 1a48000
mmap 33554432
unmmap 33554432
start __dumb_create 33554432
end __dumb_create 67108864, err 0
size 67108864, offset 1a48000
mmap success, size 67108864, offset 1a48000
mmap 67108864
unmmap 67108864
start __dumb_create 67108864
end __dumb_create 134217728, err 0
size 134217728, offset 1a48000
mmap success, size 134217728, offset 1a48000
mmap 134217728
unmmap 134217728
start __dumb_create 134217728
end __dumb_create 268435456, err 0
size 268435456, offset 1a48000
mmap success, size 268435456, offset 1a48000
mmap 268435456
unmmap 268435456
start __dumb_create 268435456
end __dumb_create 536870912, err 0
size 536870912, offset 1a48000
mmap success, size 536870912, offset 1a48000
mmap 536870912
unmmap 536870912
start __dumb_create 536870912
end __dumb_create 1073741824, err 0
size 1073741824, offset 1a48000
mmap success, size 1073741824, offset 1a48000
mmap 1073741824
unmmap 1073741824
start __dumb_create 1073741824
end __dumb_create 2147483648, err 0
size 2147483648, offset 1a48000
mmap success, size 2147483648, offset 1a48000
Killed
attached the dmesg as well[10703.523385] dumb_buffer invoked
oom-killer: gfp_mask=0x0(), order=0, oom_score_adj=1000
[10703.531385] CPU: 0 PID: 7166 Comm: dumb_buffer Not tainted
5.6.0-00335-g7111951b8d497 #1
[10703.539466] Hardware name: Supermicro
SYS-5018D-FN4T/X10SDV-8C-TLN4F, BIOS 1.1 03/02/2016
[10703.547630] Call Trace:
[10703.550080] dump_stack+0x66/0x8b
[10703.553398] dump_header+0x4a/0x220
[10703.556889] oom_kill_process+0xf6/0x150
[10703.560805] out_of_memory+0x105/0x540
[10703.564548] pagefault_out_of_memory+0x64/0x80
[10703.568987] page_fault+0x3e/0x50
[10703.572296] RIP: 0033:0x556f7b09257a
[10703.575867] Code: e8 2b fe ff ff 8b 74 24 40 44 89 f7 48 89 44 24
28 e8 ea fb ff ff 48 8b 44 24 28 48 85 c0 74 7d 48 8b 44 24 28 48 8b
4c 24 48 <80> 38 00 75 05 48 89 4c 24 20 48 8d 15 71 0b 00 00 31 ff 31
c0 be
[10703.594613] RSP: 002b:7fff025dc330 EFLAGS: 00010206
Re: [Intel-gfx] [PULL] gvt-next
On 2020.04.22 13:12:30 +0800, Zhenyu Wang wrote: > > Hi, > > Here's current gvt-next. This removes left non-upstream xen support bits > which will be kept out of tree instead. And several guest context shadow > optimizations from Yan. > > Thanks > -- Ping for merge.. > > The following changes since commit a61ac1e75105a077ec1efd6923ae3c619f862304: > > drm/i915/gvt: Wean gvt off using dev_priv (2020-03-06 10:08:10 +0800) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux tags/gvt-next-2020-04-22 > > for you to fetch changes up to fb55c735522352704c35d899d0b253453cf0e799: > > drm/i915/gvt: skip populate shadow context if guest context not changed > (2020-04-17 17:31:22 +0800) > > > gvt-next-2020-04-22 > > - remove non-upstream xen support bits (Christoph) > - guest context shadow copy optimization (Yan) > - guest context tracking for shadow skip optimization (Yan) > > > Christoph Hellwig (1): > i915/gvt: remove unused xen bits > > Yan Zhao (3): > drm/i915/gvt: access shadow ctx via its virtual address directly > drm/i915/gvt: combine access to consecutive guest context pages > drm/i915/gvt: skip populate shadow context if guest context not changed > > drivers/gpu/drm/i915/gvt/gtt.c | 15 + > drivers/gpu/drm/i915/gvt/gvt.c | 1 - > drivers/gpu/drm/i915/gvt/gvt.h | 5 ++ > drivers/gpu/drm/i915/gvt/hypercall.h | 2 - > drivers/gpu/drm/i915/gvt/scheduler.c | 127 > ++- > 5 files changed, 114 insertions(+), 36 deletions(-) > > -- > Open Source Technology Center, Intel ltd. > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 > ___ > intel-gvt-dev mailing list > intel-gvt-...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists (rev2)
== Series Details ==
Series: series starting with [1/6] drm/i915/gt: Always enable busy-stats for
execlists (rev2)
URL : https://patchwork.freedesktop.org/series/76486/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8368_full -> Patchwork_17464_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17464_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17464_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17464_full:
### IGT changes ###
Possible regressions
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-apl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-apl7/igt@p...@gen8-unprivileged-single-ctx-counters.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-apl1/igt@p...@gen8-unprivileged-single-ctx-counters.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_parallel@contexts@rcs0}:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-tglb6/igt@gem_exec_parallel@conte...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-tglb5/igt@gem_exec_parallel@conte...@rcs0.html
Known issues
Here are the changes found in Patchwork_17464_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-kbl4/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-kbl2/igt@gem_exec_susp...@basic-s3.html
* igt@kms_color@pipe-a-ctm-green-to-red:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#129])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-skl6/igt@kms_co...@pipe-a-ctm-green-to-red.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-skl9/igt@kms_co...@pipe-a-ctm-green-to-red.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-rapid-movement:
- shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-snb4/igt@kms_cursor_...@pipe-b-cursor-64x64-rapid-movement.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-snb2/igt@kms_cursor_...@pipe-b-cursor-64x64-rapid-movement.html
* igt@kms_cursor_legacy@pipe-c-torture-bo:
- shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([i915#128])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-hsw4/igt@kms_cursor_leg...@pipe-c-torture-bo.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-hsw2/igt@kms_cursor_leg...@pipe-c-torture-bo.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-skl8/igt@kms_...@bpc-switch.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-skl7/igt@kms_...@bpc-switch.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- shard-kbl: [PASS][15] -> [FAIL][16] ([i915#53] / [i915#93] /
[i915#95])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-kbl3/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-kbl2/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html
- shard-apl: [PASS][17] -> [FAIL][18] ([i915#53] / [i915#95])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-apl6/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-apl1/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-skl6/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists (rev2)
== Series Details == Series: series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists (rev2) URL : https://patchwork.freedesktop.org/series/76486/ State : success == Summary == CI Bug Log - changes from CI_DRM_8368 -> Patchwork_17464 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/index.html Known issues Here are the changes found in Patchwork_17464 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_pm: - fi-hsw-4770:[PASS][1] -> [DMESG-FAIL][2] ([i915#1791]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-hsw-4770/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/fi-hsw-4770/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@sanitycheck: - fi-bwr-2160:[PASS][3] -> [INCOMPLETE][4] ([i915#489]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-bwr-2160/igt@i915_selftest@l...@sanitycheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/fi-bwr-2160/igt@i915_selftest@l...@sanitycheck.html Possible fixes * igt@i915_selftest@live@gt_pm: - fi-bsw-kefka: [DMESG-FAIL][5] ([i915#1791]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html - fi-snb-2520m: [DMESG-FAIL][7] -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-snb-2520m/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/fi-snb-2520m/igt@i915_selftest@live@gt_pm.html - fi-whl-u: [DMESG-FAIL][9] ([i915#1791]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-whl-u/igt@i915_selftest@live@gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/fi-whl-u/igt@i915_selftest@live@gt_pm.html [i915#1791]: https://gitlab.freedesktop.org/drm/intel/issues/1791 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (47 -> 41) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8368 -> Patchwork_17464 CI-20190529: 20190529 CI_DRM_8368: b4afa978863f35e0b3f709412e967b66bb3af00c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5610: 71fed15724898a8f914666093352a964b70a62fc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17464: 5720afa836ee9f5ab6c67f839f7f923f05909be4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5720afa836ee drm/i915/gt: Restore aggressive post-boost downclocking 50df497d84b8 drm/i915/gt: Apply the aggressive downclocking to parking 45476008bc61 drm/i915/gt: Switch to manual evaluation of RPS 40d0b5f06de0 drm/i915/gt: Track use of RPS interrupts in flags 580c6e4c2a06 drm/i915/gt: Move rps.enabled/active to flags bd5217caba42 drm/i915/gt: Always enable busy-stats for execlists == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17464/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists (rev2)
== Series Details == Series: series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists (rev2) URL : https://patchwork.freedesktop.org/series/76486/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/gt: Always enable busy-stats for execlists +drivers/gpu/drm/i915/gt/sysfs_engines.c:73:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:74:10: error: bad integer constant expression -O:drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression -O:drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression Commit: drm/i915/gt: Move rps.enabled/active to flags Okay! Commit: drm/i915/gt: Track use of RPS interrupts in flags Okay! Commit: drm/i915/gt: Switch to manual evaluation of RPS Okay! Commit: drm/i915/gt: Apply the aggressive downclocking to parking Okay! Commit: drm/i915/gt: Restore aggressive post-boost downclocking Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists (rev2)
== Series Details ==
Series: series starting with [1/6] drm/i915/gt: Always enable busy-stats for
execlists (rev2)
URL : https://patchwork.freedesktop.org/series/76486/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bd5217caba42 drm/i915/gt: Always enable busy-stats for execlists
580c6e4c2a06 drm/i915/gt: Move rps.enabled/active to flags
40d0b5f06de0 drm/i915/gt: Track use of RPS interrupts in flags
45476008bc61 drm/i915/gt: Switch to manual evaluation of RPS
50df497d84b8 drm/i915/gt: Apply the aggressive downclocking to parking
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 21abf0bf168d ("drm/i915/gt:
Treat idling as a RPS downclock event")'
#12:
References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event")
total: 1 errors, 1 warnings, 0 checks, 31 lines checked
5720afa836ee drm/i915/gt: Restore aggressive post-boost downclocking
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 2a8862d2f3da ("drm/i915: Reduce
the RPS shock")'
#12:
References: 2a8862d2f3da ("drm/i915: Reduce the RPS shock")
total: 1 errors, 0 warnings, 0 checks, 34 lines checked
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists
== Series Details == Series: series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists URL : https://patchwork.freedesktop.org/series/76486/ State : success == Summary == CI Bug Log - changes from CI_DRM_8368 -> Patchwork_17463 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17463/index.html Known issues Here are the changes found in Patchwork_17463 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-rte: - fi-hsw-4770:[PASS][1] -> [SKIP][2] ([fdo#109271]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-hsw-4770/igt@i915_pm_...@basic-rte.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17463/fi-hsw-4770/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live@gt_timelines: - fi-bwr-2160:[PASS][3] -> [INCOMPLETE][4] ([i915#489]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-bwr-2160/igt@i915_selftest@live@gt_timelines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17463/fi-bwr-2160/igt@i915_selftest@live@gt_timelines.html Possible fixes * igt@i915_selftest@live@gt_pm: - fi-bsw-kefka: [DMESG-FAIL][5] ([i915#1791]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17463/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html - fi-snb-2520m: [DMESG-FAIL][7] -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-snb-2520m/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17463/fi-snb-2520m/igt@i915_selftest@live@gt_pm.html - fi-whl-u: [DMESG-FAIL][9] ([i915#1791]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8368/fi-whl-u/igt@i915_selftest@live@gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17463/fi-whl-u/igt@i915_selftest@live@gt_pm.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1791]: https://gitlab.freedesktop.org/drm/intel/issues/1791 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (47 -> 41) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8368 -> Patchwork_17463 CI-20190529: 20190529 CI_DRM_8368: b4afa978863f35e0b3f709412e967b66bb3af00c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5610: 71fed15724898a8f914666093352a964b70a62fc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17463: d4a784dd782a7beb4c84acd3b6263593dbe74fcf @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d4a784dd782a drm/i915/gt: Restore aggressive post-boost downclocking 5eedcd1d97cd drm/i915/gt: Apply the aggressive downclocking to parking 1984a028396c drm/i915/gt: Switch to manual evaluation of RPS ad4731a56b57 drm/i915/gt: Track use of RPS interrupts in flags 130a66584a4f drm/i915/gt: Move rps.enabled/active to flags 310c2635e565 drm/i915/gt: Always enable busy-stats for execlists == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17463/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists
== Series Details == Series: series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists URL : https://patchwork.freedesktop.org/series/76486/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/gt: Always enable busy-stats for execlists +drivers/gpu/drm/i915/gt/sysfs_engines.c:73:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:74:10: error: bad integer constant expression -O:drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression -O:drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression Commit: drm/i915/gt: Move rps.enabled/active to flags Okay! Commit: drm/i915/gt: Track use of RPS interrupts in flags Okay! Commit: drm/i915/gt: Switch to manual evaluation of RPS Okay! Commit: drm/i915/gt: Apply the aggressive downclocking to parking Okay! Commit: drm/i915/gt: Restore aggressive post-boost downclocking Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Switch to manual evaluation of RPS
As with the realisation for soft-rc6, we respond to idling the engines
within microseconds, far faster than the response times for HW RC6 and
RPS. Furthermore, our fast parking upon idle, prevents HW RPS from
running for many desktop workloads, as the RPS evaluation intervals are
on the order of tens of milliseconds, but the typical workload is just a
couple of milliseconds, but yet we still need to determine the best
frequency for user latency versus power.
Recognising that the HW evaluation intervals are a poor fit, and that
they were deprecated [in bspec at least] from gen10, start to wean
ourselves off them and replace the EI with a timer and our accurate
busy-stats. The principle benefit of manually evaluating RPS intervals
is that we can be more responsive for better performance and powersaving
for both spiky workloads and steady-state.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1698
Fixes: 98479ada421a ("drm/i915/gt: Treat idling as a RPS downclock event")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 82 +++-
drivers/gpu/drm/i915/gt/intel_rps.h | 10 +++
drivers/gpu/drm/i915/gt/intel_rps_types.h| 5 ++
4 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d7250b2d4175..b2c3e8df3eba 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -551,6 +551,11 @@ struct intel_engine_cs {
* Idle is defined as active == 0, active is active > 0.
*/
ktime_t start;
+
+ /**
+* @rps: Utilisation at last RPS sampling.
+*/
+ ktime_t rps;
} stats;
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 58a10b3d60ba..8658fd82d59c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -45,6 +45,62 @@ static inline void set(struct intel_uncore *uncore,
i915_reg_t reg, u32 val)
intel_uncore_write_fw(uncore, reg, val);
}
+static void rps_timer(struct timer_list *t)
+{
+ struct intel_rps *rps = from_timer(rps, t, timer);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ ktime_t dt, last;
+ s64 max_busy = 0;
+
+ for_each_engine(engine, rps_to_gt(rps), id) {
+ dt = intel_engine_get_busy_time(engine);
+ last = engine->stats.rps;
+ engine->stats.rps = dt;
+
+ max_busy = max(max_busy, ktime_to_ns(ktime_sub(dt, last)));
+ }
+
+ dt = ktime_get();
+ last = rps->pm_timestamp;
+ rps->pm_timestamp = dt;
+
+ if (intel_rps_is_active(rps)) {
+ dt = ktime_sub(dt, last);
+
+ if (10 * max_busy > 9 * dt && /* >90% busy */
+ rps->cur_freq < rps->max_freq_softlimit) {
+ rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD;
+ rps->pm_interval = 1;
+ schedule_work(>work);
+ } else if (4 * max_busy < 3 * dt && /* <75% busy */
+ rps->cur_freq > rps->min_freq_softlimit) {
+ rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD;
+ rps->pm_interval = 1;
+ schedule_work(>work);
+ } else {
+ rps->last_adj = 0;
+ }
+
+ mod_timer(>timer,
+ jiffies + msecs_to_jiffies(rps->pm_interval));
+ rps->pm_interval = min(rps->pm_interval + 1, 15u);
+ }
+}
+
+static void rps_start_timer(struct intel_rps *rps)
+{
+ rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp);
+ rps->pm_interval = 1;
+ mod_timer(>timer, jiffies + 1);
+}
+
+static void rps_stop_timer(struct intel_rps *rps)
+{
+ del_timer_sync(>timer);
+ rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp);
+}
+
static u32 rps_pm_mask(struct intel_rps *rps, u8 val)
{
u32 mask = 0;
@@ -742,8 +798,11 @@ void intel_rps_unpark(struct intel_rps *rps)
mutex_unlock(>lock);
+ rps->pm_iir = 0;
if (intel_rps_has_interrupts(rps))
rps_enable_interrupts(rps);
+ if (intel_rps_uses_timer(rps))
+ rps_start_timer(rps);
if (IS_GEN(rps_to_i915(rps), 5))
gen5_rps_update(rps);
@@ -754,6 +813,8 @@ void intel_rps_park(struct intel_rps *rps)
if (!intel_rps_clear_active(rps))
return;
+ if (intel_rps_uses_timer(rps))
+ rps_stop_timer(rps);
if (intel_rps_has_interrupts(rps))
rps_disable_interrupts(rps);
@@ -1679,10 +1740,26 @@ void
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/gt: Always enable busy-stats for execlists
== Series Details ==
Series: series starting with [1/6] drm/i915/gt: Always enable busy-stats for
execlists
URL : https://patchwork.freedesktop.org/series/76486/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
310c2635e565 drm/i915/gt: Always enable busy-stats for execlists
130a66584a4f drm/i915/gt: Move rps.enabled/active to flags
ad4731a56b57 drm/i915/gt: Track use of RPS interrupts in flags
1984a028396c drm/i915/gt: Switch to manual evaluation of RPS
5eedcd1d97cd drm/i915/gt: Apply the aggressive downclocking to parking
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 21abf0bf168d ("drm/i915/gt:
Treat idling as a RPS downclock event")'
#12:
References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event")
total: 1 errors, 1 warnings, 0 checks, 31 lines checked
d4a784dd782a drm/i915/gt: Restore aggressive post-boost downclocking
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 2a8862d2f3da ("drm/i915: Reduce
the RPS shock")'
#12:
References: 2a8862d2f3da ("drm/i915: Reduce the RPS shock")
total: 1 errors, 0 warnings, 0 checks, 34 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm/i915/gt: Switch to manual evaluation of RPS
Quoting Chris Wilson (2020-04-25 18:57:49)
> +static bool has_busy_stats(struct intel_rps *rps)
> +{
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> +
> + for_each_engine(engine, rps_to_gt(rps), id) {
> + if (!intel_engine_supports_stats(engine))
Bah. The engines are not setup by this point. For the moment, I can just
hardcode it :(
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/6] drm/i915/gt: Switch to manual evaluation of RPS
As with the realisation for soft-rc6, we respond to idling the engines
within microseconds, far faster than the response times for HW RC6 and
RPS. Furthermore, our fast parking upon idle, prevents HW RPS from
running for many desktop workloads, as the RPS evaluation intervals are
on the order of tens of milliseconds, but the typical workload is just a
couple of milliseconds, but yet we still need to determine the best
frequency for user latency versus power.
Recognising that the HW evaluation intervals are a poor fit, and that
they were deprecated [in bspec at least] from gen10, start to wean
ourselves off them and replace the EI with a timer and our accurate
busy-stats. The principle benefit of manually evaluating RPS intervals
is that we can be more responsive for better performance and powersaving
for both spiky workloads and steady-state.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1698
Fixes: 98479ada421a ("drm/i915/gt: Treat idling as a RPS downclock event")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 80 +++-
drivers/gpu/drm/i915/gt/intel_rps.h | 10 +++
drivers/gpu/drm/i915/gt/intel_rps_types.h| 5 ++
4 files changed, 99 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d7250b2d4175..b2c3e8df3eba 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -551,6 +551,11 @@ struct intel_engine_cs {
* Idle is defined as active == 0, active is active > 0.
*/
ktime_t start;
+
+ /**
+* @rps: Utilisation at last RPS sampling.
+*/
+ ktime_t rps;
} stats;
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 58a10b3d60ba..36e59b74689f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -45,6 +45,62 @@ static inline void set(struct intel_uncore *uncore,
i915_reg_t reg, u32 val)
intel_uncore_write_fw(uncore, reg, val);
}
+static void rps_timer(struct timer_list *t)
+{
+ struct intel_rps *rps = from_timer(rps, t, timer);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ ktime_t dt, last;
+ s64 max_busy = 0;
+
+ for_each_engine(engine, rps_to_gt(rps), id) {
+ dt = intel_engine_get_busy_time(engine);
+ last = engine->stats.rps;
+ engine->stats.rps = dt;
+
+ max_busy = max(max_busy, ktime_to_ns(ktime_sub(dt, last)));
+ }
+
+ dt = ktime_get();
+ last = rps->pm_timestamp;
+ rps->pm_timestamp = dt;
+
+ if (intel_rps_is_active(rps)) {
+ dt = ktime_sub(dt, last);
+
+ if (10 * max_busy > 9 * dt && /* >90% busy */
+ rps->cur_freq < rps->max_freq_softlimit) {
+ rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD;
+ rps->pm_interval = 1;
+ schedule_work(>work);
+ } else if (4 * max_busy < 3 * dt && /* <75% busy */
+ rps->cur_freq > rps->min_freq_softlimit) {
+ rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD;
+ rps->pm_interval = 1;
+ schedule_work(>work);
+ } else {
+ rps->last_adj = 0;
+ }
+
+ mod_timer(>timer,
+ jiffies + msecs_to_jiffies(rps->pm_interval));
+ rps->pm_interval = min(rps->pm_interval + 1, 15u);
+ }
+}
+
+static void rps_start_timer(struct intel_rps *rps)
+{
+ rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp);
+ rps->pm_interval = 1;
+ mod_timer(>timer, jiffies + 1);
+}
+
+static void rps_stop_timer(struct intel_rps *rps)
+{
+ del_timer_sync(>timer);
+ rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp);
+}
+
static u32 rps_pm_mask(struct intel_rps *rps, u8 val)
{
u32 mask = 0;
@@ -742,8 +798,11 @@ void intel_rps_unpark(struct intel_rps *rps)
mutex_unlock(>lock);
+ rps->pm_iir = 0;
if (intel_rps_has_interrupts(rps))
rps_enable_interrupts(rps);
+ if (intel_rps_uses_timer(rps))
+ rps_start_timer(rps);
if (IS_GEN(rps_to_i915(rps), 5))
gen5_rps_update(rps);
@@ -754,6 +813,8 @@ void intel_rps_park(struct intel_rps *rps)
if (!intel_rps_clear_active(rps))
return;
+ if (intel_rps_uses_timer(rps))
+ rps_stop_timer(rps);
if (intel_rps_has_interrupts(rps))
rps_disable_interrupts(rps);
@@ -1679,10 +1740,24 @@ void
[Intel-gfx] [PATCH 2/6] drm/i915/gt: Move rps.enabled/active to flags
Pull the boolean intel_rps.enabled and intel_rps.active into a single
flags field, in preparation for more.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 5 +--
drivers/gpu/drm/i915/gt/intel_rps.c | 37 +--
drivers/gpu/drm/i915/gt/intel_rps.h | 30 ++
drivers/gpu/drm/i915/gt/intel_rps_types.h | 8 +++--
drivers/gpu/drm/i915/gt/selftest_rps.c| 20 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 5 +--
6 files changed, 73 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 3d3ef62ed89f..3fd33cd1a400 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -556,7 +556,8 @@ static int rps_boost_show(struct seq_file *m, void *data)
struct drm_i915_private *i915 = gt->i915;
struct intel_rps *rps = >rps;
- seq_printf(m, "RPS enabled? %d\n", rps->enabled);
+ seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
+ seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
seq_printf(m, "GPU busy? %s\n", yesno(gt->awake));
seq_printf(m, "Boosts outstanding? %d\n",
atomic_read(>num_waiters));
@@ -576,7 +577,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
seq_printf(m, "Wait boosts: %d\n", atomic_read(>boosts));
- if (INTEL_GEN(i915) >= 6 && rps->enabled && gt->awake) {
+ if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
struct intel_uncore *uncore = gt->uncore;
u32 rpup, rpupei;
u32 rpdown, rpdownei;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 2ce006e58b4a..05410d19dbc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -648,7 +648,7 @@ void intel_rps_mark_interactive(struct intel_rps *rps, bool
interactive)
mutex_lock(>power.mutex);
if (interactive) {
- if (!rps->power.interactive++ && READ_ONCE(rps->active))
+ if (!rps->power.interactive++ && intel_rps_is_active(rps))
rps_set_power(rps, HIGH_POWER);
} else {
GEM_BUG_ON(!rps->power.interactive);
@@ -721,7 +721,7 @@ static int rps_set(struct intel_rps *rps, u8 val, bool
update)
void intel_rps_unpark(struct intel_rps *rps)
{
- if (!rps->enabled)
+ if (!intel_rps_is_enabled(rps))
return;
GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq);
@@ -732,8 +732,7 @@ void intel_rps_unpark(struct intel_rps *rps)
*/
mutex_lock(>lock);
- WRITE_ONCE(rps->active, true);
-
+ intel_rps_set_active(rps);
intel_rps_set(rps,
clamp(rps->cur_freq,
rps->min_freq_softlimit,
@@ -754,13 +753,12 @@ void intel_rps_park(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- if (!rps->enabled)
+ if (!intel_rps_clear_active(rps))
return;
if (INTEL_GEN(i915) >= 6)
rps_disable_interrupts(rps);
- WRITE_ONCE(rps->active, false);
if (rps->last_freq <= rps->idle_freq)
return;
@@ -802,7 +800,7 @@ void intel_rps_boost(struct i915_request *rq)
struct intel_rps *rps = _ONCE(rq->engine)->gt->rps;
unsigned long flags;
- if (i915_request_signaled(rq) || !READ_ONCE(rps->active))
+ if (i915_request_signaled(rq) || !intel_rps_is_active(rps))
return;
/* Serializes with i915_request_retire() */
@@ -831,7 +829,7 @@ int intel_rps_set(struct intel_rps *rps, u8 val)
GEM_BUG_ON(val > rps->max_freq);
GEM_BUG_ON(val < rps->min_freq);
- if (rps->active) {
+ if (intel_rps_is_active(rps)) {
err = rps_set(rps, val, true);
if (err)
return err;
@@ -1219,6 +1217,7 @@ void intel_rps_enable(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
struct intel_uncore *uncore = rps_to_uncore(rps);
+ bool enabled = false;
if (!HAS_RPS(i915))
return;
@@ -1227,19 +1226,19 @@ void intel_rps_enable(struct intel_rps *rps)
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
if (IS_CHERRYVIEW(i915))
- rps->enabled = chv_rps_enable(rps);
+ enabled = chv_rps_enable(rps);
else if (IS_VALLEYVIEW(i915))
- rps->enabled = vlv_rps_enable(rps);
+ enabled = vlv_rps_enable(rps);
else if (INTEL_GEN(i915) >= 9)
- rps->enabled = gen9_rps_enable(rps);
+ enabled = gen9_rps_enable(rps);
else if (INTEL_GEN(i915) >= 8)
- rps->enabled = gen8_rps_enable(rps);
+
[Intel-gfx] [PATCH 3/6] drm/i915/gt: Track use of RPS interrupts in flags
Use the new intel_rps.flags field to store whether or not interrupts are
being used with RPS.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 13 -
drivers/gpu/drm/i915/gt/intel_rps.h | 10 ++
drivers/gpu/drm/i915/gt/intel_rps_types.h | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c| 2 +-
4 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 05410d19dbc0..58a10b3d60ba 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -742,7 +742,7 @@ void intel_rps_unpark(struct intel_rps *rps)
mutex_unlock(>lock);
- if (INTEL_GEN(rps_to_i915(rps)) >= 6)
+ if (intel_rps_has_interrupts(rps))
rps_enable_interrupts(rps);
if (IS_GEN(rps_to_i915(rps), 5))
@@ -751,12 +751,10 @@ void intel_rps_unpark(struct intel_rps *rps)
void intel_rps_park(struct intel_rps *rps)
{
- struct drm_i915_private *i915 = rps_to_i915(rps);
-
if (!intel_rps_clear_active(rps))
return;
- if (INTEL_GEN(i915) >= 6)
+ if (intel_rps_has_interrupts(rps))
rps_disable_interrupts(rps);
if (rps->last_freq <= rps->idle_freq)
@@ -838,7 +836,7 @@ int intel_rps_set(struct intel_rps *rps, u8 val)
* Make sure we continue to get interrupts
* until we hit the minimum or maximum frequencies.
*/
- if (INTEL_GEN(rps_to_i915(rps)) >= 6) {
+ if (intel_rps_has_interrupts(rps)) {
struct intel_uncore *uncore = rps_to_uncore(rps);
set(uncore,
@@ -1737,6 +1735,11 @@ void intel_rps_init(struct intel_rps *rps)
if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
+
+ if (INTEL_GEN(i915) >= 6) {
+ rps_disable_interrupts(rps);
+ intel_rps_set_interrupts(rps);
+ }
}
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index a01decf70f31..8276c4e9d78f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -66,4 +66,14 @@ static inline bool intel_rps_clear_active(struct intel_rps
*rps)
return test_and_clear_bit(INTEL_RPS_ACTIVE, >flags);
}
+static inline bool intel_rps_has_interrupts(const struct intel_rps *rps)
+{
+ return test_bit(INTEL_RPS_INTERRUPTS, >flags);
+}
+
+static inline void intel_rps_set_interrupts(struct intel_rps *rps)
+{
+ set_bit(INTEL_RPS_INTERRUPTS, >flags);
+}
+
#endif /* INTEL_RPS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_rps_types.h
b/drivers/gpu/drm/i915/gt/intel_rps_types.h
index 1ec44f994bc5..624e93108da4 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps_types.h
@@ -34,6 +34,7 @@ struct intel_rps_ei {
enum {
INTEL_RPS_ENABLED = 0,
INTEL_RPS_ACTIVE,
+ INTEL_RPS_INTERRUPTS,
};
struct intel_rps {
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index f47b59d5943c..1fcbffb8f3db 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -878,7 +878,7 @@ int live_rps_interrupt(void *arg)
* First, let's check whether or not we are receiving interrupts.
*/
- if (!intel_rps_is_enabled(rps))
+ if (!intel_rps_has_interrupts(rps))
return 0;
intel_gt_pm_get(gt);
--
2.20.1
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[Intel-gfx] [PATCH 5/6] drm/i915/gt: Apply the aggressive downclocking to parking
We treat parking as a manual RPS timeout event, and downclock the GPU
for the next unpark and batch execution. However, having restored the
aggressive downclocking and observed that we have very light workloads
whose only interaction is through the manual parking events, carry over
the aggressive downclocking to the fake RPS events.
References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 36e59b74689f..f6eec6e67a84 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -794,8 +794,6 @@ void intel_rps_unpark(struct intel_rps *rps)
rps->min_freq_softlimit,
rps->max_freq_softlimit));
- rps->last_adj = 0;
-
mutex_unlock(>lock);
rps->pm_iir = 0;
@@ -810,6 +808,8 @@ void intel_rps_unpark(struct intel_rps *rps)
void intel_rps_park(struct intel_rps *rps)
{
+ int adj;
+
if (!intel_rps_clear_active(rps))
return;
@@ -848,8 +848,13 @@ void intel_rps_park(struct intel_rps *rps)
* (Note we accommodate Cherryview's limitation of only using an
* even bin by applying it to all.)
*/
- rps->cur_freq =
- max_t(int, round_down(rps->cur_freq - 1, 2), rps->min_freq);
+ adj = rps->last_adj;
+ if (adj < 0)
+ adj *= 2;
+ else /* CHV needs even encode values */
+ adj = -2;
+ rps->last_adj = adj;
+ rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq);
GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq);
}
--
2.20.1
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[Intel-gfx] [PATCH 6/6] drm/i915/gt: Restore aggressive post-boost downclocking
We reduced the clocks slowly after a boost event based on the
observation that the smoothness of animations suffered. However, since
reducing the evalution intervals, we should be able to respond to the
rapidly fluctuating workload of a simple desktop animation and so
restore the more aggressive downclocking.
References: 2a8862d2f3da ("drm/i915: Reduce the RPS shock")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index f6eec6e67a84..0e1775c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1626,30 +1626,18 @@ static void rps_work(struct work_struct *work)
adj = 0;
}
- rps->last_adj = adj;
-
/*
-* Limit deboosting and boosting to keep ourselves at the extremes
-* when in the respective power modes (i.e. slowly decrease frequencies
-* while in the HIGH_POWER zone and slowly increase frequencies while
-* in the LOW_POWER zone). On idle, we will hit the timeout and drop
-* to the next level quickly, and conversely if busy we expect to
-* hit a waitboost and rapidly switch into max power.
-*/
- if ((adj < 0 && rps->power.mode == HIGH_POWER) ||
- (adj > 0 && rps->power.mode == LOW_POWER))
- rps->last_adj = 0;
-
- /* sysfs frequency interfaces may have snuck in while servicing the
-* interrupt
+* sysfs frequency limits may have snuck in while
+* servicing the interrupt
*/
new_freq += adj;
new_freq = clamp_t(int, new_freq, min, max);
if (intel_rps_set(rps, new_freq)) {
drm_dbg(>drm, "Failed to set new GPU frequency\n");
- rps->last_adj = 0;
+ adj = 0;
}
+ rps->last_adj = adj;
mutex_unlock(>lock);
--
2.20.1
___
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[Intel-gfx] [PATCH 1/6] drm/i915/gt: Always enable busy-stats for execlists
In the near future, we will utilize the busy-stats on each engine to
approximate the C0 cycles of each, and use that as an input to a manual
RPS mechanism. That entails having busy-stats always enabled and so we
can remove the enable/disable routines and simplify the pmu setup. As a
consequence of always having the stats enabled, we can also show the
current active time via sysfs/engine/xcs/active_time_ns.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 76 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 44 +++
drivers/gpu/drm/i915/gt/sysfs_engines.c | 16
drivers/gpu/drm/i915/i915_pmu.c | 32 +---
drivers/gpu/drm/i915/selftests/i915_request.c | 16 +---
7 files changed, 45 insertions(+), 171 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index d9ee64e2ef79..d10e52ff059f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -310,9 +310,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
struct drm_printer *m,
const char *header, ...);
-int intel_enable_engine_stats(struct intel_engine_cs *engine);
-void intel_disable_engine_stats(struct intel_engine_cs *engine);
-
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
struct i915_request *
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b1f8527f02c8..2c6b8a37c6e2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1589,58 +1589,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
intel_engine_print_breadcrumbs(engine, m);
}
-/**
- * intel_enable_engine_stats() - Enable engine busy tracking on engine
- * @engine: engine to enable stats collection
- *
- * Start collecting the engine busyness data for @engine.
- *
- * Returns 0 on success or a negative error code.
- */
-int intel_enable_engine_stats(struct intel_engine_cs *engine)
-{
- struct intel_engine_execlists *execlists = >execlists;
- unsigned long flags;
- int err = 0;
-
- if (!intel_engine_supports_stats(engine))
- return -ENODEV;
-
- execlists_active_lock_bh(execlists);
- write_seqlock_irqsave(>stats.lock, flags);
-
- if (unlikely(engine->stats.enabled == ~0)) {
- err = -EBUSY;
- goto unlock;
- }
-
- if (engine->stats.enabled++ == 0) {
- struct i915_request * const *port;
- struct i915_request *rq;
-
- engine->stats.enabled_at = ktime_get();
-
- /* XXX submission method oblivious? */
- for (port = execlists->active; (rq = *port); port++)
- engine->stats.active++;
-
- for (port = execlists->pending; (rq = *port); port++) {
- /* Exclude any contexts already counted in active */
- if (!intel_context_inflight_count(rq->context))
- engine->stats.active++;
- }
-
- if (engine->stats.active)
- engine->stats.start = engine->stats.enabled_at;
- }
-
-unlock:
- write_sequnlock_irqrestore(>stats.lock, flags);
- execlists_active_unlock_bh(execlists);
-
- return err;
-}
-
static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
{
ktime_t total = engine->stats.total;
@@ -1649,7 +1597,7 @@ static ktime_t __intel_engine_get_busy_time(struct
intel_engine_cs *engine)
* If the engine is executing something at the moment
* add it to the total.
*/
- if (engine->stats.active)
+ if (atomic_read(>stats.active))
total = ktime_add(total,
ktime_sub(ktime_get(), engine->stats.start));
@@ -1675,28 +1623,6 @@ ktime_t intel_engine_get_busy_time(struct
intel_engine_cs *engine)
return total;
}
-/**
- * intel_disable_engine_stats() - Disable engine busy tracking on engine
- * @engine: engine to disable stats collection
- *
- * Stops collecting the engine busyness data for @engine.
- */
-void intel_disable_engine_stats(struct intel_engine_cs *engine)
-{
- unsigned long flags;
-
- if (!intel_engine_supports_stats(engine))
- return;
-
- write_seqlock_irqsave(>stats.lock, flags);
- WARN_ON_ONCE(engine->stats.enabled == 0);
- if (--engine->stats.enabled == 0) {
- engine->stats.total = __intel_engine_get_busy_time(engine);
- engine->stats.active = 0;
- }
- write_sequnlock_irqrestore(>stats.lock, flags);
-}
-
static bool match_ring(struct i915_request *rq)
Re: [Intel-gfx] [PATCH 46/59] drm/arc: Align with simple pipe helpers
Hi Daniel.
On Wed, Apr 15, 2020 at 09:40:21AM +0200, Daniel Vetter wrote:
> Simple pipe helpers only have an enable and disable hook, no more
> mode_set_nofb. Call it from our enable hook to align with that
> conversions.
>
> Atomic helpers always call mode_set_nofb and enable together, so
> there's no functional change here.
Hmmm
mode_set_nofb() is only called from drm_atomic_helper - crtc_set_mode()
crtc_set_mode() is only called from drm_atomic_helper_commit_modeset_disables()
drm_atomic_helper_commit_modeset_disables() is called from
drm_atomic_helper_commit_tail()
So it seems you are right.
>
> Signed-off-by: Daniel Vetter
> Cc: Alexey Brodkin
Acked-by: Sam Ravnborg
> ---
> drivers/gpu/drm/arc/arcpgu_crtc.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c
> b/drivers/gpu/drm/arc/arcpgu_crtc.c
> index 72719556debb..c7769edeefdf 100644
> --- a/drivers/gpu/drm/arc/arcpgu_crtc.c
> +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
> @@ -73,10 +73,9 @@ static enum drm_mode_status arc_pgu_crtc_mode_valid(struct
> drm_crtc *crtc,
> return MODE_NOCLOCK;
> }
>
> -static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
> +static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu)
> {
> - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
> - struct drm_display_mode *m = >state->adjusted_mode;
> + struct drm_display_mode *m = >pipe.crtc.state->adjusted_mode;
> u32 val;
>
> arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
> @@ -110,7 +109,7 @@ static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc
> *crtc)
> arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
> arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
>
> - arc_pgu_set_pxl_fmt(crtc);
> + arc_pgu_set_pxl_fmt(>pipe.crtc);
>
> clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
> }
> @@ -120,6 +119,8 @@ static void arc_pgu_crtc_atomic_enable(struct drm_crtc
> *crtc,
> {
> struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
>
> + arc_pgu_mode_set(arcpgu);
> +
> clk_prepare_enable(arcpgu->clk);
> arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
> arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
> @@ -139,7 +140,6 @@ static void arc_pgu_crtc_atomic_disable(struct drm_crtc
> *crtc,
>
> static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
> .mode_valid = arc_pgu_crtc_mode_valid,
> - .mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
> .atomic_enable = arc_pgu_crtc_atomic_enable,
> .atomic_disable = arc_pgu_crtc_atomic_disable,
> };
> --
> 2.25.1
>
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Re: [Intel-gfx] [CI 1/2] drm/i915/selftests: Verify context isolation
> -Original Message-
> From: Intel-gfx On Behalf Of Chris
> Wilson
> Sent: Friday, April 24, 2020 1:33 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [CI 1/2] drm/i915/selftests: Verify context isolation
>
> No unprivileged context should ever be allowed to modify logical state that is
> visible to another; there should be no backchannels available or control
> leakage for malicious actors.
>
> This test tries to write to a set of random registers using non-privileged
> instructions (ala userspace). It should only be allowed to write into its
> context state, and all writes should not be visible to a second context. To
> verify this, we store the value of the register before writing to it in
> context A
> (as this should be the default value inherited from the golden context state)
> and do a read back from context B of the same register. The reads from both
> contexts should be identical, the default value, except for a few free running
> counters (either global or local).
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> .../drm/i915/gem/selftests/i915_gem_context.c | 441 ++
> 1 file changed, 441 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index f4f933240b39..c5c3433174dc 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -1865,6 +1865,446 @@ static int igt_vm_isolation(void *arg)
> return err;
> }
>
> +static struct i915_vma *create_vma(struct i915_address_space *vm,
> +size_t sz) {
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> +
> + obj = i915_gem_object_create_internal(vm->i915, sz);
> + if (IS_ERR(obj))
> + return ERR_CAST(obj);
> +
> + vma = i915_vma_instance(obj, vm, NULL);
> + if (IS_ERR(vma))
> + i915_gem_object_put(obj);
> +
> + return vma;
> +}
> +
> +struct iso_details {
> + unsigned long count;
> +};
> +
> +enum {
> + ISO_REG = 0,
> + ISO_POISON,
> + ISO_BEFORE,
> + ISO_AFTER,
> + __ISO__
> +};
> +
> +static int iso_write(struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct drm_i915_gem_object *obj,
> + const struct iso_details *iso,
> + u32 *ctl)
> +{
> + struct i915_vma *batch, *vma;
> + struct intel_context *ce;
> + struct i915_request *rq;
> + u32 *cs;
> + int err;
> + int i;
> +
> + ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
> + if (IS_ERR(ce))
> + return PTR_ERR(ce);
> +
> + batch = create_vma(ce->vm, PAGE_ALIGN(16 * iso->count + 4));
> + if (IS_ERR(batch)) {
> + err = PTR_ERR(batch);
> + goto err_ce;
> + }
> +
> + vma = i915_vma_instance(obj, ce->vm, NULL);
> + if (IS_ERR(vma)) {
> + err = PTR_ERR(vma);
> + goto err_batch;
> + }
> +
> + err = i915_vma_pin(batch, 0, 0, PIN_USER);
> + if (err)
> + goto err_batch;
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_USER);
> + if (err)
> + goto err_unpin_batch;
> +
> + cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
> + if (IS_ERR(cs)) {
> + err = PTR_ERR(cs);
> + goto err_vma;
> + }
> +
> + for (i = 0; i < iso->count; i++) {
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = ctl[i * __ISO__ + ISO_REG];
> + *cs++ = ctl[i * __ISO__ + ISO_POISON];
> + }
> + *cs++ = MI_BATCH_BUFFER_END;
> +
> + i915_gem_object_flush_map(batch->obj);
> + i915_gem_object_unpin_map(batch->obj);
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + goto err_vma;
> + }
> +
> + i915_vma_lock(vma);
> + err = i915_request_await_object(rq, vma->obj, true);
> + if (err == 0)
> + err = i915_vma_move_to_active(vma, rq,
> EXEC_OBJECT_WRITE);
> + i915_vma_unlock(vma);
> + if (err)
> + goto err_rq;
> +
> + i915_vma_lock(batch);
> + err = i915_request_await_object(rq, batch->obj, false);
> + if (err == 0)
> + err = i915_vma_move_to_active(batch, rq, 0);
> + i915_vma_unlock(batch);
> + if (err)
> + goto err_rq;
> +
> + err = engine->emit_bb_start(rq, batch->node.start, batch->node.size,
> +0);
> +
> +err_rq:
> + i915_request_add(rq);
> +err_vma:
> + i915_vma_unpin(vma);
> +err_unpin_batch:
> + i915_vma_unpin(batch);
> +err_batch:
> + i915_vma_put(batch);
> +err_ce:
> + intel_context_put(ce);
> + return err;
> +}
> +
> +static int iso_read(struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct drm_i915_gem_object *obj,
> +
