date:20240624

✓ Fi.CI.BAT: success for drm/i915/dsb: Use chained DSBs for LUT programming

2024-06-24 Thread Patchwork

== Series Details ==

Series: drm/i915/dsb: Use chained DSBs for LUT programming
URL   : https://patchwork.freedesktop.org/series/135316/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14996 -> Patchwork_135316v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135316v1/index.html

Participating hosts (40 -> 31)
--

  Missing(9): bat-kbl-2 fi-bsw-n3050 bat-adlp-6 fi-snb-2520m fi-glk-j4005 
fi-kbl-8809g fi-elk-e7500 bat-jsl-3 bat-arlh-2 

Known issues


  Here are the changes found in Patchwork_135316v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@requests:
- bat-atsm-1: [PASS][1] -> [INCOMPLETE][2] ([i915#11262])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14996/bat-atsm-1/igt@i915_selftest@l...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135316v1/bat-atsm-1/igt@i915_selftest@l...@requests.html

  
 Possible fixes 

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- {bat-mtlp-9}:   [SKIP][3] ([i915#10580]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14996/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135316v1/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html

  * igt@kms_flip@basic-flip-vs-dpms@b-dp7:
- {bat-mtlp-9}:   [FAIL][5] ([i915#6121]) -> [PASS][6] +8 other tests 
pass
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14996/bat-mtlp-9/igt@kms_flip@basic-flip-vs-d...@b-dp7.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135316v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-d...@b-dp7.html

  * igt@kms_flip@basic-plain-flip@d-dp6:
- {bat-mtlp-9}:   [DMESG-WARN][7] ([i915#11009]) -> [PASS][8] +4 other 
tests pass
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14996/bat-mtlp-9/igt@kms_flip@basic-plain-f...@d-dp6.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135316v1/bat-mtlp-9/igt@kms_flip@basic-plain-f...@d-dp6.html

  * igt@kms_frontbuffer_tracking@basic:
- bat-arls-2: [DMESG-WARN][9] ([i915#7507]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14996/bat-arls-2/igt@kms_frontbuffer_track...@basic.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135316v1/bat-arls-2/igt@kms_frontbuffer_track...@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
  [i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
  [i915#11262]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11262
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
  [i915#7507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7507


Build changes
-

  * Linux: CI_DRM_14996 -> Patchwork_135316v1

  CI-20190529: 20190529
  CI_DRM_14996: cf83cd8ff370955a504fdf1388ea6e257da76a8b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7898: a2600953b16d6628855b89ac40f477b58933b37b @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_135316v1: cf83cd8ff370955a504fdf1388ea6e257da76a8b @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135316v1/index.html

✗ Fi.CI.SPARSE: warning for drm/i915/dsb: Use chained DSBs for LUT programming

2024-06-24 Thread Patchwork

== Series Details ==

Series: drm/i915/dsb: Use chained DSBs for LUT programming
URL   : https://patchwork.freedesktop.org/series/135316/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsb: Use chained DSBs for LUT programming

2024-06-24 Thread Patchwork

== Series Details ==

Series: drm/i915/dsb: Use chained DSBs for LUT programming
URL   : https://patchwork.freedesktop.org/series/135316/
State : warning

== Summary ==

Error: dim checkpatch failed
5cc7f6d7e392 drm/i915: Calculate vblank delay more accurately
16f9c292de2d drm/i915: Make vrr_{enabling, disabling}() usable outside 
intel_display.c
4d3041f405be drm/i915/dsb: Hook up DSB error interrupts
f79c5f5e1805 drm/i915/dsb: Convert dewake_scanline to a hw scanline number 
earlier
4d233ad01435 drm/i915/dsb: Shuffle code around
518146bad5db drm/i915/dsb: Fix dewake scanline
9269d14b790c drm/i915/dsb: Account for VRR properly in DSB scanline stuff
c98ce409a8af drm/i915/dsb: Precompute DSB_CHICKEN
256916fbb9d0 drm/i915/dsb: Introduce intel_dsb_wait_scanline_{in, out}()
c45bb5ee10c1 drm/i915/dsb: Introduce intel_dsb_chain()
9b46ebf6c051 drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANK
c36156d44a11 drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is done
f4ca5fb76d0f drm/i915/dsb: s/dsb/dsb_color_vblank/
-:145: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#145: FILE: drivers/gpu/drm/i915/display/intel_display.c:7513:
+   old_crtc_state->dsb_color_vblank = 
fetch_and_zero(_crtc_state->dsb_color_vblank);

total: 0 errors, 1 warnings, 0 checks, 123 lines checked
d133ef40d55f drm/i915/dsb: Use chained DSBs for LUT programming
-:109: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#109: FILE: drivers/gpu/drm/i915/display/intel_display.c:7514:
+   old_crtc_state->dsb_color_commit = 
fetch_and_zero(_crtc_state->dsb_color_commit);

total: 0 errors, 1 warnings, 0 checks, 88 lines checked

RE: quadbuffer stereo

2024-06-24 Thread Deucher, Alexander

[Public]

Quadbuffer stereo is not supported on Linux.

Alex

From: amd-gfx  On Behalf Of adblover
Sent: Monday, June 24, 2024 6:53 AM
To: intel-gfx@lists.freedesktop.org; amd-...@lists.freedesktop.org
Subject: quadbuffer stereo

I have no idea how to enable quadbuffer stereo (hdmi-3d) on linux for intel and 
amdgpu.

I tried using Option Stereo 12 with this result
 (WW) AMDGPU(0): Option "Stereo" is not used

Hoping for solutions for both cards (intel arc,renoir)

thanks
--

#xorg.conf that I used
Section "ServerLayout"

Identifier "xserver"

Screen  0  "screen" 0 0

InputDevice"keyb"  "CoreKeyboard"

InputDevice"mouse"  "CorePointer"

EndSection



Section "ServerFlags"

Option "AllowMouseOpenFail"  "true"  # allows the server to start up 
even if the mouse does not work

#Option "DontVTSwitch""false" # allow switching between virtual 
terminal

# Option "DontZoom""true"  # disable 
/ (resolution switching)

EndSection



Section "Files"

#RgbPath  "/usr/X11R6/lib/X11/rgb"

#ModulePath   "/usr/X11R6/lib/modules"

# More information:  http://ftp.x.org/pub/X11R7.0/doc/html/fonts.html

FontPath "/usr/share/fonts/X11/misc"

FontPath "/usr/share/fonts/X11/100dpi/:unscaled"

FontPath "/usr/share/fonts/X11/75dpi/:unscaled"

FontPath "/usr/share/fonts/X11/Type1"

FontPath "/usr/share/fonts/X11/100dpi"

FontPath "/usr/share/fonts/X11/75dpi"

FontPath "/usr/X11R6/lib/X11/fonts/misc:unscaled"

FontPath "/usr/X11R6/lib/X11/fonts/misc"

FontPath "/usr/X11R6/lib/X11/fonts/75dpi:unscaled"

FontPath "/usr/X11R6/lib/X11/fonts/75dpi"

FontPath "/usr/X11R6/lib/X11/fonts/100dpi:unscaled"

FontPath "/usr/X11R6/lib/X11/fonts/100dpi"

# True type and type1 fonts are also handled via xftlib, see /etc/X11/XftConfig!

FontPath "/usr/X11R6/lib/X11/fonts/Type1"

FontPath "/usr/share/fonts/ttf/western"

FontPath "/usr/share/fonts/ttf/decoratives"

FontPath "/usr/share/fonts/truetype/ttf-bitstream-vera"

FontPath "/usr/share/fonts/latex-ttf-fonts"

FontPath "/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType"

EndSection



Section "Module"

Load  "dbe"   # double buffer extension

Load  "dri"   # direct rendering

Load  "glx"   # 3D layer

   Load "amdgpu"

   Load "modesetting"

   Load "glamoregl"

Load  "extmod"# some commonly used server extensions (e.g. shape 
extension)

Load  "record"# recording extension

Load  "evdev" # generic input handling driver on Linux

Load  "bitmap"# bitmap fonts

 Load  "ddc"   # ddc probing of monitor

 Load  "freetype"  # font rendering

EndSection



Section "InputDevice"

Identifier  "keyb"

Option  "CoreKeyboard"

Driver  "evdev"

Option  "XkbRules"   "xorg"

Option  "XkbModel"   "pc105"

Option  "XkbLayout"  "de"

#Option  "XkbOptions" "u"

EndSection





Section "InputDevice"

Identifier  "mouse"

Driver  "evdev"

#Option  "Device" "/dev/input/mice"

#Option  "ZAxisMapping"  "4 5"

#Option  "Buttons"   "5"

#Option  "SendCoreEvents""true"



EndSection





Section "Monitor"

Identifier   "sony"

Option   "DPMS"  "true"

#HorizSync31.0 - 61.0

#VertRefresh  50.0 - 90.0

EndSection



Section "Device"

Identifier  "card"

Driver  "amdgpu"

   Option "Stereo" "12"

EndSection



Section "Screen"

Identifier "screen"

Device "card"

Monitor"sony"



SubSection "Display"

Depth 24

Modes "1920x1080"

EndSubSection

SubSection "Display"

Depth 32

Modes "1920x1080"

EndSubSection

SubSection "Extensions"

   Option "Composite" "Disable"

EndSubSection



EndSection



# Make sure you have the relevant Debian packages on your system

# to be able to use DRI (libgl1-mesa-dri for example)

Section "DRI"

Mode 0666

EndSection

[PATCH 14/14] drm/i915/dsb: Use chained DSBs for LUT programming

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

In order to better handle the necessary DSB DEwake tricks let's
switch over to using a chained DSB for the actual LUT programming.
The CPU will start 'dsb_color_commit', which in turn will start the
chained 'dsb_color_vblank'.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_atomic.c   |  2 ++
 drivers/gpu/drm/i915/display/intel_color.c| 32 +++
 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 .../drm/i915/display/intel_display_types.h|  2 +-
 4 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c 
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 55ce71be41ec..12d6ed940751 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -277,6 +277,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
crtc_state->dsb_color_vblank = NULL;
+   crtc_state->dsb_color_commit = NULL;
 
return _state->uapi;
 }
@@ -311,6 +312,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 
drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank);
+   drm_WARN_ON(crtc->dev, crtc_state->dsb_color_commit);
 
__drm_atomic_helper_crtc_destroy_state(_state->uapi);
intel_crtc_free_hw_state(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index 27acbf92d60f..5d701f48351b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1890,8 +1890,8 @@ void intel_color_commit_arm(const struct intel_crtc_state 
*crtc_state)
 
i915->display.funcs.color->color_commit_arm(crtc_state);
 
-   if (crtc_state->dsb_color_vblank)
-   intel_dsb_commit(crtc_state->dsb_color_vblank, true);
+   if (crtc_state->dsb_color_commit)
+   intel_dsb_commit(crtc_state->dsb_color_commit, false);
 }
 
 void intel_color_post_update(const struct intel_crtc_state *crtc_state)
@@ -1919,26 +1919,44 @@ void intel_color_prepare_commit(struct 
intel_atomic_state *state,
if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
return;
 
-   crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, 
INTEL_DSB_0, 1024);
+   crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, 
INTEL_DSB_1, 1024);
if (!crtc_state->dsb_color_vblank)
return;
 
i915->display.funcs.color->load_luts(crtc_state);
 
intel_dsb_finish(crtc_state->dsb_color_vblank);
+
+   crtc_state->dsb_color_commit = intel_dsb_prepare(state, crtc, 
INTEL_DSB_0, 16);
+   if (!crtc_state->dsb_color_commit) {
+   intel_dsb_cleanup(crtc_state->dsb_color_vblank);
+   crtc_state->dsb_color_vblank = NULL;
+   return;
+   }
+
+   intel_dsb_chain(state, crtc_state->dsb_color_commit,
+   crtc_state->dsb_color_vblank, true);
+
+   intel_dsb_finish(crtc_state->dsb_color_commit);
 }
 
 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
 {
-   if (!crtc_state->dsb_color_vblank)
-   return;
+   if (crtc_state->dsb_color_commit) {
+   intel_dsb_cleanup(crtc_state->dsb_color_commit);
+   crtc_state->dsb_color_commit = NULL;
+   }
 
-   intel_dsb_cleanup(crtc_state->dsb_color_vblank);
-   crtc_state->dsb_color_vblank = NULL;
+   if (crtc_state->dsb_color_vblank) {
+   intel_dsb_cleanup(crtc_state->dsb_color_vblank);
+   crtc_state->dsb_color_vblank = NULL;
+   }
 }
 
 void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
 {
+   if (crtc_state->dsb_color_commit)
+   intel_dsb_wait(crtc_state->dsb_color_commit);
if (crtc_state->dsb_color_vblank)
intel_dsb_wait(crtc_state->dsb_color_vblank);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 05a2a6942000..d5e0fa5c78b5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7511,6 +7511,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
 * FIXME get rid of this funny new->old swapping
 */
old_crtc_state->dsb_color_vblank = 
fetch_and_zero(_crtc_state->dsb_color_vblank);
+   old_crtc_state->dsb_color_commit = 
fetch_and_zero(_crtc_state->dsb_color_commit);
}
 
/* Underruns don't always raise interrupts, so check manually */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bd079cd77bda..f22de0495dd7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h

[PATCH 13/14] drm/i915/dsb: s/dsb/dsb_color_vblank/

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

We'll soon utilize several DSBs during the commit. To that end
rename the current crtc_state->dsb to crtc_state->dsb_color_vblank
to better reflect its role (color managemnent stuff programmed during
vblank).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_atomic.c   |  4 +--
 drivers/gpu/drm/i915/display/intel_color.c| 36 +--
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_types.h|  4 +--
 4 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c 
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 76aa10b6f647..55ce71be41ec 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -276,7 +276,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->do_async_flip = false;
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
-   crtc_state->dsb = NULL;
+   crtc_state->dsb_color_vblank = NULL;
 
return _state->uapi;
 }
@@ -310,7 +310,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
 {
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 
-   drm_WARN_ON(crtc->dev, crtc_state->dsb);
+   drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank);
 
__drm_atomic_helper_crtc_destroy_state(_state->uapi);
intel_crtc_free_hw_state(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index 7ac50aacec73..27acbf92d60f 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1313,8 +1313,8 @@ static void ilk_lut_write(const struct intel_crtc_state 
*crtc_state,
 {
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-   if (crtc_state->dsb)
-   intel_dsb_reg_write(crtc_state->dsb, reg, val);
+   if (crtc_state->dsb_color_vblank)
+   intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val);
else
intel_de_write_fw(i915, reg, val);
 }
@@ -1337,15 +1337,15 @@ static void ilk_load_lut_8(const struct 
intel_crtc_state *crtc_state,
 * unless we either write each entry twice,
 * or use non-posted writes
 */
-   if (crtc_state->dsb)
-   intel_dsb_nonpost_start(crtc_state->dsb);
+   if (crtc_state->dsb_color_vblank)
+   intel_dsb_nonpost_start(crtc_state->dsb_color_vblank);
 
for (i = 0; i < 256; i++)
ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
  i9xx_lut_8([i]));
 
-   if (crtc_state->dsb)
-   intel_dsb_nonpost_end(crtc_state->dsb);
+   if (crtc_state->dsb_color_vblank)
+   intel_dsb_nonpost_end(crtc_state->dsb_color_vblank);
 }
 
 static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
@@ -1870,7 +1870,7 @@ void intel_color_load_luts(const struct intel_crtc_state 
*crtc_state)
 {
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-   if (crtc_state->dsb)
+   if (crtc_state->dsb_color_vblank)
return;
 
i915->display.funcs.color->load_luts(crtc_state);
@@ -1890,8 +1890,8 @@ void intel_color_commit_arm(const struct intel_crtc_state 
*crtc_state)
 
i915->display.funcs.color->color_commit_arm(crtc_state);
 
-   if (crtc_state->dsb)
-   intel_dsb_commit(crtc_state->dsb, true);
+   if (crtc_state->dsb_color_vblank)
+   intel_dsb_commit(crtc_state->dsb_color_vblank, true);
 }
 
 void intel_color_post_update(const struct intel_crtc_state *crtc_state)
@@ -1919,33 +1919,33 @@ void intel_color_prepare_commit(struct 
intel_atomic_state *state,
if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
return;
 
-   crtc_state->dsb = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024);
-   if (!crtc_state->dsb)
+   crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, 
INTEL_DSB_0, 1024);
+   if (!crtc_state->dsb_color_vblank)
return;
 
i915->display.funcs.color->load_luts(crtc_state);
 
-   intel_dsb_finish(crtc_state->dsb);
+   intel_dsb_finish(crtc_state->dsb_color_vblank);
 }
 
 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
 {
-   if (!crtc_state->dsb)
+   if (!crtc_state->dsb_color_vblank)
return;
 
-   intel_dsb_cleanup(crtc_state->dsb);
-   crtc_state->dsb = NULL;
+   intel_dsb_cleanup(crtc_state->dsb_color_vblank);
+   crtc_state->dsb_color_vblank = NULL;
 }
 
 void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
 {
-   if (crtc_state->dsb)
-   intel_dsb_wait(crtc_state->dsb);
+   if (crtc_state->dsb_color_vblank)
+   intel_dsb_wait(crtc_state->dsb_color_vblank);
 }
 
 bool

[PATCH 10/14] drm/i915/dsb: Introduce intel_dsb_chain()

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

In order to handle the DEwake tricks without involving
the CPU we need a mechanism by which one DSB can start
another one. Add a basic function to do so. We'll extend
it later with additional code to actually deal with
DEwake.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 42 
 drivers/gpu/drm/i915/display/intel_dsb.h |  3 ++
 2 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 092cf082ac39..4c0519c41f16 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -502,6 +502,48 @@ static u32 dsb_error_int_en(struct intel_display *display)
return errors;
 }
 
+static void _intel_dsb_chain(struct intel_atomic_state *state,
+struct intel_dsb *dsb,
+struct intel_dsb *chained_dsb,
+u32 ctrl)
+{
+   struct intel_display *display = to_intel_display(state->base.dev);
+   struct intel_crtc *crtc = dsb->crtc;
+   enum pipe pipe = crtc->pipe;
+   u32 tail;
+
+   if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))
+   return;
+
+   tail = chained_dsb->free_pos * 4;
+   if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES)))
+   return;
+
+   intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id),
+   ctrl | DSB_ENABLE);
+
+   intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id),
+   dsb_chicken(state, crtc));
+
+   intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id),
+   dsb_error_int_status(display) | DSB_PROG_INT_STATUS 
|
+   dsb_error_int_en(display));
+
+   intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id),
+   
intel_dsb_buffer_ggtt_offset(_dsb->dsb_buf));
+
+   intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id),
+   intel_dsb_buffer_ggtt_offset(_dsb->dsb_buf) 
+ tail);
+}
+
+void intel_dsb_chain(struct intel_atomic_state *state,
+struct intel_dsb *dsb,
+struct intel_dsb *chained_dsb)
+{
+   _intel_dsb_chain(state, dsb, chained_dsb,
+0);
+}
+
 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
  int hw_dewake_scanline)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h 
b/drivers/gpu/drm/i915/display/intel_dsb.h
index d0737cefb393..e59fd7da0fc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -45,6 +45,9 @@ void intel_dsb_wait_scanline_in(struct intel_atomic_state 
*state,
 void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
 struct intel_dsb *dsb,
 int lower, int upper);
+void intel_dsb_chain(struct intel_atomic_state *state,
+struct intel_dsb *dsb,
+struct intel_dsb *chained_dsb);
 
 void intel_dsb_commit(struct intel_dsb *dsb,
  bool wait_for_vblank);
-- 
2.44.2

[PATCH 12/14] drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is done

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

In order to avoid the DSB keeping the DEwake permanently
asserted we must clear DSB_PMCTRL_2.DSB_FORCE_DEWAKE once
we are done. For good measure do the same for
DSB_PMCTRL.DSB_ENABLE_DEWAKE.

Experimentally this doens't seem to be actually necessary
(unlike with DSB_FORCE_DEWAKE). That is, the DSB_ENABLE_DEWAKE
doesn't seem to do anything whenever the DSB is not active.
But I'd hate to waste a ton of power in case there I'm wrong
and there is some way DEwake could remaing asserted. One extra
register write is a small price to pay for some peace of mind.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index cf710f0bf430..fad37e7856b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -464,8 +464,10 @@ void intel_dsb_finish(struct intel_dsb *dsb)
/*
 * DSB_FORCE_DEWAKE remains active even after DSB is
 * disabled, so make sure to clear it (if set during
-* intel_dsb_commit()).
+* intel_dsb_commit()). And clear DSB_ENABLE_DEWAKE as
+* well for good measure.
 */
+   intel_dsb_reg_write(dsb, DSB_PMCTRL(crtc->pipe, dsb->id), 0);
intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id),
   DSB_FORCE_DEWAKE, 0);
 
-- 
2.44.2

[PATCH 11/14] drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANK

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Allow intel_dsb_chain() to start the chained DSB
at start of the undelaye vblank. This is slightly
more involved than simply setting the bit as we
must use the DEwake mechanism to eliminate pkgC
latency.

And DSB_ENABLE_DEWAKE itself is problematic in that
it allows us to configure just a single scanline,
and if the current scanline is already past that
DSB_ENABLE_DEWAKE won't do anything, rendering the
whole thing moot.

The current workaround involves checking the pipe's current
scanline with the CPU, and if it looks like we're about to
miss the configured DEwake scanline we set DSB_FORCE_DEWAKE
to immediately assert DEwake. This is somewhat racy since the
hardware is making progress all the while we're checking it on
the CPU.

We can make things less racy by chaining two DSBs and handling
the DSB_FORCE_DEWAKE stuff entirely without CPU involvement:
1. CPU starts the first DSB immediately
2. First DSB configures the second DSB, including its dewake_scanline
3. First DSB starts the second w/ DSB_WAIT_FOR_VBLANK
4. First DSB asserts DSB_FORCE_DEWAKE
5. First DSB waits until we're outside the dewake_scanline-vblank_start
   window
6. First DSB deasserts DSB_FORCE_DEWAKE

That will guarantee that the we are fully awake when the second
DSB starts to actually execute.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 43 +---
 drivers/gpu/drm/i915/display/intel_dsb.h |  3 +-
 2 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 4c0519c41f16..cf710f0bf430 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -130,8 +130,8 @@ static int dsb_vtotal(struct intel_atomic_state *state,
return intel_mode_vtotal(_state->hw.adjusted_mode);
 }
 
-static int dsb_dewake_scanline(struct intel_atomic_state *state,
-  struct intel_crtc *crtc)
+static int dsb_dewake_scanline_start(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
 {
const struct intel_crtc_state *crtc_state = 
pre_commit_crtc_state(state, crtc);
struct drm_i915_private *i915 = to_i915(state->base.dev);
@@ -141,6 +141,14 @@ static int dsb_dewake_scanline(struct intel_atomic_state 
*state,
intel_usecs_to_scanlines(_state->hw.adjusted_mode, 
latency);
 }
 
+static int dsb_dewake_scanline_end(struct intel_atomic_state *state,
+  struct intel_crtc *crtc)
+{
+   const struct intel_crtc_state *crtc_state = 
pre_commit_crtc_state(state, crtc);
+
+   return intel_mode_vdisplay(_state->hw.adjusted_mode);
+}
+
 static int dsb_scanline_to_hw(struct intel_atomic_state *state,
  struct intel_crtc *crtc, int scanline)
 {
@@ -529,19 +537,44 @@ static void _intel_dsb_chain(struct intel_atomic_state 
*state,
dsb_error_int_status(display) | DSB_PROG_INT_STATUS 
|
dsb_error_int_en(display));
 
+   if (ctrl & DSB_WAIT_FOR_VBLANK) {
+   int dewake_scanline = dsb_dewake_scanline_start(state, crtc);
+   int hw_dewake_scanline = dsb_scanline_to_hw(state, crtc, 
dewake_scanline);
+
+   intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id),
+   DSB_ENABLE_DEWAKE |
+   
DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline));
+   }
+
intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id),

intel_dsb_buffer_ggtt_offset(_dsb->dsb_buf));
 
intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id),
intel_dsb_buffer_ggtt_offset(_dsb->dsb_buf) 
+ tail);
+
+   if (ctrl & DSB_WAIT_FOR_VBLANK) {
+   /*
+* Keep DEwake alive via the first DSB, in
+* case we're already past dewake_scanline,
+* and thus DSB_ENABLE_DEWAKE on the second
+* DSB won't do its job.
+*/
+   intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(pipe, dsb->id),
+  DSB_FORCE_DEWAKE, DSB_FORCE_DEWAKE);
+
+   intel_dsb_wait_scanline_out(state, dsb,
+   dsb_dewake_scanline_start(state, 
crtc),
+   dsb_dewake_scanline_end(state, 
crtc));
+   }
 }
 
 void intel_dsb_chain(struct intel_atomic_state *state,
 struct intel_dsb *dsb,
-struct intel_dsb *chained_dsb)
+struct intel_dsb *chained_dsb,
+bool wait_for_vblank)
 {
_intel_dsb_chain(state, dsb, chained_dsb,
-0);
+wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
 }
 
 static void

[PATCH 09/14] drm/i915/dsb: Introduce intel_dsb_wait_scanline_{in, out}()

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Add functions to emit a DSB scanline window wait instructions.
We can either wait for the scanline to be IN the window
or OUT of the window.

The hardware doesn't handle wraparound so we must manually
deal with it by swapping the IN range to the inverse OUT
range, or vice versa.

Also add a bit of paranoia to catch the edge case of waiting
for the entire frame. That doesn't make sense since an IN
wait would be a nop, and an OUT wait would imply waiting
forever. Most of the time this also results in both scanline
ranges (original and inverted) to have lower=upper+1
which is nonsense from the hw POV.

For now we are only handling the case where the scanline wait
happens prior to latching the double buffered registers during
the commit (which might change the timings due to LRR/VRR/etc.)

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 73 
 drivers/gpu/drm/i915/display/intel_dsb.h |  6 ++
 2 files changed, 79 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 81937908c798..092cf082ac39 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -362,6 +362,79 @@ void intel_dsb_nonpost_end(struct intel_dsb *dsb)
intel_dsb_noop(dsb, 4);
 }
 
+static void intel_dsb_emit_wait_dsl(struct intel_dsb *dsb,
+   u32 opcode, int lower, int upper)
+{
+   u64 window = ((u64)upper << DSB_SCANLINE_UPPER_SHIFT) |
+   ((u64)lower << DSB_SCANLINE_LOWER_SHIFT);
+
+   intel_dsb_emit(dsb, lower_32_bits(window),
+  (opcode << DSB_OPCODE_SHIFT) |
+  upper_32_bits(window));
+}
+
+static void intel_dsb_wait_dsl(struct intel_atomic_state *state,
+  struct intel_dsb *dsb,
+  int lower_in, int upper_in,
+  int lower_out, int upper_out)
+{
+   struct intel_crtc *crtc = dsb->crtc;
+
+   lower_in = dsb_scanline_to_hw(state, crtc, lower_in);
+   upper_in = dsb_scanline_to_hw(state, crtc, upper_in);
+
+   lower_out = dsb_scanline_to_hw(state, crtc, lower_out);
+   upper_out = dsb_scanline_to_hw(state, crtc, upper_out);
+
+   if (upper_in >= lower_in)
+   intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_IN,
+   lower_in, upper_in);
+   else if (upper_out >= lower_out)
+   intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT,
+   lower_out, upper_out);
+   else
+   drm_WARN_ON(crtc->base.dev, 1); /* assert_dsl_ok() should have 
caught it already */
+}
+
+static void assert_dsl_ok(struct intel_atomic_state *state,
+ struct intel_dsb *dsb,
+ int start, int end)
+{
+   struct intel_crtc *crtc = dsb->crtc;
+   int vtotal = dsb_vtotal(state, crtc);
+
+   /*
+* Waiting for the entire frame doesn't make sense,
+* (IN==don't wait, OUT=wait forever).
+*/
+   drm_WARN(crtc->base.dev, (end - start + vtotal) % vtotal == vtotal - 1,
+"[CRTC:%d:%s] DSB %d bad scanline window wait: %d-%d 
(vt=%d)\n",
+crtc->base.base.id, crtc->base.name, dsb->id,
+start, end, vtotal);
+}
+
+void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
+   struct intel_dsb *dsb,
+   int start, int end)
+{
+   assert_dsl_ok(state, dsb, start, end);
+
+   intel_dsb_wait_dsl(state, dsb,
+  start, end,
+  end + 1, start - 1);
+}
+
+void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
+struct intel_dsb *dsb,
+int start, int end)
+{
+   assert_dsl_ok(state, dsb, start, end);
+
+   intel_dsb_wait_dsl(state, dsb,
+  end + 1, start - 1,
+  start, end);
+}
+
 static void intel_dsb_align_tail(struct intel_dsb *dsb)
 {
u32 aligned_tail, tail;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h 
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 84fc2f8434d1..d0737cefb393 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -39,6 +39,12 @@ void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
 void intel_dsb_noop(struct intel_dsb *dsb, int count);
 void intel_dsb_nonpost_start(struct intel_dsb *dsb);
 void intel_dsb_nonpost_end(struct intel_dsb *dsb);
+void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
+   struct intel_dsb *dsb,
+   int lower, int upper);
+void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
+struct intel_dsb *dsb,
+

[PATCH 06/14] drm/i915/dsb: Fix dewake scanline

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Currently we calculate the DEwake scanline based on
the delayed vblank start, while in reality it should be computed
based on the undelayed vblank start (as that is where the DSB
actually starts). Currently it doesn't really matter as we
don't have any vblank delay configured, but that may change
in the future so let's be accurate in what we do.

We can also remove the max() as intel_crtc_scanline_to_hw()
can deal with negative numbers, which there really shouldn't
be anyway.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index d3e5e5263603..e871af5517b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -86,16 +86,10 @@ struct intel_dsb {
 static int dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-   const struct drm_display_mode *adjusted_mode = 
_state->hw.adjusted_mode;
unsigned int latency = skl_watermark_max_latency(i915, 0);
-   int vblank_start;
 
-   if (crtc_state->vrr.enable)
-   vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-   else
-   vblank_start = intel_mode_vblank_start(adjusted_mode);
-
-   return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, 
latency));
+   return intel_mode_vdisplay(_state->hw.adjusted_mode) -
+   intel_usecs_to_scanlines(_state->hw.adjusted_mode, 
latency);
 }
 
 static u32 dsb_chicken(struct intel_crtc *crtc)
-- 
2.44.2

[PATCH 08/14] drm/i915/dsb: Precompute DSB_CHICKEN

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Adjust the code that determines the correct DSB_CHICKEN value
to be usable for use within DSB commands themselves. Ie.
precompute it based on our knowledge of what the hardware state
(VRR vs. not mainly) will be at the time of the commit.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b362a3050c7f..81937908c798 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -43,6 +43,7 @@ struct intel_dsb {
 */
unsigned int ins_start_offset;
 
+   u32 chicken;
int hw_dewake_scanline;
 };
 
@@ -149,9 +150,10 @@ static int dsb_scanline_to_hw(struct intel_atomic_state 
*state,
return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % 
vtotal;
 }
 
-static u32 dsb_chicken(struct intel_crtc *crtc)
+static u32 dsb_chicken(struct intel_atomic_state *state,
+  struct intel_crtc *crtc)
 {
-   if (crtc->mode_flags & I915_MODE_FLAG_VRR)
+   if (pre_commit_is_vrr_active(state, crtc))
return DSB_SKIP_WAITS_EN |
DSB_CTRL_WAIT_SAFE_WINDOW |
DSB_CTRL_NO_WAIT_VBLANK |
@@ -449,7 +451,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 
ctrl,
  ctrl | DSB_ENABLE);
 
intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id),
- dsb_chicken(crtc));
+ dsb->chicken);
 
intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
  dsb_error_int_status(display) | DSB_PROG_INT_STATUS |
@@ -580,6 +582,7 @@ struct intel_dsb *intel_dsb_prepare(struct 
intel_atomic_state *state,
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
 
+   dsb->chicken = dsb_chicken(state, crtc);
dsb->hw_dewake_scanline =
dsb_scanline_to_hw(state, crtc, dsb_dewake_scanline(state, 
crtc));
 
-- 
2.44.2

[PATCH 07/14] drm/i915/dsb: Account for VRR properly in DSB scanline stuff

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

When determining various scanlines for DSB use we should take into
account whether VRR is active at the time when the DSB uses said
scanline information. For now all DSB scanline usage occurs prior
to the actual commit, so we only need to care about the state of
VRR at that time.

I've decided to move intel_crtc_scanline_to_hw() in its entirety
to the DSB code as it will also need to know the actual state
of VRR in order to do its job 100% correctly.

TODO: figure out how much of this could be moved to some
  more generic place and perhaps be shared with the CPU
  vblank evasion code/etc...

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c |  4 +-
 drivers/gpu/drm/i915/display/intel_display.h |  3 +
 drivers/gpu/drm/i915/display/intel_dsb.c | 65 ++--
 drivers/gpu/drm/i915/display/intel_vblank.c  | 10 +--
 drivers/gpu/drm/i915/display/intel_vblank.h  |  3 +-
 5 files changed, 67 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 01a5faa3fea5..592483651b3c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1031,8 +1031,8 @@ static bool intel_crtc_vrr_enabling(struct 
intel_atomic_state *state,
  vrr_params_changed(old_crtc_state, new_crtc_state)));
 }
 
-static bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
-struct intel_crtc *crtc)
+bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
 {
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index b0cf6ca70952..b21d9578d5db 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -532,6 +532,9 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state 
*crtc_state);
 
 void intel_update_watermarks(struct drm_i915_private *i915);
 
+bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+
 /* modesetting */
 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
  const char *reason, u8 pipe_mask);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index e871af5517b5..b362a3050c7f 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -83,15 +83,72 @@ struct intel_dsb {
 #define DSB_OPCODE_POLL0xA
 /* see DSB_REG_VALUE_MASK */
 
-static int dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)
+static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
 {
-   struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+   const struct intel_crtc_state *old_crtc_state =
+   intel_atomic_get_old_crtc_state(state, crtc);
+   const struct intel_crtc_state *new_crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+
+   /* VRR will be enabled afterwards, if necessary */
+   if (intel_crtc_needs_modeset(new_crtc_state))
+   return false;
+
+   /* VRR will have been disabled during intel_pre_plane_update() */
+   return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, 
crtc);
+}
+
+static const struct intel_crtc_state *
+pre_commit_crtc_state(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+   const struct intel_crtc_state *old_crtc_state =
+   intel_atomic_get_old_crtc_state(state, crtc);
+   const struct intel_crtc_state *new_crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+
+   /*
+* During fastsets/etc. the transcoder is still
+* running with the old timings at this point.
+*/
+   if (intel_crtc_needs_modeset(new_crtc_state))
+   return new_crtc_state;
+   else
+   return old_crtc_state;
+}
+
+static int dsb_vtotal(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+   const struct intel_crtc_state *crtc_state = 
pre_commit_crtc_state(state, crtc);
+
+   if (pre_commit_is_vrr_active(state, crtc))
+   return crtc_state->vrr.vmax;
+   else
+   return intel_mode_vtotal(_state->hw.adjusted_mode);
+}
+
+static int dsb_dewake_scanline(struct intel_atomic_state *state,
+  struct intel_crtc *crtc)
+{
+   const struct intel_crtc_state *crtc_state = 
pre_commit_crtc_state(state, crtc);
+   struct drm_i915_private *i915 =

[PATCH 04/14] drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlier

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Currently we switch from out software idea of a scanline
to the hw's idea of a scanline during the commit phase in
_intel_dsb_commit(). While that is slightly easier due to
fastsets fiddling with the timings, we'll also need to
generate proper hw scanline numbers already when emitting
DSB scanline wait instructions. So this approach won't
do in the future. Switch to hw scanline numbers earlier.

Also intel_dsb_dewake_scanline() itself already makes
some assumptions about VRR that don't take into account
VRR toggling during fastsets, so technically delaying
the sw->hw conversion doesn't even help us.

The other reason for delaying the conversion was that we
are using intel_get_crtc_scanline() during intel_dsb_commit()
which gives us the current sw scanline. But this is pretty
low level stuff anyway so just using raw PIPEDSL reads seems
fine here, and that of course gives us the hw scanline
directly, reducing the need to do so many conversions.

v2: Return the non-hw scanline from intel_dsb_dewake_scanline()

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dsb.c| 21 -
 drivers/gpu/drm/i915/display/intel_vblank.c |  9 -
 drivers/gpu/drm/i915/display/intel_vblank.h |  3 ++-
 3 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index ded696363258..cee33c66a26b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -6,6 +6,7 @@
 
 #include "i915_drv.h"
 #include "i915_irq.h"
+#include "i915_reg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
@@ -42,7 +43,7 @@ struct intel_dsb {
 */
unsigned int ins_start_offset;
 
-   int dewake_scanline;
+   int hw_dewake_scanline;
 };
 
 /**
@@ -376,7 +377,7 @@ static u32 dsb_error_int_en(struct intel_display *display)
 }
 
 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
- int dewake_scanline)
+ int hw_dewake_scanline)
 {
struct intel_crtc *crtc = dsb->crtc;
struct intel_display *display = to_intel_display(crtc->base.dev);
@@ -406,10 +407,8 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 
ctrl,
intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),
  intel_dsb_buffer_ggtt_offset(>dsb_buf));
 
-   if (dewake_scanline >= 0) {
-   int diff, hw_dewake_scanline;
-
-   hw_dewake_scanline = intel_crtc_scanline_to_hw(crtc, 
dewake_scanline);
+   if (hw_dewake_scanline >= 0) {
+   int diff, position;
 
intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id),
  DSB_ENABLE_DEWAKE |
@@ -419,7 +418,9 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 
ctrl,
 * Force DEwake immediately if we're already past
 * or close to racing past the target scanline.
 */
-   diff = dewake_scanline - intel_get_crtc_scanline(crtc);
+   position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & 
PIPEDSL_LINE_MASK;
+
+   diff = hw_dewake_scanline - position;
intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id),
  (diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE : 
0) |
  DSB_BLOCK_DEWAKE_EXTENSION);
@@ -441,7 +442,7 @@ void intel_dsb_commit(struct intel_dsb *dsb,
 {
_intel_dsb_commit(dsb,
  wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0,
- wait_for_vblank ? dsb->dewake_scanline : -1);
+ wait_for_vblank ? dsb->hw_dewake_scanline : -1);
 }
 
 void intel_dsb_wait(struct intel_dsb *dsb)
@@ -529,7 +530,9 @@ struct intel_dsb *intel_dsb_prepare(struct 
intel_atomic_state *state,
dsb->size = size / 4; /* in dwords */
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
-   dsb->dewake_scanline = intel_dsb_dewake_scanline(crtc_state);
+
+   dsb->hw_dewake_scanline =
+   intel_crtc_scanline_to_hw(crtc_state, 
intel_dsb_dewake_scanline(crtc_state));
 
return dsb;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c 
b/drivers/gpu/drm/i915/display/intel_vblank.c
index f183e0d4b2ba..56c8033eec4c 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -284,13 +284,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc 
*crtc)
return (position + vtotal + crtc->scanline_offset) % vtotal;
 }
 
-int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
+int intel_crtc_scanline_to_hw(const struct intel_crtc_state *crtc_state,
+ int scanline)
 {
-   const struct drm_vblank_crtc *vblank =

[PATCH 05/14] drm/i915/dsb: Shuffle code around

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Relocate intel_dsb_dewake_scanline() and dsb_chicken() upwards
in the file. I need to reuse these while emitting DSB
commands, and I'd like to keep the DSB command emission
stuff more or less grouped together in the file.

Also drop the intel_ prefix from intel_dsb_dewake_scanline() since
it's all internal stuff and thus doesn't need so much namespacing.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 56 
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index cee33c66a26b..d3e5e5263603 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -83,6 +83,33 @@ struct intel_dsb {
 #define DSB_OPCODE_POLL0xA
 /* see DSB_REG_VALUE_MASK */
 
+static int dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+   const struct drm_display_mode *adjusted_mode = 
_state->hw.adjusted_mode;
+   unsigned int latency = skl_watermark_max_latency(i915, 0);
+   int vblank_start;
+
+   if (crtc_state->vrr.enable)
+   vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
+   else
+   vblank_start = intel_mode_vblank_start(adjusted_mode);
+
+   return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, 
latency));
+}
+
+static u32 dsb_chicken(struct intel_crtc *crtc)
+{
+   if (crtc->mode_flags & I915_MODE_FLAG_VRR)
+   return DSB_SKIP_WAITS_EN |
+   DSB_CTRL_WAIT_SAFE_WINDOW |
+   DSB_CTRL_NO_WAIT_VBLANK |
+   DSB_INST_WAIT_SAFE_WINDOW |
+   DSB_INST_NO_WAIT_VBLANK;
+   else
+   return DSB_SKIP_WAITS_EN;
+}
+
 static bool assert_dsb_has_room(struct intel_dsb *dsb)
 {
struct intel_crtc *crtc = dsb->crtc;
@@ -313,33 +340,6 @@ void intel_dsb_finish(struct intel_dsb *dsb)
intel_dsb_buffer_flush_map(>dsb_buf);
 }
 
-static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)
-{
-   struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-   const struct drm_display_mode *adjusted_mode = 
_state->hw.adjusted_mode;
-   unsigned int latency = skl_watermark_max_latency(i915, 0);
-   int vblank_start;
-
-   if (crtc_state->vrr.enable)
-   vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-   else
-   vblank_start = intel_mode_vblank_start(adjusted_mode);
-
-   return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, 
latency));
-}
-
-static u32 dsb_chicken(struct intel_crtc *crtc)
-{
-   if (crtc->mode_flags & I915_MODE_FLAG_VRR)
-   return DSB_SKIP_WAITS_EN |
-   DSB_CTRL_WAIT_SAFE_WINDOW |
-   DSB_CTRL_NO_WAIT_VBLANK |
-   DSB_INST_WAIT_SAFE_WINDOW |
-   DSB_INST_NO_WAIT_VBLANK;
-   else
-   return DSB_SKIP_WAITS_EN;
-}
-
 static u32 dsb_error_int_status(struct intel_display *display)
 {
struct drm_i915_private *i915 = to_i915(display->drm);
@@ -532,7 +532,7 @@ struct intel_dsb *intel_dsb_prepare(struct 
intel_atomic_state *state,
dsb->ins_start_offset = 0;
 
dsb->hw_dewake_scanline =
-   intel_crtc_scanline_to_hw(crtc_state, 
intel_dsb_dewake_scanline(crtc_state));
+   intel_crtc_scanline_to_hw(crtc_state, 
dsb_dewake_scanline(crtc_state));
 
return dsb;
 
-- 
2.44.2

[PATCH 03/14] drm/i915/dsb: Hook up DSB error interrupts

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Enable all DSB error/fault interrupts so that we can see if
anything goes terribly wrong.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 17 ++
 drivers/gpu/drm/i915/display/intel_dsb.c  | 58 +++
 drivers/gpu/drm/i915/display/intel_dsb.h  |  6 ++
 drivers/gpu/drm/i915/i915_reg.h   |  4 ++
 4 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 5219ba295c74..7169db984651 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -14,6 +14,7 @@
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
 #include "intel_dp_aux.h"
+#include "intel_dsb.h"
 #include "intel_fdi_regs.h"
 #include "intel_fifo_underrun.h"
 #include "intel_gmbus.h"
@@ -1143,6 +1144,17 @@ void gen8_de_irq_handler(struct drm_i915_private 
*dev_priv, u32 master_ctl)
 
intel_uncore_write(_priv->uncore, GEN8_DE_PIPE_IIR(pipe), 
iir);
 
+   if (HAS_DSB(dev_priv)) {
+   if (iir & GEN12_DSB_INT(INTEL_DSB_0))
+   intel_dsb_irq_handler(_priv->display, pipe, 
INTEL_DSB_0);
+
+   if (iir & GEN12_DSB_INT(INTEL_DSB_1))
+   intel_dsb_irq_handler(_priv->display, pipe, 
INTEL_DSB_1);
+
+   if (iir & GEN12_DSB_INT(INTEL_DSB_2))
+   intel_dsb_irq_handler(_priv->display, pipe, 
INTEL_DSB_2);
+   }
+
if (iir & GEN8_PIPE_VBLANK)
intel_handle_vblank(dev_priv, pipe);
 
@@ -1718,6 +1730,11 @@ void gen8_de_irq_postinstall(struct drm_i915_private 
*dev_priv)
de_port_masked |= DSI0_TE | DSI1_TE;
}
 
+   if (HAS_DSB(dev_priv))
+   de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) |
+   GEN12_DSB_INT(INTEL_DSB_1) |
+   GEN12_DSB_INT(INTEL_DSB_2);
+
de_pipe_enables = de_pipe_masked |
GEN8_PIPE_VBLANK |
gen8_de_pipe_underrun_mask(dev_priv) |
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2ab3765f6c06..ded696363258 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -339,6 +339,42 @@ static u32 dsb_chicken(struct intel_crtc *crtc)
return DSB_SKIP_WAITS_EN;
 }
 
+static u32 dsb_error_int_status(struct intel_display *display)
+{
+   struct drm_i915_private *i915 = to_i915(display->drm);
+   u32 errors;
+
+   errors = DSB_GTT_FAULT_INT_STATUS |
+   DSB_RSPTIMEOUT_INT_STATUS |
+   DSB_POLL_ERR_INT_STATUS;
+
+   /*
+* All the non-existing status bits operate as
+* normal r/w bits, so any attempt to clear them
+* will just end up setting them. Never do that so
+* we won't mistake them for actual error interrupts.
+*/
+   if (DISPLAY_VER(i915) >= 14)
+   errors |= DSB_ATS_FAULT_INT_STATUS;
+
+   return errors;
+}
+
+static u32 dsb_error_int_en(struct intel_display *display)
+{
+   struct drm_i915_private *i915 = to_i915(display->drm);
+   u32 errors;
+
+   errors = DSB_GTT_FAULT_INT_EN |
+   DSB_RSPTIMEOUT_INT_EN |
+   DSB_POLL_ERR_INT_EN;
+
+   if (DISPLAY_VER(i915) >= 14)
+   errors |= DSB_ATS_FAULT_INT_EN;
+
+   return errors;
+}
+
 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
  int dewake_scanline)
 {
@@ -363,6 +399,10 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 
ctrl,
intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id),
  dsb_chicken(crtc));
 
+   intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
+ dsb_error_int_status(display) | DSB_PROG_INT_STATUS |
+ dsb_error_int_en(display));
+
intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),
  intel_dsb_buffer_ggtt_offset(>dsb_buf));
 
@@ -430,6 +470,9 @@ void intel_dsb_wait(struct intel_dsb *dsb)
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0);
+
+   intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
+ dsb_error_int_status(display) | DSB_PROG_INT_STATUS);
 }
 
 /**
@@ -513,3 +556,18 @@ void intel_dsb_cleanup(struct intel_dsb *dsb)
intel_dsb_buffer_cleanup(>dsb_buf);
kfree(dsb);
 }
+
+void intel_dsb_irq_handler(struct intel_display *display,
+  enum pipe pipe, enum intel_dsb_id dsb_id)
+{
+   struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(display->drm), 
pipe);
+   u32 tmp, errors;
+
+   tmp =

[PATCH 02/14] drm/i915: Make vrr_{enabling, disabling}() usable outside intel_display.c

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Give vrr_enabling() and vrr_disabling() slightly fancier names, and
pass in the whole atomic state so that they'll be easier to use.
We'll need to call at least the disabling part from the DSB code
soon enough (so that we can do vblank evasions/etc. correctly on
the DSB).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 26 +---
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index c2c388212e2e..01a5faa3fea5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1014,9 +1014,14 @@ static bool cmrr_params_changed(const struct 
intel_crtc_state *old_crtc_state,
old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
 }
 
-static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
-const struct intel_crtc_state *new_crtc_state)
+static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
 {
+   const struct intel_crtc_state *old_crtc_state =
+   intel_atomic_get_old_crtc_state(state, crtc);
+   const struct intel_crtc_state *new_crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+
if (!new_crtc_state->hw.active)
return false;
 
@@ -1026,9 +1031,14 @@ static bool vrr_enabling(const struct intel_crtc_state 
*old_crtc_state,
  vrr_params_changed(old_crtc_state, new_crtc_state)));
 }
 
-static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
- const struct intel_crtc_state *new_crtc_state)
+static bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
 {
+   const struct intel_crtc_state *old_crtc_state =
+   intel_atomic_get_old_crtc_state(state, crtc);
+   const struct intel_crtc_state *new_crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+
if (!old_crtc_state->hw.active)
return false;
 
@@ -1181,7 +1191,7 @@ static void intel_pre_plane_update(struct 
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
 
-   if (vrr_disabling(old_crtc_state, new_crtc_state)) {
+   if (intel_crtc_vrr_disabling(state, crtc)) {
intel_vrr_disable(old_crtc_state);
intel_crtc_update_active_timings(old_crtc_state, false);
}
@@ -6830,8 +6840,6 @@ static void commit_pipe_post_planes(struct 
intel_atomic_state *state,
struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   const struct intel_crtc_state *old_crtc_state =
-   intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
 
@@ -6844,7 +6852,7 @@ static void commit_pipe_post_planes(struct 
intel_atomic_state *state,
!intel_crtc_needs_modeset(new_crtc_state))
skl_detach_scalers(new_crtc_state);
 
-   if (vrr_enabling(old_crtc_state, new_crtc_state))
+   if (intel_crtc_vrr_enabling(state, crtc))
intel_vrr_enable(new_crtc_state);
 }
 
@@ -6944,7 +6952,7 @@ static void intel_update_crtc(struct intel_atomic_state 
*state,
 *
 * FIXME Should be synchronized with the start of vblank somehow...
 */
-   if (vrr_enabling(old_crtc_state, new_crtc_state) ||
+   if (intel_crtc_vrr_enabling(state, crtc) ||
new_crtc_state->update_m_n || new_crtc_state->update_lrr)
intel_crtc_update_active_timings(new_crtc_state,
 new_crtc_state->vrr.enable);
-- 
2.44.2

[PATCH 01/14] drm/i915: Calculate vblank delay more accurately

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Calculate the vblank delay in the vblank evasion code correctly
for interlaced modes.

The current code assumes that we won't be using an interlaced mode.
That assumption is actually valid since we've defeatured interlaced
scanout in commit f71c9b7bc35f ("drm/i915/display: Prune Interlace
modes for Display >=12") for DSB capable platforms. However the
feature is still present in the hardware, and if we ever find the
need to re-enable it seems better to calculate the vblank delay
correctly.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c 
b/drivers/gpu/drm/i915/display/intel_vblank.c
index 5b065e1cd4e4..f183e0d4b2ba 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -652,7 +652,8 @@ void intel_vblank_evade_init(const struct intel_crtc_state 
*old_crtc_state,
 */
if (intel_color_uses_dsb(new_crtc_state) ||
new_crtc_state->update_m_n || new_crtc_state->update_lrr)
-   evade->min -= adjusted_mode->crtc_vblank_start - 
adjusted_mode->crtc_vdisplay;
+   evade->min -= intel_mode_vblank_start(adjusted_mode) -
+   intel_mode_vdisplay(adjusted_mode);
 }
 
 /* must be called with vblank interrupt already enabled! */
-- 
2.44.2

[PATCH 00/14] drm/i915/dsb: Use chained DSBs for LUT programming

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Handle the DSB's DEwake shenanigans more elegantly
by chaining two DSBs together.

Ville Syrjälä (14):
  drm/i915: Calculate vblank delay more accurately
  drm/i915: Make vrr_{enabling,disabling}() usable outside
intel_display.c
  drm/i915/dsb: Hook up DSB error interrupts
  drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlier
  drm/i915/dsb: Shuffle code around
  drm/i915/dsb: Fix dewake scanline
  drm/i915/dsb: Account for VRR properly in DSB scanline stuff
  drm/i915/dsb: Precompute DSB_CHICKEN
  drm/i915/dsb: Introduce intel_dsb_wait_scanline_{in,out}()
  drm/i915/dsb: Introduce intel_dsb_chain()
  drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANK
  drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is done
  drm/i915/dsb: s/dsb/dsb_color_vblank/
  drm/i915/dsb: Use chained DSBs for LUT programming

 drivers/gpu/drm/i915/display/intel_atomic.c   |   6 +-
 drivers/gpu/drm/i915/display/intel_color.c|  56 ++-
 drivers/gpu/drm/i915/display/intel_display.c  |  29 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   3 +
 .../gpu/drm/i915/display/intel_display_irq.c  |  17 +
 .../drm/i915/display/intel_display_types.h|   4 +-
 drivers/gpu/drm/i915/display/intel_dsb.c  | 327 --
 drivers/gpu/drm/i915/display/intel_dsb.h  |  16 +
 drivers/gpu/drm/i915/display/intel_vblank.c   |  14 +-
 drivers/gpu/drm/i915/display/intel_vblank.h   |   2 +-
 drivers/gpu/drm/i915/i915_reg.h   |   4 +
 11 files changed, 401 insertions(+), 77 deletions(-)

-- 
2.44.2

✓ Fi.CI.BAT: success for drm/i915: Enable CCS+10bpc and CCS+async flips

2024-06-24 Thread Patchwork

== Series Details ==

Series: drm/i915: Enable CCS+10bpc and CCS+async flips
URL   : https://patchwork.freedesktop.org/series/135306/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14995 -> Patchwork_135306v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/index.html

Participating hosts (38 -> 35)
--

  Additional (1): fi-pnv-d510 
  Missing(4): bat-kbl-2 bat-dg2-11 fi-snb-2520m fi-bsw-n3050 

Known issues


  Here are the changes found in Patchwork_135306v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-pnv-d510:NOTRUN -> [SKIP][1] +32 other tests skip
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/fi-pnv-d510/igt@gem_lmem_swapp...@basic.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_lrc:
- {bat-twl-1}:[INCOMPLETE][2] ([i915#10886]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14995/bat-twl-1/igt@i915_selftest@live@gt_lrc.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/bat-twl-1/igt@i915_selftest@live@gt_lrc.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-dp7:
- {bat-mtlp-9}:   [DMESG-WARN][4] ([i915#11009]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14995/bat-mtlp-9/igt@kms_flip@basic-flip-vs-wf_vbl...@d-dp7.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-wf_vbl...@d-dp7.html

  * igt@kms_force_connector_basic@force-connector-state:
- {bat-mtlp-9}:   [FAIL][6] ([i915#11375]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14995/bat-mtlp-9/igt@kms_force_connector_ba...@force-connector-state.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/bat-mtlp-9/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_frontbuffer_tracking@basic:
- bat-arls-2: [DMESG-WARN][8] ([i915#7507]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14995/bat-arls-2/igt@kms_frontbuffer_track...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/bat-arls-2/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-1:
- bat-dg2-8:  [FAIL][10] ([i915#11379]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14995/bat-dg2-8/igt@kms_pipe_crc_basic@hang-read-...@pipe-b-dp-1.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/bat-dg2-8/igt@kms_pipe_crc_basic@hang-read-...@pipe-b-dp-1.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-6:
- {bat-mtlp-9}:   [DMESG-FAIL][12] ([i915#11009]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14995/bat-mtlp-9/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-6.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/bat-mtlp-9/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-6.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
  [i915#10886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10886
  [i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
  [i915#11375]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11375
  [i915#11379]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11379
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#7507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7507
  [i915#9159]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9159


Build changes
-

  * Linux: CI_DRM_14995 -> Patchwork_135306v1

  CI-20190529: 20190529
  CI_DRM_14995: 31d8e23bbf793469d597f3a17888fa55fffe7195 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7897: 9119f9c5dbbb969438b3424dc2f3b30f3b442aab @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_135306v1: 31d8e23bbf793469d597f3a17888fa55fffe7195 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/index.html

✗ Fi.CI.SPARSE: warning for drm/i915: Enable CCS+10bpc and CCS+async flips

2024-06-24 Thread Patchwork

== Series Details ==

Series: drm/i915: Enable CCS+10bpc and CCS+async flips
URL   : https://patchwork.freedesktop.org/series/135306/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'

[PATCH 5/5] drm/i915: Allow async flips with CCS on ICL

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Apparently ICL can do async flips with CCS. In fact it already
seems to work on GLK, but apparently can lead to underruns there
so we'll only enable it for ICL.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 21 +++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 0b0c5ef1d48e..eeba224b9f25 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6243,7 +6243,26 @@ static int intel_async_flip_check_hw(struct 
intel_atomic_state *state, struct in
return -EINVAL;
}
break;
-
+   case I915_FORMAT_MOD_Y_TILED_CCS:
+   case I915_FORMAT_MOD_Yf_TILED_CCS:
+   /*
+* Display WA #0731: skl
+* WaDisableRCWithAsyncFlip: skl
+* "When render decompression is enabled, hardware
+*  internally converts the Async flips to Sync flips."
+*
+* Display WA #1159: glk
+* "Async flip with render compression may result in
+*  intermittent underrun corruption."
+*/
+   if (DISPLAY_VER(i915) < 11) {
+   drm_dbg_kms(>drm,
+   "[PLANE:%d:%s] Modifier 0x%llx does 
not support async flip on display ver %d\n",
+   plane->base.base.id, 
plane->base.name,
+   new_plane_state->hw.fb->modifier, 
DISPLAY_VER(i915));
+   return -EINVAL;
+   }
+   break;
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
-- 
2.44.2

[PATCH 4/5] drm/i915: Allow async flips with render compression on TGL+

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Looks like CCS + async flips has been a thing for a while now.
Enable this for TGL+ render compression modifiers.

Note that we can't update AUX_DIST during async flips we must
check to make sure it remains unchanged.

We also can't do clear color. Supposedly there was some attempt
to make it work, but apparently the issues only got ironed out
in MTL. For now we'll not worry about it and refuse async flips
with clear color modifiers.

Bspec claims that media compression doesn't support async flips.
Based on a quick test it does seem to work to some degree, but
perhaps it has issues as well. Let's trust the spec here and
continue to refuse async flips + media compression.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c| 14 +-
 .../gpu/drm/i915/display/skl_universal_plane.c  | 17 ++---
 .../gpu/drm/i915/display/skl_universal_plane.h  |  3 +++
 3 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index c782e65a7123..0b0c5ef1d48e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6248,6 +6248,9 @@ static int intel_async_flip_check_hw(struct 
intel_atomic_state *state, struct in
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
case I915_FORMAT_MOD_4_TILED:
+   case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+   case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
+   case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
break;
default:
drm_dbg_kms(>drm,
@@ -6257,7 +6260,8 @@ static int intel_async_flip_check_hw(struct 
intel_atomic_state *state, struct in
return -EINVAL;
}
 
-   if (new_plane_state->hw.fb->format->num_planes > 1) {
+   if 
(intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format,
+   
new_plane_state->hw.fb->modifier)) {
drm_dbg_kms(>drm,
"[PLANE:%d:%s] Planar formats do not 
support async flips\n",
plane->base.base.id, plane->base.name);
@@ -6303,6 +6307,14 @@ static int intel_async_flip_check_hw(struct 
intel_atomic_state *state, struct in
return -EINVAL;
}
 
+   if (skl_plane_aux_dist(old_plane_state, 0) !=
+   skl_plane_aux_dist(new_plane_state, 0)) {
+   drm_dbg_kms(>drm,
+   "[PLANE:%d:%s] AUX_DIST cannot be changed 
in async flip\n",
+   plane->base.base.id, plane->base.name);
+   return -EINVAL;
+   }
+
if (!drm_rect_equals(_plane_state->uapi.src, 
_plane_state->uapi.src) ||
!drm_rect_equals(_plane_state->uapi.dst, 
_plane_state->uapi.dst)) {
drm_dbg_kms(>drm,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c80a89b71ef7..6f4b3839724d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -528,15 +528,18 @@ static u32 tgl_plane_min_alignment(struct intel_plane 
*plane,
if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915))
return mult * 16 * 1024;
return mult * 4 * 1024;
-   case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
-   case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
-   case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
-   case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
-   case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+   if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915))
+   return mult * 16 * 1024;
+   fallthrough;
+   case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+   case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+   case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+   case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
+   case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
/*
 * Align to at least 4x1 main surface
 * tiles (16K) to match 64B of AUX.
@@ -1185,8 +1188,8 @@ static u32 skl_plane_surf(const struct intel_plane_state 
*plane_state,
return plane_surf;
 }
 
-static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
- int color_plane)
+u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
+

[PATCH 2/5] drm/i915: Expose CCS for 10bpc RGB formats on TGL+

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

CCS + 10bpc formats has been a thing for a while now. Expose it
it on TGL+.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fb.c   | 36 +++
 .../drm/i915/display/skl_universal_plane.c|  8 ++---
 2 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index f23547a88b1f..43d0574814a6 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -66,6 +66,18 @@ static const struct drm_format_info gen12_ccs_formats[] = {
{ .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+   { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+   { .format = DRM_FORMAT_ARGB2101010, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_ABGR2101010, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  .hsub = 2, .vsub = 1, .is_yuv = true },
@@ -112,6 +124,18 @@ static const struct drm_format_info gen12_ccs_cc_formats[] 
= {
{ .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 
1, 1, 1 },
  .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 
1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+   { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 
1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+   { .format = DRM_FORMAT_ARGB2101010, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 
1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_ABGR2101010, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 
1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
 };
 
 static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
@@ -127,6 +151,18 @@ static const struct drm_format_info 
gen12_flat_ccs_cc_formats[] = {
{ .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
+ .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+   { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
+ .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+   { .format = DRM_FORMAT_ARGB2101010, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_ABGR2101010, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
 };
 
 struct intel_modifier_desc {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ba5a628b4757..92e5db82cbd9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2314,6 +2314,10 @@ static bool gen12_plane_format_mod_supported(struct 
drm_plane *_plane,
case DRM_FORMAT_XBGR:
case DRM_FORMAT_ARGB:
case DRM_FORMAT_ABGR:
+   case DRM_FORMAT_XRGB2101010:
+   case DRM_FORMAT_XBGR2101010:
+   case DRM_FORMAT_ARGB2101010:
+   case DRM_FORMAT_ABGR2101010:
if (intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
@@ -2330,10 +2334,6 @@ static bool gen12_plane_format_mod_supported(struct 
drm_plane *_plane,
return

[PATCH 3/5] drm/i915: Enable 10bpc + CCS on ICL

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

ICL supports 10bpc compressed scanout. Enable it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fb.c   |  8 +++
 .../drm/i915/display/skl_universal_plane.c| 65 +++
 2 files changed, 73 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index 43d0574814a6..1376476b7d60 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -44,6 +44,14 @@ static const struct drm_format_info skl_ccs_formats[] = {
  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
{ .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
+   { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
+   { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
+   { .format = DRM_FORMAT_ARGB2101010, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
+   { .format = DRM_FORMAT_ABGR2101010, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 92e5db82cbd9..c80a89b71ef7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2301,6 +2301,60 @@ static bool skl_plane_format_mod_supported(struct 
drm_plane *_plane,
}
 }
 
+static bool icl_plane_format_mod_supported(struct drm_plane *_plane,
+  u32 format, u64 modifier)
+{
+   struct intel_plane *plane = to_intel_plane(_plane);
+
+   if (!intel_fb_plane_supports_modifier(plane, modifier))
+   return false;
+
+   switch (format) {
+   case DRM_FORMAT_XRGB:
+   case DRM_FORMAT_XBGR:
+   case DRM_FORMAT_ARGB:
+   case DRM_FORMAT_ABGR:
+   case DRM_FORMAT_XRGB2101010:
+   case DRM_FORMAT_XBGR2101010:
+   case DRM_FORMAT_ARGB2101010:
+   case DRM_FORMAT_ABGR2101010:
+   if (intel_fb_is_ccs_modifier(modifier))
+   return true;
+   fallthrough;
+   case DRM_FORMAT_RGB565:
+   case DRM_FORMAT_YUYV:
+   case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_UYVY:
+   case DRM_FORMAT_VYUY:
+   case DRM_FORMAT_NV12:
+   case DRM_FORMAT_XYUV:
+   case DRM_FORMAT_P010:
+   case DRM_FORMAT_P012:
+   case DRM_FORMAT_P016:
+   case DRM_FORMAT_XVYU2101010:
+   if (modifier == I915_FORMAT_MOD_Yf_TILED)
+   return true;
+   fallthrough;
+   case DRM_FORMAT_C8:
+   case DRM_FORMAT_XBGR16161616F:
+   case DRM_FORMAT_ABGR16161616F:
+   case DRM_FORMAT_XRGB16161616F:
+   case DRM_FORMAT_ARGB16161616F:
+   case DRM_FORMAT_Y210:
+   case DRM_FORMAT_Y212:
+   case DRM_FORMAT_Y216:
+   case DRM_FORMAT_XVYU12_16161616:
+   case DRM_FORMAT_XVYU16161616:
+   if (modifier == DRM_FORMAT_MOD_LINEAR ||
+   modifier == I915_FORMAT_MOD_X_TILED ||
+   modifier == I915_FORMAT_MOD_Y_TILED)
+   return true;
+   fallthrough;
+   default:
+   return false;
+   }
+}
+
 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 u32 format, u64 modifier)
 {
@@ -2362,6 +2416,15 @@ static const struct drm_plane_funcs skl_plane_funcs = {
.format_mod_supported = skl_plane_format_mod_supported,
 };
 
+static const struct drm_plane_funcs icl_plane_funcs = {
+   .update_plane = drm_atomic_helper_update_plane,
+   .disable_plane = drm_atomic_helper_disable_plane,
+   .destroy = intel_plane_destroy,
+   .atomic_duplicate_state = intel_plane_duplicate_state,
+   .atomic_destroy_state = intel_plane_destroy_state,
+   .format_mod_supported = icl_plane_format_mod_supported,
+};
+
 static const struct drm_plane_funcs gen12_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -2538,6 +2601,8 @@ skl_universal_plane_create(struct drm_i915_private 
*dev_priv,
 
if (DISPLAY_VER(dev_priv) >= 12)
plane_funcs = _plane_funcs;
+   else if (DISPLAY_VER(dev_priv) == 11)
+   plane_funcs = _plane_funcs;
else
plane_funcs = _plane_funcs;
 
-- 
2.44.2

[PATCH 1/5] drm/i915: Disable compression tricks on JSL

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Bspec asks us to disable some compression trick on JSL. While the
bspec description is pretty vague it looks like this is some extra
trick for 10bpc+ CCS which presumably the ICL derived display engine
doesn't support.

Note that we aren't currently exposing 10bpc CCS scanout support,
but once that gets added this presumably becomes an issue.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index e42b3a5d4e63..af53c40e6c21 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -432,6 +432,7 @@
 #define XEHPG_INSTDONE_GEOM_SVGMCR_REG(0x666c)
 
 #define CACHE_MODE_0_GEN7  _MMIO(0x7000) /* IVB+ */
+#define   DISABLE_REPACKING_FOR_COMPRESSIONREG_BIT(15) /* jsl+ */
 #define   RC_OP_FLUSH_ENABLE   (1 << 0)
 #define   HIZ_RAW_STALL_OPT_DISABLE(1 << 2)
 #define CACHE_MODE_1   _MMIO(0x7004) /* IVB+ */
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 09a287c1aedd..a424b442493f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2286,6 +2286,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
 GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
 
+   if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) {
+   /*
+* "Disable Repacking for Compression (masked R/W access)
+*  before rendering compressed surfaces for display."
+*/
+   wa_masked_en(wal, CACHE_MODE_0_GEN7,
+DISABLE_REPACKING_FOR_COMPRESSION);
+   }
+
if (GRAPHICS_VER(i915) == 11) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
-- 
2.44.2

[PATCH 0/5] drm/i915: Enable CCS+10bpc and CCS+async flips

2024-06-24 Thread Ville Syrjala

From: Ville Syrjälä 

Add support for compressed 10bpc scanout, and async flips
with render compression.

Ville Syrjälä (5):
  drm/i915: Disable compression tricks on JSL
  drm/i915: Expose CCS for 10bpc RGB formats on TGL+
  drm/i915: Enable 10bpc + CCS on ICL
  drm/i915: Allow async flips with render compression on TGL+
  drm/i915: Allow async flips with CCS on ICL

 drivers/gpu/drm/i915/display/intel_display.c  | 35 +++-
 drivers/gpu/drm/i915/display/intel_fb.c   | 44 +
 .../drm/i915/display/skl_universal_plane.c| 90 ---
 .../drm/i915/display/skl_universal_plane.h|  3 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  9 ++
 6 files changed, 169 insertions(+), 13 deletions(-)

-- 
2.44.2

Re: [PATCH v2 0/9] drm/i915: Polish plane surface alignment handling

2024-06-24 Thread Ville Syrjälä

On Wed, Jun 19, 2024 at 02:38:16PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 12, 2024 at 11:47:03PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > intel_surf_alignment() in particular has devolved into
> > a complete mess. Redesign the code so that we can handle
> > alignment restrictions in a nicer. Also adjust alignment
> > for TGL+ to actually match the hardware requirements.
> > 
> > v2: Drop the per-plane vma stuff as it was borked
> > Don't temporarily remove the 2MiB DPT alignment for UV on TGL
> > 
> > Ville Syrjälä (9):
> >   drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format()
> >   drm: Export drm_plane_has_format()
> 
> Maarten/Maxime/Thomas, can I get an ack for merging these via
> drm-intel please?

Series pushed to drm-intel-next with Thomas's irc ack.

Thanks for the reviews and acks.

> 
> >   drm/i915: Introduce the plane->min_alignment() vfunc
> >   drm/i915: Introduce fb->min_alignment
> >   drm/i915: Split cursor alignment to per-platform vfuncs
> >   drm/i915: Split pre-skl platforms out from intel_surf_alignment()
> >   drm/i915: Move intel_surf_alignment() into skl_univerals_plane.c
> >   drm/i915: Update plane alignment requirements for TGL+
> >   drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff
> > 
> >  drivers/gpu/drm/drm_atomic.c  |   7 +-
> >  drivers/gpu/drm/drm_crtc.c|   6 +-
> >  drivers/gpu/drm/drm_crtc_internal.h   |   2 -
> >  drivers/gpu/drm/drm_plane.c   |  23 ++-
> >  drivers/gpu/drm/i915/display/i9xx_plane.c |  75 -
> >  drivers/gpu/drm/i915/display/intel_cursor.c   |  38 +
> >  .../drm/i915/display/intel_display_types.h|   5 +
> >  drivers/gpu/drm/i915/display/intel_fb.c   | 151 --
> >  drivers/gpu/drm/i915/display/intel_fb.h   |   3 -
> >  drivers/gpu/drm/i915/display/intel_fb_pin.c   |  39 +++--
> >  drivers/gpu/drm/i915/display/intel_fb_pin.h   |   3 +-
> >  drivers/gpu/drm/i915/display/intel_fbdev.c|   5 +-
> >  drivers/gpu/drm/i915/display/intel_sprite.c   |  26 +++
> >  .../drm/i915/display/skl_universal_plane.c|  85 +-
> >  drivers/gpu/drm/xe/display/xe_fb_pin.c|   3 +-
> >  drivers/gpu/drm/xe/display/xe_plane_initial.c |   4 +-
> 
> Lucas, can you give me an ack for the merging the xe
> changes via drm-intel?
> 
> >  include/drm/drm_plane.h   |   2 +
> >  17 files changed, 309 insertions(+), 168 deletions(-)
> > 
> > -- 
> > 2.44.2
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: Linux 6.10-rc1

2024-06-24 Thread Gerhard Stoiber


Hello!
 
Ideas welcome, especially some way to see what graphics is doing.


I'm unsure about the distro you are using but try package intel_gpu_top. 
It displays irqs/s and a bunch of other utilization statistics.



Hope this helps.

--
BR,
Gerhard

Re: [PATCH v7] drm/i915/panelreplay: Panel replay workaround with VRR

2024-06-24 Thread Ville Syrjälä

On Fri, Jun 21, 2024 at 05:55:13AM +, Manna, Animesh wrote:
> 
> 
> > -Original Message-
> > From: Ville Syrjälä 
> > Sent: Thursday, June 20, 2024 11:06 PM
> > To: Manna, Animesh 
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> > Hogander, Jouni ; Murthy, Arun R
> > ; Golani, Mitulkumar Ajitkumar
> > 
> > Subject: Re: [PATCH v7] drm/i915/panelreplay: Panel replay workaround with
> > VRR
> > 
> > On Wed, Jun 19, 2024 at 04:01:01PM +0300, Ville Syrjälä wrote:
> > > On Tue, Jun 18, 2024 at 04:52:15PM +0530, Animesh Manna wrote:
> > > > Panel Replay VSC SDP not getting sent when VRR is enabled and W1 and
> > > > W2 are 0. So Program Set Context Latency in
> > > > TRANS_SET_CONTEXT_LATENCY register to at least a value of 1.
> > > >
> > > > HSD: 14015406119
> > > >
> > > > v1: Initial version.
> > > > v2: Update timings stored in adjusted_mode struct. [Ville]
> > > > v3: Add WA in compute_config(). [Ville]
> > > > v4:
> > > > - Add DISPLAY_VER() check and improve code comment. [Rodrigo]
> > > > - Introduce centralized intel_crtc_vblank_delay(). [Ville]
> > > > v5: Move to crtc_compute_config(). [Ville]
> > > > v6: Restrict DISPLAY_VER till 14. [Mitul]
> > > > v7:
> > > > - Corrected code-comment. [Mitul]
> > > > - dev_priv local variable removed. [Jani]
> > > >
> > > > Reviewed-by: Mitul Golani 
> > > > Signed-off-by: Animesh Manna 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c | 21
> > > >   drivers/gpu/drm/i915/display/intel_display.h |
> > > > 1 +
> > > >  2 files changed, 22 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 7bc4f3de691e..c3ff3a5c5fa3 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -2515,6 +2515,10 @@ static int intel_crtc_compute_config(struct
> > intel_atomic_state *state,
> > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > int ret;
> > > >
> > > > +   /* wa_14015401596: display versions 13, 14 */
> > > > +   if (IS_DISPLAY_VER(to_i915(crtc->base.dev), 13, 14))
> > > > +   intel_crtc_vblank_delay(crtc_state);
> > > > +
> > > > ret = intel_dpll_crtc_compute_clock(state, crtc);
> > > > if (ret)
> > > > return ret;
> > > > @@ -3924,6 +3928,23 @@ bool intel_crtc_get_pipe_config(struct
> > intel_crtc_state *crtc_state)
> > > > return true;
> > > >  }
> > > >
> > > > +void intel_crtc_vblank_delay(struct intel_crtc_state *crtc_state) {
> > > > +   struct drm_display_mode *adjusted_mode =
> > > > +_state->hw.adjusted_mode;
> > > > +
> > > > +   /*
> > > > +* wa_14015401596 for display versions 13, 14.
> > > > +* Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY
> > register
> > > > +* to at least a value of 1 when Panel Replay is enabled with 
> > > > VRR.
> > > > +* Value for TRANS_SET_CONTEXT_LATENCY is calculated by
> > substracting
> > > > +* crtc_vdisplay from crtc_vblank_start, so incrementing
> > crtc_vblank_start
> > > > +* by 1 if both are equal.
> > > > +*/
> > > > +   if (crtc_state->vrr.enable && crtc_state->has_panel_replay &&
> > > > +   adjusted_mode->crtc_vblank_start == adjusted_mode-
> > >crtc_vdisplay)
> > > > +   adjusted_mode->crtc_vblank_start += 1; }
> > >
> > > This is probably too late actually. We already used the previous value
> > > to calculate the VRR guardband/pipeline full values, which may or may
> > > not now be incorrect. So NAK for now until someone actually checks how
> > > it all works (I don't recall the details right now).
> > 
> > I double checked this and the guardband/pipeline full values do indeed need
> > to be calculated based on the delayed vblank. So unfortunately this needs to
> > be done before VRR computation, which is a bit annoying if we'd need to
> > tweak this also for HDMI or DSI.
> > But for now we shouldn't actually need other adjustements as I'm going to
> > be doing the DSB stuff without relying on delayed vblank.
> 
> Sure, I will add a change for recalculating guardband.
> No need to change pipeline full value as this workaround is for display 
> version >= 13.

I don't want to see any platform specific hacks for this.
The code must do the right thing on any platform if the
vblank delay gets changed.

> Currently this workaround is only for panel replay, so HDMI and DSI is out of 
> scope.
> As I understood, DSB stuff will be taken care separately, is it ok if I move 
> the adjustment in encoder-compute-config, more specifically in 
> psr-compute-config where we will know about vrr and panel replay is enabled 
> or not and recalculate the guardband ?

Recalculating stuff twice is not great. I suppose we'll just
have to split the VRR computation into two phases, with the
second phase calculating the

quadbuffer stereo

2024-06-24 Thread adblover

I have no idea how to enable quadbuffer stereo (hdmi-3d) on linux for intel and 
amdgpu.

I tried using Option Stereo 12 with this result
(WW) AMDGPU(0): Option "Stereo" is not used

Hoping for solutions for both cards (intel arc,renoir)

thanks
--

#xorg.conf that I used
Section "ServerLayout"

Identifier "xserver"
Screen  0  "screen" 0 0
InputDevice"keyb"  "CoreKeyboard"
InputDevice"mouse"  "CorePointer"
EndSection

Section "ServerFlags"
Option "AllowMouseOpenFail"  "true"  # allows the server to start up 
even if the mouse does not work
#Option "DontVTSwitch""false" # allow switching between virtual 
terminal
# Option "DontZoom""true"  # disable 
/ (resolution switching)
EndSection

Section "Files"
#RgbPath  "/usr/X11R6/lib/X11/rgb"
#ModulePath   "/usr/X11R6/lib/modules"
# More information:  http://ftp.x.org/pub/X11R7.0/doc/html/fonts.html
FontPath "/usr/share/fonts/X11/misc"
FontPath "/usr/share/fonts/X11/100dpi/:unscaled"
FontPath "/usr/share/fonts/X11/75dpi/:unscaled"
FontPath "/usr/share/fonts/X11/Type1"
FontPath "/usr/share/fonts/X11/100dpi"
FontPath "/usr/share/fonts/X11/75dpi"
FontPath "/usr/X11R6/lib/X11/fonts/misc:unscaled"
FontPath "/usr/X11R6/lib/X11/fonts/misc"
FontPath "/usr/X11R6/lib/X11/fonts/75dpi:unscaled"
FontPath "/usr/X11R6/lib/X11/fonts/75dpi"
FontPath "/usr/X11R6/lib/X11/fonts/100dpi:unscaled"
FontPath "/usr/X11R6/lib/X11/fonts/100dpi"
# True type and type1 fonts are also handled via xftlib, see /etc/X11/XftConfig!
FontPath "/usr/X11R6/lib/X11/fonts/Type1"
FontPath "/usr/share/fonts/ttf/western"
FontPath "/usr/share/fonts/ttf/decoratives"
FontPath "/usr/share/fonts/truetype/ttf-bitstream-vera"
FontPath "/usr/share/fonts/latex-ttf-fonts"
FontPath "/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType"
EndSection

Section "Module"
Load  "dbe"   # double buffer extension
Load  "dri"   # direct rendering
Load  "glx"   # 3D layer
Load "amdgpu"
Load "modesetting"
Load "glamoregl"
Load  "extmod"# some commonly used server extensions (e.g. shape 
extension)
Load  "record"# recording extension
Load  "evdev" # generic input handling driver on Linux
Load  "bitmap"# bitmap fonts
 Load  "ddc"   # ddc probing of monitor
 Load  "freetype"  # font rendering
EndSection

Section "InputDevice"
Identifier  "keyb"
Option  "CoreKeyboard"
Driver  "evdev"
Option  "XkbRules"   "xorg"
Option  "XkbModel"   "pc105"
Option  "XkbLayout"  "de"
#Option  "XkbOptions" "u"
EndSection

Section "InputDevice"
Identifier  "mouse"
Driver  "evdev"
#Option  "Device" "/dev/input/mice"
#Option  "ZAxisMapping"  "4 5"
#Option  "Buttons"   "5"
#Option  "SendCoreEvents""true"

EndSection

Section "Monitor"
Identifier   "sony"
Option   "DPMS"  "true"
#HorizSync31.0 - 61.0
#VertRefresh  50.0 - 90.0
EndSection

Section "Device"
Identifier  "card"
Driver  "amdgpu"
Option "Stereo" "12"
EndSection

Section "Screen"
Identifier "screen"
Device "card"
Monitor"sony"

SubSection "Display"
Depth 24
Modes "1920x1080"
EndSubSection
SubSection "Display"
Depth 32
Modes "1920x1080"
EndSubSection
SubSection "Extensions"
Option "Composite" "Disable"
EndSubSection

EndSection

# Make sure you have the relevant Debian packages on your system
# to be able to use DRI (libgl1-mesa-dri for example)
Section "DRI"
Mode 0666
EndSection

RE: [PATCH] drm/i915/display: Consider adjusted_pixel_rate to be u64

2024-06-24 Thread Kandpal, Suraj




> -Original Message-
> From: Golani, Mitulkumar Ajitkumar
> 
> Sent: Friday, June 21, 2024 1:05 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Vivi, Rodrigo ;
> jani.nik...@linux.intel.com; Kandpal, Suraj ;
> Nautiyal, Ankit K ; nat...@kernel.org
> Subject: [PATCH] drm/i915/display: Consider adjusted_pixel_rate to be u64
> 
> Consider adjusted_pixel_rate to be a u64 to match the return type of
> mul_u32_u32() and avoid any compiler dependency for do_div.
> 
> Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
> Cc: Mitul Golani 
> Cc: Ankit Nautiyal 
> Cc: Suraj Kandpal 
> Cc: Jani Nikula 
> Cc: Rodrigo Vivi 
> Cc: Nathan Chancellor 
> Cc: intel...@lists.freedesktop.org
> Signed-off-by: Mitul Golani 

Thanks for the patches and reviews
Pushed to drm-intel-next

Regards,
Suraj Kandpal
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 6430da25957d..5a0da64c7db3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -137,7 +137,7 @@ static unsigned int
>  cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool
> video_mode_required)  {
>   int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
> - long long adjusted_pixel_rate;
> + u64 adjusted_pixel_rate;
>   struct drm_display_mode *adjusted_mode = _state-
> >hw.adjusted_mode;
> 
>   desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> --
> 2.45.2

Re: [PATCH] drm/i915/display: Consider adjusted_pixel_rate to be u64

2024-06-24 Thread Jani Nikula

On Fri, 21 Jun 2024, Mitul Golani  wrote:
> Consider adjusted_pixel_rate to be a u64 to match the return
> type of mul_u32_u32() and avoid any compiler dependency for
> do_div.

You should mention this fixes 32-bit builds. Might also want to give a
link to the actual build failure, and give credit to the reporter:

Closes: https://lore.kernel.org/r/20240619154207.GA1125704@thelio-3990X
Reported-by: Nathan Chancellor 

>
> Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
> Cc: Mitul Golani 
> Cc: Ankit Nautiyal 
> Cc: Suraj Kandpal 
> Cc: Jani Nikula 
> Cc: Rodrigo Vivi 
> Cc: Nathan Chancellor 
> Cc: intel...@lists.freedesktop.org
> Signed-off-by: Mitul Golani 
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 6430da25957d..5a0da64c7db3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -137,7 +137,7 @@ static unsigned int
>  cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool 
> video_mode_required)
>  {
>   int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
> - long long adjusted_pixel_rate;
> + u64 adjusted_pixel_rate;
>   struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
>  
>   desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);

-- 
Jani Nikula, Intel

✗ Fi.CI.BAT: failure for Use VRR timing generator for fixed refresh rate modes (rev2)

2024-06-24 Thread Patchwork

== Series Details ==

Series: Use VRR timing generator for fixed refresh rate modes (rev2)
URL   : https://patchwork.freedesktop.org/series/134383/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14990 -> Patchwork_134383v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_134383v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_134383v2, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/index.html

Participating hosts (36 -> 33)
--

  Missing(3): fi-glk-j4005 bat-arlh-2 bat-jsl-3 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_134383v2:

### IGT changes ###

 Possible regressions 

  * igt@kms_psr@psr-cursor-plane-move@edp-1:
- bat-arls-2: [PASS][1] -> [FAIL][2] +2 other tests fail
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-arls-2/igt@kms_psr@psr-cursor-plane-m...@edp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-arls-2/igt@kms_psr@psr-cursor-plane-m...@edp-1.html

  * igt@kms_psr@psr-primary-page-flip@edp-1:
- bat-arlh-1: [PASS][3] -> [FAIL][4] +2 other tests fail
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-arlh-1/igt@kms_psr@psr-primary-page-f...@edp-1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-arlh-1/igt@kms_psr@psr-primary-page-f...@edp-1.html

  
 Warnings 

  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-arls-2: [SKIP][5] ([i915#10196] / [i915#4077] / [i915#9688]) 
-> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-arls-2/igt@kms_psr@psr-primary-mmap-...@edp-1.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-arls-2/igt@kms_psr@psr-primary-mmap-...@edp-1.html
- bat-arlh-1: [SKIP][7] ([i915#10196]) -> [FAIL][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-arlh-1/igt@kms_psr@psr-primary-mmap-...@edp-1.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-arlh-1/igt@kms_psr@psr-primary-mmap-...@edp-1.html

  
Known issues


  Here are the changes found in Patchwork_134383v2 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- bat-dg2-8:  [DMESG-FAIL][9] ([i915#9500]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-dg2-8/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-dg2-8/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_flip@basic-flip-vs-dpms@d-dp7:
- {bat-mtlp-9}:   [DMESG-WARN][11] ([i915#11009]) -> [PASS][12] +1 
other test pass
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-mtlp-9/igt@kms_flip@basic-flip-vs-d...@d-dp7.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-mtlp-9/igt@kms_flip@basic-flip-vs-d...@d-dp7.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp6:
- {bat-mtlp-9}:   [DMESG-FAIL][13] ([i915#11009] / [i915#4229]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-mtlp-9/igt@kms_flip@basic-flip-vs-wf_vbl...@a-dp6.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-mtlp-9/igt@kms_flip@basic-flip-vs-wf_vbl...@a-dp6.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-b-dp-7:
- {bat-mtlp-9}:   [FAIL][15] ([i915#10979]) -> [PASS][16] +2 other 
tests pass
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-b-dp-7.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-b-dp-7.html

  * igt@kms_pipe_crc_basic@read-crc@pipe-d-dp-6:
- {bat-mtlp-9}:   [DMESG-FAIL][17] ([i915#11009]) -> [PASS][18] +1 
other test pass
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14990/bat-mtlp-9/igt@kms_pipe_crc_basic@read-...@pipe-d-dp-6.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134383v2/bat-mtlp-9/igt@kms_pipe_crc_basic@read-...@pipe-d-dp-6.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10196
  [i915#10979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10979
  [i915#11009]:

✗ Fi.CI.SPARSE: warning for Use VRR timing generator for fixed refresh rate modes (rev2)

2024-06-24 Thread Patchwork

== Series Details ==

Series: Use VRR timing generator for fixed refresh rate modes (rev2)
URL   : https://patchwork.freedesktop.org/series/134383/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'

✓ Fi.CI.BAT: success for drm/i915/dsb: Use chained DSBs for LUT programming

✗ Fi.CI.SPARSE: warning for drm/i915/dsb: Use chained DSBs for LUT programming

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsb: Use chained DSBs for LUT programming

RE: quadbuffer stereo

[PATCH 14/14] drm/i915/dsb: Use chained DSBs for LUT programming

[PATCH 13/14] drm/i915/dsb: s/dsb/dsb_color_vblank/

[PATCH 10/14] drm/i915/dsb: Introduce intel_dsb_chain()

[PATCH 12/14] drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is done

[PATCH 11/14] drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANK

[PATCH 09/14] drm/i915/dsb: Introduce intel_dsb_wait_scanline_{in, out}()

[PATCH 06/14] drm/i915/dsb: Fix dewake scanline

[PATCH 08/14] drm/i915/dsb: Precompute DSB_CHICKEN

[PATCH 07/14] drm/i915/dsb: Account for VRR properly in DSB scanline stuff

[PATCH 04/14] drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlier

[PATCH 05/14] drm/i915/dsb: Shuffle code around

[PATCH 03/14] drm/i915/dsb: Hook up DSB error interrupts

[PATCH 02/14] drm/i915: Make vrr_{enabling, disabling}() usable outside intel_display.c

[PATCH 01/14] drm/i915: Calculate vblank delay more accurately

[PATCH 00/14] drm/i915/dsb: Use chained DSBs for LUT programming

✓ Fi.CI.BAT: success for drm/i915: Enable CCS+10bpc and CCS+async flips

✗ Fi.CI.SPARSE: warning for drm/i915: Enable CCS+10bpc and CCS+async flips

[PATCH 5/5] drm/i915: Allow async flips with CCS on ICL

[PATCH 4/5] drm/i915: Allow async flips with render compression on TGL+

[PATCH 2/5] drm/i915: Expose CCS for 10bpc RGB formats on TGL+

[PATCH 3/5] drm/i915: Enable 10bpc + CCS on ICL

[PATCH 1/5] drm/i915: Disable compression tricks on JSL

[PATCH 0/5] drm/i915: Enable CCS+10bpc and CCS+async flips

Re: [PATCH v2 0/9] drm/i915: Polish plane surface alignment handling

Re: Linux 6.10-rc1

Re: [PATCH v7] drm/i915/panelreplay: Panel replay workaround with VRR

quadbuffer stereo

RE: [PATCH] drm/i915/display: Consider adjusted_pixel_rate to be u64

Re: [PATCH] drm/i915/display: Consider adjusted_pixel_rate to be u64

✗ Fi.CI.BAT: failure for Use VRR timing generator for fixed refresh rate modes (rev2)

✗ Fi.CI.SPARSE: warning for Use VRR timing generator for fixed refresh rate modes (rev2)

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