Re: [Intel-gfx] [PATCH 14/17] drm/i915/icl: Calculate link clock using the new registers

[Paulo Zanoni]

Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> From: Arkadiusz Hiler 
> 
> Start using the new registers for ICL and on.

This patch doesn't make sense at this point of the series since we
don't run this code on ICL. I'll put it at the correct series.

> 
> Cc: Manasi Navare 
> Cc: Rodrigo Vivi 
> Reviewed-by: Paulo Zanoni 
> Signed-off-by: Arkadiusz Hiler 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 88a6c5107975..c1f1966d471c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1371,8 +1371,13 @@ static int cnl_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
>   uint32_t cfgcr0, cfgcr1;
>   uint32_t p0, p1, p2, dco_freq, ref_clock;
>  
> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> + if (INTEL_GEN(dev_priv) >= 11) {
> + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> + } else {
> + cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> + cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> + }
>  
>   p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
>   p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
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[Intel-gfx] [PATCH 14/17] drm/i915/icl: Calculate link clock using the new registers

[Paulo Zanoni]

From: Arkadiusz Hiler 

Start using the new registers for ICL and on.

Cc: Manasi Navare 
Cc: Rodrigo Vivi 
Reviewed-by: Paulo Zanoni 
Signed-off-by: Arkadiusz Hiler 
---
 drivers/gpu/drm/i915/intel_ddi.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 88a6c5107975..c1f1966d471c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1371,8 +1371,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private 
*dev_priv,
uint32_t cfgcr0, cfgcr1;
uint32_t p0, p1, p2, dco_freq, ref_clock;
 
-   cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
-   cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+   if (INTEL_GEN(dev_priv) >= 11) {
+   cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
+   cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
+   } else {
+   cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+   cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+   }
 
p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
-- 
2.14.3

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