On Wed, Mar 01, 2023 at 03:54:20PM +0200, Jani Nikula wrote:
> Follow the contemporary naming style. Include some indentation fixes
> while at it on the affected statements.
>
> One function needs to keep using dev_priv due to implicit dev_priv usage
> in a macro.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_clock_gating.c | 589 +++---
> 1 file changed, 296 insertions(+), 293 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c
> b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 8cfc19b48760..2c5302bcba19 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -44,9 +44,9 @@ struct drm_i915_clock_gating_funcs {
> void (*init_clock_gating)(struct drm_i915_private *i915);
> };
>
> -static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void gen9_init_clock_gating(struct drm_i915_private *i915)
> {
> - if (HAS_LLC(dev_priv)) {
> + if (HAS_LLC(i915)) {
> /*
>* WaCompressedResourceDisplayNewHashMode:skl,kbl
>* Display WA #0390: skl,kbl
> @@ -54,41 +54,42 @@ static void gen9_init_clock_gating(struct
> drm_i915_private *dev_priv)
>* Must match Sampler, Pixel Back End, and Media. See
>* WaCompressedResourceSamplerPbeMediaNewHashMode.
>*/
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0,
> SKL_DE_COMPRESSED_HASH_MODE);
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0,
> SKL_DE_COMPRESSED_HASH_MODE);
> }
>
> /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0,
> SKL_EDP_PSR_FIX_RDWRAP);
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0,
> SKL_EDP_PSR_FIX_RDWRAP);
>
> /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, 0,
> MASK_WAKEMEM);
> + intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
>
> /*
>* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
>* Display WA #0859: skl,bxt,kbl,glk,cfl
>*/
> - intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0,
> DISP_FBC_MEMORY_WAKE);
> + intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> }
>
> -static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void bxt_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(dev_priv);
> + gen9_init_clock_gating(i915);
>
> /* WaDisableSDEUnitClockGating:bxt */
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0,
> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0,
> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>
> /*
>* FIXME:
>* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
>*/
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0,
> GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
> + intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0,
> GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>
> /*
>* Wa: Backlight PWM may stop in the asserted state, causing backlight
>* to stay fully on.
>*/
> - intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0,
> intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
> -PWM1_GATING_DIS | PWM2_GATING_DIS);
> + intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
> +intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0)
> |
> +PWM1_GATING_DIS | PWM2_GATING_DIS);
>
> /*
>* Lower the display internal timeout.
> @@ -96,42 +97,43 @@ static void bxt_init_clock_gating(struct drm_i915_private
> *dev_priv)
>* is off and a MMIO access is attempted by any privilege
>* application, using batch buffers or any other means.
>*/
> - intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
> + intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
>
> /*
>* WaFbcTurnOffFbcWatermark:bxt
>* Display WA #0562: bxt
>*/
> - intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
> + intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
>
> /*
>* WaFbcHighMemBwCorruptionAvoidance:bxt
>* Display WA #0883: bxt
>*/
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0,
> DPFC_DISABLE_DUMMY0);
> + intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0,
> DPFC_DISABLE_DUMMY0);
> }
>
> -static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void glk_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(dev_priv);
> + gen9_init_clock_gating(