Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/icl: Add new supported CD clocks
On Fri, 2019-06-21 at 09:15 -0700, Matt Roper wrote:
> On Thu, Jun 20, 2019 at 05:45:54PM -0700, José Roberto de Souza
> wrote:
> > Now 180, 172.8 and 192 MHz are supported.
> >
> > 180 and 172.8 MHz CD clocks will only be used when audio is not
> > enabled as state by BSpec and implemented in
> > intel_crtc_compute_min_cdclk(), CD clock must be at least twice of
> > Azalia BCLK and BCLK by default is 96 MHz, it could be set to 48
> > MHz
> > but we are not reading it.
> >
> > BSpec: 20598
> > BSpec: 15729
> > Cc: Clint Taylor
> > Cc: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
>
> I think Ville wanted a 'static' on the range arrays. But aside from
> that, the changes here match the bspec, so
>
> Reviewed-by: Matt Roper
Oh I forgot that.
I did the audio test while on low cd clock frequencies, going to wait
one more day before fix that.
>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++---
> >
> > 1 file changed, 21 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 8993ab283562..8eef177b2bbd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1756,9 +1756,10 @@ static void cnl_sanitize_cdclk(struct
> > drm_i915_private *dev_priv)
> >
> > static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> > {
> > - int ranges_24[] = { 312000, 552000, 648000 };
> > - int ranges_19_38[] = { 307200, 556800, 652800 };
> > - int *ranges;
> > + const int ranges_24[] = { 18, 192000, 312000, 552000,
> > 648000 };
> > + const int ranges_19_38[] = { 172800, 192000, 307200, 556800,
> > 652800 };
> > + const int *ranges;
> > + int len, i;
> >
> > switch (ref) {
> > default:
> > @@ -1766,19 +1767,22 @@ static int icl_calc_cdclk(int min_cdclk,
> > unsigned int ref)
> > /* fall through */
> > case 24000:
> > ranges = ranges_24;
> > + len = ARRAY_SIZE(ranges_24);
> > break;
> > case 19200:
> > case 38400:
> > ranges = ranges_19_38;
> > + len = ARRAY_SIZE(ranges_19_38);
> > break;
> > }
> >
> > - if (min_cdclk > ranges[1])
> > - return ranges[2];
> > - else if (min_cdclk > ranges[0])
> > - return ranges[1];
> > - else
> > - return ranges[0];
> > + for (i = 0; i < len; i++) {
> > + if (min_cdclk <= ranges[i])
> > + return ranges[i];
> > + }
> > +
> > + WARN_ON(min_cdclk > ranges[len - 1]);
> > + return ranges[len - 1];
> > }
> >
> > static int icl_calc_cdclk_pll_vco(struct drm_i915_private
> > *dev_priv, int cdclk)
> > @@ -1792,16 +1796,24 @@ static int icl_calc_cdclk_pll_vco(struct
> > drm_i915_private *dev_priv, int cdclk)
> > default:
> > MISSING_CASE(cdclk);
> > /* fall through */
> > + case 172800:
> > case 307200:
> > case 556800:
> > case 652800:
> > WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> > dev_priv->cdclk.hw.ref != 38400);
> > break;
> > + case 18:
> > case 312000:
> > case 552000:
> > case 648000:
> > WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> > + break;
> > + case 192000:
> > + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> > + dev_priv->cdclk.hw.ref != 38400 &&
> > + dev_priv->cdclk.hw.ref != 24000);
> > + break;
> > }
> >
> > ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> > --
> > 2.22.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/icl: Add new supported CD clocks
On Thu, Jun 20, 2019 at 05:45:54PM -0700, José Roberto de Souza wrote:
> Now 180, 172.8 and 192 MHz are supported.
>
> 180 and 172.8 MHz CD clocks will only be used when audio is not
> enabled as state by BSpec and implemented in
> intel_crtc_compute_min_cdclk(), CD clock must be at least twice of
> Azalia BCLK and BCLK by default is 96 MHz, it could be set to 48 MHz
> but we are not reading it.
>
> BSpec: 20598
> BSpec: 15729
> Cc: Clint Taylor
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
I think Ville wanted a 'static' on the range arrays. But aside from
that, the changes here match the bspec, so
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++---
> 1 file changed, 21 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8993ab283562..8eef177b2bbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1756,9 +1756,10 @@ static void cnl_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
>
> static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> {
> - int ranges_24[] = { 312000, 552000, 648000 };
> - int ranges_19_38[] = { 307200, 556800, 652800 };
> - int *ranges;
> + const int ranges_24[] = { 18, 192000, 312000, 552000, 648000 };
> + const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };
> + const int *ranges;
> + int len, i;
>
> switch (ref) {
> default:
> @@ -1766,19 +1767,22 @@ static int icl_calc_cdclk(int min_cdclk, unsigned int
> ref)
> /* fall through */
> case 24000:
> ranges = ranges_24;
> + len = ARRAY_SIZE(ranges_24);
> break;
> case 19200:
> case 38400:
> ranges = ranges_19_38;
> + len = ARRAY_SIZE(ranges_19_38);
> break;
> }
>
> - if (min_cdclk > ranges[1])
> - return ranges[2];
> - else if (min_cdclk > ranges[0])
> - return ranges[1];
> - else
> - return ranges[0];
> + for (i = 0; i < len; i++) {
> + if (min_cdclk <= ranges[i])
> + return ranges[i];
> + }
> +
> + WARN_ON(min_cdclk > ranges[len - 1]);
> + return ranges[len - 1];
> }
>
> static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int
> cdclk)
> @@ -1792,16 +1796,24 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
> default:
> MISSING_CASE(cdclk);
> /* fall through */
> + case 172800:
> case 307200:
> case 556800:
> case 652800:
> WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> dev_priv->cdclk.hw.ref != 38400);
> break;
> + case 18:
> case 312000:
> case 552000:
> case 648000:
> WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + break;
> + case 192000:
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400 &&
> + dev_priv->cdclk.hw.ref != 24000);
> + break;
> }
>
> ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> --
> 2.22.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH v2 1/3] drm/i915/icl: Add new supported CD clocks
Now 180, 172.8 and 192 MHz are supported.
180 and 172.8 MHz CD clocks will only be used when audio is not
enabled as state by BSpec and implemented in
intel_crtc_compute_min_cdclk(), CD clock must be at least twice of
Azalia BCLK and BCLK by default is 96 MHz, it could be set to 48 MHz
but we are not reading it.
BSpec: 20598
BSpec: 15729
Cc: Clint Taylor
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++---
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 8993ab283562..8eef177b2bbd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1756,9 +1756,10 @@ static void cnl_sanitize_cdclk(struct drm_i915_private
*dev_priv)
static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
{
- int ranges_24[] = { 312000, 552000, 648000 };
- int ranges_19_38[] = { 307200, 556800, 652800 };
- int *ranges;
+ const int ranges_24[] = { 18, 192000, 312000, 552000, 648000 };
+ const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };
+ const int *ranges;
+ int len, i;
switch (ref) {
default:
@@ -1766,19 +1767,22 @@ static int icl_calc_cdclk(int min_cdclk, unsigned int
ref)
/* fall through */
case 24000:
ranges = ranges_24;
+ len = ARRAY_SIZE(ranges_24);
break;
case 19200:
case 38400:
ranges = ranges_19_38;
+ len = ARRAY_SIZE(ranges_19_38);
break;
}
- if (min_cdclk > ranges[1])
- return ranges[2];
- else if (min_cdclk > ranges[0])
- return ranges[1];
- else
- return ranges[0];
+ for (i = 0; i < len; i++) {
+ if (min_cdclk <= ranges[i])
+ return ranges[i];
+ }
+
+ WARN_ON(min_cdclk > ranges[len - 1]);
+ return ranges[len - 1];
}
static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
@@ -1792,16 +1796,24 @@ static int icl_calc_cdclk_pll_vco(struct
drm_i915_private *dev_priv, int cdclk)
default:
MISSING_CASE(cdclk);
/* fall through */
+ case 172800:
case 307200:
case 556800:
case 652800:
WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
dev_priv->cdclk.hw.ref != 38400);
break;
+ case 18:
case 312000:
case 552000:
case 648000:
WARN_ON(dev_priv->cdclk.hw.ref != 24000);
+ break;
+ case 192000:
+ WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
+ dev_priv->cdclk.hw.ref != 38400 &&
+ dev_priv->cdclk.hw.ref != 24000);
+ break;
}
ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
--
2.22.0
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