Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663

2022-11-23 Thread Gustavo Sousa 
On Wed, Nov 23, 2022 at 10:36:48AM -0800, Matt Atwood wrote:
> Wa_18019271663 applies to all DG2 steppings and skus.
> 
> Bspec: 66622
> 
> Signed-off-by: Matt Atwood 

Reviewed-by: Gustavo Sousa 

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 74379d3c5a4d..784152548472 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -429,9 +429,10 @@
>  #define   RC_OP_FLUSH_ENABLE (1 << 0)
>  #define   HIZ_RAW_STALL_OPT_DISABLE  (1 << 2)
>  #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
> -#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE  (1 << 6)
> -#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE  (1 << 6)
> -#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
> +#define   MSAA_OPTIMIZATION_REDUC_DISABLEREG_BIT(11)
> +#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE  REG_BIT(6)
> +#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE  REG_BIT(6)
> +#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1)
>  
>  #define GEN7_GT_MODE _MMIO(0x7008)
>  #define   GEN9_IZ_HASHING_MASK(slice)(0x3 << ((slice) * 2))
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 870db5a202dd..1b0e40e68a9d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct 
> intel_engine_cs *engine,
>  
>   /* Wa_15010599737:dg2 */
>   wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
> +
> + /* Wa_18019271663:dg2 */
> + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
>  }
>  
>  static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
> -- 
> 2.38.1
>

[Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663

2022-11-23 Thread Matt Atwood 
Wa_18019271663 applies to all DG2 steppings and skus.

Bspec: 66622

Signed-off-by: Matt Atwood 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 74379d3c5a4d..784152548472 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -429,9 +429,10 @@
 #define   RC_OP_FLUSH_ENABLE   (1 << 0)
 #define   HIZ_RAW_STALL_OPT_DISABLE(1 << 2)
 #define CACHE_MODE_1   _MMIO(0x7004) /* IVB+ */
-#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6)
-#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE(1 << 6)
-#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
+#define   MSAA_OPTIMIZATION_REDUC_DISABLE  REG_BIT(11)
+#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLEREG_BIT(6)
+#define   GEN8_4x4_STC_OPTIMIZATION_DISABLEREG_BIT(6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   REG_BIT(1)
 
 #define GEN7_GT_MODE   _MMIO(0x7008)
 #define   GEN9_IZ_HASHING_MASK(slice)  (0x3 << ((slice) * 2))
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 870db5a202dd..1b0e40e68a9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs 
*engine,
 
/* Wa_15010599737:dg2 */
wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
+
+   /* Wa_18019271663:dg2 */
+   wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
-- 
2.38.1