Re: [Intel-gfx] [PATCH 2/8] drm/i915/icl: add definitions for the ICL PLL registers
On Wed, Mar 28, 2018 at 02:57:57PM -0700, Paulo Zanoni wrote: > There's a lot of code for the PLL enabling, so let's first only > introduce the register definitions in order to make patch reviewing a > little easier. > > v2: Coding style (Jani). > v3: Preparation for upstreaming. > v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James). > > Cc: James Ausmus > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/i915_reg.h | 149 > > 1 file changed, 149 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 250ff271bcf1..b79b2a8930da 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8701,6 +8701,12 @@ enum skl_power_gate { > #define PORT_CLK_SEL_NONE (7<<29) > #define PORT_CLK_SEL_MASK (7<<29) > > +/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ > +#define DDI_CLK_SEL(port)PORT_CLK_SEL(port) > +#define DDI_CLK_SEL_NONE(0x0 << 28) > +#define DDI_CLK_SEL_MG (0x8 << 28) > +#define DDI_CLK_SEL_MASK(0xF << 28) > + > /* Transcoder clock selection */ > #define _TRANS_CLK_SEL_A 0x46140 > #define _TRANS_CLK_SEL_B 0x46144 > @@ -8831,6 +8837,7 @@ enum skl_power_gate { > * CNL Clocks > */ > #define DPCLKA_CFGCR0_MMIO(0x6C200) > +#define DPCLKA_CFGCR0_ICL_MMIO(0x164280) > #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : > \ > (port)+10)) > #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 > : \ > @@ -8847,10 +8854,141 @@ enum skl_power_gate { > #define PLL_POWER_STATE (1 << 26) > #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) > > +#define _MG_PLL1_ENABLE 0x46030 > +#define _MG_PLL2_ENABLE 0x46034 > +#define _MG_PLL3_ENABLE 0x46038 > +#define _MG_PLL4_ENABLE 0x4603C > +/* Bits are the same as DPLL0_ENABLE */ > +#define MG_PLL_ENABLE(port) _MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \ > +_MG_PLL2_ENABLE) > + > +#define _MG_REFCLKIN_CTL_PORT1 0x16892C > +#define _MG_REFCLKIN_CTL_PORT2 0x16992C > +#define _MG_REFCLKIN_CTL_PORT3 0x16A92C > +#define _MG_REFCLKIN_CTL_PORT4 0x16B92C > +#define MG_REFCLKIN_CTL_OD_2_MUX(x)((x) << 8) > +#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \ > + _MG_REFCLKIN_CTL_PORT1, \ > + _MG_REFCLKIN_CTL_PORT2) > + > +#define _MG_CLKTOP2_CORECLKCTL1_PORT10x1688D8 > +#define _MG_CLKTOP2_CORECLKCTL1_PORT20x1698D8 > +#define _MG_CLKTOP2_CORECLKCTL1_PORT30x16A8D8 > +#define _MG_CLKTOP2_CORECLKCTL1_PORT40x16B8D8 > +#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16) > +#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8) > +#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \ > + _MG_CLKTOP2_CORECLKCTL1_PORT1, \ > + _MG_CLKTOP2_CORECLKCTL1_PORT2) > + > +#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4 > +#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4 > +#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4 > +#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4 > +#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16) > +#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12) > +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) > +#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ > + _MG_CLKTOP2_HSCLKCTL_PORT1, \ > + _MG_CLKTOP2_HSCLKCTL_PORT2) > + > +#define _MG_PLL_DIV0_PORT1 0x168A00 > +#define _MG_PLL_DIV0_PORT2 0x169A00 > +#define _MG_PLL_DIV0_PORT3 0x16AA00 > +#define _MG_PLL_DIV0_PORT4 0x16BA00 > +#define MG_PLL_DIV0_FRACNEN_H (1 << 30) > +#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) > +#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) > +#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \ > + _MG_PLL_DIV0_PORT2) > + > +#define _MG_PLL_DIV1_PORT1
[Intel-gfx] [PATCH 2/8] drm/i915/icl: add definitions for the ICL PLL registers
There's a lot of code for the PLL enabling, so let's first only introduce the register definitions in order to make patch reviewing a little easier. v2: Coding style (Jani). v3: Preparation for upstreaming. v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James). Cc: James Ausmus Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 149 1 file changed, 149 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 250ff271bcf1..b79b2a8930da 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8701,6 +8701,12 @@ enum skl_power_gate { #define PORT_CLK_SEL_NONE (7<<29) #define PORT_CLK_SEL_MASK (7<<29) +/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ +#define DDI_CLK_SEL(port) PORT_CLK_SEL(port) +#define DDI_CLK_SEL_NONE (0x0 << 28) +#define DDI_CLK_SEL_MG(0x8 << 28) +#define DDI_CLK_SEL_MASK (0xF << 28) + /* Transcoder clock selection */ #define _TRANS_CLK_SEL_A 0x46140 #define _TRANS_CLK_SEL_B 0x46144 @@ -8831,6 +8837,7 @@ enum skl_power_gate { * CNL Clocks */ #define DPCLKA_CFGCR0 _MMIO(0x6C200) +#define DPCLKA_CFGCR0_ICL _MMIO(0x164280) #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ (port)+10)) #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ @@ -8847,10 +8854,141 @@ enum skl_power_gate { #define PLL_POWER_STATE (1 << 26) #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) +#define _MG_PLL1_ENABLE0x46030 +#define _MG_PLL2_ENABLE0x46034 +#define _MG_PLL3_ENABLE0x46038 +#define _MG_PLL4_ENABLE0x4603C +/* Bits are the same as DPLL0_ENABLE */ +#define MG_PLL_ENABLE(port)_MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \ + _MG_PLL2_ENABLE) + +#define _MG_REFCLKIN_CTL_PORT1 0x16892C +#define _MG_REFCLKIN_CTL_PORT2 0x16992C +#define _MG_REFCLKIN_CTL_PORT3 0x16A92C +#define _MG_REFCLKIN_CTL_PORT4 0x16B92C +#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8) +#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \ +_MG_REFCLKIN_CTL_PORT1, \ +_MG_REFCLKIN_CTL_PORT2) + +#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8 +#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8 +#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8 +#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8 +#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16) +#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8) +#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \ + _MG_CLKTOP2_CORECLKCTL1_PORT1, \ + _MG_CLKTOP2_CORECLKCTL1_PORT2) + +#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4 +#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4 +#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4 +#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4 +#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16) +#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12) +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) +#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ +_MG_CLKTOP2_HSCLKCTL_PORT1, \ +_MG_CLKTOP2_HSCLKCTL_PORT2) + +#define _MG_PLL_DIV0_PORT1 0x168A00 +#define _MG_PLL_DIV0_PORT2 0x169A00 +#define _MG_PLL_DIV0_PORT3 0x16AA00 +#define _MG_PLL_DIV0_PORT4 0x16BA00 +#define MG_PLL_DIV0_FRACNEN_H(1 << 30) +#define MG_PLL_DIV0_FBDIV_FRAC(x)((x) << 8) +#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) +#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \ +_MG_PLL_DIV0_PORT2) + +#define _MG_PLL_DIV1_PORT1 0x168A04 +#define _MG_PLL_DIV1_PORT2 0x169A04 +#define _MG_PLL_DIV1_PORT3 0x16AA04 +#define _MG_PLL_DIV1_PORT4 0x16BA04 +#define MG_PLL_DIV1_IREF_NDIVRATIO(x)((x) << 16) +#defin