Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Cleanup interface for MCR operations

2022-06-17 Thread Harish Chegondi
On Tue, Jun 14, 2022 at 05:10:19PM -0700, Matt Roper wrote:
> Let's replace the assortment of intel_gt_* and intel_uncore_* functions
> that operate on MCR registers with a cleaner set of interfaces:
> 
>   * intel_gt_mcr_read -- unicast read from specific instance
>   * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
> instance
>   * intel_gt_mcr_unicast_write -- unicast write to specific instance
>   * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
> 
> We'll also replace the historic "slice" and "subslice" terminology with
> "group" and "instance" to match the documentation for more recent
> platforms; these days MCR steering applies to more types of replication
> than just slice/subslice.
> 
> v2:
>  - Reference the new kerneldoc from i915.rst.  (Jani)
>  - Tweak the wording of the documentation for a couple functions to
>clarify the difference between "_fw" and non-"_fw" forms.
> 
> Signed-off-by: Matt Roper 
> Acked-by: Jani Nikula 
> ---
>  Documentation/gpu/i915.rst  |  12 +
>  drivers/gpu/drm/i915/gem/i915_gem_stolen.c  |   2 +-
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  33 ++-
>  drivers/gpu/drm/i915/gt/intel_gt_debugfs.c  |   2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.c  | 239 
>  drivers/gpu/drm/i915/gt/intel_gt_mcr.h  |  43 ++--
>  drivers/gpu/drm/i915/gt/intel_region_lmem.c |   4 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c |   8 +-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  |   2 +-
>  9 files changed, 200 insertions(+), 145 deletions(-)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 54060cd6c419..4e59db1cfb00 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -246,6 +246,18 @@ Display State Buffer
>  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
> :internal:
>  
> +GT Programming
> +==
> +
> +Multicast/Replicated (MCR) Registers
> +
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +   :doc: GT Multicast/Replicated (MCR) Register Support
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +   :internal:
> +
>  Memory Management and Command Submission
>  
>  
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index da30503d3ca2..fa54823d1219 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, 
> u16 type,
>   } else {
>   resource_size_t lmem_range;
>  
> - lmem_range = intel_gt_read_register(>gt0, 
> XEHPSDV_TILE0_ADDR_RANGE) & 0x;
> + lmem_range = intel_gt_mcr_read_any(>gt0, 
> XEHPSDV_TILE0_ADDR_RANGE) & 0x;
>   lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
>   lmem_size *= SZ_1G;
>   }
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 244af1bdb7db..136cc44c3deb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct 
> intel_engine_cs *engine)
>   ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>  }
>  
> -static u32
> -read_subslice_reg(const struct intel_engine_cs *engine,
> -   int slice, int subslice, i915_reg_t reg)
> -{
> - return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
> -slice, subslice);
> -}
> -
>  /* NB: please notice the memset */
>  void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>  struct intel_instdone *instdone)
> @@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct 
> intel_engine_cs *engine,
>   if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>   for_each_instdone_gslice_dss_xehp(i915, sseu, iter, 
> slice, subslice) {
>   instdone->sampler[slice][subslice] =
> - read_subslice_reg(engine, slice, 
> subslice,
> -   
> GEN7_SAMPLER_INSTDONE);
> + intel_gt_mcr_read(engine->gt,
> +   GEN7_SAMPLER_INSTDONE,
> +   slice, subslice);
>   instdone->row[slice][subslice] =
> - read_subslice_reg(engine, slice, 
> subslice,
> -   GEN7_ROW_INSTDONE);
> + intel_gt_mcr_read(engine->gt,
> + 

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Cleanup interface for MCR operations

2022-06-17 Thread Matt Roper
On Fri, Jun 17, 2022 at 06:57:20AM -0700, Harish Chegondi wrote:
> On Tue, Jun 14, 2022 at 05:10:19PM -0700, Matt Roper wrote:
> > Let's replace the assortment of intel_gt_* and intel_uncore_* functions
> > that operate on MCR registers with a cleaner set of interfaces:
> > 
> >   * intel_gt_mcr_read -- unicast read from specific instance
> >   * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
> > instance
> >   * intel_gt_mcr_unicast_write -- unicast write to specific instance
> >   * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
> > 
> > We'll also replace the historic "slice" and "subslice" terminology with
> > "group" and "instance" to match the documentation for more recent
> > platforms; these days MCR steering applies to more types of replication
> > than just slice/subslice.
> > 
> > v2:
> >  - Reference the new kerneldoc from i915.rst.  (Jani)
> >  - Tweak the wording of the documentation for a couple functions to
> >clarify the difference between "_fw" and non-"_fw" forms.
> > 
> > Signed-off-by: Matt Roper 
> > Acked-by: Jani Nikula 
> > ---
> >  Documentation/gpu/i915.rst  |  12 +
> >  drivers/gpu/drm/i915/gem/i915_gem_stolen.c  |   2 +-
> >  drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  33 ++-
> >  drivers/gpu/drm/i915/gt/intel_gt_debugfs.c  |   2 +-
> >  drivers/gpu/drm/i915/gt/intel_gt_mcr.c  | 239 
> >  drivers/gpu/drm/i915/gt/intel_gt_mcr.h  |  43 ++--
> >  drivers/gpu/drm/i915/gt/intel_region_lmem.c |   4 +-
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c |   8 +-
> >  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  |   2 +-
> >  9 files changed, 200 insertions(+), 145 deletions(-)
> > 
> > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> > index 54060cd6c419..4e59db1cfb00 100644
> > --- a/Documentation/gpu/i915.rst
> > +++ b/Documentation/gpu/i915.rst
> > @@ -246,6 +246,18 @@ Display State Buffer
> >  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
> > :internal:
> >  
> > +GT Programming
> > +==
> > +
> > +Multicast/Replicated (MCR) Registers
> > +
> > +
> > +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +   :doc: GT Multicast/Replicated (MCR) Register Support
> > +
> > +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +   :internal:
> > +
> >  Memory Management and Command Submission
> >  
> >  
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
> > b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > index da30503d3ca2..fa54823d1219 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > @@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private 
> > *i915, u16 type,
> > } else {
> > resource_size_t lmem_range;
> >  
> > -   lmem_range = intel_gt_read_register(>gt0, 
> > XEHPSDV_TILE0_ADDR_RANGE) & 0x;
> > +   lmem_range = intel_gt_mcr_read_any(>gt0, 
> > XEHPSDV_TILE0_ADDR_RANGE) & 0x;
> > lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
> > lmem_size *= SZ_1G;
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 244af1bdb7db..136cc44c3deb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct 
> > intel_engine_cs *engine)
> > ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
> >  }
> >  
> > -static u32
> > -read_subslice_reg(const struct intel_engine_cs *engine,
> > - int slice, int subslice, i915_reg_t reg)
> > -{
> > -   return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
> > -  slice, subslice);
> > -}
> > -
> >  /* NB: please notice the memset */
> >  void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> >struct intel_instdone *instdone)
> > @@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct 
> > intel_engine_cs *engine,
> > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> > for_each_instdone_gslice_dss_xehp(i915, sseu, iter, 
> > slice, subslice) {
> > instdone->sampler[slice][subslice] =
> > -   read_subslice_reg(engine, slice, 
> > subslice,
> > - 
> > GEN7_SAMPLER_INSTDONE);
> > +   intel_gt_mcr_read(engine->gt,
> > + GEN7_SAMPLER_INSTDONE,
> > + slice, subslice);
> > instdone->row[slice][subslice] =
> > -