Re: [PATCH v4 3/3] edac: Supporting AST2400 and AST2600 edac driver
> Adding AST2400 and AST2600 edac driver support.
>
> Signed-off-by: Troy Lee
Reviewed-by: Stefan Schaeckeler
> ---
drivers/edac/Kconfig | 6 +++---
> drivers/edac/aspeed_edac.c | 7 +--
> 2 files changed, 8 insertions(+), 5 deletions(-)
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 7a47680d6f07..c410331e8ee8 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -515,10 +515,10 @@ config EDAC_QCOM
> health, you should probably say 'Y' here.
>
> config EDAC_ASPEED
> - tristate "Aspeed AST 2500 SoC"
> - depends on MACH_ASPEED_G5
> + tristate "Aspeed AST BMC SoC"
> + depends on ARCH_ASPEED
> help
> - Support for error detection and correction on the Aspeed AST 2500 SoC.
> + Support for error detection and correction on the Aspeed AST BMC SoC.
>
> First, ECC must be configured in the bootloader. Then, this driver
> will expose error counters via the EDAC kernel framework.
> diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
> index fde809efc520..a46da56d6d54 100644
> --- a/drivers/edac/aspeed_edac.c
> +++ b/drivers/edac/aspeed_edac.c
> @@ -239,7 +239,7 @@ static int init_csrows(struct mem_ctl_info *mci)
> int rc;
>
> /* retrieve info about physical memory from device tree */
> - np = of_find_node_by_path("/memory");
> + np = of_find_node_by_name(NULL, "memory");
> if (!np) {
> dev_err(mci->pdev, "dt: missing /memory node\n");
> return -ENODEV;
> @@ -375,10 +375,13 @@ static int aspeed_remove(struct platform_device *pdev)
>
>
> static const struct of_device_id aspeed_of_match[] = {
> + { .compatible = "aspeed,ast2400-sdram-edac" },
> { .compatible = "aspeed,ast2500-sdram-edac" },
> + { .compatible = "aspeed,ast2600-sdram-edac" },
> {},
> };
>
> +MODULE_DEVICE_TABLE(of, aspeed_of_match);
>
> static struct platform_driver aspeed_driver = {
> .driver = {
> @@ -392,5 +395,5 @@ module_platform_driver(aspeed_driver);
>
> MODULE_LICENSE("GPL");
> MODULE_AUTHOR("Stefan Schaeckeler ");
> -MODULE_DESCRIPTION("Aspeed AST2500 EDAC driver");
> +MODULE_DESCRIPTION("Aspeed BMC SoC EDAC driver");
> MODULE_VERSION("1.0");
> --
> 2.17.1
Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
Hello Troy, > Hi Stefan, > > The driver was ported from latest ASPEED BSP, so I only test with ECC-on/off > from u-boot and check if driver runs correctly. I noticed now most changes are these "exports". As you removed them a later revision, the patch looks now lean and clean. I'll give you my Reviewed-by tag after you addressed Andrew's last comment. > The test doc you provided is very nice and detailed, I'll try to reproduce > the > injection test in v2 patch. It does not harm to redo the testing. That is time-consuming and with your current, now trivial changes, it's not really necessary. Stefan
Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
Hello Troy, > Adding AST2400 and AST2600 edac driver support. > > Signed-off-by: Troy Lee > --- > drivers/edac/Kconfig | 6 +- > drivers/edac/aspeed_edac.c | 114 + > 2 files changed, 94 insertions(+), 26 deletions(-) Uh, there are quite some non-trivial changes. I'll have a look over the coming weekend. Testing an edac driver comes with challenges. Did you test your code? If so, how? That's how I was testing my original edac 2500 driver http://students.engr.scu.edu/~sschaeck/misc/aspeed-edac.html Stefan
Re: [PATCH 1/2] EDAC/aspeed: Fix handling of platform_get_irq() error
> platform_get_irq() returns -ERRNO on error. In such case comparison
> to 0 would pass the check.
>
> Fixes: 9b7e6242ee4e ("EDAC, aspeed: Add an Aspeed AST2500 EDAC driver")
> Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Stefan Schaeckeler
> ---
> drivers/edac/aspeed_edac.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
> index b194658b8b5c..fbec28dc661d 100644
> --- a/drivers/edac/aspeed_edac.c
> +++ b/drivers/edac/aspeed_edac.c
> @@ -209,8 +209,8 @@ static int config_irq(void *ctx, struct platform_device
> *pdev)
> /* register interrupt handler */
> irq = platform_get_irq(pdev, 0);
> dev_dbg(>dev, "got irq %d\n", irq);
> -if (!irq)
> -return -ENODEV;
> +if (irq < 0)
> +return irq;
>
> rc = devm_request_irq(>dev, irq, mcr_isr, IRQF_TRIGGER_HIGH,
> DRV_NAME, ctx);
> --
> 2.17.1
>
>
Re: [PATCH 01/17] ARM: dts: aspeed-g5: Move EDAC node to APB
On Thursday, July 25, 2019 at 10:40 PM, Andrew Jeffery wrote: > Previously the register interface was not attached to any internal bus, > which is not correct - it lives on the APB. > > Cc: Stefan M Schaeckeler > Signed-off-by: Andrew Jeffery > --- > arch/arm/boot/dts/aspeed-g5.dtsi | 14 +++--- > 1 file changed, 7 insertions(+), 7 deletions(-) Reviewed-by: Stefan Schaeckeler
Re: [PATCH 02/17] ARM: dts: aspeed-g5: Use recommended generic node name for SDMC
On Thursday, July 25, 2019 at 10:40 PM, Andrew Jeffery wrote:
> The EDAC is a sub-function of the SDRAM Memory Controller. Rename the
> node to the appropriate generic node name.
>
> Cc: Stefan M Schaeckeler
> Signed-off-by: Andrew Jeffery
> ---
> arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Stefan Schaeckeler
Re: [PATCH -next] EDAC: aspeed: Remove set but not used variable 'np'
On Tuesday, May 28, 2019 at 6:27 PM, Andrew Jeffery wrote: > On Sun, 26 May 2019, at 00:12, YueHaibing wrote: > > Fixes gcc '-Wunused-but-set-variable' warning: > > > > drivers/edac/aspeed_edac.c: In function aspeed_probe: > > drivers/edac/aspeed_edac.c:284:22: warning: variable np set but not > > used [-Wunused-but-set-variable] > > > > It is never used and can be removed. > > > > Signed-off-by: YueHaibing > > Reviewed-by: Andrew Jeffery Reviewed-by: Stefan Schaeckeler > > --- > > drivers/edac/aspeed_edac.c | 4 > > 1 file changed, 4 deletions(-) > > > > diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c > > index 11833c0a5d07..5634437bb39d 100644 > > --- a/drivers/edac/aspeed_edac.c > > +++ b/drivers/edac/aspeed_edac.c > > @@ -281,15 +281,11 @@ static int aspeed_probe(struct platform_device *pdev) > > struct device *dev = >dev; > > struct edac_mc_layer layers[2]; > > struct mem_ctl_info *mci; > > - struct device_node *np; > > struct resource *res; > > void __iomem *regs; > > u32 reg04; > > int rc; > > > > - /* setup regmap */ > > - np = dev->of_node; > > - > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > if (!res) > > return -ENOENT; > > -- > > 2.17.1
[PATCH v2 1/2] EDAC: Add Aspeed AST2500 EDAC driver
From: Stefan M Schaeckeler
Add support for the Aspeed AST2500 SoC EDAC driver.
Signed-off-by: Stefan M Schaeckeler
---
MAINTAINERS | 6 +
arch/arm/boot/dts/aspeed-g5.dtsi | 7 +
drivers/edac/Kconfig | 8 +
drivers/edac/Makefile| 1 +
drivers/edac/aspeed_edac.c | 421 +++
5 files changed, 443 insertions(+)
create mode 100644 drivers/edac/aspeed_edac.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3318f30903b2..1feb92b14029 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5315,6 +5315,12 @@ L: linux-e...@vger.kernel.org
S: Maintained
F: drivers/edac/amd64_edac*
+EDAC-AST2500
+M: Stefan Schaeckeler
+S: Supported
+F: drivers/edac/aspeed_edac.c
+F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+
EDAC-CALXEDA
M: Robert Richter
L: linux-e...@vger.kernel.org
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8..b4e479ab5a2d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -47,6 +47,13 @@
reg = <0x8000 0>;
};
+ edac: sdram@1e6e {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e 0x174>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 41c9ccdd20d6..2ef2bb763577 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -475,4 +475,12 @@ config EDAC_QCOM
For debugging issues having to do with stability and overall system
health, you should probably say 'Y' here.
+config EDAC_ASPEED
+ tristate "Aspeed AST 2500 SoC"
+ depends on MACH_ASPEED_G5
+ help
+ Support for error detection and correction on the Aspeed AST 2500 SoC.
+
+ First, ECC must be configured in the bootloader. Then, this driver
+ will expose error counters via the edac kernel framework.
endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 716096d08ea0..e1f23d4ff860 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
obj-$(CONFIG_EDAC_TI) += ti_edac.o
obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o
+obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o
diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
new file mode 100644
index ..11833c0a5d07
--- /dev/null
+++ b/drivers/edac/aspeed_edac.c
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018, 2019 Cisco Systems
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "edac_module.h"
+
+
+#define DRV_NAME "aspeed-edac"
+
+
+#define ASPEED_MCR_PROT0x00 /* protection key register */
+#define ASPEED_MCR_CONF0x04 /* configuration register */
+#define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */
+#define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error */
+#define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable error */
+#define ASPEED_MCR_LASTASPEED_MCR_ADDR_REC
+
+
+#define ASPEED_MCR_PROT_PASSWD 0xfc600309
+#define ASPEED_MCR_CONF_DRAM_TYPE BIT(4)
+#define ASPEED_MCR_CONF_ECC BIT(7)
+#define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31)
+#define ASPEED_MCR_INTR_CTRL_CNT_REC GENMASK(23, 16)
+#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
+#define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1))
+
+
+static struct regmap *aspeed_regmap;
+
+
+static int regmap_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ void __iomem *regs = (void __iomem *)context;
+
+ /* enable write to MCR register set */
+ writel(ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
+
+ writel(val, regs + reg);
+
+ /* disable write to MCR register set */
+ writel(~ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
+
+ return 0;
+}
+
+
+static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ void __iomem *regs = (void __iomem *)context;
+
+ *val = readl(regs + reg);
+
+ return 0;
+}
+
+static bool regmap_is_volatile(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case ASPEED_MCR_PROT:
+ case ASPEED_MCR_INTR_CTRL:
+ case ASPEED_MCR_ADDR_UNREC:
+ case ASPEED_MCR_ADDR_REC:
+ return true;
+ default:
+ return false;
+ }
+}
+
+
+static const struct r
[PATCH v2 2/2] dt-bindings: edac: Aspeed AST2500
From: Stefan M Schaeckeler
Add support for EDAC on the Aspeed AST2500 SoC.
Signed-off-by: Stefan M Schaeckeler
---
.../bindings/edac/aspeed-sdram-edac.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
new file mode 100644
index ..6a0f3d90d682
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -0,0 +1,25 @@
+Aspeed AST2500 SoC EDAC node
+
+The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC
(error
+correction check).
+
+The memory controller supports SECDED (single bit error correction, double bit
+error detection) and single bit error auto scrubbing by reserving 8 bits for
+every 64 bit word (effectively reducing available memory to 8/9).
+
+Note, the bootloader must configure ECC mode in the memory controller.
+
+
+Required properties:
+- compatible: should be "aspeed,ast2500-sdram-edac"
+- reg:sdram controller register set should be <0x1e6e 0x174>
+- interrupts: should be AVIC interrupt #0
+
+
+Example:
+
+ edac: sdram@1e6e {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e 0x174>;
+ interrupts = <0>;
+ };
--
2.19.1
[PATCH v2 0/2] Add support for the Aspeed AST2500 SoC EDAC driver
From: Stefan M Schaeckeler Add support for the Aspeed AST2500 SoC EDAC driver. Changes since v1: - Addressed all cosmetic issues - Fixed (un-)recoverable address calculation in reg58 and reg5c - Removed status field from the example device tree binding - Added little more text to Kconfig Stefan M Schaeckeler (2): EDAC: Add Aspeed AST2500 EDAC driver dt-bindings: edac: Aspeed AST2500 .../bindings/edac/aspeed-sdram-edac.txt | 25 ++ MAINTAINERS | 6 + arch/arm/boot/dts/aspeed-g5.dtsi | 7 + drivers/edac/Kconfig | 8 + drivers/edac/Makefile | 1 + drivers/edac/aspeed_edac.c| 421 ++ 6 files changed, 468 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt create mode 100644 drivers/edac/aspeed_edac.c -- 2.19.1
Re: [PATCH 1/2] EDAC: Add Aspeed AST2500 EDAC driver
Hello Boris, Thank you for your feedback. > From: Borislav Petkov > > On Sun, Dec 16, 2018 at 10:01:56PM -0800, Stefan Schaeckeler wrote: > > From: Stefan M Schaeckeler > > > > Add support for the Aspeed AST2500 SoC EDAC driver. > > > > Signed-off-by: Stefan M Schaeckeler > > --- > > MAINTAINERS | 6 + > > arch/arm/boot/dts/aspeed-g5.dtsi | 7 + > > drivers/edac/Kconfig | 7 + > > drivers/edac/Makefile| 1 + > > drivers/edac/aspeed_edac.c | 457 +++ > > 5 files changed, 478 insertions(+) > > create mode 100644 drivers/edac/aspeed_edac.c > > I couldn't see anything out of the ordinary - only nitpicks below. [...] > > diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c > > new file mode 100644 > > index ..d6ed119909eb > > --- /dev/null > > +++ b/drivers/edac/aspeed_edac.c > > @@ -0,0 +1,457 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2018 Cisco Systems > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License > > + * as published by the Free Software Foundation; either version > > + * 2 of the License, or (at your option) any later version. > > You have the SPDX license identifier - no need for that text. That's interesting. I did a grep over all 16944 GPL licensed files with an SPDX identifier. 785 of them have a license text while 16159 don't. I will remove mine. > > +static int aspeed_edac_regmap_reg_write(void *context, unsigned int reg, > > + unsigned int val) > > All the static functions don't need the "aspeed_edac" prefix. When stripping off aspeed_edac_, some static function names will become quite "bare-bone": aspeed_edac_init(), aspeed_edac_exit(), aspeed_edac_probe(), aspeed_edac_remove(), aspeed_edac_of_match(), aspeed_edac_isr(), aspeed_edac_config_irq(). Does your suggestion also apply to static variables? E.g. aspeed_edac_regmap, aspeed_edac_regmap_config, aspeed_edac_driver? Also, here some variable names would become quite "bare-bone". Stefan
Re: [PATCH 1/2] EDAC: Add Aspeed AST2500 EDAC driver
Let me start with reviewing my own driver. Perhaps someone could review it as
well, please?
I found a cosmetic issue and a bug. See inline.
> From: Stefan Schaeckeler
>
> From: Stefan M Schaeckeler
>
> Add support for the Aspeed AST2500 SoC EDAC driver.
>
> Signed-off-by: Stefan M Schaeckeler
> ---
> MAINTAINERS | 6 +
> arch/arm/boot/dts/aspeed-g5.dtsi | 7 +
> drivers/edac/Kconfig | 7 +
> drivers/edac/Makefile| 1 +
> drivers/edac/aspeed_edac.c | 457 +++
> 5 files changed, 478 insertions(+)
> create mode 100644 drivers/edac/aspeed_edac.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3318f30903b2..1feb92b14029 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5315,6 +5315,12 @@ L: linux-e...@vger.kernel.org
> S: Maintained
> F: drivers/edac/amd64_edac*
>
> +EDAC-AST2500
> +M: Stefan Schaeckeler
> +S: Supported
> +F: drivers/edac/aspeed_edac.c
> +F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> +
> EDAC-CALXEDA
> M: Robert Richter
> L: linux-e...@vger.kernel.org
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi
> b/arch/arm/boot/dts/aspeed-g5.dtsi
> index d107459fc0f8..b4e479ab5a2d 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -47,6 +47,13 @@
> reg = <0x8000 0>;
> };
>
> + edac: sdram@1e6e {
> + compatible = "aspeed,ast2500-sdram-edac";
> + reg = <0x1e6e 0x174>;
> + interrupts = <0>;
> + status = "disabled";
> + };
> +
> ahb {
> compatible = "simple-bus";
> #address-cells = <1>;
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 41c9ccdd20d6..67834430b0a1 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -475,4 +475,11 @@ config EDAC_QCOM
> For debugging issues having to do with stability and overall system
> health, you should probably say 'Y' here.
>
> +config EDAC_ASPEED
> + tristate "Aspeed AST 2500 SoC"
> + depends on MACH_ASPEED_G5
> + help
> + Support for error detection and correction on the
> + Aspeed AST 2500 SoC.
> +
> endif # EDAC
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index 716096d08ea0..e1f23d4ff860 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -78,3 +78,4 @@ obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
> obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
> obj-$(CONFIG_EDAC_TI)+= ti_edac.o
> obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o
> +obj-$(CONFIG_EDAC_ASPEED)+= aspeed_edac.o
> diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
> new file mode 100644
> index ..d6ed119909eb
> --- /dev/null
> +++ b/drivers/edac/aspeed_edac.c
> @@ -0,0 +1,457 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 Cisco Systems
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
Including asm/page.h does not seem to be necessary.
> +#include "edac_module.h"
> +
> +
> +#define DRV_NAME "aspeed-edac"
> +
> +
> +/* registers */
> +#define ASPEED_MCR_PROT0x00 /* protection key register */
> +#define ASPEED_MCR_CONF0x04 /* configuration register */
> +#define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */
> +#define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error
> */
> +#define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable error */
> +#define ASPEED_MCR_LASTASPEED_MCR_ADDR_REC
> +
> +
> +/* bits and masks */
> +#define ASPEED_MCR_PROT_PASSWD 0xfc600309
> +#define ASPEED_MCR_CONF_DRAM_TYPE BIT(4)
> +#define ASPEED_MCR_CONF_ECC BIT(7)
> +#define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31)
> +#define ASPEED_MCR_INTR_CTRL_CNT_REC GENMASK(23, 16)
> +#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
> +#define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1))
> +
> +
> +
> +static int aspeed_edac_reg
[PATCH 1/2] EDAC: Add Aspeed AST2500 EDAC driver
From: Stefan M Schaeckeler
Add support for the Aspeed AST2500 SoC EDAC driver.
Signed-off-by: Stefan M Schaeckeler
---
MAINTAINERS | 6 +
arch/arm/boot/dts/aspeed-g5.dtsi | 7 +
drivers/edac/Kconfig | 7 +
drivers/edac/Makefile| 1 +
drivers/edac/aspeed_edac.c | 457 +++
5 files changed, 478 insertions(+)
create mode 100644 drivers/edac/aspeed_edac.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3318f30903b2..1feb92b14029 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5315,6 +5315,12 @@ L: linux-e...@vger.kernel.org
S: Maintained
F: drivers/edac/amd64_edac*
+EDAC-AST2500
+M: Stefan Schaeckeler
+S: Supported
+F: drivers/edac/aspeed_edac.c
+F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+
EDAC-CALXEDA
M: Robert Richter
L: linux-e...@vger.kernel.org
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8..b4e479ab5a2d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -47,6 +47,13 @@
reg = <0x8000 0>;
};
+ edac: sdram@1e6e {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e 0x174>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 41c9ccdd20d6..67834430b0a1 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -475,4 +475,11 @@ config EDAC_QCOM
For debugging issues having to do with stability and overall system
health, you should probably say 'Y' here.
+config EDAC_ASPEED
+ tristate "Aspeed AST 2500 SoC"
+ depends on MACH_ASPEED_G5
+ help
+ Support for error detection and correction on the
+ Aspeed AST 2500 SoC.
+
endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 716096d08ea0..e1f23d4ff860 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
obj-$(CONFIG_EDAC_TI) += ti_edac.o
obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o
+obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o
diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
new file mode 100644
index ..d6ed119909eb
--- /dev/null
+++ b/drivers/edac/aspeed_edac.c
@@ -0,0 +1,457 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Cisco Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "edac_module.h"
+
+
+#define DRV_NAME "aspeed-edac"
+
+
+/* registers */
+#define ASPEED_MCR_PROT0x00 /* protection key register */
+#define ASPEED_MCR_CONF0x04 /* configuration register */
+#define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */
+#define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error */
+#define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable error */
+#define ASPEED_MCR_LASTASPEED_MCR_ADDR_REC
+
+
+/* bits and masks */
+#define ASPEED_MCR_PROT_PASSWD 0xfc600309
+#define ASPEED_MCR_CONF_DRAM_TYPE BIT(4)
+#define ASPEED_MCR_CONF_ECC BIT(7)
+#define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31)
+#define ASPEED_MCR_INTR_CTRL_CNT_REC GENMASK(23, 16)
+#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
+#define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1))
+
+
+
+static int aspeed_edac_regmap_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ void __iomem *regs = (void __iomem *)context;
+
+ /* enable write to MCR register set */
+ writel(ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
+
+ writel(val, regs + reg);
+
+ /* disable write to MCR register set */
+ writel(~ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
+
+ return 0;
+}
+
+
+static int aspeed_edac_regmap_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ void __iomem *regs = (void __iomem *)context;
+
+ *val = readl(regs + reg);
+
+ return 0;
+}
+
+static bool aspeed_edac_regmap_is_volatile(struct device *dev,
+ unsigned int reg)
+{
+
[PATCH 2/2] dt-bindings: edac: Aspeed AST2500
From: Stefan M Schaeckeler
Add support for the Aspeed AST2500 SoC EDAC driver.
Signed-off-by: Stefan M Schaeckeler
---
.../bindings/edac/aspeed-sdram-edac.txt | 34 +++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
new file mode 100644
index ..57ba852883c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -0,0 +1,34 @@
+Aspeed AST2500 SoC EDAC device driver
+
+The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC
(error
+correction check).
+
+The memory controller supports SECDED (single bit error correction, double bit
+error detection) and single bit error auto scrubbing by reserving 8 bits for
+every 64 bit word (effectively reducing available memory to 8/9).
+
+First, ECC must be configured in u-boot. Then, this driver will expose error
+counters via the edac kernel framework.
+
+A note on memory organization in ECC mode: every 512 bytes are followed by 64
+bytes of ECC codes. The address remapping is done in hardware and is fully
+transparent to firmware and software. Because of this, ECC mode must be
+configured in u-boot as part of the memory initialization as one can not switch
+from one mode to another when executing in memory.
+
+
+
+Required properties:
+- compatible: should be "aspeed,ast2500-sdram-edac"
+- reg:sdram controller register set should be <0x1e6e 0x174>
+- interrupts: should be AVIC interrupt #0
+
+
+Example:
+
+ edac: sdram@1e6e {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e 0x174>;
+ interrupts = <0>;
+ status = "okay";
+ };
--
2.19.1
[PATCH 0/2] Add support for the Aspeed AST2500 SoC EDAC driver.
From: Stefan M Schaeckeler Add support for the Aspeed AST2500 SoC EDAC driver. Note, I only have access to AST2500 hardware and documentation. The AST2500 documentation explicitly states that the sdram controller is not backward compatible with AST2400 and hence this driver is not supporting it. Best, Stefan Stefan M Schaeckeler (2): EDAC: Add Aspeed AST2500 EDAC driver dt-bindings: edac: Aspeed AST2500 .../bindings/edac/aspeed-sdram-edac.txt | 34 ++ MAINTAINERS | 6 + arch/arm/boot/dts/aspeed-g5.dtsi | 7 + drivers/edac/Kconfig | 7 + drivers/edac/Makefile | 1 + drivers/edac/aspeed_edac.c| 457 ++ 6 files changed, 512 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt create mode 100644 drivers/edac/aspeed_edac.c -- 2.19.1
Re: [PATCH] mtd: mtdoops: optionally dump boottime
Hello Richard and others, > I get the use-case, but why is this only for mtdoops? Powerpc's nvram module also stores oops messages and does so by adding an additional timestamp, as well (search for kmsg_dump_get_buffer() in arch/powerpc/kernel/nvram_64.c). This timestamp is the number of seconds since 1970 and stored as a 64 bit integer in the nvram header. Basically, the last kmesg timestamp is a few ms less than this additionally stored timestamp. Recording boottime would be more elegant, I guess. > IMHO this needs to go into generic code such that all kmsg dumpers can > benefit from it. This would be not that easy: #1 kmsg_dump_get_buffer(...size...) returns the most recent bytes. Consecutive calls return older chunks. It would be natural to return the boottime as the first line, e.g. in the last call, but some clients such as mtdoops call kmsg_dump_get_buffer() only once. The returned buffer may be complete including boottime, or not. #2 consistency with other clients: nvram_64.c has the same requirement of storing a kind of wall-time but does it in a completely different way: no readable ascii text timestamp preprended to the kmsg buffer but a 64 bit timestamp in its header. Note, I don't think we should make mtdoops behave like nvram_64.c by storing the timestamp as a 64 bit integer (in its header) b/c most people do a cat or string of the mtd device /dev/mtdX and a 64 bit integer would just read as garbage. I hope we can have separate implementations for recording additional timestamps. Later, I'll send a patch with stylistic changes unless we completely disagree on how to move forward. Stefan
Re: [PATCH] mtd: mtdoops: optionally dump boottime
Hello Richard and others, > I get the use-case, but why is this only for mtdoops? Powerpc's nvram module also stores oops messages and does so by adding an additional timestamp, as well (search for kmsg_dump_get_buffer() in arch/powerpc/kernel/nvram_64.c). This timestamp is the number of seconds since 1970 and stored as a 64 bit integer in the nvram header. Basically, the last kmesg timestamp is a few ms less than this additionally stored timestamp. Recording boottime would be more elegant, I guess. > IMHO this needs to go into generic code such that all kmsg dumpers can > benefit from it. This would be not that easy: #1 kmsg_dump_get_buffer(...size...) returns the most recent bytes. Consecutive calls return older chunks. It would be natural to return the boottime as the first line, e.g. in the last call, but some clients such as mtdoops call kmsg_dump_get_buffer() only once. The returned buffer may be complete including boottime, or not. #2 consistency with other clients: nvram_64.c has the same requirement of storing a kind of wall-time but does it in a completely different way: no readable ascii text timestamp preprended to the kmsg buffer but a 64 bit timestamp in its header. Note, I don't think we should make mtdoops behave like nvram_64.c by storing the timestamp as a 64 bit integer (in its header) b/c most people do a cat or string of the mtd device /dev/mtdX and a 64 bit integer would just read as garbage. I hope we can have separate implementations for recording additional timestamps. Later, I'll send a patch with stylistic changes unless we completely disagree on how to move forward. Stefan
