Re: [PATCH v3 0/5] RISC-V: Add kexec/kdump support

[Yixun Lan]

Hi Nick

On 4/5/21 8:57 AM, Nick Kossifidis wrote:
> This patch series adds kexec/kdump and crash kernel
> support on RISC-V. For testing the patches a patched
> version of kexec-tools is needed (still a work in
> progress) which can be found at:
>
> https://riscv.ics.forth.gr/kexec-tools-patched.tar.xz
>
> v3:
>   * Rebase on newer kernel tree
>   * Minor cleanups
>   * Split UAPI changes to a separate patch
>   * Improve / cleanup init_resources
>   * Resolve Palmer's comments
>
> v2:
>   * Rebase on newer kernel tree
>   * Minor cleanups
>   * Properly populate the ioresources tre, so that it
> can be used later on for implementing strict /dev/mem
>   * Use linux,usable-memory on /memory instead of a new binding
>   * USe a reserved-memory node for ELF core header
>
> Nick Kossifidis (5):
>RISC-V: Add EM_RISCV to kexec UAPI header
>RISC-V: Add kexec support
>RISC-V: Improve init_resources
>RISC-V: Add kdump support
>RISC-V: Add crash kernel support
>
>   arch/riscv/Kconfig  |  25 
>   arch/riscv/include/asm/elf.h|   6 +
>   arch/riscv/include/asm/kexec.h  |  54 +++
>   arch/riscv/kernel/Makefile  |   6 +
>   arch/riscv/kernel/crash_dump.c  |  46 ++
>   arch/riscv/kernel/crash_save_regs.S |  56 +++
>   arch/riscv/kernel/kexec_relocate.S  | 222 
>   arch/riscv/kernel/machine_kexec.c   | 193 
>   arch/riscv/kernel/setup.c   | 113 --
>   arch/riscv/mm/init.c| 110 ++
>   include/uapi/linux/kexec.h  |   1 +
>   11 files changed, 787 insertions(+), 45 deletions(-)
>   create mode 100644 arch/riscv/include/asm/kexec.h
>   create mode 100644 arch/riscv/kernel/crash_dump.c
>   create mode 100644 arch/riscv/kernel/crash_save_regs.S
>   create mode 100644 arch/riscv/kernel/kexec_relocate.S
>   create mode 100644 arch/riscv/kernel/machine_kexec.c
>

Just ask out of curiosity (maybe out of topic)..
Is crash analysis [1] capable of parsing RISC-V kdump image? No?

Or, any plan working on it?

[1] https://github.com/crash-utility/crash

Yxun Lan

Re: macb broken on HiFive Unleashed

[Yixun Lan]

HI Andreas, Zong:

On Fri, Mar 19, 2021 at 4:51 PM Andreas Schwab  wrote:
>
> On Mär 19 2021, Yixun Lan wrote:
>
> > what's the exact root cause? and any solution?
>
> Try reverting the five commits starting with
> 732374a0b440d9a79c8412f318a25cd37ba6f4e2.
>
I confirm reverting those five patches make the ethernet work again
tested with kernel version 5.11.7

Yixun Lan

Re: [PATCH v7 0/5] clk: add driver for the SiFive FU740

[Yixun Lan]

HI Zong, Andreas:

On Fri, Mar 19, 2021 at 8:21 AM Zong Li  wrote:
>
> On Thu, Mar 18, 2021 at 10:07 AM Zong Li  wrote:
> >
> > On Wed, Mar 17, 2021 at 3:45 AM Andreas Schwab  
> > wrote:
> > >
> > > On Dez 09 2020, Zong Li wrote:
> > >
> > > > Add a driver for the SiFive FU740 PRCI IP block, which handles more
> > > > clocks than FU540. These patches also refactor the original
> > > > implementation by spliting the dependent-code of fu540 and fu740
> > > > respectively.
> > >
> > > That breaks ethernet on the fu540.
> > >
> >
> > I would check that, thanks for the report.
> >
>
> Hi Andreas,
>
> Could you please point me out how to test the ethernet from your side?
> I had tried to quick test by using iperf and wget, the ethernet seems
> to work fine to me.
>
I will give it a shot during this weekend, since I'm facing the same issue..

Yixun Lan

Re: macb broken on HiFive Unleashed

[Yixun Lan]

HI Andreas:

On Fri, Mar 19, 2021 at 8:28 AM Yixun Lan  wrote:
>
> HI Andreas:
>
> On Wed, Mar 17, 2021 at 4:27 PM Andreas Schwab  wrote:
> >
> > It turned out to be a broken clock driver.
> >
>
> what's the exact root cause? and any solution?
> seems I face the same issue, upgrade kernel to 5.11, then eth0 fail to bring 
> up
>
oh, sorry for the noise, just saw you already commented in another thread..

https://lkml.kernel.org/r/87v99qyjaz@igel.home

Re: macb broken on HiFive Unleashed

[Yixun Lan]

HI Andreas:

On Wed, Mar 17, 2021 at 4:27 PM Andreas Schwab  wrote:
>
> It turned out to be a broken clock driver.
>

what's the exact root cause? and any solution?
seems I face the same issue, upgrade kernel to 5.11, then eth0 fail to bring up

Yixun Lan

Re: [PATCH 2/2] Bug Fix for last patch

[Yixun Lan]

Hi Jiuyang

On Tue, Mar 16, 2021 at 1:56 AM Jiuyang Liu  wrote:
>
> Sorry for the noise, Andrew gave me feedbacks, and pointed two bugs in
> last patch.
> 1. asid should be thread safe, which is not the intent.
> 2. asid extracting logic was wrong.
>
> This patch fixes these bugs.
>
> Signed-off-by: Jiuyang Liu 
> ---
>  arch/riscv/include/asm/tlbflush.h | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/tlbflush.h 
> b/arch/riscv/include/asm/tlbflush.h
> index 4b25f51f163d..1f9b62b3670b 100644
> --- a/arch/riscv/include/asm/tlbflush.h
> +++ b/arch/riscv/include/asm/tlbflush.h
> @@ -22,10 +22,14 @@ static inline void local_flush_tlb_page(unsigned long 
> addr)
> __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory");
>  }
>
> -static unsigned long asid;
> +static inline unsigned long get_current_asid(void)
> +{
> +   return (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK;
> +}
> +
>  static inline void local_flush_tlb_asid(void)
>  {
> -   asid = csr_read(CSR_SATP) | (SATP_ASID_MASK << SATP_ASID_SHIFT);
> +   unsigned long asid = get_current_asid();
> __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) : "memory");
>  }
>

This patch title is  too obscure to parse, it should clearly reflect
what's the changes doing here

my two suggestions
1) if previous patches have already been merged, then you probably
should fix title (the commit message)
 and re-send the patch? and maybe add a "Fixes" tag here
2) if previous patches still under reviewing.. then
  a) you can send an update patches series (can squash this fix)
  b) or maintainer willing to squash this fix for you?

Re: [PATCH v5 2/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Hi Jerome, Jianxin:

see my comments

On 10:58 Wed 24 Oct , Jerome Brunet wrote:
> On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> > From: Yixun Lan 
> > 
> > Document the MMC sub clock controller driver, the potential consumer
> > of this driver is MMC or NAND. Also add four clock bindings IDs which
> > provided by this driver.
> > 
> > Reviewed-by: Rob Herring 
> > Signed-off-by: Yixun Lan 
> > Signed-off-by: Jianxin Pan 
> > ---
> >  .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 31 
> > ++
> >  include/dt-bindings/clock/amlogic,mmc-clkc.h   | 17 
> >  2 files changed, 48 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
> >  create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
> > b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
> > new file mode 100644
> > index 000..9e6d343
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
> > @@ -0,0 +1,31 @@
> > +* Amlogic MMC Sub Clock Controller Driver
> > +
> > +The Amlogic MMC clock controller generates and supplies clock to support
> > +MMC and NAND controller
> > +
> > +Required Properties:
> > +
> > +- compatible: should be:
> > +   "amlogic,gx-mmc-clkc"
> > +   "amlogic,axg-mmc-clkc"
> > +
> > +- #clock-cells: should be 1.
> > +- clocks: phandles to clocks corresponding to the clock-names property
> > +- clock-names: list of parent clock names
> > +   - "clkin0", "clkin1"
> > +
> > +Parent node should have the following properties :
> > +- compatible: "amlogic,axg-mmc-clkc", "syscon".
> > +- reg: base address and size of the MMC control register space.
> 
> I get why Stephen is confused by your description, I am too. The example
> contradict the documentation.
> 
> The  documentation above says that the parent node should be a syscon with the
> mmc register space.
> 
> But your example shows this in the node itself.
> 

yes, I think the documentation need to be fixed

for the final solution, we decide to make 'mmc-clkc' an independent node
instead of being a sub-node of 'mmc', so both of them may exist in parallel..

the DT part may like this:

sd_emmc_c_clkc: clock-controller@7000 {
compatible = "amlogic,axg-mmc-clkc", "syscon";
reg = <0x0 0x7000 0x0 0x4>;
...
};

sd_emmc_c: mmc@7000 {
compatible = "amlogic,axg-mmc";
reg = <0x0 0x7000 0x0 0x800>;
...
};


> > +
> > +Example: Clock controller node:
> > +
> > +sd_mmc_c_clkc: clock-controller@7000 {
> > +   compatible = "amlogic,axg-mmc-clkc", "syscon";
> > +   reg = <0x0 0x7000 0x0 0x4>;
> > +   #clock-cells = <1>;
> > +
> > +   clock-names = "clkin0", "clkin1";
> > +   clocks = < CLKID_SD_MMC_C_CLK0>,
> > +< CLKID_FCLK_DIV2>;
> > +};
> > diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h 
> > b/include/dt-bindings/clock/amlogic,mmc-clkc.h
> > new file mode 100644
> > index 000..162b949
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
> > @@ -0,0 +1,17 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > +/*
> > + * Meson MMC sub clock tree IDs
> > + *
> > + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> > + * Author: Yixun Lan 
> > + */
> > +
> > +#ifndef __MMC_CLKC_H
> > +#define __MMC_CLKC_H
> > +
> > +#define CLKID_MMC_DIV  1
> > +#define CLKID_MMC_PHASE_CORE   2
> > +#define CLKID_MMC_PHASE_TX 3
> > +#define CLKID_MMC_PHASE_RX 4
> > +
> > +#endif
> 
> 
> 
> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v5 2/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Hi Jerome, Jianxin:

see my comments

On 10:58 Wed 24 Oct , Jerome Brunet wrote:
> On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> > From: Yixun Lan 
> > 
> > Document the MMC sub clock controller driver, the potential consumer
> > of this driver is MMC or NAND. Also add four clock bindings IDs which
> > provided by this driver.
> > 
> > Reviewed-by: Rob Herring 
> > Signed-off-by: Yixun Lan 
> > Signed-off-by: Jianxin Pan 
> > ---
> >  .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 31 
> > ++
> >  include/dt-bindings/clock/amlogic,mmc-clkc.h   | 17 
> >  2 files changed, 48 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
> >  create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
> > b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
> > new file mode 100644
> > index 000..9e6d343
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
> > @@ -0,0 +1,31 @@
> > +* Amlogic MMC Sub Clock Controller Driver
> > +
> > +The Amlogic MMC clock controller generates and supplies clock to support
> > +MMC and NAND controller
> > +
> > +Required Properties:
> > +
> > +- compatible: should be:
> > +   "amlogic,gx-mmc-clkc"
> > +   "amlogic,axg-mmc-clkc"
> > +
> > +- #clock-cells: should be 1.
> > +- clocks: phandles to clocks corresponding to the clock-names property
> > +- clock-names: list of parent clock names
> > +   - "clkin0", "clkin1"
> > +
> > +Parent node should have the following properties :
> > +- compatible: "amlogic,axg-mmc-clkc", "syscon".
> > +- reg: base address and size of the MMC control register space.
> 
> I get why Stephen is confused by your description, I am too. The example
> contradict the documentation.
> 
> The  documentation above says that the parent node should be a syscon with the
> mmc register space.
> 
> But your example shows this in the node itself.
> 

yes, I think the documentation need to be fixed

for the final solution, we decide to make 'mmc-clkc' an independent node
instead of being a sub-node of 'mmc', so both of them may exist in parallel..

the DT part may like this:

sd_emmc_c_clkc: clock-controller@7000 {
compatible = "amlogic,axg-mmc-clkc", "syscon";
reg = <0x0 0x7000 0x0 0x4>;
...
};

sd_emmc_c: mmc@7000 {
compatible = "amlogic,axg-mmc";
reg = <0x0 0x7000 0x0 0x800>;
...
};


> > +
> > +Example: Clock controller node:
> > +
> > +sd_mmc_c_clkc: clock-controller@7000 {
> > +   compatible = "amlogic,axg-mmc-clkc", "syscon";
> > +   reg = <0x0 0x7000 0x0 0x4>;
> > +   #clock-cells = <1>;
> > +
> > +   clock-names = "clkin0", "clkin1";
> > +   clocks = < CLKID_SD_MMC_C_CLK0>,
> > +< CLKID_FCLK_DIV2>;
> > +};
> > diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h 
> > b/include/dt-bindings/clock/amlogic,mmc-clkc.h
> > new file mode 100644
> > index 000..162b949
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
> > @@ -0,0 +1,17 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > +/*
> > + * Meson MMC sub clock tree IDs
> > + *
> > + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> > + * Author: Yixun Lan 
> > + */
> > +
> > +#ifndef __MMC_CLKC_H
> > +#define __MMC_CLKC_H
> > +
> > +#define CLKID_MMC_DIV  1
> > +#define CLKID_MMC_PHASE_CORE   2
> > +#define CLKID_MMC_PHASE_TX 3
> > +#define CLKID_MMC_PHASE_RX 4
> > +
> > +#endif
> 
> 
> 
> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

[PATCH v4 3/3] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.

Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.

To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.

Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Kconfig|  10 ++
 drivers/clk/meson/Makefile   |   1 +
 drivers/clk/meson/mmc-clkc.c | 275 +++
 3 files changed, 286 insertions(+)
 create mode 100644 drivers/clk/meson/mmc-clkc.c

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f682b4..8b8ccbcfed1d 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,16 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
 
+config COMMON_CLK_MMC_MESON
+   tristate "Meson MMC Sub Clock Controller Driver"
+   depends on COMMON_CLK_AMLOGIC
+   select MFD_SYSCON
+   select REGMAP
+   help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ which include S905 (GXBB, GXL), A113D/X (AXG) devices.
+ Say Y if you want this clock enabled.
+
 config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 39ce5661b654..31c16d524a4b 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index ..6aa055f7e62c
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+#define CLKID_MMC_MUX  0
+
+#define SD_EMMC_CLOCK  0
+#define   CLK_DIV_MASK GENMASK(5, 0)
+#define   CLK_SRC_MASK GENMASK(7, 6)
+#define   CLK_CORE_PHASE_MASK  GENMASK(9, 8)
+#define   CLK_TX_PHASE_MASKGENMASK(11, 10)
+#define   CLK_RX_PHASE_MASKGENMASK(13, 12)
+#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define   CLK_V2_ALWAYS_ON BIT(24)
+
+#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define   CLK_V3_ALWAYS_ON BIT(28)
+
+#define   CLK_DELAY_STEP_PS200
+#define   CLK_PHASE_STEP   30
+#define   CLK_PHASE_POINT_NUM  (360 / CLK_PHASE_STEP)
+
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS   5
+
+struct mmc_clkc_data {
+   struct meson_clk_phase_delay_data   tx;
+   struct meson_clk_phase_delay_data   rx;
+};
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+   .offset = SD_EMMC_CLOCK,
+   .mask   = 0x3,
+   .shift  = 6,
+   .flags  = CLK_DIVIDER_ROUND_CLOSEST,
+};
+
+static struct clk_regmap_div_data mmc_clkc_div_data = {
+   .offset = SD_EMMC_CLOCK,
+   .shift  = 0,
+   .width  = 6,
+   .flags  = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED,
+};
+
+static struct meson_clk_phase_delay_data mmc_clkc_core_phase_delay = {
+   .phase_mask = CLK_CORE_PHASE_MASK,
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_MASK,
+   .delay_mask = CLK_V2_TX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+   {
+   .phase_mask = CLK_RX_PHASE_MASK,
+   .delay_mask = CLK_V2_RX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_MASK,
+   .delay_mask = CLK_V3_TX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+   {
+   .phase_mask = CLK_RX_PHASE_MAS

[PATCH v4 2/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.

Reviewed-by: Rob Herring 
Signed-off-by: Yixun Lan 
---
 .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
 include/dt-bindings/clock/amlogic,mmc-clkc.h  | 17 ++
 2 files changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index ..9e6d34389be8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,31 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+   "amlogic,gx-mmc-clkc"
+   "amlogic,axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+   - "clkin0", "clkin1"
+
+Parent node should have the following properties :
+- compatible: "amlogic,axg-mmc-clkc", "syscon".
+- reg: base address and size of the MMC control register space.
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+   compatible = "amlogic,axg-mmc-clkc", "syscon";
+   reg = <0x0 0x7000 0x0 0x4>;
+   #clock-cells = <1>;
+
+   clock-names = "clkin0", "clkin1";
+   clocks = < CLKID_SD_MMC_C_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h 
b/include/dt-bindings/clock/amlogic,mmc-clkc.h
new file mode 100644
index ..162b94949119
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan 
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV  1
+#define CLKID_MMC_PHASE_CORE   2
+#define CLKID_MMC_PHASE_TX 3
+#define CLKID_MMC_PHASE_RX 4
+
+#endif
-- 
2.17.1

[PATCH v4 1/3] clk: meson: add emmc sub clock phase delay driver

[Yixun Lan]

Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.

Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Makefile  |  2 +-
 drivers/clk/meson/clk-phase-delay.c | 96 +
 drivers/clk/meson/clkc.h| 13 
 3 files changed, 110 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/clk-phase-delay.c

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c40d848..39ce5661b654 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,7 +2,7 @@
 # Makefile for Meson specific clk
 #
 
-obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o 
clk-phase-delay.o
 obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
 obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
diff --git a/drivers/clk/meson/clk-phase-delay.c 
b/drivers/clk/meson/clk-phase-delay.c
new file mode 100644
index ..6f226814cfec
--- /dev/null
+++ b/drivers/clk/meson/clk-phase-delay.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include "clkc.h"
+
+#define SD_EMMC_CLOCK  0
+
+static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
+{
+   struct clk_regmap *clk = to_clk_regmap(hw);
+   struct meson_clk_phase_delay_data *ph =
+   meson_clk_get_phase_delay_data(clk);
+   unsigned int phase_num = 1 <<  hweight_long(ph->phase_mask);
+   unsigned long period_ps, p, d;
+   int degrees;
+   u32 val;
+
+   regmap_read(clk->map, SD_EMMC_CLOCK, );
+   p = (val & ph->phase_mask) >> __ffs(ph->phase_mask);
+   degrees = p * 360 / phase_num;
+
+   if (ph->delay_mask) {
+   period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
+clk_hw_get_rate(hw));
+   d = (val & ph->delay_mask) >> __ffs(ph->delay_mask);
+   degrees += d * ph->delay_step_ps * 360 / period_ps;
+   degrees %= 360;
+   }
+
+   return degrees;
+}
+
+static void meson_clk_apply_phase_delay(struct clk_regmap *clk,
+   unsigned int phase,
+   unsigned int delay)
+{
+   struct meson_clk_phase_delay_data *ph = clk->data;
+   u32 val;
+
+   regmap_read(clk->map, SD_EMMC_CLOCK, );
+
+   val &= ~ph->phase_mask;
+   val |= phase << __ffs(ph->phase_mask);
+
+   if (ph->delay_mask) {
+   val &= ~ph->delay_mask;
+   val |= delay << __ffs(ph->delay_mask);
+   }
+
+   regmap_write(clk->map, SD_EMMC_CLOCK, val);
+}
+
+static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
+{
+   struct clk_regmap *clk = to_clk_regmap(hw);
+   struct meson_clk_phase_delay_data *ph =
+   meson_clk_get_phase_delay_data(clk);
+   unsigned int phase_num = 1 <<  hweight_long(ph->phase_mask);
+   unsigned long period_ps, d = 0, r;
+   u64 p;
+
+   p = degrees % 360;
+
+   if (!ph->delay_mask) {
+   p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
+   } else {
+   period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
+clk_hw_get_rate(hw));
+
+   /* First compute the phase index (p), the remainder (r) is the
+* part we'll try to acheive using the delays (d).
+*/
+   r = do_div(p, 360 / phase_num);
+   d = DIV_ROUND_CLOSEST(r * period_ps,
+ 360 * ph->delay_step_ps);
+   d = min(d, ph->delay_mask >> __ffs(ph->delay_mask));
+   }
+
+   meson_clk_apply_phase_delay(clk, p, d);
+   return 0;
+}
+
+const struct clk_ops meson_clk_phase_delay_ops = {
+   .get_phase = meson_clk_phase_delay_get_phase,
+   .set_phase = meson_clk_phase_delay_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 24cec16b6038..499834dd34f2 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -113,6 +113,18 @@ struct clk_regmap _name = {
\
},  \
 };
 
+struct meson_clk_phase_delay_data {
+   unsigned long   phase_mask;
+   unsigned long   delay_mask;
+   unsigned intdelay_step_ps;
+};
+
+

[PATCH v4 3/3] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.

Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.

To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.

Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Kconfig|  10 ++
 drivers/clk/meson/Makefile   |   1 +
 drivers/clk/meson/mmc-clkc.c | 275 +++
 3 files changed, 286 insertions(+)
 create mode 100644 drivers/clk/meson/mmc-clkc.c

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f682b4..8b8ccbcfed1d 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,16 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
 
+config COMMON_CLK_MMC_MESON
+   tristate "Meson MMC Sub Clock Controller Driver"
+   depends on COMMON_CLK_AMLOGIC
+   select MFD_SYSCON
+   select REGMAP
+   help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ which include S905 (GXBB, GXL), A113D/X (AXG) devices.
+ Say Y if you want this clock enabled.
+
 config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 39ce5661b654..31c16d524a4b 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index ..6aa055f7e62c
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+#define CLKID_MMC_MUX  0
+
+#define SD_EMMC_CLOCK  0
+#define   CLK_DIV_MASK GENMASK(5, 0)
+#define   CLK_SRC_MASK GENMASK(7, 6)
+#define   CLK_CORE_PHASE_MASK  GENMASK(9, 8)
+#define   CLK_TX_PHASE_MASKGENMASK(11, 10)
+#define   CLK_RX_PHASE_MASKGENMASK(13, 12)
+#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define   CLK_V2_ALWAYS_ON BIT(24)
+
+#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define   CLK_V3_ALWAYS_ON BIT(28)
+
+#define   CLK_DELAY_STEP_PS200
+#define   CLK_PHASE_STEP   30
+#define   CLK_PHASE_POINT_NUM  (360 / CLK_PHASE_STEP)
+
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS   5
+
+struct mmc_clkc_data {
+   struct meson_clk_phase_delay_data   tx;
+   struct meson_clk_phase_delay_data   rx;
+};
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+   .offset = SD_EMMC_CLOCK,
+   .mask   = 0x3,
+   .shift  = 6,
+   .flags  = CLK_DIVIDER_ROUND_CLOSEST,
+};
+
+static struct clk_regmap_div_data mmc_clkc_div_data = {
+   .offset = SD_EMMC_CLOCK,
+   .shift  = 0,
+   .width  = 6,
+   .flags  = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED,
+};
+
+static struct meson_clk_phase_delay_data mmc_clkc_core_phase_delay = {
+   .phase_mask = CLK_CORE_PHASE_MASK,
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_MASK,
+   .delay_mask = CLK_V2_TX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+   {
+   .phase_mask = CLK_RX_PHASE_MASK,
+   .delay_mask = CLK_V2_RX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_MASK,
+   .delay_mask = CLK_V3_TX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+   {
+   .phase_mask = CLK_RX_PHASE_MAS

[PATCH v4 2/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.

Reviewed-by: Rob Herring 
Signed-off-by: Yixun Lan 
---
 .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
 include/dt-bindings/clock/amlogic,mmc-clkc.h  | 17 ++
 2 files changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index ..9e6d34389be8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,31 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+   "amlogic,gx-mmc-clkc"
+   "amlogic,axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+   - "clkin0", "clkin1"
+
+Parent node should have the following properties :
+- compatible: "amlogic,axg-mmc-clkc", "syscon".
+- reg: base address and size of the MMC control register space.
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+   compatible = "amlogic,axg-mmc-clkc", "syscon";
+   reg = <0x0 0x7000 0x0 0x4>;
+   #clock-cells = <1>;
+
+   clock-names = "clkin0", "clkin1";
+   clocks = < CLKID_SD_MMC_C_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h 
b/include/dt-bindings/clock/amlogic,mmc-clkc.h
new file mode 100644
index ..162b94949119
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan 
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV  1
+#define CLKID_MMC_PHASE_CORE   2
+#define CLKID_MMC_PHASE_TX 3
+#define CLKID_MMC_PHASE_RX 4
+
+#endif
-- 
2.17.1

[PATCH v4 1/3] clk: meson: add emmc sub clock phase delay driver

[Yixun Lan]

Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.

Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Makefile  |  2 +-
 drivers/clk/meson/clk-phase-delay.c | 96 +
 drivers/clk/meson/clkc.h| 13 
 3 files changed, 110 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/clk-phase-delay.c

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c40d848..39ce5661b654 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,7 +2,7 @@
 # Makefile for Meson specific clk
 #
 
-obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o 
clk-phase-delay.o
 obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
 obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
diff --git a/drivers/clk/meson/clk-phase-delay.c 
b/drivers/clk/meson/clk-phase-delay.c
new file mode 100644
index ..6f226814cfec
--- /dev/null
+++ b/drivers/clk/meson/clk-phase-delay.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include "clkc.h"
+
+#define SD_EMMC_CLOCK  0
+
+static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
+{
+   struct clk_regmap *clk = to_clk_regmap(hw);
+   struct meson_clk_phase_delay_data *ph =
+   meson_clk_get_phase_delay_data(clk);
+   unsigned int phase_num = 1 <<  hweight_long(ph->phase_mask);
+   unsigned long period_ps, p, d;
+   int degrees;
+   u32 val;
+
+   regmap_read(clk->map, SD_EMMC_CLOCK, );
+   p = (val & ph->phase_mask) >> __ffs(ph->phase_mask);
+   degrees = p * 360 / phase_num;
+
+   if (ph->delay_mask) {
+   period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
+clk_hw_get_rate(hw));
+   d = (val & ph->delay_mask) >> __ffs(ph->delay_mask);
+   degrees += d * ph->delay_step_ps * 360 / period_ps;
+   degrees %= 360;
+   }
+
+   return degrees;
+}
+
+static void meson_clk_apply_phase_delay(struct clk_regmap *clk,
+   unsigned int phase,
+   unsigned int delay)
+{
+   struct meson_clk_phase_delay_data *ph = clk->data;
+   u32 val;
+
+   regmap_read(clk->map, SD_EMMC_CLOCK, );
+
+   val &= ~ph->phase_mask;
+   val |= phase << __ffs(ph->phase_mask);
+
+   if (ph->delay_mask) {
+   val &= ~ph->delay_mask;
+   val |= delay << __ffs(ph->delay_mask);
+   }
+
+   regmap_write(clk->map, SD_EMMC_CLOCK, val);
+}
+
+static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
+{
+   struct clk_regmap *clk = to_clk_regmap(hw);
+   struct meson_clk_phase_delay_data *ph =
+   meson_clk_get_phase_delay_data(clk);
+   unsigned int phase_num = 1 <<  hweight_long(ph->phase_mask);
+   unsigned long period_ps, d = 0, r;
+   u64 p;
+
+   p = degrees % 360;
+
+   if (!ph->delay_mask) {
+   p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
+   } else {
+   period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
+clk_hw_get_rate(hw));
+
+   /* First compute the phase index (p), the remainder (r) is the
+* part we'll try to acheive using the delays (d).
+*/
+   r = do_div(p, 360 / phase_num);
+   d = DIV_ROUND_CLOSEST(r * period_ps,
+ 360 * ph->delay_step_ps);
+   d = min(d, ph->delay_mask >> __ffs(ph->delay_mask));
+   }
+
+   meson_clk_apply_phase_delay(clk, p, d);
+   return 0;
+}
+
+const struct clk_ops meson_clk_phase_delay_ops = {
+   .get_phase = meson_clk_phase_delay_get_phase,
+   .set_phase = meson_clk_phase_delay_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 24cec16b6038..499834dd34f2 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -113,6 +113,18 @@ struct clk_regmap _name = {
\
},  \
 };
 
+struct meson_clk_phase_delay_data {
+   unsigned long   phase_mask;
+   unsigned long   delay_mask;
+   unsigned intdelay_step_ps;
+};
+
+

[PATCH v4 0/3] clk: meson: add a sub EMMC clock controller support

[Yixun Lan]

This driver will add a MMC clock controller driver support.
The original idea about adding a clock controller is during the
discussion in the NAND driver mainline effort[1].

This driver is tested in the S400 board (AXG platform) with NAND driver.

Changes since v3 [4]:
 - separate clk-phase-delay driver
 - replace clk_get_rate() with clk_hw_get_rate()
 - collect Rob's R-Y
 - drop 'meson-' prefix from compatible string

Changes since v2 [3]:
 - squash dt-binding clock-id patch
 - update license
 - fix alignment
 - construct a clk register helper() function

Changes since v1 [2]:
 - implement phase clock
 - update compatible name
 - adjust file name
 - divider probe() into small functions, and re-use them

[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com
[3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com
[4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com

Yixun Lan (3):
  clk: meson: add emmc sub clock phase delay driver
  clk: meson: add DT documentation for emmc clock controller
  clk: meson: add sub MMC clock controller driver

 .../bindings/clock/amlogic,mmc-clkc.txt   |  31 ++
 drivers/clk/meson/Kconfig |  10 +
 drivers/clk/meson/Makefile|   3 +-
 drivers/clk/meson/clk-phase-delay.c   |  96 ++
 drivers/clk/meson/clkc.h  |  13 +
 drivers/clk/meson/mmc-clkc.c  | 275 ++
 include/dt-bindings/clock/amlogic,mmc-clkc.h  |  17 ++
 7 files changed, 444 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 drivers/clk/meson/clk-phase-delay.c
 create mode 100644 drivers/clk/meson/mmc-clkc.c
 create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h

-- 
2.17.1

[PATCH v4 0/3] clk: meson: add a sub EMMC clock controller support

[Yixun Lan]

This driver will add a MMC clock controller driver support.
The original idea about adding a clock controller is during the
discussion in the NAND driver mainline effort[1].

This driver is tested in the S400 board (AXG platform) with NAND driver.

Changes since v3 [4]:
 - separate clk-phase-delay driver
 - replace clk_get_rate() with clk_hw_get_rate()
 - collect Rob's R-Y
 - drop 'meson-' prefix from compatible string

Changes since v2 [3]:
 - squash dt-binding clock-id patch
 - update license
 - fix alignment
 - construct a clk register helper() function

Changes since v1 [2]:
 - implement phase clock
 - update compatible name
 - adjust file name
 - divider probe() into small functions, and re-use them

[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com
[3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com
[4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com

Yixun Lan (3):
  clk: meson: add emmc sub clock phase delay driver
  clk: meson: add DT documentation for emmc clock controller
  clk: meson: add sub MMC clock controller driver

 .../bindings/clock/amlogic,mmc-clkc.txt   |  31 ++
 drivers/clk/meson/Kconfig |  10 +
 drivers/clk/meson/Makefile|   3 +-
 drivers/clk/meson/clk-phase-delay.c   |  96 ++
 drivers/clk/meson/clkc.h  |  13 +
 drivers/clk/meson/mmc-clkc.c  | 275 ++
 include/dt-bindings/clock/amlogic,mmc-clkc.h  |  17 ++
 7 files changed, 444 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 drivers/clk/meson/clk-phase-delay.c
 create mode 100644 drivers/clk/meson/mmc-clkc.c
 create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h

-- 
2.17.1

Re: [PATCH v3 2/2] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

Hi Jerome

On 07/30/18 16:57, Jerome Brunet wrote:
> On Fri, 2018-07-27 at 09:45 -0700, Stephen Boyd wrote:
>> Quoting Stephen Boyd (2018-07-27 09:41:40)
>>> Quoting Yixun Lan (2018-07-27 07:52:23)
>>>> HI Stephen:
>>>>
>>>> On 07/26/2018 11:20 PM, Stephen Boyd wrote:
>>>>> Quoting Yixun Lan (2018-07-12 14:12:44)
>>>>>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>>>>>> new file mode 100644
>>>>>> index ..36c4c7cd69a6
>>>>>> --- /dev/null
>>>>>> +++ b/drivers/clk/meson/mmc-clkc.c
>>>>>> @@ -0,0 +1,367 @@
>>>>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>>>>> +/*
>>>>>> + * Amlogic Meson MMC Sub Clock Controller Driver
>>>>>> + *
>>>>>> + * Copyright (c) 2017 Baylibre SAS.
>>>>>> + * Author: Jerome Brunet 
>>>>>> + *
>>>>>> + * Copyright (c) 2018 Amlogic, inc.
>>>>>> + * Author: Yixun Lan 
>>>>>> + */
>>>>>> +
>>>>>> +#include 
>>>>>
>>>>> Is this include used?
>>>>>
>>>>
>>>> this is needed by clk_get_rate()
>>>> see drivers/clk/meson/mmc-clkc.c:204
>>>
>>> Hmm ok. That's unfortunate.
>>
>> You should be able to read the hardware to figure out the clk frequency?
>> This may be a sign that the phase clk_ops are bad and should be passing
>> in the frequency of the parent clk to the op so that phase can be
>> calculated. Jerome?
>>
> 
> It could be a away to do it but:
> a) if we modify the API, we would need to update every clock driver using it.
>There is not that many users of the phase API but still, it is annoying
> b) This particular driver need the parent rate, other might need something 
> else
> I guess. (parent phase ??, duty cycle ??) 
> 
> I think the real problem here it that you are using the consumer API. You 
> should
> be using the provider API like clk_hw_get_rate. Look at the clk-divider.c 
> which
> use clk_hw_round_rate() on the parent clock. 
I will replace it with clk_hw_get_rate()

> 
> Clock drivers should deal with 'struct clk_hw', not 'struct clk'. I think it 
> was
> mentioned in the past that the 'clk' within 'struct clk_hw' might be removed
> someday.
> 
> Yixun, please don't put your clock driver within the controller driver. Please
> implement your 'phase-delay' clock in its own file and export the ops, like
> every other clock in the amlogic directory. Also, please review your list of
> '#define', some of them are unnecessary copy/paste from the MMC driver.
> 
will implement a clk-phase-delay.c

I can move the extra CC list

Yixun

Re: [PATCH v3 2/2] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

Hi Jerome

On 07/30/18 16:57, Jerome Brunet wrote:
> On Fri, 2018-07-27 at 09:45 -0700, Stephen Boyd wrote:
>> Quoting Stephen Boyd (2018-07-27 09:41:40)
>>> Quoting Yixun Lan (2018-07-27 07:52:23)
>>>> HI Stephen:
>>>>
>>>> On 07/26/2018 11:20 PM, Stephen Boyd wrote:
>>>>> Quoting Yixun Lan (2018-07-12 14:12:44)
>>>>>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>>>>>> new file mode 100644
>>>>>> index ..36c4c7cd69a6
>>>>>> --- /dev/null
>>>>>> +++ b/drivers/clk/meson/mmc-clkc.c
>>>>>> @@ -0,0 +1,367 @@
>>>>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>>>>> +/*
>>>>>> + * Amlogic Meson MMC Sub Clock Controller Driver
>>>>>> + *
>>>>>> + * Copyright (c) 2017 Baylibre SAS.
>>>>>> + * Author: Jerome Brunet 
>>>>>> + *
>>>>>> + * Copyright (c) 2018 Amlogic, inc.
>>>>>> + * Author: Yixun Lan 
>>>>>> + */
>>>>>> +
>>>>>> +#include 
>>>>>
>>>>> Is this include used?
>>>>>
>>>>
>>>> this is needed by clk_get_rate()
>>>> see drivers/clk/meson/mmc-clkc.c:204
>>>
>>> Hmm ok. That's unfortunate.
>>
>> You should be able to read the hardware to figure out the clk frequency?
>> This may be a sign that the phase clk_ops are bad and should be passing
>> in the frequency of the parent clk to the op so that phase can be
>> calculated. Jerome?
>>
> 
> It could be a away to do it but:
> a) if we modify the API, we would need to update every clock driver using it.
>There is not that many users of the phase API but still, it is annoying
> b) This particular driver need the parent rate, other might need something 
> else
> I guess. (parent phase ??, duty cycle ??) 
> 
> I think the real problem here it that you are using the consumer API. You 
> should
> be using the provider API like clk_hw_get_rate. Look at the clk-divider.c 
> which
> use clk_hw_round_rate() on the parent clock. 
I will replace it with clk_hw_get_rate()

> 
> Clock drivers should deal with 'struct clk_hw', not 'struct clk'. I think it 
> was
> mentioned in the past that the 'clk' within 'struct clk_hw' might be removed
> someday.
> 
> Yixun, please don't put your clock driver within the controller driver. Please
> implement your 'phase-delay' clock in its own file and export the ops, like
> every other clock in the amlogic directory. Also, please review your list of
> '#define', some of them are unnecessary copy/paste from the MMC driver.
> 
will implement a clk-phase-delay.c

I can move the extra CC list

Yixun

[PATCH v3 0/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

  This patch series try to add pinctrl driver support for
the Meson-G12A SoC.

  The pinctrl driver for Meson-G12A SoC share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
But, a new driver is needed here due to the differences in the pins.

Changes since v2 at [2]
 - use ${FUNCTION}_${DOMAIN}_${PORT}_${PINFUNC}_${BANK}${PINNUM}
   to rename some pins
 - fix tdm groups
 - explain the similarity of pinmux between AXG and G12A - thanks Martin 
 - collect Rob's Reviewed-by

Changes since v1 at [1]
 - add Martin's Ack, Xingyu's Signed-off
 - squash patch 1,2 (documentation & header file)
 - explain pinctrl IP
 - notice GPIOE located in AO bank

[1] https://lkml.kernel.org/r/20180704224511.29350-1-yixun@amlogic.com
[2] https://lkml.kernel.org/r/20180714232754.5402-1-yixun@amlogic.com

Yixun Lan (2):
  documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin
controllers
  pinctrl: meson-g12a: add pinctrl driver support

 .../bindings/pinctrl/meson,pinctrl.txt|2 +
 drivers/pinctrl/meson/Kconfig |6 +
 drivers/pinctrl/meson/Makefile|1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c| 1404 +
 include/dt-bindings/gpio/meson-g12a-gpio.h|  114 ++
 5 files changed, 1527 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
 create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h

-- 
2.18.0

[PATCH v3 2/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
A new driver is needed here due to the differences in the pins.

Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.

For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.

Please note, the GPIOE is actually located at AO (always on) bank.

Acked-by: Martin Blumenstingl 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 drivers/pinctrl/meson/Kconfig  |6 +
 drivers/pinctrl/meson/Makefile |1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1404 
 3 files changed, 1411 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index c80951d6caff..9ab537eb78a3 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
 config PINCTRL_MESON_AXG_PMX
bool
 
+config PINCTRL_MESON_G12A
+   bool "Meson g12a Soc pinctrl driver"
+   depends on ARM64
+   select PINCTRL_MESON_AXG_PMX
+   default y
+
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 3c6580c2d9d7..cf283f48f9d8 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
 obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
+obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
new file mode 100644
index ..d494492e98e9
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -0,0 +1,1404 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+static const struct pinctrl_pin_desc meson_g12a_periphs_pins[] = {
+   MESON_PIN(GPIOZ_0),
+   MESON_PIN(GPIOZ_1),
+   MESON_PIN(GPIOZ_2),
+   MESON_PIN(GPIOZ_3),
+   MESON_PIN(GPIOZ_4),
+   MESON_PIN(GPIOZ_5),
+   MESON_PIN(GPIOZ_6),
+   MESON_PIN(GPIOZ_7),
+   MESON_PIN(GPIOZ_8),
+   MESON_PIN(GPIOZ_9),
+   MESON_PIN(GPIOZ_10),
+   MESON_PIN(GPIOZ_11),
+   MESON_PIN(GPIOZ_12),
+   MESON_PIN(GPIOZ_13),
+   MESON_PIN(GPIOZ_14),
+   MESON_PIN(GPIOZ_15),
+   MESON_PIN(GPIOH_0),
+   MESON_PIN(GPIOH_1),
+   MESON_PIN(GPIOH_2),
+   MESON_PIN(GPIOH_3),
+   MESON_PIN(GPIOH_4),
+   MESON_PIN(GPIOH_5),
+   MESON_PIN(GPIOH_6),
+   MESON_PIN(GPIOH_7),
+   MESON_PIN(GPIOH_8),
+   MESON_PIN(BOOT_0),
+   MESON_PIN(BOOT_1),
+   MESON_PIN(BOOT_2),
+   MESON_PIN(BOOT_3),
+   MESON_PIN(BOOT_4),
+   MESON_PIN(BOOT_5),
+   MESON_PIN(BOOT_6),
+   MESON_PIN(BOOT_7),
+   MESON_PIN(BOOT_8),
+   MESON_PIN(BOOT_9),
+   MESON_PIN(BOOT_10),
+   MESON_PIN(BOOT_11),
+   MESON_PIN(BOOT_12),
+   MESON_PIN(BOOT_13),
+   MESON_PIN(BOOT_14),
+   MESON_PIN(BOOT_15),
+   MESON_PIN(GPIOC_0),
+   MESON_PIN(GPIOC_1),
+   MESON_PIN(GPIOC_2),
+   MESON_PIN(GPIOC_3),
+   MESON_PIN(GPIOC_4),
+   MESON_PIN(GPIOC_5),
+   MESON_PIN(GPIOC_6),
+   MESON_PIN(GPIOC_7),
+   MESON_PIN(GPIOA_0),
+   MESON_PIN(GPIOA_1),
+   MESON_PIN(GPIOA_2),
+   MESON_PIN(GPIOA_3),
+   MESON_PIN(GPIOA_4),
+   MESON_PIN(GPIOA_5),
+   MESON_PIN(GPIOA_6),
+   MESON_PIN(GPIOA_7),
+   MESON_PIN(GPIOA_8),
+   MESON_PIN(GPIOA_9),
+   MESON_PIN(GPIOA_10),
+   MESON_PIN(GPIOA_11),
+   MESON_PIN(GPIOA_12),
+   MESON_PIN(GPIOA_13),
+   MESON_PIN(GPIOA_14),
+   MESON_PIN(GPIOA_15),
+   MESON_PIN(GPIOX_0),
+   MESON_PIN(GPIOX_1),
+   MESON_PIN(GPIOX_2),
+   MESON_PIN(GPIOX_3),
+   MESON_PIN(GPIOX_4),
+   MESON_PIN(GPIOX_5),
+   MESON_PIN(GPIOX_6),
+   MESON_PIN(GPIOX_7),
+   MESON_PIN(GPIOX_8),
+   MESON_PIN(GPIOX_9),
+   MESON_PIN(GPIOX_10),
+   MESON_PIN(GPIOX_11),
+   MESON_PIN(GPIOX_12),
+   MESON_PIN(GPIOX_13),
+   MESON_PIN(GPIOX_1

[PATCH v3 0/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

  This patch series try to add pinctrl driver support for
the Meson-G12A SoC.

  The pinctrl driver for Meson-G12A SoC share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
But, a new driver is needed here due to the differences in the pins.

Changes since v2 at [2]
 - use ${FUNCTION}_${DOMAIN}_${PORT}_${PINFUNC}_${BANK}${PINNUM}
   to rename some pins
 - fix tdm groups
 - explain the similarity of pinmux between AXG and G12A - thanks Martin 
 - collect Rob's Reviewed-by

Changes since v1 at [1]
 - add Martin's Ack, Xingyu's Signed-off
 - squash patch 1,2 (documentation & header file)
 - explain pinctrl IP
 - notice GPIOE located in AO bank

[1] https://lkml.kernel.org/r/20180704224511.29350-1-yixun@amlogic.com
[2] https://lkml.kernel.org/r/20180714232754.5402-1-yixun@amlogic.com

Yixun Lan (2):
  documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin
controllers
  pinctrl: meson-g12a: add pinctrl driver support

 .../bindings/pinctrl/meson,pinctrl.txt|2 +
 drivers/pinctrl/meson/Kconfig |6 +
 drivers/pinctrl/meson/Makefile|1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c| 1404 +
 include/dt-bindings/gpio/meson-g12a-gpio.h|  114 ++
 5 files changed, 1527 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
 create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h

-- 
2.18.0

[PATCH v3 2/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
A new driver is needed here due to the differences in the pins.

Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.

For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.

Please note, the GPIOE is actually located at AO (always on) bank.

Acked-by: Martin Blumenstingl 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 drivers/pinctrl/meson/Kconfig  |6 +
 drivers/pinctrl/meson/Makefile |1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1404 
 3 files changed, 1411 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index c80951d6caff..9ab537eb78a3 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
 config PINCTRL_MESON_AXG_PMX
bool
 
+config PINCTRL_MESON_G12A
+   bool "Meson g12a Soc pinctrl driver"
+   depends on ARM64
+   select PINCTRL_MESON_AXG_PMX
+   default y
+
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 3c6580c2d9d7..cf283f48f9d8 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
 obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
+obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
new file mode 100644
index ..d494492e98e9
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -0,0 +1,1404 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+static const struct pinctrl_pin_desc meson_g12a_periphs_pins[] = {
+   MESON_PIN(GPIOZ_0),
+   MESON_PIN(GPIOZ_1),
+   MESON_PIN(GPIOZ_2),
+   MESON_PIN(GPIOZ_3),
+   MESON_PIN(GPIOZ_4),
+   MESON_PIN(GPIOZ_5),
+   MESON_PIN(GPIOZ_6),
+   MESON_PIN(GPIOZ_7),
+   MESON_PIN(GPIOZ_8),
+   MESON_PIN(GPIOZ_9),
+   MESON_PIN(GPIOZ_10),
+   MESON_PIN(GPIOZ_11),
+   MESON_PIN(GPIOZ_12),
+   MESON_PIN(GPIOZ_13),
+   MESON_PIN(GPIOZ_14),
+   MESON_PIN(GPIOZ_15),
+   MESON_PIN(GPIOH_0),
+   MESON_PIN(GPIOH_1),
+   MESON_PIN(GPIOH_2),
+   MESON_PIN(GPIOH_3),
+   MESON_PIN(GPIOH_4),
+   MESON_PIN(GPIOH_5),
+   MESON_PIN(GPIOH_6),
+   MESON_PIN(GPIOH_7),
+   MESON_PIN(GPIOH_8),
+   MESON_PIN(BOOT_0),
+   MESON_PIN(BOOT_1),
+   MESON_PIN(BOOT_2),
+   MESON_PIN(BOOT_3),
+   MESON_PIN(BOOT_4),
+   MESON_PIN(BOOT_5),
+   MESON_PIN(BOOT_6),
+   MESON_PIN(BOOT_7),
+   MESON_PIN(BOOT_8),
+   MESON_PIN(BOOT_9),
+   MESON_PIN(BOOT_10),
+   MESON_PIN(BOOT_11),
+   MESON_PIN(BOOT_12),
+   MESON_PIN(BOOT_13),
+   MESON_PIN(BOOT_14),
+   MESON_PIN(BOOT_15),
+   MESON_PIN(GPIOC_0),
+   MESON_PIN(GPIOC_1),
+   MESON_PIN(GPIOC_2),
+   MESON_PIN(GPIOC_3),
+   MESON_PIN(GPIOC_4),
+   MESON_PIN(GPIOC_5),
+   MESON_PIN(GPIOC_6),
+   MESON_PIN(GPIOC_7),
+   MESON_PIN(GPIOA_0),
+   MESON_PIN(GPIOA_1),
+   MESON_PIN(GPIOA_2),
+   MESON_PIN(GPIOA_3),
+   MESON_PIN(GPIOA_4),
+   MESON_PIN(GPIOA_5),
+   MESON_PIN(GPIOA_6),
+   MESON_PIN(GPIOA_7),
+   MESON_PIN(GPIOA_8),
+   MESON_PIN(GPIOA_9),
+   MESON_PIN(GPIOA_10),
+   MESON_PIN(GPIOA_11),
+   MESON_PIN(GPIOA_12),
+   MESON_PIN(GPIOA_13),
+   MESON_PIN(GPIOA_14),
+   MESON_PIN(GPIOA_15),
+   MESON_PIN(GPIOX_0),
+   MESON_PIN(GPIOX_1),
+   MESON_PIN(GPIOX_2),
+   MESON_PIN(GPIOX_3),
+   MESON_PIN(GPIOX_4),
+   MESON_PIN(GPIOX_5),
+   MESON_PIN(GPIOX_6),
+   MESON_PIN(GPIOX_7),
+   MESON_PIN(GPIOX_8),
+   MESON_PIN(GPIOX_9),
+   MESON_PIN(GPIOX_10),
+   MESON_PIN(GPIOX_11),
+   MESON_PIN(GPIOX_12),
+   MESON_PIN(GPIOX_13),
+   MESON_PIN(GPIOX_1

[PATCH v3 1/2] documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin controllers

[Yixun Lan]

Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.

Acked-by: Martin Blumenstingl 
Reviewed-by: Rob Herring 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 .../bindings/pinctrl/meson,pinctrl.txt|   2 +
 include/dt-bindings/gpio/meson-g12a-gpio.h| 114 ++
 2 files changed, 116 insertions(+)
 create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 54ecb8ab7788..82ead40311f6 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -13,6 +13,8 @@ Required properties for the root node:
  "amlogic,meson-gxl-aobus-pinctrl"
  "amlogic,meson-axg-periphs-pinctrl"
  "amlogic,meson-axg-aobus-pinctrl"
+ "amlogic,meson-g12a-periphs-pinctrl"
+ "amlogic,meson-g12a-aobus-pinctrl"
  - reg: address and size of registers controlling irq functionality
 
 === GPIO sub-nodes ===
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h 
b/include/dt-bindings/gpio/meson-g12a-gpio.h
new file mode 100644
index ..f7bd69350d18
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ */
+
+#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
+#define _DT_BINDINGS_MESON_G12A_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0   0
+#define GPIOAO_1   1
+#define GPIOAO_2   2
+#define GPIOAO_3   3
+#define GPIOAO_4   4
+#define GPIOAO_5   5
+#define GPIOAO_6   6
+#define GPIOAO_7   7
+#define GPIOAO_8   8
+#define GPIOAO_9   9
+#define GPIOAO_10  10
+#define GPIOAO_11  11
+#define GPIOE_012
+#define GPIOE_113
+#define GPIOE_214
+
+/* Second GPIO chip */
+#define GPIOZ_00
+#define GPIOZ_11
+#define GPIOZ_22
+#define GPIOZ_33
+#define GPIOZ_44
+#define GPIOZ_55
+#define GPIOZ_66
+#define GPIOZ_77
+#define GPIOZ_88
+#define GPIOZ_99
+#define GPIOZ_10   10
+#define GPIOZ_11   11
+#define GPIOZ_12   12
+#define GPIOZ_13   13
+#define GPIOZ_14   14
+#define GPIOZ_15   15
+#define GPIOH_016
+#define GPIOH_117
+#define GPIOH_218
+#define GPIOH_319
+#define GPIOH_420
+#define GPIOH_521
+#define GPIOH_622
+#define GPIOH_723
+#define GPIOH_824
+#define BOOT_0 25
+#define BOOT_1 26
+#define BOOT_2 27
+#define BOOT_3 28
+#define BOOT_4 29
+#define BOOT_5 30
+#define BOOT_6 31
+#define BOOT_7 32
+#define BOOT_8 33
+#define BOOT_9 34
+#define BOOT_1035
+#define BOOT_1136
+#define BOOT_1237
+#define BOOT_1338
+#define BOOT_1439
+#define BOOT_1540
+#define GPIOC_041
+#define GPIOC_142
+#define GPIOC_243
+#define GPIOC_344
+#define GPIOC_445
+#define GPIOC_546
+#define GPIOC_647
+#define GPIOC_748
+#define GPIOA_049
+#define GPIOA_150
+#define GPIOA_251
+#define GPIOA_352
+#define GPIOA_453
+#define GPIOA_554
+#define GPIOA_655
+#define GPIOA_756
+#define GPIOA_857
+#define GPIOA_958
+#define GPIOA_10   59
+#define GPIOA_11   60
+#define GPIOA_12   61
+#define GPIOA_13   62
+#define GPIOA_14   63
+#define GPIOA_15   64
+#define GPIOX_065
+#define GPIOX_166
+#define GPIOX_267
+#define GPIOX_368
+#define GPIOX_469
+#define GPIOX_570
+#define GPIOX_671
+#define GPIOX_772
+#define GPIOX_873
+#define GPIOX_974
+#define GPIOX_10   75
+#define GPIOX_11   76
+#define GPIOX_12   77
+#define GPIOX_13   78
+#define GPIOX_14   79
+#define GPIOX_15   80
+#define GPIOX_16   81
+#define GPIOX_17   82
+#define GPIOX_18   83
+#define GPIOX_19   84
+
+#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
-- 
2.18.0

[PATCH v3 1/2] documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin controllers

[Yixun Lan]

Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.

Acked-by: Martin Blumenstingl 
Reviewed-by: Rob Herring 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 .../bindings/pinctrl/meson,pinctrl.txt|   2 +
 include/dt-bindings/gpio/meson-g12a-gpio.h| 114 ++
 2 files changed, 116 insertions(+)
 create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 54ecb8ab7788..82ead40311f6 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -13,6 +13,8 @@ Required properties for the root node:
  "amlogic,meson-gxl-aobus-pinctrl"
  "amlogic,meson-axg-periphs-pinctrl"
  "amlogic,meson-axg-aobus-pinctrl"
+ "amlogic,meson-g12a-periphs-pinctrl"
+ "amlogic,meson-g12a-aobus-pinctrl"
  - reg: address and size of registers controlling irq functionality
 
 === GPIO sub-nodes ===
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h 
b/include/dt-bindings/gpio/meson-g12a-gpio.h
new file mode 100644
index ..f7bd69350d18
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ */
+
+#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
+#define _DT_BINDINGS_MESON_G12A_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0   0
+#define GPIOAO_1   1
+#define GPIOAO_2   2
+#define GPIOAO_3   3
+#define GPIOAO_4   4
+#define GPIOAO_5   5
+#define GPIOAO_6   6
+#define GPIOAO_7   7
+#define GPIOAO_8   8
+#define GPIOAO_9   9
+#define GPIOAO_10  10
+#define GPIOAO_11  11
+#define GPIOE_012
+#define GPIOE_113
+#define GPIOE_214
+
+/* Second GPIO chip */
+#define GPIOZ_00
+#define GPIOZ_11
+#define GPIOZ_22
+#define GPIOZ_33
+#define GPIOZ_44
+#define GPIOZ_55
+#define GPIOZ_66
+#define GPIOZ_77
+#define GPIOZ_88
+#define GPIOZ_99
+#define GPIOZ_10   10
+#define GPIOZ_11   11
+#define GPIOZ_12   12
+#define GPIOZ_13   13
+#define GPIOZ_14   14
+#define GPIOZ_15   15
+#define GPIOH_016
+#define GPIOH_117
+#define GPIOH_218
+#define GPIOH_319
+#define GPIOH_420
+#define GPIOH_521
+#define GPIOH_622
+#define GPIOH_723
+#define GPIOH_824
+#define BOOT_0 25
+#define BOOT_1 26
+#define BOOT_2 27
+#define BOOT_3 28
+#define BOOT_4 29
+#define BOOT_5 30
+#define BOOT_6 31
+#define BOOT_7 32
+#define BOOT_8 33
+#define BOOT_9 34
+#define BOOT_1035
+#define BOOT_1136
+#define BOOT_1237
+#define BOOT_1338
+#define BOOT_1439
+#define BOOT_1540
+#define GPIOC_041
+#define GPIOC_142
+#define GPIOC_243
+#define GPIOC_344
+#define GPIOC_445
+#define GPIOC_546
+#define GPIOC_647
+#define GPIOC_748
+#define GPIOA_049
+#define GPIOA_150
+#define GPIOA_251
+#define GPIOA_352
+#define GPIOA_453
+#define GPIOA_554
+#define GPIOA_655
+#define GPIOA_756
+#define GPIOA_857
+#define GPIOA_958
+#define GPIOA_10   59
+#define GPIOA_11   60
+#define GPIOA_12   61
+#define GPIOA_13   62
+#define GPIOA_14   63
+#define GPIOA_15   64
+#define GPIOX_065
+#define GPIOX_166
+#define GPIOX_267
+#define GPIOX_368
+#define GPIOX_469
+#define GPIOX_570
+#define GPIOX_671
+#define GPIOX_772
+#define GPIOX_873
+#define GPIOX_974
+#define GPIOX_10   75
+#define GPIOX_11   76
+#define GPIOX_12   77
+#define GPIOX_13   78
+#define GPIOX_14   79
+#define GPIOX_15   80
+#define GPIOX_16   81
+#define GPIOX_17   82
+#define GPIOX_18   83
+#define GPIOX_19   84
+
+#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
-- 
2.18.0

Re: [PATCH 3/4] ARM64: dts: meson-gx: add dmcbus and canvas nodes.

[Yixun Lan]

hi Maxime:

On Sun, Aug 5, 2018 at 4:02 AM, Maxime Jourdan  wrote:
>>> +   sysctrl_DMC: system-controller@0 {
>>> +   compatible = 
>>> "amlogic,meson-gx-dmc-sysctrl", "syscon", "simple-mfd";
>>
>> we'd like to drop 'meson-' prefix, so better using "amlogic,gx-dmc-sysctrl",
>> please take a look at the discussion here [1]
>>
>> [1] https://lkml.kernel.org/r/7hk1prmg4w@baylibre.com
>>
>
> On that subject, should I remove the meson keyword from dts only, or
> from everything ?
>
remove the 'meson-' from dts is enough..

> e.g use amlogic_canvas_* symbols instead of meson_canvas_*, name the
> source file "amlogic-canvas.c", etc. ?
>
Actually, I'd suggest to keep using meson_canvas_* in the code for the
consistency,
unless Kevin or Jerome/Neil has something to say?

Yixun

Re: [PATCH 3/4] ARM64: dts: meson-gx: add dmcbus and canvas nodes.

[Yixun Lan]

hi Maxime:

On Sun, Aug 5, 2018 at 4:02 AM, Maxime Jourdan  wrote:
>>> +   sysctrl_DMC: system-controller@0 {
>>> +   compatible = 
>>> "amlogic,meson-gx-dmc-sysctrl", "syscon", "simple-mfd";
>>
>> we'd like to drop 'meson-' prefix, so better using "amlogic,gx-dmc-sysctrl",
>> please take a look at the discussion here [1]
>>
>> [1] https://lkml.kernel.org/r/7hk1prmg4w@baylibre.com
>>
>
> On that subject, should I remove the meson keyword from dts only, or
> from everything ?
>
remove the 'meson-' from dts is enough..

> e.g use amlogic_canvas_* symbols instead of meson_canvas_*, name the
> source file "amlogic-canvas.c", etc. ?
>
Actually, I'd suggest to keep using meson_canvas_* in the code for the
consistency,
unless Kevin or Jerome/Neil has something to say?

Yixun

Re: [PATCH 1/4] soc: amlogic: add meson-canvas driver

[Yixun Lan]

HI Maxime

thanks for contributing the patches ;-)

On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan  wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those SoCs like vdec/vpu rely on those canvas to read/write
> pixels.
>
> Signed-off-by: Maxime Jourdan 
> ---
>  drivers/soc/amlogic/Kconfig  |   7 +
>  drivers/soc/amlogic/Makefile |   1 +
>  drivers/soc/amlogic/meson-canvas.c   | 182 +++
>  include/linux/soc/amlogic/meson-canvas.h |  37 +
>  4 files changed, 227 insertions(+)
>  create mode 100644 drivers/soc/amlogic/meson-canvas.c
>  create mode 100644 include/linux/soc/amlogic/meson-canvas.h
>
> diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
> index b04f6e4aedbc..5bd049899d88 100644
> --- a/drivers/soc/amlogic/Kconfig
> +++ b/drivers/soc/amlogic/Kconfig
> @@ -1,5 +1,12 @@
>  menu "Amlogic SoC drivers"
>
> +config MESON_CANVAS
> +   bool "Amlogic Meson Canvas driver"
shouldn't this a 'tristate'? since you'd make the driver a kernel module..

> +   depends on ARCH_MESON || COMPILE_TEST
> +   default ARCH_MESON
> +   help
> + Say yes to support the canvas IP within Amlogic Meson Soc family.
> +
>  config MESON_GX_SOCINFO
> bool "Amlogic Meson GX SoC Information driver"
> depends on ARCH_MESON || COMPILE_TEST
> diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
> index 8fa321893928..0ab16d35ac36 100644
> --- a/drivers/soc/amlogic/Makefile
> +++ b/drivers/soc/amlogic/Makefile
> @@ -1,3 +1,4 @@
> +obj-$(CONFIG_MESON_CANVAS) += meson-canvas.o
>  obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
>  obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
>  obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
> diff --git a/drivers/soc/amlogic/meson-canvas.c 
> b/drivers/soc/amlogic/meson-canvas.c
> new file mode 100644
> index ..671eb89c8904
> --- /dev/null
> +++ b/drivers/soc/amlogic/meson-canvas.c
> @@ -0,0 +1,182 @@
> +/*
> + * Copyright (C) 2018 Maxime Jourdan
> + * Copyright (C) 2016 BayLibre, SAS
> + * Author: Neil Armstrong 
> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> + * Copyright (C) 2014 Endless Mobile
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see .
> + */
use SPDX license header as Neil already mentioned
check doc: Documentation/process/license-rules.rst

> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define NUM_CANVAS 256
> +
> +/* DMC Registers */
> +#define DMC_CAV_LUT_DATAL  0x48 /* 0x12 offset in data sheet */
> +   #define CANVAS_WIDTH_LBIT   29
> +   #define CANVAS_WIDTH_LWID   3
> +#define DMC_CAV_LUT_DATAH  0x4c /* 0x13 offset in data sheet */
> +   #define CANVAS_WIDTH_HBIT   0
> +   #define CANVAS_HEIGHT_BIT   9
> +   #define CANVAS_BLKMODE_BIT  24
> +#define DMC_CAV_LUT_ADDR   0x50 /* 0x14 offset in data sheet */
> +   #define CANVAS_LUT_WR_EN(0x2 << 8)
> +   #define CANVAS_LUT_RD_EN(0x1 << 8)
> +
> +struct meson_canvas {
> +   struct device *dev;
> +   struct regmap *regmap_dmc;
> +   struct mutex lock;
> +   u8 used[NUM_CANVAS];
> +};
> +
> +static struct meson_canvas canvas = { 0 };
> +
> +static int meson_canvas_setup(uint8_t canvas_index, uint32_t addr,
> +   uint32_t stride, uint32_t height,
> +   unsigned int wrap,
> +   unsigned int blkmode,
> +   unsigned int endian)
use "./scripts/checkpatch.pl --strict" to check
you will get a few complaints..

> +{
> +   struct regmap *regmap = canvas.regmap_dmc;
> +   u32 val;
> +
> +   mutex_lock();
> +
> +   if (!canvas.used[canvas_index]) {
> +   dev_err(canvas.dev,
> +   "Trying to setup non allocated canvas %u\n",
> +   canvas_index);
> +   mutex_unlock();
> +   return -EINVAL;
> +   }
> +
> +   regmap_write(regmap, DMC_CAV_LUT_DATAL,
> +   ((addr + 7) >> 3) |
> +   (((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
> +
> +   regmap_write(regmap, 

Re: [PATCH 1/4] soc: amlogic: add meson-canvas driver

[Yixun Lan]

HI Maxime

thanks for contributing the patches ;-)

On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan  wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those SoCs like vdec/vpu rely on those canvas to read/write
> pixels.
>
> Signed-off-by: Maxime Jourdan 
> ---
>  drivers/soc/amlogic/Kconfig  |   7 +
>  drivers/soc/amlogic/Makefile |   1 +
>  drivers/soc/amlogic/meson-canvas.c   | 182 +++
>  include/linux/soc/amlogic/meson-canvas.h |  37 +
>  4 files changed, 227 insertions(+)
>  create mode 100644 drivers/soc/amlogic/meson-canvas.c
>  create mode 100644 include/linux/soc/amlogic/meson-canvas.h
>
> diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
> index b04f6e4aedbc..5bd049899d88 100644
> --- a/drivers/soc/amlogic/Kconfig
> +++ b/drivers/soc/amlogic/Kconfig
> @@ -1,5 +1,12 @@
>  menu "Amlogic SoC drivers"
>
> +config MESON_CANVAS
> +   bool "Amlogic Meson Canvas driver"
shouldn't this a 'tristate'? since you'd make the driver a kernel module..

> +   depends on ARCH_MESON || COMPILE_TEST
> +   default ARCH_MESON
> +   help
> + Say yes to support the canvas IP within Amlogic Meson Soc family.
> +
>  config MESON_GX_SOCINFO
> bool "Amlogic Meson GX SoC Information driver"
> depends on ARCH_MESON || COMPILE_TEST
> diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
> index 8fa321893928..0ab16d35ac36 100644
> --- a/drivers/soc/amlogic/Makefile
> +++ b/drivers/soc/amlogic/Makefile
> @@ -1,3 +1,4 @@
> +obj-$(CONFIG_MESON_CANVAS) += meson-canvas.o
>  obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
>  obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
>  obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
> diff --git a/drivers/soc/amlogic/meson-canvas.c 
> b/drivers/soc/amlogic/meson-canvas.c
> new file mode 100644
> index ..671eb89c8904
> --- /dev/null
> +++ b/drivers/soc/amlogic/meson-canvas.c
> @@ -0,0 +1,182 @@
> +/*
> + * Copyright (C) 2018 Maxime Jourdan
> + * Copyright (C) 2016 BayLibre, SAS
> + * Author: Neil Armstrong 
> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> + * Copyright (C) 2014 Endless Mobile
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see .
> + */
use SPDX license header as Neil already mentioned
check doc: Documentation/process/license-rules.rst

> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define NUM_CANVAS 256
> +
> +/* DMC Registers */
> +#define DMC_CAV_LUT_DATAL  0x48 /* 0x12 offset in data sheet */
> +   #define CANVAS_WIDTH_LBIT   29
> +   #define CANVAS_WIDTH_LWID   3
> +#define DMC_CAV_LUT_DATAH  0x4c /* 0x13 offset in data sheet */
> +   #define CANVAS_WIDTH_HBIT   0
> +   #define CANVAS_HEIGHT_BIT   9
> +   #define CANVAS_BLKMODE_BIT  24
> +#define DMC_CAV_LUT_ADDR   0x50 /* 0x14 offset in data sheet */
> +   #define CANVAS_LUT_WR_EN(0x2 << 8)
> +   #define CANVAS_LUT_RD_EN(0x1 << 8)
> +
> +struct meson_canvas {
> +   struct device *dev;
> +   struct regmap *regmap_dmc;
> +   struct mutex lock;
> +   u8 used[NUM_CANVAS];
> +};
> +
> +static struct meson_canvas canvas = { 0 };
> +
> +static int meson_canvas_setup(uint8_t canvas_index, uint32_t addr,
> +   uint32_t stride, uint32_t height,
> +   unsigned int wrap,
> +   unsigned int blkmode,
> +   unsigned int endian)
use "./scripts/checkpatch.pl --strict" to check
you will get a few complaints..

> +{
> +   struct regmap *regmap = canvas.regmap_dmc;
> +   u32 val;
> +
> +   mutex_lock();
> +
> +   if (!canvas.used[canvas_index]) {
> +   dev_err(canvas.dev,
> +   "Trying to setup non allocated canvas %u\n",
> +   canvas_index);
> +   mutex_unlock();
> +   return -EINVAL;
> +   }
> +
> +   regmap_write(regmap, DMC_CAV_LUT_DATAL,
> +   ((addr + 7) >> 3) |
> +   (((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
> +
> +   regmap_write(regmap, 

Re: [PATCH 3/4] ARM64: dts: meson-gx: add dmcbus and canvas nodes.

[Yixun Lan]

Hi Maxime

great job! thanks for contributing the patches..

On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan  wrote:
> Wrap the canvas node in a syscon node.
>
> Signed-off-by: Maxime Jourdan 
> ---
>  arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 17 +
>  1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi 
> b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index b8dc4dbb391b..d104b9e111fb 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -423,6 +423,23 @@
> };
> };
>
> +   dmcbus: bus@c8838000 {
> +   compatible = "simple-bus";
> +   reg = <0x0 0xc8838000 0x0 0x1000>;
> +   #address-cells = <2>;
> +   #size-cells = <2>;
> +   ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x1000>;
> +
> +   sysctrl_DMC: system-controller@0 {
> +   compatible = "amlogic,meson-gx-dmc-sysctrl", 
> "syscon", "simple-mfd";

we'd like to drop 'meson-' prefix, so better using "amlogic,gx-dmc-sysctrl",
please take a look at the discussion here [1]

[1] https://lkml.kernel.org/r/7hk1prmg4w@baylibre.com

> +   reg = <0x0 0x0 0x0 0x1000>;
> +
> +   canvas: canvas-provider@0 {
> +   compatible = "amlogic,meson-canvas";
ditto

> +   };
> +   };
> +   };
> +
> hiubus: bus@c883c000 {
> compatible = "simple-bus";
> reg = <0x0 0xc883c000 0x0 0x2000>;
> --
> 2.17.1
>
>
> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH 3/4] ARM64: dts: meson-gx: add dmcbus and canvas nodes.

[Yixun Lan]

Hi Maxime

great job! thanks for contributing the patches..

On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan  wrote:
> Wrap the canvas node in a syscon node.
>
> Signed-off-by: Maxime Jourdan 
> ---
>  arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 17 +
>  1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi 
> b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index b8dc4dbb391b..d104b9e111fb 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -423,6 +423,23 @@
> };
> };
>
> +   dmcbus: bus@c8838000 {
> +   compatible = "simple-bus";
> +   reg = <0x0 0xc8838000 0x0 0x1000>;
> +   #address-cells = <2>;
> +   #size-cells = <2>;
> +   ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x1000>;
> +
> +   sysctrl_DMC: system-controller@0 {
> +   compatible = "amlogic,meson-gx-dmc-sysctrl", 
> "syscon", "simple-mfd";

we'd like to drop 'meson-' prefix, so better using "amlogic,gx-dmc-sysctrl",
please take a look at the discussion here [1]

[1] https://lkml.kernel.org/r/7hk1prmg4w@baylibre.com

> +   reg = <0x0 0x0 0x0 0x1000>;
> +
> +   canvas: canvas-provider@0 {
> +   compatible = "amlogic,meson-canvas";
ditto

> +   };
> +   };
> +   };
> +
> hiubus: bus@c883c000 {
> compatible = "simple-bus";
> reg = <0x0 0xc883c000 0x0 0x2000>;
> --
> 2.17.1
>
>
> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [RFC PATCH v2 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

Hi Boris


On 08/02/2018 05:50 AM, Boris Brezillon wrote:
> Hi Yixun,
> 
> On Thu, 19 Jul 2018 17:46:12 +0800
> Yixun Lan  wrote:
> 
> I haven't finished reviewing the driver yet (I'll try to do that later
> this week), but I already pointed a few things to fix/improve.
> 

thanks for the fully review, we really appreciate your time ;-)

I will comment on a few general items first, then clarify others after
talking to the NAND/ASIC team

>> +
>> +static int meson_nfc_exec_op(struct nand_chip *chip,
>> + const struct nand_operation *op, bool check_only)
>> +{
>> +
>> +static int meson_nfc_buffer_init(struct mtd_info *mtd)
>> +{
>> +struct nand_chip *nand = mtd_to_nand(mtd);
>> +struct meson_nfc *nfc = nand_get_controller_data(nand);
>> +int info_bytes, page_bytes;
>> +int nsectors;
>> +
>> +nsectors = mtd->writesize / nand->ecc.size;
>> +info_bytes = nsectors * PER_INFO_BYTE;
>> +page_bytes = mtd->writesize + mtd->oobsize;
>> +
>> +if (nfc->data_buf && nfc->info_buf)
>> +return 0;
>> +
>> +nfc->data_buf = kmalloc(page_bytes, GFP_KERNEL);
> 
> I'm pretty sure that does not work if you have several chips. Either
> you have one buffer tied to the NFC, and it has to be large enough to
> handle the NAND with the largest page, or you have one buffer per chip.
> 
em, we will fix this in next version,

>> +if (!nfc->data_buf)
>> +return -ENOMEM;
>> +
>> +nfc->info_buf = kmalloc(info_bytes, GFP_KERNEL);
>> +if (!nfc->info_buf) {
>> +kfree(nfc->data_buf);
>> +return -ENOMEM;
>> +}
>> +
> 
> Those buffers are not removed in the cleanup/error path.
> 
indeed, thanks for pointing out.
we actually realized this error after sent out this patch ..
>> +return 0;
>> +}
>> +
>> +static int meson_nfc_calc_set_timing(struct meson_nfc *nfc,
>> + int rc_min, int rea_max, int rhoh_min)
..

>> +
>> +static int
>> +meson_nfc_nand_chip_init(struct device *dev,
>> + struct meson_nfc *nfc, struct device_node *np)
>> +{
>> +struct meson_nfc_nand_chip *chip;
>> +struct nand_chip *nand;
>> +struct mtd_info *mtd;
>> +int ret, nsels, i, len = 0;
>> +char cs_id[16];
>> +u32 tmp;
>> +
>> +if (!of_get_property(np, "reg", ))
>> +return -EINVAL;
>> +
>> +nsels /= sizeof(u32);
>> +if (!nsels || nsels > MAX_CE_NUM) {
>> +dev_err(dev, "invalid reg property size\n");
>> +return -EINVAL;
>> +}
>> +
>> +chip = devm_kzalloc(dev, sizeof(*chip) + (nsels * sizeof(u8)),
>> +GFP_KERNEL);
>> +if (!chip)
>> +return -ENOMEM;
>> +
>> +chip->nsels = nsels;
>> +
>> +for (i = 0; i < nsels; i++) {
>> +ret = of_property_read_u32_index(np, "reg", i, );
>> +if (ret) {
>> +dev_err(dev, "could not retrieve reg property: %d\n",
>> +ret);
>> +return ret;
>> +}
>> +chip->sels[i] = tmp;
> 
> You should probably keep track of all the already assigned CS lines, to
> prevent situations where the same controller-CS is used twice
> (copy error when writing the DT).
> 

will do in next version, we would consider to use a bitmap for tracking
this ..
>> +len += snprintf(cs_id + len, 16, "%s%d", i ? "-" : ".", tmp);
> 
> Hm, do we really need to be that accurate? I'd suggest using the first
> CS only.
> 
ok, this would much simple..
thanks for the suggestion and the detail sample code in the following
section ;-)
>> +}
>> +
>> +chip->is_scramble =
>> +of_property_read_bool(np, "amlogic,nand-enable-scrambler");
> 
> I think I already complained about that :P. If you think this is still
> needed (meaning that the autodetection + NAND_NEED_SCRAMBLING flag are
> not enough), I'll need a detailed explanation ;-).
> 

yes, we saw this kind comment in DT patch already, we will try to fix this..
>> +
>> +nand = >nand;
>> +nand_set_flash_node(nand, np);
>> +nand_set_controller_data(nand, nfc);
>> +
>> +nand->options |= NAND_USE_BOUNCE_BUFFER;
>> +nand->select_chip = meson_nfc_select_chip;
>> +

Re: [RFC PATCH v2 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

Hi Boris


On 08/02/2018 05:50 AM, Boris Brezillon wrote:
> Hi Yixun,
> 
> On Thu, 19 Jul 2018 17:46:12 +0800
> Yixun Lan  wrote:
> 
> I haven't finished reviewing the driver yet (I'll try to do that later
> this week), but I already pointed a few things to fix/improve.
> 

thanks for the fully review, we really appreciate your time ;-)

I will comment on a few general items first, then clarify others after
talking to the NAND/ASIC team

>> +
>> +static int meson_nfc_exec_op(struct nand_chip *chip,
>> + const struct nand_operation *op, bool check_only)
>> +{
>> +
>> +static int meson_nfc_buffer_init(struct mtd_info *mtd)
>> +{
>> +struct nand_chip *nand = mtd_to_nand(mtd);
>> +struct meson_nfc *nfc = nand_get_controller_data(nand);
>> +int info_bytes, page_bytes;
>> +int nsectors;
>> +
>> +nsectors = mtd->writesize / nand->ecc.size;
>> +info_bytes = nsectors * PER_INFO_BYTE;
>> +page_bytes = mtd->writesize + mtd->oobsize;
>> +
>> +if (nfc->data_buf && nfc->info_buf)
>> +return 0;
>> +
>> +nfc->data_buf = kmalloc(page_bytes, GFP_KERNEL);
> 
> I'm pretty sure that does not work if you have several chips. Either
> you have one buffer tied to the NFC, and it has to be large enough to
> handle the NAND with the largest page, or you have one buffer per chip.
> 
em, we will fix this in next version,

>> +if (!nfc->data_buf)
>> +return -ENOMEM;
>> +
>> +nfc->info_buf = kmalloc(info_bytes, GFP_KERNEL);
>> +if (!nfc->info_buf) {
>> +kfree(nfc->data_buf);
>> +return -ENOMEM;
>> +}
>> +
> 
> Those buffers are not removed in the cleanup/error path.
> 
indeed, thanks for pointing out.
we actually realized this error after sent out this patch ..
>> +return 0;
>> +}
>> +
>> +static int meson_nfc_calc_set_timing(struct meson_nfc *nfc,
>> + int rc_min, int rea_max, int rhoh_min)
..

>> +
>> +static int
>> +meson_nfc_nand_chip_init(struct device *dev,
>> + struct meson_nfc *nfc, struct device_node *np)
>> +{
>> +struct meson_nfc_nand_chip *chip;
>> +struct nand_chip *nand;
>> +struct mtd_info *mtd;
>> +int ret, nsels, i, len = 0;
>> +char cs_id[16];
>> +u32 tmp;
>> +
>> +if (!of_get_property(np, "reg", ))
>> +return -EINVAL;
>> +
>> +nsels /= sizeof(u32);
>> +if (!nsels || nsels > MAX_CE_NUM) {
>> +dev_err(dev, "invalid reg property size\n");
>> +return -EINVAL;
>> +}
>> +
>> +chip = devm_kzalloc(dev, sizeof(*chip) + (nsels * sizeof(u8)),
>> +GFP_KERNEL);
>> +if (!chip)
>> +return -ENOMEM;
>> +
>> +chip->nsels = nsels;
>> +
>> +for (i = 0; i < nsels; i++) {
>> +ret = of_property_read_u32_index(np, "reg", i, );
>> +if (ret) {
>> +dev_err(dev, "could not retrieve reg property: %d\n",
>> +ret);
>> +return ret;
>> +}
>> +chip->sels[i] = tmp;
> 
> You should probably keep track of all the already assigned CS lines, to
> prevent situations where the same controller-CS is used twice
> (copy error when writing the DT).
> 

will do in next version, we would consider to use a bitmap for tracking
this ..
>> +len += snprintf(cs_id + len, 16, "%s%d", i ? "-" : ".", tmp);
> 
> Hm, do we really need to be that accurate? I'd suggest using the first
> CS only.
> 
ok, this would much simple..
thanks for the suggestion and the detail sample code in the following
section ;-)
>> +}
>> +
>> +chip->is_scramble =
>> +of_property_read_bool(np, "amlogic,nand-enable-scrambler");
> 
> I think I already complained about that :P. If you think this is still
> needed (meaning that the autodetection + NAND_NEED_SCRAMBLING flag are
> not enough), I'll need a detailed explanation ;-).
> 

yes, we saw this kind comment in DT patch already, we will try to fix this..
>> +
>> +nand = >nand;
>> +nand_set_flash_node(nand, np);
>> +nand_set_controller_data(nand, nfc);
>> +
>> +nand->options |= NAND_USE_BOUNCE_BUFFER;
>> +nand->select_chip = meson_nfc_select_chip;
>> +

[PATCH] clk: meson-axg: pcie: drop the mpll3 clock parent

[Yixun Lan]

We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.

Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: Jianxin Qin 
Signed-off-by: Yixun Lan 

---
hi Jerome:
  I'm sorry we found this during latest PCIe driver test.

  I'm fine with either pull this as a fixup for 4.18 or
queued for next 4.19, since the PCIe driver is not merged yet,
just do as you feel what's fit best, thanks.

Yixun
---
 drivers/clk/meson/axg.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 2d458092884a..246c23df64a8 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -700,12 +700,14 @@ static struct clk_regmap axg_pcie_mux = {
.offset = HHI_PCIE_PLL_CNTL6,
.mask = 0x1,
.shift = 2,
+   /* skip the parent mpll3, reserved for debug */
+   .table = (u32[]){ 1 },
},
.hw.init = &(struct clk_init_data){
.name = "pcie_mux",
.ops = _regmap_mux_ops,
-   .parent_names = (const char *[]){ "mpll3", "pcie_pll" },
-   .num_parents = 2,
+   .parent_names = (const char *[]){ "pcie_pll" },
+   .num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
 };
-- 
2.18.0

[PATCH] clk: meson-axg: pcie: drop the mpll3 clock parent

[Yixun Lan]

We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.

Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: Jianxin Qin 
Signed-off-by: Yixun Lan 

---
hi Jerome:
  I'm sorry we found this during latest PCIe driver test.

  I'm fine with either pull this as a fixup for 4.18 or
queued for next 4.19, since the PCIe driver is not merged yet,
just do as you feel what's fit best, thanks.

Yixun
---
 drivers/clk/meson/axg.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 2d458092884a..246c23df64a8 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -700,12 +700,14 @@ static struct clk_regmap axg_pcie_mux = {
.offset = HHI_PCIE_PLL_CNTL6,
.mask = 0x1,
.shift = 2,
+   /* skip the parent mpll3, reserved for debug */
+   .table = (u32[]){ 1 },
},
.hw.init = &(struct clk_init_data){
.name = "pcie_mux",
.ops = _regmap_mux_ops,
-   .parent_names = (const char *[]){ "mpll3", "pcie_pll" },
-   .num_parents = 2,
+   .parent_names = (const char *[]){ "pcie_pll" },
+   .num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
 };
-- 
2.18.0

Re: [PATCH v3 2/2] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

HI Stephen:

On 07/26/2018 11:20 PM, Stephen Boyd wrote:
> Quoting Yixun Lan (2018-07-12 14:12:44)
>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>> new file mode 100644
>> index ..36c4c7cd69a6
>> --- /dev/null
>> +++ b/drivers/clk/meson/mmc-clkc.c
>> @@ -0,0 +1,367 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Amlogic Meson MMC Sub Clock Controller Driver
>> + *
>> + * Copyright (c) 2017 Baylibre SAS.
>> + * Author: Jerome Brunet 
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Yixun Lan 
>> + */
>> +
>> +#include 
> 
> Is this include used?
> 
this is needed by clk_get_rate()
see drivers/clk/meson/mmc-clkc.c:204

>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "clkc.h"
>> +
>> +
>> +static struct clk_regmap *
>> +mmc_clkc_register_other_clk(struct device *dev, struct regmap *map,
>> +   char *suffix, char *parent_suffix,
>> +   unsigned long flags,
>> +   const struct clk_ops *ops, void *data)
>> +{
>> +   struct clk_init_data init;
>> +   struct clk_regmap *clk;
>> +   char *parent;
>> +
>> +   parent = kasprintf(GFP_KERNEL, "%s#%s", dev_name(dev), 
>> parent_suffix);
>> +   if (!parent)
>> +   return ERR_PTR(-ENOMEM);
>> +
>> +   init.ops = ops;
>> +   init.flags = flags;
>> +   init.parent_names = (const char* const []){ parent, };
> 
> Can't this just be ?
sure, I can fix this

> 
>> +   init.num_parents = 1;
>> +
>> +   clk = mmc_clkc_register_clk(dev, map, , suffix, data);
>> +   if (IS_ERR(clk))
>> +   dev_err(dev, "Core %s clock registration failed\n", suffix);
>> +
>> +   kfree(parent);
>> +   return clk;
>> +}
>> +
>> +static int mmc_clkc_probe(struct platform_device *pdev)
>> +{
>> +   struct clk_hw_onecell_data *onecell_data;
>> +   struct device *dev = >dev;
>> +   struct mmc_clkc_data *data;
>> +   struct regmap *map;
>> +   struct clk_regmap *mux, *div, *core, *rx, *tx;
>> +
>> +   data = (struct mmc_clkc_data *)of_device_get_match_data(dev);
> 
> This cast is unnecessary. Pleas remove.
> 
Ok, I will try to fix in next version


this was trying to silence the ’const‘ cast warning [1]
I could make a 'const struct mmc_clkc_data *data' declare, but need to
fix further cast warning issue..


[1] drivers/clk/meson/mmc-clkc.c: In function ‘mmc_clkc_probe’:
drivers/clk/meson/mmc-clkc.c:302:7: warning: assignment discards ‘const’
qualifier from pointer target type [-Wdiscarded-qualifiers]
  data = of_device_get_match_data(dev);
   ^

Re: [PATCH v3 2/2] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

HI Stephen:

On 07/26/2018 11:20 PM, Stephen Boyd wrote:
> Quoting Yixun Lan (2018-07-12 14:12:44)
>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>> new file mode 100644
>> index ..36c4c7cd69a6
>> --- /dev/null
>> +++ b/drivers/clk/meson/mmc-clkc.c
>> @@ -0,0 +1,367 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Amlogic Meson MMC Sub Clock Controller Driver
>> + *
>> + * Copyright (c) 2017 Baylibre SAS.
>> + * Author: Jerome Brunet 
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Yixun Lan 
>> + */
>> +
>> +#include 
> 
> Is this include used?
> 
this is needed by clk_get_rate()
see drivers/clk/meson/mmc-clkc.c:204

>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "clkc.h"
>> +
>> +
>> +static struct clk_regmap *
>> +mmc_clkc_register_other_clk(struct device *dev, struct regmap *map,
>> +   char *suffix, char *parent_suffix,
>> +   unsigned long flags,
>> +   const struct clk_ops *ops, void *data)
>> +{
>> +   struct clk_init_data init;
>> +   struct clk_regmap *clk;
>> +   char *parent;
>> +
>> +   parent = kasprintf(GFP_KERNEL, "%s#%s", dev_name(dev), 
>> parent_suffix);
>> +   if (!parent)
>> +   return ERR_PTR(-ENOMEM);
>> +
>> +   init.ops = ops;
>> +   init.flags = flags;
>> +   init.parent_names = (const char* const []){ parent, };
> 
> Can't this just be ?
sure, I can fix this

> 
>> +   init.num_parents = 1;
>> +
>> +   clk = mmc_clkc_register_clk(dev, map, , suffix, data);
>> +   if (IS_ERR(clk))
>> +   dev_err(dev, "Core %s clock registration failed\n", suffix);
>> +
>> +   kfree(parent);
>> +   return clk;
>> +}
>> +
>> +static int mmc_clkc_probe(struct platform_device *pdev)
>> +{
>> +   struct clk_hw_onecell_data *onecell_data;
>> +   struct device *dev = >dev;
>> +   struct mmc_clkc_data *data;
>> +   struct regmap *map;
>> +   struct clk_regmap *mux, *div, *core, *rx, *tx;
>> +
>> +   data = (struct mmc_clkc_data *)of_device_get_match_data(dev);
> 
> This cast is unnecessary. Pleas remove.
> 
Ok, I will try to fix in next version


this was trying to silence the ’const‘ cast warning [1]
I could make a 'const struct mmc_clkc_data *data' declare, but need to
fix further cast warning issue..


[1] drivers/clk/meson/mmc-clkc.c: In function ‘mmc_clkc_probe’:
drivers/clk/meson/mmc-clkc.c:302:7: warning: assignment discards ‘const’
qualifier from pointer target type [-Wdiscarded-qualifiers]
  data = of_device_get_match_data(dev);
   ^

Re: [PATCH v3 1/2] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

HI Rob

On 07/25/2018 07:29 AM, Rob Herring wrote:
> On Thu, Jul 12, 2018 at 09:12:43PM +0000, Yixun Lan wrote:
>> Document the MMC sub clock controller driver, the potential consumer
>> of this driver is MMC or NAND. Also add three clock bindings IDs which
>> provided by this driver.
>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
>>  .../clock/amlogic,meson-mmc-clkc.h| 16 ++
>>  2 files changed, 47 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>  create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
> 
> Reviewed-by: Rob Herring 
> 

Thanks for the review!

There is a discussion about dropping "meson-" prefix in the compatible
string[1]

So, I will send another version with the new compatible name adjusted
from "amlogic,meson-axg-mmc-clkc" to "amlogic,axg-mmc-clkc"..
probably also rename the dt-bindings header file to amlogc,mmc-clkc.h

[1]  https://lkml.kernel.org/r/7hk1prmg4w@baylibre.com


Yixun

Re: [PATCH v3 1/2] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

HI Rob

On 07/25/2018 07:29 AM, Rob Herring wrote:
> On Thu, Jul 12, 2018 at 09:12:43PM +0000, Yixun Lan wrote:
>> Document the MMC sub clock controller driver, the potential consumer
>> of this driver is MMC or NAND. Also add three clock bindings IDs which
>> provided by this driver.
>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
>>  .../clock/amlogic,meson-mmc-clkc.h| 16 ++
>>  2 files changed, 47 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>  create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
> 
> Reviewed-by: Rob Herring 
> 

Thanks for the review!

There is a discussion about dropping "meson-" prefix in the compatible
string[1]

So, I will send another version with the new compatible name adjusted
from "amlogic,meson-axg-mmc-clkc" to "amlogic,axg-mmc-clkc"..
probably also rename the dt-bindings header file to amlogc,mmc-clkc.h

[1]  https://lkml.kernel.org/r/7hk1prmg4w@baylibre.com


Yixun

Re: [PATCH] arm64: dts: meson: Switch simple-mfd and syscon order

[Yixun Lan]

HI Neil

On 07/26/2018 10:13 PM, Neil Armstrong wrote:
> The order between "syscon" and "simple-mfd" is important because in these
> particular cases, the node needs to be first a "simple-mfd" to expose
> it's sub-nodes, and later on a "syscon" to permit other nodes to access
> this register space through the "syscon" mechanism.
> 

could you explain a bit which specific case that it need compatible
"simple-mfd" come first? is this a problem in kernel side? because I see
you have a comment below about problem in U-Boot..


also while Rob review the mmc-clkc patch, he raise a suggestion to  drop
"syscon" in drivers/mfd/syscon.c, see [1], will that solve or affect
your problem?

[1]
https://lkml.kernel.org/r/CAL_Jsq+r+7BaJAPBn3L26sdxATVyDiuC=v3xe+yz0-27q0r...@mail.gmail.com

> Signed-off-by: Neil Armstrong 
> ---
> This also has a consequence for U-Boot since the U-Boot DM is much simpler
> and can only associate a single device to a node, thus here we want these
> nodes to be an mfd bus to be able to probe the sub-nodes.
> 
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  arch/arm64/boot/dts/amlogic/meson-gx.dtsi  | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 6adc8d3..3f0de9d 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -342,7 +342,7 @@
>   ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
>  
>   sysctrl: system-controller@0 {
> - compatible = "amlogic,meson-axg-hhi-sysctrl", 
> "syscon", "simple-mfd";
> + compatible = "amlogic,meson-axg-hhi-sysctrl", 
> "simple-mfd", "syscon";
>   reg = <0 0 0 0x400>;
>  
>   clkc: clock-controller {
> @@ -1180,7 +1180,7 @@
>   ranges = <0x0 0x0 0x0 0xff80 0x0 0x10>;
>  
>   sysctrl_AO: sys-ctrl@0 {
> - compatible = "amlogic,meson-axg-ao-sysctrl", 
> "syscon", "simple-mfd";
> + compatible = "amlogic,meson-axg-ao-sysctrl", 
> "simple-mfd", "syscon";
>   reg =  <0x0 0x0 0x0 0x100>;
>  
>   clkc_AO: clock-controller {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi 
> b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index b8dc4db..d88699f 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -344,7 +344,7 @@
>   ranges = <0x0 0x0 0x0 0xc810 0x0 0x10>;
>  
>   sysctrl_AO: sys-ctrl@0 {
> - compatible = "amlogic,meson-gx-ao-sysctrl", 
> "syscon", "simple-mfd";
> + compatible = "amlogic,meson-gx-ao-sysctrl", 
> "simple-mfd", "syscon";
>   reg =  <0x0 0x0 0x0 0x100>;
>  
>   pwrc_vpu: power-controller-vpu {
> @@ -431,7 +431,7 @@
>   ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
>  
>   sysctrl: system-controller@0 {
> - compatible = "amlogic,meson-gx-hhi-sysctrl", 
> "syscon", "simple-mfd";
> + compatible = "amlogic,meson-gx-hhi-sysctrl", 
> "simple-mfd", "syscon";
>   reg = <0 0 0 0x400>;
>   };
>  
> 

Re: [PATCH] arm64: dts: meson: Switch simple-mfd and syscon order

[Yixun Lan]

HI Neil

On 07/26/2018 10:13 PM, Neil Armstrong wrote:
> The order between "syscon" and "simple-mfd" is important because in these
> particular cases, the node needs to be first a "simple-mfd" to expose
> it's sub-nodes, and later on a "syscon" to permit other nodes to access
> this register space through the "syscon" mechanism.
> 

could you explain a bit which specific case that it need compatible
"simple-mfd" come first? is this a problem in kernel side? because I see
you have a comment below about problem in U-Boot..


also while Rob review the mmc-clkc patch, he raise a suggestion to  drop
"syscon" in drivers/mfd/syscon.c, see [1], will that solve or affect
your problem?

[1]
https://lkml.kernel.org/r/CAL_Jsq+r+7BaJAPBn3L26sdxATVyDiuC=v3xe+yz0-27q0r...@mail.gmail.com

> Signed-off-by: Neil Armstrong 
> ---
> This also has a consequence for U-Boot since the U-Boot DM is much simpler
> and can only associate a single device to a node, thus here we want these
> nodes to be an mfd bus to be able to probe the sub-nodes.
> 
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  arch/arm64/boot/dts/amlogic/meson-gx.dtsi  | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 6adc8d3..3f0de9d 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -342,7 +342,7 @@
>   ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
>  
>   sysctrl: system-controller@0 {
> - compatible = "amlogic,meson-axg-hhi-sysctrl", 
> "syscon", "simple-mfd";
> + compatible = "amlogic,meson-axg-hhi-sysctrl", 
> "simple-mfd", "syscon";
>   reg = <0 0 0 0x400>;
>  
>   clkc: clock-controller {
> @@ -1180,7 +1180,7 @@
>   ranges = <0x0 0x0 0x0 0xff80 0x0 0x10>;
>  
>   sysctrl_AO: sys-ctrl@0 {
> - compatible = "amlogic,meson-axg-ao-sysctrl", 
> "syscon", "simple-mfd";
> + compatible = "amlogic,meson-axg-ao-sysctrl", 
> "simple-mfd", "syscon";
>   reg =  <0x0 0x0 0x0 0x100>;
>  
>   clkc_AO: clock-controller {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi 
> b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index b8dc4db..d88699f 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -344,7 +344,7 @@
>   ranges = <0x0 0x0 0x0 0xc810 0x0 0x10>;
>  
>   sysctrl_AO: sys-ctrl@0 {
> - compatible = "amlogic,meson-gx-ao-sysctrl", 
> "syscon", "simple-mfd";
> + compatible = "amlogic,meson-gx-ao-sysctrl", 
> "simple-mfd", "syscon";
>   reg =  <0x0 0x0 0x0 0x100>;
>  
>   pwrc_vpu: power-controller-vpu {
> @@ -431,7 +431,7 @@
>   ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
>  
>   sysctrl: system-controller@0 {
> - compatible = "amlogic,meson-gx-hhi-sysctrl", 
> "syscon", "simple-mfd";
> + compatible = "amlogic,meson-gx-hhi-sysctrl", 
> "simple-mfd", "syscon";
>   reg = <0 0 0 0x400>;
>   };
>  
> 

Re: [PATCH v2 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

HI Kevin

On 07/23/2018 10:12 PM, Kevin Hilman wrote:
> Yixun Lan  writes:
> 
> [...]
> 
>>>
>>>> Second, we might like to convert eMMC driver to also use mmc-clkc model.
>>>
>>> IMO, this should be done as part of merging this series. Otherwise, we
>>> have duplicated code for the same thing.
>>
>> IMO, I'd leave this out of this series, since this patch series is quite
>> complete as itself. Although, the downside is code duplication.
>>
>> Still, I need to hear Jerome, or Kevin's option, to see if or how we
>> should proceed the eMMC's clock conversion.
>>
>> I could think of three option myself
>> 1) don't do the conversion, downside is code duplication, upside is NO
>> DT change, no compatibility issue
>> 2) add a syscon node into eMMC DT node, then only convert clock part
>> into this mmc-clkc model, while still leave other eMMC register access
>> as the usual iomap way (still no race condition)
>> 3) convert all eMMC register access by using regmap interface.
>>
>> both 2) and 3) need to update the DT.
>>
>> and probably 2) is a compromise way, and 1) is also OK, 3) is probably
>> the worst way due to dramatically change (I think this was already
>> rejected in the previous discussion)
> 
> Because the devices (NAND and eMMC_C) are mutually exclusive, taking the
> step-by-step approach is fine (and preferred) by me.
> 
> Phase 1:
> - add new mmc-clk provider
> - add NAND driver using new mmc-clk provider
> - boards using NAND should ensure emmc_c is disabled in DT
> 
> This allows us to not touch the MMC driver or existing upstream
> bindings.  Yes, this means there is duplicate code in the MMC driver and
> the new mmc-clk provider, but that can be removed in the next phase.
> 
Great, the approach to address this issue is reasonable.
We'd like to focus on phase 1 first, thanks

> Phase 2:
> - convert MMC driver to use new mmc-clk provider
> - update MMC users in DT and bindings
> 
Ok.


Yixun

Re: [PATCH v2 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

HI Kevin

On 07/23/2018 10:12 PM, Kevin Hilman wrote:
> Yixun Lan  writes:
> 
> [...]
> 
>>>
>>>> Second, we might like to convert eMMC driver to also use mmc-clkc model.
>>>
>>> IMO, this should be done as part of merging this series. Otherwise, we
>>> have duplicated code for the same thing.
>>
>> IMO, I'd leave this out of this series, since this patch series is quite
>> complete as itself. Although, the downside is code duplication.
>>
>> Still, I need to hear Jerome, or Kevin's option, to see if or how we
>> should proceed the eMMC's clock conversion.
>>
>> I could think of three option myself
>> 1) don't do the conversion, downside is code duplication, upside is NO
>> DT change, no compatibility issue
>> 2) add a syscon node into eMMC DT node, then only convert clock part
>> into this mmc-clkc model, while still leave other eMMC register access
>> as the usual iomap way (still no race condition)
>> 3) convert all eMMC register access by using regmap interface.
>>
>> both 2) and 3) need to update the DT.
>>
>> and probably 2) is a compromise way, and 1) is also OK, 3) is probably
>> the worst way due to dramatically change (I think this was already
>> rejected in the previous discussion)
> 
> Because the devices (NAND and eMMC_C) are mutually exclusive, taking the
> step-by-step approach is fine (and preferred) by me.
> 
> Phase 1:
> - add new mmc-clk provider
> - add NAND driver using new mmc-clk provider
> - boards using NAND should ensure emmc_c is disabled in DT
> 
> This allows us to not touch the MMC driver or existing upstream
> bindings.  Yes, this means there is duplicate code in the MMC driver and
> the new mmc-clk provider, but that can be removed in the next phase.
> 
Great, the approach to address this issue is reasonable.
We'd like to focus on phase 1 first, thanks

> Phase 2:
> - convert MMC driver to use new mmc-clk provider
> - update MMC users in DT and bindings
> 
Ok.


Yixun

Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver

[Yixun Lan]

On 07/19/2018 10:06 PM, Kevin Hilman wrote:
> Yixun Lan  writes:
> 
> [...]
> 
>>>
>>> As Jerome said, I think consistency is an important goal, so leaving off
>>> the "meson-" for drivers/clk is fine with me.
>>>
>> ok
>>
>>> Also for consistency, for the rest of the drivers, keeping "meson-" is
>>> probably the right thing to do.
>>>
>> ok, for the above, you are talking about the already exist compatible
>> names? or the patches we will push in the future?
> 
> I'm talking about future patches.
> 
ok

>>> However, patches would be welcome to add compatibles without the "meson"
>>> for the rest of the drivers & documentation as well, but please do not
>>> remove any compatibles.
>>>
>> I assume you are talking about the patches in the future we will push?
>> to drop the "meson".
>>
>> I'm confused here, as the above two paragraphs conflict with each other
> 
> Yeah, what I wrote is confusing, sorry about that.
> 
> What I mean is that new patches should stay consistent with compatibles
> in their existing drivers/subsystems.  That means keeping the "meson-"
> prefix for everything except drivers/clk.
> 
sounds good to me.

> In addition to that, patches would be welcome for *adding* compatibles
> without "meson" to all the current drivers.
> 
not sure if I parse above correctly, so let me rephrase..

for "all the current drivers", do you mean all the drivers which already
accepted at mainline kernel, which are mmc, uart, spi, i2c ..

all of them follow "amlogic,meson-${SOC}-${FUNCTION}", so do you propose
to add compatbiles like "amlogic,${SOC}-${FUNCTION}" ?

take i2c for example, there is "amlogic,meson-axg-i2c" already, do you
want to add another "amlogic,axg-i2c" ? I feel this will adding more
confusion..

How about only following the "amlogic,${SOC}-${FUNCTION}" syntax in the
new added drivers in the future, for example NAND, PCIE driver which we
want to push (those drivers doesn't exist in current mainline kernel).


Yixun

Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver

[Yixun Lan]

On 07/19/2018 10:06 PM, Kevin Hilman wrote:
> Yixun Lan  writes:
> 
> [...]
> 
>>>
>>> As Jerome said, I think consistency is an important goal, so leaving off
>>> the "meson-" for drivers/clk is fine with me.
>>>
>> ok
>>
>>> Also for consistency, for the rest of the drivers, keeping "meson-" is
>>> probably the right thing to do.
>>>
>> ok, for the above, you are talking about the already exist compatible
>> names? or the patches we will push in the future?
> 
> I'm talking about future patches.
> 
ok

>>> However, patches would be welcome to add compatibles without the "meson"
>>> for the rest of the drivers & documentation as well, but please do not
>>> remove any compatibles.
>>>
>> I assume you are talking about the patches in the future we will push?
>> to drop the "meson".
>>
>> I'm confused here, as the above two paragraphs conflict with each other
> 
> Yeah, what I wrote is confusing, sorry about that.
> 
> What I mean is that new patches should stay consistent with compatibles
> in their existing drivers/subsystems.  That means keeping the "meson-"
> prefix for everything except drivers/clk.
> 
sounds good to me.

> In addition to that, patches would be welcome for *adding* compatibles
> without "meson" to all the current drivers.
> 
not sure if I parse above correctly, so let me rephrase..

for "all the current drivers", do you mean all the drivers which already
accepted at mainline kernel, which are mmc, uart, spi, i2c ..

all of them follow "amlogic,meson-${SOC}-${FUNCTION}", so do you propose
to add compatbiles like "amlogic,${SOC}-${FUNCTION}" ?

take i2c for example, there is "amlogic,meson-axg-i2c" already, do you
want to add another "amlogic,axg-i2c" ? I feel this will adding more
confusion..

How about only following the "amlogic,${SOC}-${FUNCTION}" syntax in the
new added drivers in the future, for example NAND, PCIE driver which we
want to push (those drivers doesn't exist in current mainline kernel).


Yixun

Re: [RFC PATCH v2 1/2] dt-bindings: nand: meson: add Amlogic NAND controller driver

[Yixun Lan]

Hi Boris:
 see my comments, thanks for the quick response

On 07/19/18 17:57, Boris Brezillon wrote:
> On Thu, 19 Jul 2018 17:46:11 +0800
> Yixun Lan  wrote:
> 
>> From: Liang Yang 
>>
>> Add Amlogic NAND controller dt-bindings for Meson SoC,
>> Current this driver support GXBB/GXL/AXG platform.
>>
>> Signed-off-by: Liang Yang 
>> Signed-off-by: Yixun Lan 
>> ---
>>  .../bindings/mtd/amlogic,meson-nand.txt   | 95 +++
>>  1 file changed, 95 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt 
>> b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> new file mode 100644
>> index ..31f910dcd27a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> @@ -0,0 +1,95 @@
>> +Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
>> +
>> +This file documents the properties in addition to those available in
>> +the MTD NAND bindings.
>> +
>> +Required properties:
>> +- compatible : contains one of:
>> +  - "amlogic,meson-gxl-nfc"
>> +  - "amlogic,meson-axg-nfc"
>> +- clocks :
>> +A list of phandle + clock-specifier pairs for the clocks listed
>> +in clock-names.
>> +
>> +- clock-names: Should contain the following:
>> +"core" - NFC module gate clock
>> +"device" - device clock from eMMC sub clock controller
>> +
>> +- pins : Select pins which NFC need.
>> +- nand_pins: Detail NAND pins information.
> 
> You should document pinctrl-0 and pinctrl-names, not pins and nand_pins.
> 
Ok, will fix this

>> +- amlogic,mmc-syscon: Required for NAND clocks, it's shared with 
>> SD/eMMC
>> +controller port C
> 
> Are you sure this is still needed, even after exposing MMC/NAND clks
> through the CCF?
> 
yes, the SD_EMMC_CLOCK register from eMMC space explore a few other bit
that not fit well into clock model, thus we still need to access them
from NAND driver, we know it's kind of ugly..

#define SD_EMMC_CLOCK   0x00
#define   CLK_ALWAYS_ON BIT(28)
#define   CLK_SELECT_NAND BIT(31)
#define   CLK_DIV_MASK  GENMASK(5, 0)

we probably could get rid of CLK_DIV_MASK, but need to keep other two


> You forgot
> - #address-cells
> - #size-cells
> - reg
> - interrupts
> - 
> 
will fix these
>> +
>> +Optional children nodes:
>> +Children nodes represent the available nand chips.
>> +
>> +Optional properties:
>> +- amlogic,nand-enable-scrambler: enable the NAND scrambler feature.
>> +- (absent) = scrambler is disabled
>> +- (present) = scrambler is enabled
> 
> I keep thinking this is not needed if you have the NAND chip properly
> defined (NAND_NEED_SCRAMBLING flag set in chip->options).
> 
Ok, we will try this flag
>> +
>> +
>> +Other properties:
>> +see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
>> +
>> +Example demonstrate on AXG SoC:
>> +
>> +sd_emmc_c_clkc: mmc@7000 {
>> +compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
>> +reg = <0x0 0x7000 0x0 0x800>;
>> +status = "okay";
>> +};
>> +
>> +nand: nfc@7800 {
>> +compatible = "amlogic,meson-axg-nfc";
>> +reg = <0x0 0x7800 0x0 0x100>;
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +interrupts = ;
>> +status = "disabled";
>> +
>> +clocks = < CLKID_SD_EMMC_C>,
>> +<_emmc_c_clkc CLKID_MMC_DIV>;
>> +clock-names = "core", "device";
>> +amlogic,mmc-syscon = <_emmc_c_clkc>;
>> +
>> +status = "okay";
>> +
>> +pinctrl-names = "default";
>> +pinctrl-0 = <_pins>;
>> +
>> +nand@0 {
>> +reg = <0>;
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +
>> +nand-on-flash-bbt;
>> +nand-ecc-mode = "hw";
>> +nand-ecc-strength = <8>;
>> +nand-ecc-step-size 

Re: [RFC PATCH v2 1/2] dt-bindings: nand: meson: add Amlogic NAND controller driver

[Yixun Lan]

Hi Boris:
 see my comments, thanks for the quick response

On 07/19/18 17:57, Boris Brezillon wrote:
> On Thu, 19 Jul 2018 17:46:11 +0800
> Yixun Lan  wrote:
> 
>> From: Liang Yang 
>>
>> Add Amlogic NAND controller dt-bindings for Meson SoC,
>> Current this driver support GXBB/GXL/AXG platform.
>>
>> Signed-off-by: Liang Yang 
>> Signed-off-by: Yixun Lan 
>> ---
>>  .../bindings/mtd/amlogic,meson-nand.txt   | 95 +++
>>  1 file changed, 95 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt 
>> b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> new file mode 100644
>> index ..31f910dcd27a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> @@ -0,0 +1,95 @@
>> +Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
>> +
>> +This file documents the properties in addition to those available in
>> +the MTD NAND bindings.
>> +
>> +Required properties:
>> +- compatible : contains one of:
>> +  - "amlogic,meson-gxl-nfc"
>> +  - "amlogic,meson-axg-nfc"
>> +- clocks :
>> +A list of phandle + clock-specifier pairs for the clocks listed
>> +in clock-names.
>> +
>> +- clock-names: Should contain the following:
>> +"core" - NFC module gate clock
>> +"device" - device clock from eMMC sub clock controller
>> +
>> +- pins : Select pins which NFC need.
>> +- nand_pins: Detail NAND pins information.
> 
> You should document pinctrl-0 and pinctrl-names, not pins and nand_pins.
> 
Ok, will fix this

>> +- amlogic,mmc-syscon: Required for NAND clocks, it's shared with 
>> SD/eMMC
>> +controller port C
> 
> Are you sure this is still needed, even after exposing MMC/NAND clks
> through the CCF?
> 
yes, the SD_EMMC_CLOCK register from eMMC space explore a few other bit
that not fit well into clock model, thus we still need to access them
from NAND driver, we know it's kind of ugly..

#define SD_EMMC_CLOCK   0x00
#define   CLK_ALWAYS_ON BIT(28)
#define   CLK_SELECT_NAND BIT(31)
#define   CLK_DIV_MASK  GENMASK(5, 0)

we probably could get rid of CLK_DIV_MASK, but need to keep other two


> You forgot
> - #address-cells
> - #size-cells
> - reg
> - interrupts
> - 
> 
will fix these
>> +
>> +Optional children nodes:
>> +Children nodes represent the available nand chips.
>> +
>> +Optional properties:
>> +- amlogic,nand-enable-scrambler: enable the NAND scrambler feature.
>> +- (absent) = scrambler is disabled
>> +- (present) = scrambler is enabled
> 
> I keep thinking this is not needed if you have the NAND chip properly
> defined (NAND_NEED_SCRAMBLING flag set in chip->options).
> 
Ok, we will try this flag
>> +
>> +
>> +Other properties:
>> +see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
>> +
>> +Example demonstrate on AXG SoC:
>> +
>> +sd_emmc_c_clkc: mmc@7000 {
>> +compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
>> +reg = <0x0 0x7000 0x0 0x800>;
>> +status = "okay";
>> +};
>> +
>> +nand: nfc@7800 {
>> +compatible = "amlogic,meson-axg-nfc";
>> +reg = <0x0 0x7800 0x0 0x100>;
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +interrupts = ;
>> +status = "disabled";
>> +
>> +clocks = < CLKID_SD_EMMC_C>,
>> +<_emmc_c_clkc CLKID_MMC_DIV>;
>> +clock-names = "core", "device";
>> +amlogic,mmc-syscon = <_emmc_c_clkc>;
>> +
>> +status = "okay";
>> +
>> +pinctrl-names = "default";
>> +pinctrl-0 = <_pins>;
>> +
>> +nand@0 {
>> +reg = <0>;
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +
>> +nand-on-flash-bbt;
>> +nand-ecc-mode = "hw";
>> +nand-ecc-strength = <8>;
>> +nand-ecc-step-size 

Re: [PATCH 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

HI Boris


On 07/19/18 16:39, Boris Brezillon wrote:
> Hi Yixun,
> 
> On Thu, 19 Jul 2018 16:13:47 +0800
> Yixun Lan  wrote:
> 
>>>>> You're doing DMA on those buffers, and devm_kzalloc() is not
>>>>> DMA-friendly (returned buffers are not aligned on a cache line). Also,
>>>>> you don't have to allocate your own buffers because the core already
>>>>> allocate them (chip->data_buf, chip->oob_poi). All you need to do is
>>>>> set the NAND_USE_BOUNCE_BUFFER flag in chip->options to make sure
>>>>> you're always passed a DMA-able buffer.
>>>>> 
>>>>
>>>> thanks for the suggestion, we've migrated to use the
>>>> dmam_alloc_coherent() API  
>>>
>>> kzalloc() should be just fine, no need to alloc a DMA coherent region. 
>>>   
>>
>> we're a little bit confused here, isn't devm_kzalloc (previously we are
>> using) a variant of kzalloc? and since the NAND controller is doing DMA
>> here, using DMA coherent API is more proper way?
> 
> Well, making buffers DMA coherent might be expensive, especially if you
> access them a lot (unless you have a coherency unit and the cache is
> kept enabled).
> 
> Regarding the "why is devm_kzalloc() is not DMA-safe?" question, I'd
> recommend that you read this discussion [1].
> 
great, thanks for the info.

we fixed this in patch v2

>>>>>> +mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
>>>>>> +   "%s:nand", dev_name(dev));
>>>>>> +if (!mtd->name) {
>>>>>> +dev_err(nfc->dev, "Failed to allocate mtd->name\n");
>>>>>> +return -ENOMEM;
>>>>>> +}
>>>>>
>>>>> You set the name after nand_scan_ident() and make it conditional (only
>>>>> if ->name == NULL) so that the label property defined in the DT takes
>>>>> precedence over the default name.
>>>>  
>> for setting mtd->name conditional, do you mean doing something like this?
>>
>> if (!mtd->name)
>>  mtd->name = devm_kasprintf(..)
> 
> Yes, that's what I meant.
> 
>>
>> but we found mtd->name = "ffe07800.nfc" after function
>> nand_scan_ident(), which is same value as dev_name(dev)..
>> and there is no cs information encoded there.
> 
> Hm, that shouldn't be the case. Maybe you can add traces to find out
> who is setting mtd->name to this value.
> 
will trace this, then get back to you
>>
>>>>  
>>>>> Also, I recommend suffixing this name
>>>>> with the CS id, just in case you ever need to support connecting several
>>>>> chips to the same controller. 
>>>>> 
>>>>
>>>> we actually didn't get the point here, cs is about chip selection with
>>>> multiple nand chip? and how to get this information?  
>>>
>>> Well, you currently seem to only support one chip per controller, but I
>>> guess the IP can handle several CS lines. So my recommendation is about
>>> choosing a name so that you can later easily add support for multiple
>>> chips without breaking setups where mtdparts is used.
>>>
>>> To sum-up, assuming your NAND chip is always connected to CS0 (on the
>>> controller side), I'd suggest doing:
>>>   
>> yes, this is exactly how the hardware connected.
>>> mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
>>>"%s:nand.%d", dev_name(dev), cs_id);
>>>
>>> where cs_id is the value you extracted from the reg property of the
>>> NAND node.
>>>   
>> Ok, you right.
>> current, the NAND chip is only use one CS (which CE0) for now, what's in
>> the DT is
>>
>> nand@0 {
>>  reg = < 0 >;
>>  ..
>> };
>>
>> so for the multiple chips it would something like this in DT?
>>
>> nand@0 {
>>   reg = < 0 >;
>> };
>>
>> nand@1 {
>>   reg = < 1 >;
>> };
> 
> Yep, that's for 2 single-die chips.
> 
>>
>> or even
>> nand@0 {
>>   reg = < 0 2 >;
>> };
>>
>> nand@1 {
> 
> nand@3 {
> 
>>   reg = < 3 4 >;
>> };
> 
> And this is describing 2 dual-die chips.
> 
>>
>> do we need to encode all the cs information here? not sure if we
>> understand this correctly, but could send out the patch for review..
> 
> Yes, reg should contain an array of controller-side CS lines used to
> select the chip (or a specific die in a chip, the index in the reg
> table being the id of the die).
>
much clear about this, thanks

Yixun

Re: [PATCH 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

HI Boris


On 07/19/18 16:39, Boris Brezillon wrote:
> Hi Yixun,
> 
> On Thu, 19 Jul 2018 16:13:47 +0800
> Yixun Lan  wrote:
> 
>>>>> You're doing DMA on those buffers, and devm_kzalloc() is not
>>>>> DMA-friendly (returned buffers are not aligned on a cache line). Also,
>>>>> you don't have to allocate your own buffers because the core already
>>>>> allocate them (chip->data_buf, chip->oob_poi). All you need to do is
>>>>> set the NAND_USE_BOUNCE_BUFFER flag in chip->options to make sure
>>>>> you're always passed a DMA-able buffer.
>>>>> 
>>>>
>>>> thanks for the suggestion, we've migrated to use the
>>>> dmam_alloc_coherent() API  
>>>
>>> kzalloc() should be just fine, no need to alloc a DMA coherent region. 
>>>   
>>
>> we're a little bit confused here, isn't devm_kzalloc (previously we are
>> using) a variant of kzalloc? and since the NAND controller is doing DMA
>> here, using DMA coherent API is more proper way?
> 
> Well, making buffers DMA coherent might be expensive, especially if you
> access them a lot (unless you have a coherency unit and the cache is
> kept enabled).
> 
> Regarding the "why is devm_kzalloc() is not DMA-safe?" question, I'd
> recommend that you read this discussion [1].
> 
great, thanks for the info.

we fixed this in patch v2

>>>>>> +mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
>>>>>> +   "%s:nand", dev_name(dev));
>>>>>> +if (!mtd->name) {
>>>>>> +dev_err(nfc->dev, "Failed to allocate mtd->name\n");
>>>>>> +return -ENOMEM;
>>>>>> +}
>>>>>
>>>>> You set the name after nand_scan_ident() and make it conditional (only
>>>>> if ->name == NULL) so that the label property defined in the DT takes
>>>>> precedence over the default name.
>>>>  
>> for setting mtd->name conditional, do you mean doing something like this?
>>
>> if (!mtd->name)
>>  mtd->name = devm_kasprintf(..)
> 
> Yes, that's what I meant.
> 
>>
>> but we found mtd->name = "ffe07800.nfc" after function
>> nand_scan_ident(), which is same value as dev_name(dev)..
>> and there is no cs information encoded there.
> 
> Hm, that shouldn't be the case. Maybe you can add traces to find out
> who is setting mtd->name to this value.
> 
will trace this, then get back to you
>>
>>>>  
>>>>> Also, I recommend suffixing this name
>>>>> with the CS id, just in case you ever need to support connecting several
>>>>> chips to the same controller. 
>>>>> 
>>>>
>>>> we actually didn't get the point here, cs is about chip selection with
>>>> multiple nand chip? and how to get this information?  
>>>
>>> Well, you currently seem to only support one chip per controller, but I
>>> guess the IP can handle several CS lines. So my recommendation is about
>>> choosing a name so that you can later easily add support for multiple
>>> chips without breaking setups where mtdparts is used.
>>>
>>> To sum-up, assuming your NAND chip is always connected to CS0 (on the
>>> controller side), I'd suggest doing:
>>>   
>> yes, this is exactly how the hardware connected.
>>> mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
>>>"%s:nand.%d", dev_name(dev), cs_id);
>>>
>>> where cs_id is the value you extracted from the reg property of the
>>> NAND node.
>>>   
>> Ok, you right.
>> current, the NAND chip is only use one CS (which CE0) for now, what's in
>> the DT is
>>
>> nand@0 {
>>  reg = < 0 >;
>>  ..
>> };
>>
>> so for the multiple chips it would something like this in DT?
>>
>> nand@0 {
>>   reg = < 0 >;
>> };
>>
>> nand@1 {
>>   reg = < 1 >;
>> };
> 
> Yep, that's for 2 single-die chips.
> 
>>
>> or even
>> nand@0 {
>>   reg = < 0 2 >;
>> };
>>
>> nand@1 {
> 
> nand@3 {
> 
>>   reg = < 3 4 >;
>> };
> 
> And this is describing 2 dual-die chips.
> 
>>
>> do we need to encode all the cs information here? not sure if we
>> understand this correctly, but could send out the patch for review..
> 
> Yes, reg should contain an array of controller-side CS lines used to
> select the chip (or a specific die in a chip, the index in the reg
> table being the id of the die).
>
much clear about this, thanks

Yixun

[RFC PATCH v2 0/2] mtd: rawnand: meson: add Amlogic NAND driver support

[Yixun Lan]

  These two patches try to add initial NAND driver support for Amlogic Meson
SoCs, current it has been tested on GXL(p212) and AXG(s400) platform.

  Note this patch series actually depend on the eMMC clkc patch[2] which
still not merged.

Changes since v1 at [1]:
   - adopt property amlogic,nand-enable-scrambler - thanks Martin
   - drop nand pins in DT
   - convert clk access to emmc clkc model 
   - fix regiser field definition alignment
   - convert devm_kmalloc to kmalloc API
   - drop nand-user-mode 
   - parse cs id from DT
   - rework n2m, m2n function
   - explain why insert two "IDLE" command
   - implement exec_op()
   - drop meson_nfc_get_nand_chip_dts()
   - release resource once error occur in meson_nfc_nand_chips_init(), 
   - call nand_cleanup(nand) once mtd_device_register fail

Items not addressed in this version:
   - convert to ECC conf helper() 
   - how to construct mtd->name

[1] https://lkml.kernel.org/r/20180613161314.14894-1-yixun@amlogic.com
[2] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com

Liang Yang (1):
  dt-bindings: nand: meson: add Amlogic NAND controller driver

Yixun Lan (1):
  mtd: rawnand: meson: add support for Amlogic NAND flash controller

 .../bindings/mtd/amlogic,meson-nand.txt   |   95 ++
 drivers/mtd/nand/raw/Kconfig  |   10 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/meson_nand.c | 1333 +
 4 files changed, 1439 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
 create mode 100644 drivers/mtd/nand/raw/meson_nand.c

-- 
2.18.0

[RFC PATCH v2 1/2] dt-bindings: nand: meson: add Amlogic NAND controller driver

[Yixun Lan]

From: Liang Yang 

Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.

Signed-off-by: Liang Yang 
Signed-off-by: Yixun Lan 
---
 .../bindings/mtd/amlogic,meson-nand.txt   | 95 +++
 1 file changed, 95 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt 
b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
new file mode 100644
index ..31f910dcd27a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
@@ -0,0 +1,95 @@
+Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
+
+This file documents the properties in addition to those available in
+the MTD NAND bindings.
+
+Required properties:
+- compatible : contains one of:
+  - "amlogic,meson-gxl-nfc"
+  - "amlogic,meson-axg-nfc"
+- clocks :
+   A list of phandle + clock-specifier pairs for the clocks listed
+   in clock-names.
+
+- clock-names: Should contain the following:
+   "core" - NFC module gate clock
+   "device" - device clock from eMMC sub clock controller
+
+- pins : Select pins which NFC need.
+- nand_pins: Detail NAND pins information.
+- amlogic,mmc-syscon   : Required for NAND clocks, it's shared with SD/eMMC
+   controller port C
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Optional properties:
+- amlogic,nand-enable-scrambler: enable the NAND scrambler feature.
+   - (absent) = scrambler is disabled
+   - (present) = scrambler is enabled
+
+
+Other properties:
+see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+
+Example demonstrate on AXG SoC:
+
+   sd_emmc_c_clkc: mmc@7000 {
+   compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+   reg = <0x0 0x7000 0x0 0x800>;
+   status = "okay";
+   };
+
+   nand: nfc@7800 {
+   compatible = "amlogic,meson-axg-nfc";
+   reg = <0x0 0x7800 0x0 0x100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   interrupts = ;
+   status = "disabled";
+
+   clocks = < CLKID_SD_EMMC_C>,
+   <_emmc_c_clkc CLKID_MMC_DIV>;
+   clock-names = "core", "device";
+   amlogic,mmc-syscon = <_emmc_c_clkc>;
+
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+
+   nand@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   nand-on-flash-bbt;
+   nand-ecc-mode = "hw";
+   nand-ecc-strength = <8>;
+   nand-ecc-step-size = <1024>;
+
+   amlogic,nand-enable-scrambler;
+
+   partition@0 {
+   label = "boot";
+   reg = <0x 0x0020>;
+   read-only;
+   };
+   partition@20 {
+   label = "env";
+   reg = <0x0020 0x0040>;
+   };
+   partition@60 {
+   label = "system";
+   reg = <0x0060 0x00a0>;
+   };
+   partition@100 {
+   label = "rootfs";
+   reg = <0x0100 0x0300>;
+   };
+   partition@400 {
+   label = "media";
+   reg = <0x0400 0x800>;
+   };
+   };
+   };
-- 
2.18.0

[RFC PATCH v2 0/2] mtd: rawnand: meson: add Amlogic NAND driver support

[Yixun Lan]

  These two patches try to add initial NAND driver support for Amlogic Meson
SoCs, current it has been tested on GXL(p212) and AXG(s400) platform.

  Note this patch series actually depend on the eMMC clkc patch[2] which
still not merged.

Changes since v1 at [1]:
   - adopt property amlogic,nand-enable-scrambler - thanks Martin
   - drop nand pins in DT
   - convert clk access to emmc clkc model 
   - fix regiser field definition alignment
   - convert devm_kmalloc to kmalloc API
   - drop nand-user-mode 
   - parse cs id from DT
   - rework n2m, m2n function
   - explain why insert two "IDLE" command
   - implement exec_op()
   - drop meson_nfc_get_nand_chip_dts()
   - release resource once error occur in meson_nfc_nand_chips_init(), 
   - call nand_cleanup(nand) once mtd_device_register fail

Items not addressed in this version:
   - convert to ECC conf helper() 
   - how to construct mtd->name

[1] https://lkml.kernel.org/r/20180613161314.14894-1-yixun@amlogic.com
[2] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com

Liang Yang (1):
  dt-bindings: nand: meson: add Amlogic NAND controller driver

Yixun Lan (1):
  mtd: rawnand: meson: add support for Amlogic NAND flash controller

 .../bindings/mtd/amlogic,meson-nand.txt   |   95 ++
 drivers/mtd/nand/raw/Kconfig  |   10 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/meson_nand.c | 1333 +
 4 files changed, 1439 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
 create mode 100644 drivers/mtd/nand/raw/meson_nand.c

-- 
2.18.0

[RFC PATCH v2 1/2] dt-bindings: nand: meson: add Amlogic NAND controller driver

[Yixun Lan]

From: Liang Yang 

Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.

Signed-off-by: Liang Yang 
Signed-off-by: Yixun Lan 
---
 .../bindings/mtd/amlogic,meson-nand.txt   | 95 +++
 1 file changed, 95 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt 
b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
new file mode 100644
index ..31f910dcd27a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
@@ -0,0 +1,95 @@
+Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
+
+This file documents the properties in addition to those available in
+the MTD NAND bindings.
+
+Required properties:
+- compatible : contains one of:
+  - "amlogic,meson-gxl-nfc"
+  - "amlogic,meson-axg-nfc"
+- clocks :
+   A list of phandle + clock-specifier pairs for the clocks listed
+   in clock-names.
+
+- clock-names: Should contain the following:
+   "core" - NFC module gate clock
+   "device" - device clock from eMMC sub clock controller
+
+- pins : Select pins which NFC need.
+- nand_pins: Detail NAND pins information.
+- amlogic,mmc-syscon   : Required for NAND clocks, it's shared with SD/eMMC
+   controller port C
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Optional properties:
+- amlogic,nand-enable-scrambler: enable the NAND scrambler feature.
+   - (absent) = scrambler is disabled
+   - (present) = scrambler is enabled
+
+
+Other properties:
+see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+
+Example demonstrate on AXG SoC:
+
+   sd_emmc_c_clkc: mmc@7000 {
+   compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+   reg = <0x0 0x7000 0x0 0x800>;
+   status = "okay";
+   };
+
+   nand: nfc@7800 {
+   compatible = "amlogic,meson-axg-nfc";
+   reg = <0x0 0x7800 0x0 0x100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   interrupts = ;
+   status = "disabled";
+
+   clocks = < CLKID_SD_EMMC_C>,
+   <_emmc_c_clkc CLKID_MMC_DIV>;
+   clock-names = "core", "device";
+   amlogic,mmc-syscon = <_emmc_c_clkc>;
+
+   status = "okay";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+
+   nand@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   nand-on-flash-bbt;
+   nand-ecc-mode = "hw";
+   nand-ecc-strength = <8>;
+   nand-ecc-step-size = <1024>;
+
+   amlogic,nand-enable-scrambler;
+
+   partition@0 {
+   label = "boot";
+   reg = <0x 0x0020>;
+   read-only;
+   };
+   partition@20 {
+   label = "env";
+   reg = <0x0020 0x0040>;
+   };
+   partition@60 {
+   label = "system";
+   reg = <0x0060 0x00a0>;
+   };
+   partition@100 {
+   label = "rootfs";
+   reg = <0x0100 0x0300>;
+   };
+   partition@400 {
+   label = "media";
+   reg = <0x0400 0x800>;
+   };
+   };
+   };
-- 
2.18.0

[RFC PATCH v2 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.

Signed-off-by: Liang Yang 
Signed-off-by: Yixun Lan 
---
 drivers/mtd/nand/raw/Kconfig  |   10 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/meson_nand.c | 1333 +
 3 files changed, 1344 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/meson_nand.c

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 6871ff0fd300..d4a72b258b44 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -530,4 +530,14 @@ config MTD_NAND_MTK
  Enables support for NAND controller on MTK SoCs.
  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_MESON
+   tristate "Support for NAND controller on Amlogic's Meson SoCs"
+   depends on ARCH_MESON || COMPILE_TEST
+   depends on COMMON_CLK_AMLOGIC
+   select COMMON_CLK_REGMAP_MESON
+   select MFD_SYSCON
+   help
+ Enables support for NAND controller on Amlogic's Meson SoCs.
+ This controller is found on Meson GXBB, GXL, AXG SoCs.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..6e9101f7b855 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)+= 
hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_MESON)   += meson_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/meson_nand.c 
b/drivers/mtd/nand/raw/meson_nand.c
new file mode 100644
index ..2458312f22fa
--- /dev/null
+++ b/drivers/mtd/nand/raw/meson_nand.c
@@ -0,0 +1,1333 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson Nand Flash Controller Driver
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Liang Yang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NFC_REG_CMD0x00
+#define   NFC_CMD_DRD  (0x8 << 14)
+#define   NFC_CMD_IDLE (0xc << 14)
+#define   NFC_CMD_DWR  (0x4 << 14)
+#define   NFC_CMD_CLE  (0x5 << 14)
+#define   NFC_CMD_ALE  (0x6 << 14)
+#define   NFC_CMD_ADL  ((0 << 16) | (3 << 20))
+#define   NFC_CMD_ADH  ((1 << 16) | (3 << 20))
+#define   NFC_CMD_AIL  ((2 << 16) | (3 << 20))
+#define   NFC_CMD_AIH  ((3 << 16) | (3 << 20))
+#define   NFC_CMD_SEED ((8 << 16) | (3 << 20))
+#define   NFC_CMD_M2N  ((0 << 17) | (2 << 20))
+#define   NFC_CMD_N2M  ((1 << 17) | (2 << 20))
+#define   NFC_CMD_RB   BIT(20)
+#define   NFC_CMD_IO6  ((0xb << 10) | (1 << 18))
+
+#define NFC_REG_CFG0x04
+#define NFC_REG_DADR   0x08
+#define NFC_REG_IADR   0x0c
+#define NFC_REG_BUF0x10
+#define NFC_REG_INFO   0x14
+#define NFC_REG_DC 0x18
+#define NFC_REG_ADR0x1c
+#define NFC_REG_DL 0x20
+#define NFC_REG_DH 0x24
+#define NFC_REG_CADR   0x28
+#define NFC_REG_SADR   0x2c
+#define NFC_REG_PINS   0x30
+#define NFC_REG_VER0x38
+
+#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages)  \
+   (   \
+   (cmd_dir)   |   \
+   ((ran) << 19)   |   \
+   ((bch) << 14)   |   \
+   ((short_mode) << 13)|   \
+   (((page_size) & 0x7f) << 6) |   \
+   ((pages) & 0x3f)\
+   )
+
+#define GENCMDDADDRL(adl, addr)((adl) | ((addr) & 0x))
+#define GENCMDDADDRH(adh, addr)((adh) | (((addr) >> 16) & 
0x))
+#define GENCMDIADDRL(ail, addr)((ail) | ((addr) & 0x))
+#define GENCMDIADDRH(aih, addr)((aih) | (((addr) >> 16) & 
0x))
+
+#define RB_STA(x)  (1 << (26 + (x)))
+#defineDMA_DIR(dir)((dir) ? NFC_CMD_N2M : 
NFC_CMD_M2N)
+
+#define NAND_TWB_TIME_CYCLE10
+
+#define ECC_CHECK_RETURN_FF(-1)
+
+#define NAND_CE0   (0xe << 10)
+#define NAND_CE1   

[RFC PATCH v2 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.

Signed-off-by: Liang Yang 
Signed-off-by: Yixun Lan 
---
 drivers/mtd/nand/raw/Kconfig  |   10 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/meson_nand.c | 1333 +
 3 files changed, 1344 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/meson_nand.c

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 6871ff0fd300..d4a72b258b44 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -530,4 +530,14 @@ config MTD_NAND_MTK
  Enables support for NAND controller on MTK SoCs.
  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_MESON
+   tristate "Support for NAND controller on Amlogic's Meson SoCs"
+   depends on ARCH_MESON || COMPILE_TEST
+   depends on COMMON_CLK_AMLOGIC
+   select COMMON_CLK_REGMAP_MESON
+   select MFD_SYSCON
+   help
+ Enables support for NAND controller on Amlogic's Meson SoCs.
+ This controller is found on Meson GXBB, GXL, AXG SoCs.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..6e9101f7b855 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)+= 
hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_MESON)   += meson_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/meson_nand.c 
b/drivers/mtd/nand/raw/meson_nand.c
new file mode 100644
index ..2458312f22fa
--- /dev/null
+++ b/drivers/mtd/nand/raw/meson_nand.c
@@ -0,0 +1,1333 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson Nand Flash Controller Driver
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Liang Yang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NFC_REG_CMD0x00
+#define   NFC_CMD_DRD  (0x8 << 14)
+#define   NFC_CMD_IDLE (0xc << 14)
+#define   NFC_CMD_DWR  (0x4 << 14)
+#define   NFC_CMD_CLE  (0x5 << 14)
+#define   NFC_CMD_ALE  (0x6 << 14)
+#define   NFC_CMD_ADL  ((0 << 16) | (3 << 20))
+#define   NFC_CMD_ADH  ((1 << 16) | (3 << 20))
+#define   NFC_CMD_AIL  ((2 << 16) | (3 << 20))
+#define   NFC_CMD_AIH  ((3 << 16) | (3 << 20))
+#define   NFC_CMD_SEED ((8 << 16) | (3 << 20))
+#define   NFC_CMD_M2N  ((0 << 17) | (2 << 20))
+#define   NFC_CMD_N2M  ((1 << 17) | (2 << 20))
+#define   NFC_CMD_RB   BIT(20)
+#define   NFC_CMD_IO6  ((0xb << 10) | (1 << 18))
+
+#define NFC_REG_CFG0x04
+#define NFC_REG_DADR   0x08
+#define NFC_REG_IADR   0x0c
+#define NFC_REG_BUF0x10
+#define NFC_REG_INFO   0x14
+#define NFC_REG_DC 0x18
+#define NFC_REG_ADR0x1c
+#define NFC_REG_DL 0x20
+#define NFC_REG_DH 0x24
+#define NFC_REG_CADR   0x28
+#define NFC_REG_SADR   0x2c
+#define NFC_REG_PINS   0x30
+#define NFC_REG_VER0x38
+
+#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages)  \
+   (   \
+   (cmd_dir)   |   \
+   ((ran) << 19)   |   \
+   ((bch) << 14)   |   \
+   ((short_mode) << 13)|   \
+   (((page_size) & 0x7f) << 6) |   \
+   ((pages) & 0x3f)\
+   )
+
+#define GENCMDDADDRL(adl, addr)((adl) | ((addr) & 0x))
+#define GENCMDDADDRH(adh, addr)((adh) | (((addr) >> 16) & 
0x))
+#define GENCMDIADDRL(ail, addr)((ail) | ((addr) & 0x))
+#define GENCMDIADDRH(aih, addr)((aih) | (((addr) >> 16) & 
0x))
+
+#define RB_STA(x)  (1 << (26 + (x)))
+#defineDMA_DIR(dir)((dir) ? NFC_CMD_N2M : 
NFC_CMD_M2N)
+
+#define NAND_TWB_TIME_CYCLE10
+
+#define ECC_CHECK_RETURN_FF(-1)
+
+#define NAND_CE0   (0xe << 10)
+#define NAND_CE1   

Re: [PATCH 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

HI Boris:

thanks for the quick response.

On 07/19/18 03:08, Boris Brezillon wrote:
> Hi Yixun,
> 
> On Wed, 18 Jul 2018 17:38:56 +0800
> Yixun Lan  wrote:
> 
>>>> +
>>>> +#define NFC_REG_CMD   0x00
>>>> +#define NFC_REG_CFG   0x04
>>>> +#define NFC_REG_DADR  0x08
>>>> +#define NFC_REG_IADR  0x0c
>>>> +#define NFC_REG_BUF   0x10
>>>> +#define NFC_REG_INFO  0x14
>>>> +#define NFC_REG_DC0x18
>>>> +#define NFC_REG_ADR   0x1c
>>>> +#define NFC_REG_DL0x20
>>>> +#define NFC_REG_DH0x24
>>>> +#define NFC_REG_CADR  0x28
>>>> +#define NFC_REG_SADR  0x2c
>>>> +#define NFC_REG_PINS  0x30
>>>> +#define NFC_REG_VER   0x38
>>>> +  
>>>
>>> Can you put the reg offsets next to their field definitions?
>>>   
>> actually, we would prefer to put all the CMD definition below the reg
>> offset, so it will better reflect what's it belong to.
> 
> Just to be clear, I meant something like:
> 
> #define NFC_CMD   0x00
> #define NFC_CMD_DRD   (0x8 << 14)
> #define NFC_CMD_IDLE  (0xc << 14)
> ...
> 
> #define NFC_CFG   0x04
> #define NFC_CFG_XXX   xxx
> ...
> 
> I find it easier to guess which register the fields are attached to when
> it's defined like that, but I won't block the driver for such a tiny
> detail. 
> 
yes, this is exactly what I mean

>>>> +static void meson_nfc_cmd_ctrl(struct mtd_info *mtd,
>>>> +  int cmd, unsigned int ctrl)  
>>>   
>>> ->cmd_ctrl() has recently been deprecated in favor of ->exec_op(). You  
>>> can have a look at the marvell, v610 or fsmc drivers if you want to
>>> have an idea of how ->exec_op() should be implemented. Miquel and I are
>>> also here to help if you have any questions.
>>>   
>>
>> follow your suggestion, we have implemented the exec_op() interface,
>> we'd really appreciate if you can help to review this ..
> 
> Sure, just send a v2 and we'll review it.
> 
> 
>>>> +
>>>> +static void meson_nfc_cmd_m2n(struct meson_nfc *nfc, int raw)  
>>>
>>> n2m -> nand2mem ?
>>>   
>> yes, it is
> 
> Then please use nand2mem, it's clearer.
we end at dropping the n2m function. by converting them into

static void
meson_nfc_cmd_access(
struct meson_nfc *nfc,
struct mtd_info *mtd, int raw, bool dir)


> 
>>>> +static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
>>>> +{
>>>> +  meson_nfc_cmd_idle(nfc, 0);
>>>> +  meson_nfc_cmd_idle(nfc, 0);  
>>>
>>> Two calls to cmd_idle(), is this expected or a copy error? If
>>> that's expected it definitely deserves a comment explaining why?
>>>   
>>
>> yes, it is intentional
>>
>> we will put these comments into the function.
>>  /*
>>  * The Nand flash controller is designed as two stages pipleline -
>>  *  a) fetch and b) excute.
>>  * So, there might be cases when the driver see command queue is
>> empty,
>>  * but the Nand flash controller still has two commands buffered,
>>  * one is fetched into NFC request queue (ready to run), and another
>>  * is actively executing.
>>  */
>>
> 
> So pushing 2 "IDLE" commands guarantees that the pipeline is emptied,
> right? The comment looks incomplete, you should explain what those
> meson_nfc_cmd_idle() are for.
> 
thanks

the meson_nfc_cmd_idle() function itself is quite straightforward, and
we feel explain that inserting 2 "IDLE" commands to drain out the
pipeline is enough.

>>>> +static int meson_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
>>>> +{
>>>> +  struct nand_chip *nand = mtd_to_nand(mtd);
>>>> +  struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
>>>> +  struct meson_nfc *nfc = nand_get_controller_data(nand);
>>>> +  struct meson_nand_ecc *meson_ecc = nfc->data->ecc;
>>>> +  int num = nfc->data->ecc_num;
>>>> +  int nsectors, i, bytes;
>>>> +
>>>> +  /* support only ecc hw mode */
>>>> +  if (nand->ecc.mode != NAND_ECC_HW) {  
>>>
>>> Given that you supp

Re: [PATCH 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

HI Boris:

thanks for the quick response.

On 07/19/18 03:08, Boris Brezillon wrote:
> Hi Yixun,
> 
> On Wed, 18 Jul 2018 17:38:56 +0800
> Yixun Lan  wrote:
> 
>>>> +
>>>> +#define NFC_REG_CMD   0x00
>>>> +#define NFC_REG_CFG   0x04
>>>> +#define NFC_REG_DADR  0x08
>>>> +#define NFC_REG_IADR  0x0c
>>>> +#define NFC_REG_BUF   0x10
>>>> +#define NFC_REG_INFO  0x14
>>>> +#define NFC_REG_DC0x18
>>>> +#define NFC_REG_ADR   0x1c
>>>> +#define NFC_REG_DL0x20
>>>> +#define NFC_REG_DH0x24
>>>> +#define NFC_REG_CADR  0x28
>>>> +#define NFC_REG_SADR  0x2c
>>>> +#define NFC_REG_PINS  0x30
>>>> +#define NFC_REG_VER   0x38
>>>> +  
>>>
>>> Can you put the reg offsets next to their field definitions?
>>>   
>> actually, we would prefer to put all the CMD definition below the reg
>> offset, so it will better reflect what's it belong to.
> 
> Just to be clear, I meant something like:
> 
> #define NFC_CMD   0x00
> #define NFC_CMD_DRD   (0x8 << 14)
> #define NFC_CMD_IDLE  (0xc << 14)
> ...
> 
> #define NFC_CFG   0x04
> #define NFC_CFG_XXX   xxx
> ...
> 
> I find it easier to guess which register the fields are attached to when
> it's defined like that, but I won't block the driver for such a tiny
> detail. 
> 
yes, this is exactly what I mean

>>>> +static void meson_nfc_cmd_ctrl(struct mtd_info *mtd,
>>>> +  int cmd, unsigned int ctrl)  
>>>   
>>> ->cmd_ctrl() has recently been deprecated in favor of ->exec_op(). You  
>>> can have a look at the marvell, v610 or fsmc drivers if you want to
>>> have an idea of how ->exec_op() should be implemented. Miquel and I are
>>> also here to help if you have any questions.
>>>   
>>
>> follow your suggestion, we have implemented the exec_op() interface,
>> we'd really appreciate if you can help to review this ..
> 
> Sure, just send a v2 and we'll review it.
> 
> 
>>>> +
>>>> +static void meson_nfc_cmd_m2n(struct meson_nfc *nfc, int raw)  
>>>
>>> n2m -> nand2mem ?
>>>   
>> yes, it is
> 
> Then please use nand2mem, it's clearer.
we end at dropping the n2m function. by converting them into

static void
meson_nfc_cmd_access(
struct meson_nfc *nfc,
struct mtd_info *mtd, int raw, bool dir)


> 
>>>> +static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
>>>> +{
>>>> +  meson_nfc_cmd_idle(nfc, 0);
>>>> +  meson_nfc_cmd_idle(nfc, 0);  
>>>
>>> Two calls to cmd_idle(), is this expected or a copy error? If
>>> that's expected it definitely deserves a comment explaining why?
>>>   
>>
>> yes, it is intentional
>>
>> we will put these comments into the function.
>>  /*
>>  * The Nand flash controller is designed as two stages pipleline -
>>  *  a) fetch and b) excute.
>>  * So, there might be cases when the driver see command queue is
>> empty,
>>  * but the Nand flash controller still has two commands buffered,
>>  * one is fetched into NFC request queue (ready to run), and another
>>  * is actively executing.
>>  */
>>
> 
> So pushing 2 "IDLE" commands guarantees that the pipeline is emptied,
> right? The comment looks incomplete, you should explain what those
> meson_nfc_cmd_idle() are for.
> 
thanks

the meson_nfc_cmd_idle() function itself is quite straightforward, and
we feel explain that inserting 2 "IDLE" commands to drain out the
pipeline is enough.

>>>> +static int meson_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
>>>> +{
>>>> +  struct nand_chip *nand = mtd_to_nand(mtd);
>>>> +  struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
>>>> +  struct meson_nfc *nfc = nand_get_controller_data(nand);
>>>> +  struct meson_nand_ecc *meson_ecc = nfc->data->ecc;
>>>> +  int num = nfc->data->ecc_num;
>>>> +  int nsectors, i, bytes;
>>>> +
>>>> +  /* support only ecc hw mode */
>>>> +  if (nand->ecc.mode != NAND_ECC_HW) {  
>>>
>>> Given that you supp

Re: [PATCH 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

Hi Roris

thanks for all your suggestions!

It actually takes us some time to digest all your comments ;-)
and get back to you on these questions.


On 06/25/18 03:38, Boris Brezillon wrote:
> 
> 
> Hi Yixun,
> 
> On Wed, 13 Jun 2018 16:13:14 +0000
> Yixun Lan  wrote:
> 
>> From: Liang Yang 
>>
>> Add initial support for the Amlogic NAND flash controller which found
>> in the Meson-GXBB/GXL/AXG SoCs.
>>
>> Singed-off-by: Liang Yang 
>> Signed-off-by: Yixun Lan 
>> ---
>>  drivers/mtd/nand/raw/Kconfig  |8 +
>>  drivers/mtd/nand/raw/Makefile |3 +
>>  drivers/mtd/nand/raw/meson_nand.c | 1422 +
>>  3 files changed, 1433 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/meson_nand.c
> 
> Can you run checkpatch.pl --strict and fix the coding style issues?
> 
sure, we will be more cautious about this

>>
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..b3c17a3ca8f4 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,12 @@ config MTD_NAND_MTK
>>Enables support for NAND controller on MTK SoCs.
>>This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>  
>> +config MTD_NAND_MESON
>> +tristate "Support for NAND flash controller on Amlogic's Meson SoCs"
>> +depends on ARCH_MESON || COMPILE_TEST
>> +select COMMON_CLK_REGMAP_MESON
>> +select MFD_SYSCON
>> +help
>> +  Enables support for NAND controller on Amlogic's Meson SoCs.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..cdf6162f38c3 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -1,5 +1,7 @@
>>  # SPDX-License-Identifier: GPL-2.0
>>  
>> +ccflags-$(CONFIG_MTD_NAND_MESON) += -I$(srctree)/drivers/clk/meson
> 
> Please don't do that. If you need to expose common regs, put them
> in include/linux/soc/meson/. I'm also not sure why you need to access
> the clk regs directly. Why can't you expose the MMC/NAND clk as a clk
> provider whose driver would be placed in drivers/clk and which would use
> the mmc syscon. This way the same clk driver could be used for both
> MMC and NAND clk indifferently, and the NAND driver would be much
> simpler.
> 

this is already addressed in another thread, as we will model it as a
standard clock driver.

so this cflags can be dropped.

>> +
>>  obj-$(CONFIG_MTD_NAND)  += nand.o
>>  obj-$(CONFIG_MTD_NAND_ECC)  += nand_ecc.o
>>  obj-$(CONFIG_MTD_NAND_BCH)  += nand_bch.o
>> @@ -56,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += 
>> hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>  obj-$(CONFIG_MTD_NAND_MTK)  += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_MESON)+= meson_nand.o
>>  
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>  nand-objs += nand_amd.o
>> diff --git a/drivers/mtd/nand/raw/meson_nand.c 
>> b/drivers/mtd/nand/raw/meson_nand.c
>> new file mode 100644
>> index ..28abc3684772
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/meson_nand.c
>> @@ -0,0 +1,1422 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Amlogic Meson Nand Flash Controller Driver
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Liang Yang 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include "clk-regmap.h"
>> +
>> +#define NFC_REG_CMD 0x00
>> +#define NFC_REG_CFG 0x04
>> +#define NFC_REG_DADR0x08
>> +#define NFC_REG_IADR0x0c
>> +#define NFC_REG_BUF 0x10
>> +#define NFC_REG_INFO0x14
>> +#define NFC_REG_DC  0x18
>> +#define NFC_REG_ADR 0x1c
>> +#define NFC_REG_DL  0x20
>> +#define NFC_REG_DH  0x24
>> +#define NFC_REG_CADR0x28
>> +#define NFC_REG_SADR0x2c
>> +#define NFC_REG_PINS0x30
>> +#define NFC_REG_VER 0x38
>> +
> 
> Can you put the reg offsets next to their field definitions?
> 
actually,

Re: [PATCH 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller

[Yixun Lan]

Hi Roris

thanks for all your suggestions!

It actually takes us some time to digest all your comments ;-)
and get back to you on these questions.


On 06/25/18 03:38, Boris Brezillon wrote:
> 
> 
> Hi Yixun,
> 
> On Wed, 13 Jun 2018 16:13:14 +0000
> Yixun Lan  wrote:
> 
>> From: Liang Yang 
>>
>> Add initial support for the Amlogic NAND flash controller which found
>> in the Meson-GXBB/GXL/AXG SoCs.
>>
>> Singed-off-by: Liang Yang 
>> Signed-off-by: Yixun Lan 
>> ---
>>  drivers/mtd/nand/raw/Kconfig  |8 +
>>  drivers/mtd/nand/raw/Makefile |3 +
>>  drivers/mtd/nand/raw/meson_nand.c | 1422 +
>>  3 files changed, 1433 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/meson_nand.c
> 
> Can you run checkpatch.pl --strict and fix the coding style issues?
> 
sure, we will be more cautious about this

>>
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..b3c17a3ca8f4 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,12 @@ config MTD_NAND_MTK
>>Enables support for NAND controller on MTK SoCs.
>>This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>  
>> +config MTD_NAND_MESON
>> +tristate "Support for NAND flash controller on Amlogic's Meson SoCs"
>> +depends on ARCH_MESON || COMPILE_TEST
>> +select COMMON_CLK_REGMAP_MESON
>> +select MFD_SYSCON
>> +help
>> +  Enables support for NAND controller on Amlogic's Meson SoCs.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..cdf6162f38c3 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -1,5 +1,7 @@
>>  # SPDX-License-Identifier: GPL-2.0
>>  
>> +ccflags-$(CONFIG_MTD_NAND_MESON) += -I$(srctree)/drivers/clk/meson
> 
> Please don't do that. If you need to expose common regs, put them
> in include/linux/soc/meson/. I'm also not sure why you need to access
> the clk regs directly. Why can't you expose the MMC/NAND clk as a clk
> provider whose driver would be placed in drivers/clk and which would use
> the mmc syscon. This way the same clk driver could be used for both
> MMC and NAND clk indifferently, and the NAND driver would be much
> simpler.
> 

this is already addressed in another thread, as we will model it as a
standard clock driver.

so this cflags can be dropped.

>> +
>>  obj-$(CONFIG_MTD_NAND)  += nand.o
>>  obj-$(CONFIG_MTD_NAND_ECC)  += nand_ecc.o
>>  obj-$(CONFIG_MTD_NAND_BCH)  += nand_bch.o
>> @@ -56,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += 
>> hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>  obj-$(CONFIG_MTD_NAND_MTK)  += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_MESON)+= meson_nand.o
>>  
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>  nand-objs += nand_amd.o
>> diff --git a/drivers/mtd/nand/raw/meson_nand.c 
>> b/drivers/mtd/nand/raw/meson_nand.c
>> new file mode 100644
>> index ..28abc3684772
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/meson_nand.c
>> @@ -0,0 +1,1422 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Amlogic Meson Nand Flash Controller Driver
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Liang Yang 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include "clk-regmap.h"
>> +
>> +#define NFC_REG_CMD 0x00
>> +#define NFC_REG_CFG 0x04
>> +#define NFC_REG_DADR0x08
>> +#define NFC_REG_IADR0x0c
>> +#define NFC_REG_BUF 0x10
>> +#define NFC_REG_INFO0x14
>> +#define NFC_REG_DC  0x18
>> +#define NFC_REG_ADR 0x1c
>> +#define NFC_REG_DL  0x20
>> +#define NFC_REG_DH  0x24
>> +#define NFC_REG_CADR0x28
>> +#define NFC_REG_SADR0x2c
>> +#define NFC_REG_PINS0x30
>> +#define NFC_REG_VER 0x38
>> +
> 
> Can you put the reg offsets next to their field definitions?
> 
actually,

Re: [PATCH 3/3] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

HI Martin

On 07/14/18 23:30, Martin Blumenstingl wrote:
> Hi Yixun,
> 
> On Wed, Jul 4, 2018 at 4:50 PM Yixun Lan  wrote:
>>
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
> my understanding is that:
> - AXG and G12A use the same mechanism (register layout) to configure
> the pin controller
> - however, the pin mapping differs between AXG and G12A (because G12A
> has more pins in the GPIOZ bank, G12A has a GPIOH bank which AXG
> doesn't have at all, G12A has less pins in the GPIOA and GPIOX
>  banks than AXG and finally AXG has a GPIOY bank which G12A doesn't have)
> 
> maybe you can update the commit description to make it clear that
> - "similar IP" means that the pinmux ops (register layout) are the same
> - a new driver is needed due to the differences in the pins
> 
exactly! thanks for this input

> I am assuming that the pin function names are taken from the
> datasheets (as I don't have access to the datasheets of this SoC)
> these names are slightly inconsistent, but if it's what's written in
> the datasheet then I'm fine with it.
> an example (there are too many places to name them all):
> "uart_rx_ao_a" (this is for the RX line of the uart_ao_a controller)
yes, the name is taken from the datasheet, so this chaos is actually
coming from the datasheet..

as I'm writing in another thread, we are using follow syntax to do the
naming.
${FUNCTION}_${DOMAIN}_${PORT}_${PINFUNC}_${BANK}${PINNUM}

take " uart_ao_a_tx_c" as an example
FUNCTION = uart
DOMAIN= ao (may omit if it's belong to EE domain)
PORT=a (may omit if only one port)
PINFUNC = tx
BANK = C (may omit if only one BANK)
PINNUM = ? (only if two more same function in one BANK)


I'm trying to fix this in code level to make it slightly more
consistent. and yes, we raised this issue to internal ASIC team, hope
they can improve this in next generation SoC..


> vs "pwm_ao_a_hiz" (this is for the "HIZ" line of the the pwm_ao_a
> controller) -> to have a consistent naming it would either have to be
> "uart_ao_a_rx" or "pwm_hiz_ao_a"
indeed, we pick 'pwm_ao_a_hiz'

> 
>> Signed-off-by: Yixun Lan 
> with the few notes fixed (see below):
> Acked-by: Martin Blumenstingl 
> 
thanks

>> ---
>>  drivers/pinctrl/meson/Kconfig  |6 +
>>  drivers/pinctrl/meson/Makefile |1 +
>>  drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1432 
>>  3 files changed, 1439 insertions(+)
>>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
>>
>> diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
>> index c80951d6caff..9ab537eb78a3 100644
>> --- a/drivers/pinctrl/meson/Kconfig
>> +++ b/drivers/pinctrl/meson/Kconfig
>> @@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
>>  config PINCTRL_MESON_AXG_PMX
>> bool
>>
>> +config PINCTRL_MESON_G12A
>> +   bool "Meson g12a Soc pinctrl driver"
>> +   depends on ARM64
>> +   select PINCTRL_MESON_AXG_PMX
>> +   default y
>> +
>>  endif
>> diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
>> index 3c6580c2d9d7..cf283f48f9d8 100644
>> --- a/drivers/pinctrl/meson/Makefile
>> +++ b/drivers/pinctrl/meson/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
>>  obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
>> +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
>> diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
>> b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> new file mode 100644
>> index ..2711bad5d252
>> --- /dev/null
>> +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> @@ -0,0 +1,1432 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +/*
>> + * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
>> + *
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + * Author: Xingyu Chen 
>> + * Author: Yixun Lan 
> same as with the dt-bindings patch: do we also need a "Signed-off-by"
> from Xingyu Chen?
> 
sure, will do this

>> + */
>> +
>> +#include 
>> +#include "pinctrl-meson.h"
>> +#include "pinctrl-meson-axg-pmx.h"

[,,.]
>> +
>> +/* pwm_a */
>> +static const unsigned int pwm_a_pins[] = { GPIOX_6 };
>> +
>> +/* pwm_b */
>> +static const unsigned int pwm_b_x7_pins[]

Re: [PATCH 3/3] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

HI Martin

On 07/14/18 23:30, Martin Blumenstingl wrote:
> Hi Yixun,
> 
> On Wed, Jul 4, 2018 at 4:50 PM Yixun Lan  wrote:
>>
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
> my understanding is that:
> - AXG and G12A use the same mechanism (register layout) to configure
> the pin controller
> - however, the pin mapping differs between AXG and G12A (because G12A
> has more pins in the GPIOZ bank, G12A has a GPIOH bank which AXG
> doesn't have at all, G12A has less pins in the GPIOA and GPIOX
>  banks than AXG and finally AXG has a GPIOY bank which G12A doesn't have)
> 
> maybe you can update the commit description to make it clear that
> - "similar IP" means that the pinmux ops (register layout) are the same
> - a new driver is needed due to the differences in the pins
> 
exactly! thanks for this input

> I am assuming that the pin function names are taken from the
> datasheets (as I don't have access to the datasheets of this SoC)
> these names are slightly inconsistent, but if it's what's written in
> the datasheet then I'm fine with it.
> an example (there are too many places to name them all):
> "uart_rx_ao_a" (this is for the RX line of the uart_ao_a controller)
yes, the name is taken from the datasheet, so this chaos is actually
coming from the datasheet..

as I'm writing in another thread, we are using follow syntax to do the
naming.
${FUNCTION}_${DOMAIN}_${PORT}_${PINFUNC}_${BANK}${PINNUM}

take " uart_ao_a_tx_c" as an example
FUNCTION = uart
DOMAIN= ao (may omit if it's belong to EE domain)
PORT=a (may omit if only one port)
PINFUNC = tx
BANK = C (may omit if only one BANK)
PINNUM = ? (only if two more same function in one BANK)


I'm trying to fix this in code level to make it slightly more
consistent. and yes, we raised this issue to internal ASIC team, hope
they can improve this in next generation SoC..


> vs "pwm_ao_a_hiz" (this is for the "HIZ" line of the the pwm_ao_a
> controller) -> to have a consistent naming it would either have to be
> "uart_ao_a_rx" or "pwm_hiz_ao_a"
indeed, we pick 'pwm_ao_a_hiz'

> 
>> Signed-off-by: Yixun Lan 
> with the few notes fixed (see below):
> Acked-by: Martin Blumenstingl 
> 
thanks

>> ---
>>  drivers/pinctrl/meson/Kconfig  |6 +
>>  drivers/pinctrl/meson/Makefile |1 +
>>  drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1432 
>>  3 files changed, 1439 insertions(+)
>>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
>>
>> diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
>> index c80951d6caff..9ab537eb78a3 100644
>> --- a/drivers/pinctrl/meson/Kconfig
>> +++ b/drivers/pinctrl/meson/Kconfig
>> @@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
>>  config PINCTRL_MESON_AXG_PMX
>> bool
>>
>> +config PINCTRL_MESON_G12A
>> +   bool "Meson g12a Soc pinctrl driver"
>> +   depends on ARM64
>> +   select PINCTRL_MESON_AXG_PMX
>> +   default y
>> +
>>  endif
>> diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
>> index 3c6580c2d9d7..cf283f48f9d8 100644
>> --- a/drivers/pinctrl/meson/Makefile
>> +++ b/drivers/pinctrl/meson/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
>>  obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
>> +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
>> diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
>> b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> new file mode 100644
>> index ..2711bad5d252
>> --- /dev/null
>> +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> @@ -0,0 +1,1432 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +/*
>> + * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
>> + *
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + * Author: Xingyu Chen 
>> + * Author: Yixun Lan 
> same as with the dt-bindings patch: do we also need a "Signed-off-by"
> from Xingyu Chen?
> 
sure, will do this

>> + */
>> +
>> +#include 
>> +#include "pinctrl-meson.h"
>> +#include "pinctrl-meson-axg-pmx.h"

[,,.]
>> +
>> +/* pwm_a */
>> +static const unsigned int pwm_a_pins[] = { GPIOX_6 };
>> +
>> +/* pwm_b */
>> +static const unsigned int pwm_b_x7_pins[]

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

HI Jerome


On 07/16/18 17:54, Jerome Brunet wrote:
> 
 +/* uart_ao_a_ee */
 +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
 +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
>>>
>>> Same comment as Martin about naming consistency ... drop c2 and c3 here.
>>>
>>
>> there is already uart_ao_rx_a_pins[]  uart_ao_tx_a_pins[] , see
>>
>>  794 static const unsigned int uart_ao_tx_a_pins[]   = {
>> GPIOAO_0 };
>>  795 static const unsigned int uart_ao_rx_a_pins[]   = {
>> GPIOAO_1 };
>>
>> in the G12A ASIC design, some AO device (from function perspective)
>> route the pin to EE domain, for maximize pin mux utilization.
>>
>> if you don't like this naming scheme, I could rename it into
>>   uart_ao_rx_a_ee_pins[]
>>   uart_ao_tx_a_ee_pins[]
>>
> 
> What we are asking when requesting consistency is to respect a scheme.
> 
> 1) If the pin function is available only once:
> ${FUNCTION}_${PINFUNC}
> 2) If the pin function is available on the several banks
> ${FUNCTION}_${PINFUNC}_${BANK}
> 3)  If the pin function is available on the several pins of the same bank
> ${FUNCTION}_${PINfFUNC}_${BANK}${PINNUN}
> 

to be more accurate, I extend the syntax to

${FUNCTION}_${DOMAIN}_${PORT}_${PINFUNC}_${BANK}${PINNUM}

take " uart_ao_a_tx_c" as an example
FUNCTION = uart
DOMAIN= ao (may omit if it's belong to EE domain)
PORT=a (may omit if only one port)
PINFUNC = tx
BANK = C (may omit if only one BANK)
PINNUM = ? (only if two more same function in one BANK)


previous in AXG driver we follow scheme
${FUNCTION}_${DOMAIN}_${PINFUNC}_${PORT}_${BANK}${PINNUM}

which may bring confusion, since both PORT and BANK may use alphabet
character, it's hard to tell which is PORT or BANK at first glance.
even worse, sometimes either of PORT or BANK may be omitted..


> Either your function is uart_ao_a_ee and it is available only once then
> you should drop  c2 and c3
> 
> uart_ao_a_ee_rx and uart_ao_a_ee_tx
> 
> or the function is uart_ao_a which is available on ao and c bank then name
> should be 
> 
> uart_ao_a_rx_c, uart_ao_a_tx_c,
> 
we will take this way, has a note says it in the BANK-C sounds more
accurate,

> 
>> which mean uart_ao rx pin at port A route to EE domain's physical pin.
>>
> 
> [...]
> 
>>
 c const unsigned int pwm_f_h_pins[]= { GPIOH_5 };
 +
 +/* cec_ao_ee */
 +static const unsigned int cec_ao_a_ee_pins[]= { GPIOH_3 };
 +static const unsigned int cec_ao_b_ee_pins[]= { GPIOH_3 };
>>>
>>> Naming consistency : cec_ao_ee_a ? cec_ao_ee_b ?
>>>
>>
>> I'd prefer the original version, which mean cec_ao controller at port a
>> route to EE domain's physical pin.
>>
>> I would check this driver to see if there is inconsistency.
> 
> Then the function is CEC_AO not CEC_AO_EE.
> 
> Either the function is cec_ao_ee of cell A and B then name should be 
> 
> cec_ao_ee_a and cec_ao_ee_b
> 
> or function is cec_ao on bank H (also available on bank ao)
> 
> Then name should be cec_ao_a_h, cec_ao_b_h
> 
Ok, we will take this way


> Please choose.
> 
>>
>>
 +
 +/* jtag_b */
 +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
 +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
 +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
 +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
 +
 +/* bt565 */
 +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 };
 +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 };
 +static const unsigned int bt565_a_clk_pins[]= { GPIOZ_3 };
 +static const unsigned int bt565_a_din0_pins[]   = { GPIOZ_4 };
 +static const unsigned int bt565_a_din1_pins[]   = { GPIOZ_5 };
 +static const unsigned int bt565_a_din2_pins[]   = { GPIOZ_6 };
 +static const unsigned int bt565_a_din3_pins[]   = { GPIOZ_7 };
 +static const unsigned int bt565_a_din4_pins[]   = { GPIOZ_8 };
 +static const unsigned int bt565_a_din5_pins[]   = { GPIOZ_9 };
 +static const unsigned int bt565_a_din6_pins[]   = { GPIOZ_10 
 };
 +static const unsigned int bt565_a_din7_pins[]   = { GPIOZ_11 
 };
>>>
>>> Why bt565_a and no bt565 only ?
>>>
>>
>> After talking to Xingyu, this naming is actually taken from the pin mux
>> documentation, it's BT565_A there.
>>
>> I'm not sure if you insist to drop the _a suffix, personally I'd just
>> leave it as it is, for better consistence with documentation.
> 
> Then function name should be bt565_a
> 
sure, will fix this
>>
>>
 +
 +/* tsin_a */
 +static const unsigned int tsin_a_valid_pins[]   = { GPIOX_2 };
 +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 };
 +static const unsigned int tsin_a_din0_pins[]= { GPIOX_0 };
 

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

HI Jerome


On 07/16/18 17:54, Jerome Brunet wrote:
> 
 +/* uart_ao_a_ee */
 +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
 +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
>>>
>>> Same comment as Martin about naming consistency ... drop c2 and c3 here.
>>>
>>
>> there is already uart_ao_rx_a_pins[]  uart_ao_tx_a_pins[] , see
>>
>>  794 static const unsigned int uart_ao_tx_a_pins[]   = {
>> GPIOAO_0 };
>>  795 static const unsigned int uart_ao_rx_a_pins[]   = {
>> GPIOAO_1 };
>>
>> in the G12A ASIC design, some AO device (from function perspective)
>> route the pin to EE domain, for maximize pin mux utilization.
>>
>> if you don't like this naming scheme, I could rename it into
>>   uart_ao_rx_a_ee_pins[]
>>   uart_ao_tx_a_ee_pins[]
>>
> 
> What we are asking when requesting consistency is to respect a scheme.
> 
> 1) If the pin function is available only once:
> ${FUNCTION}_${PINFUNC}
> 2) If the pin function is available on the several banks
> ${FUNCTION}_${PINFUNC}_${BANK}
> 3)  If the pin function is available on the several pins of the same bank
> ${FUNCTION}_${PINfFUNC}_${BANK}${PINNUN}
> 

to be more accurate, I extend the syntax to

${FUNCTION}_${DOMAIN}_${PORT}_${PINFUNC}_${BANK}${PINNUM}

take " uart_ao_a_tx_c" as an example
FUNCTION = uart
DOMAIN= ao (may omit if it's belong to EE domain)
PORT=a (may omit if only one port)
PINFUNC = tx
BANK = C (may omit if only one BANK)
PINNUM = ? (only if two more same function in one BANK)


previous in AXG driver we follow scheme
${FUNCTION}_${DOMAIN}_${PINFUNC}_${PORT}_${BANK}${PINNUM}

which may bring confusion, since both PORT and BANK may use alphabet
character, it's hard to tell which is PORT or BANK at first glance.
even worse, sometimes either of PORT or BANK may be omitted..


> Either your function is uart_ao_a_ee and it is available only once then
> you should drop  c2 and c3
> 
> uart_ao_a_ee_rx and uart_ao_a_ee_tx
> 
> or the function is uart_ao_a which is available on ao and c bank then name
> should be 
> 
> uart_ao_a_rx_c, uart_ao_a_tx_c,
> 
we will take this way, has a note says it in the BANK-C sounds more
accurate,

> 
>> which mean uart_ao rx pin at port A route to EE domain's physical pin.
>>
> 
> [...]
> 
>>
 c const unsigned int pwm_f_h_pins[]= { GPIOH_5 };
 +
 +/* cec_ao_ee */
 +static const unsigned int cec_ao_a_ee_pins[]= { GPIOH_3 };
 +static const unsigned int cec_ao_b_ee_pins[]= { GPIOH_3 };
>>>
>>> Naming consistency : cec_ao_ee_a ? cec_ao_ee_b ?
>>>
>>
>> I'd prefer the original version, which mean cec_ao controller at port a
>> route to EE domain's physical pin.
>>
>> I would check this driver to see if there is inconsistency.
> 
> Then the function is CEC_AO not CEC_AO_EE.
> 
> Either the function is cec_ao_ee of cell A and B then name should be 
> 
> cec_ao_ee_a and cec_ao_ee_b
> 
> or function is cec_ao on bank H (also available on bank ao)
> 
> Then name should be cec_ao_a_h, cec_ao_b_h
> 
Ok, we will take this way


> Please choose.
> 
>>
>>
 +
 +/* jtag_b */
 +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
 +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
 +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
 +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
 +
 +/* bt565 */
 +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 };
 +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 };
 +static const unsigned int bt565_a_clk_pins[]= { GPIOZ_3 };
 +static const unsigned int bt565_a_din0_pins[]   = { GPIOZ_4 };
 +static const unsigned int bt565_a_din1_pins[]   = { GPIOZ_5 };
 +static const unsigned int bt565_a_din2_pins[]   = { GPIOZ_6 };
 +static const unsigned int bt565_a_din3_pins[]   = { GPIOZ_7 };
 +static const unsigned int bt565_a_din4_pins[]   = { GPIOZ_8 };
 +static const unsigned int bt565_a_din5_pins[]   = { GPIOZ_9 };
 +static const unsigned int bt565_a_din6_pins[]   = { GPIOZ_10 
 };
 +static const unsigned int bt565_a_din7_pins[]   = { GPIOZ_11 
 };
>>>
>>> Why bt565_a and no bt565 only ?
>>>
>>
>> After talking to Xingyu, this naming is actually taken from the pin mux
>> documentation, it's BT565_A there.
>>
>> I'm not sure if you insist to drop the _a suffix, personally I'd just
>> leave it as it is, for better consistence with documentation.
> 
> Then function name should be bt565_a
> 
sure, will fix this
>>
>>
 +
 +/* tsin_a */
 +static const unsigned int tsin_a_valid_pins[]   = { GPIOX_2 };
 +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 };
 +static const unsigned int tsin_a_din0_pins[]= { GPIOX_0 };
 

Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver

[Yixun Lan]

HI Kevin

just want to clarify..

On 07/16/18 21:38, Kevin Hilman wrote:
> Jerome Brunet  writes:
> 
>> On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
>>>
>>> On 07/10/18 05:53, Martin Blumenstingl wrote:
>>>> On Mon, Jul 9, 2018 at 1:14 PM Jian Hu  wrote:
> 
> [...]
> 
>>>>> +
>>>>> +static const struct of_device_id clkc_match_table[] = {
>>>>> +   { .compatible = "amlogic,g12a-clkc" },
>>>>
>>>> I wonder if that should be "amlogic,meson-g12a-clkc" (I know that AXG
>>>> and GXBB/GXL/GXM omit the "meson-" prefix, but I am not sure if that's
>>>> correct - I'll CC Rob Herring on the dt-bindings patch)
>>>>
>>>
>>> we're fine with either way, since the g12a is recently new added SoC.
>>>
>>> but I guess those old compatibles which already exist won't be changed,
>>> as it will break the DT
>>
>> Yes, I doubt we are going to change the compatibles. With or without the 
>> meson
>> prefix, I suppose it going to stay that way.
> 
> Correct, we will not change existing compatibles.  Adding new ones for
> clarity is fine though.
> 
fine

>> It is worth thinking about it for new drivers though.
>> We already have the "amlogic,", so do we really to prefix even more with 
>> "meson-
>> "
>>
>> Also, if we were really strict about that scheme, should meson8b compatible 
>> be
>>
>> "amlogic,meson-meson8b-foo-bar" ... the SoC is meson8b, not just 8b after 
>> all ?
>>
>> For the particular case of the clock controller, I don't care very much, as 
>> long
>> as the compatible is coherent with documentation.
>>
>> I might have a preference for the current compatible ... just for consistency
>> with the other clock controllers.
> 
> In hindsight, I think using the "meson" prefix was a mistake.  It's
> redunant, IMO, but it's how we've been doing things for all the drivers,
> except for drivers/clk, which, honestly, I hadn't even noticed until
> now.
> 
> As Jerome said, I think consistency is an important goal, so leaving off
> the "meson-" for drivers/clk is fine with me.
> 
ok

> Also for consistency, for the rest of the drivers, keeping "meson-" is
> probably the right thing to do.
> 
ok, for the above, you are talking about the already exist compatible
names? or the patches we will push in the future?

> However, patches would be welcome to add compatibles without the "meson"
> for the rest of the drivers & documentation as well, but please do not
> remove any compatibles.
> 
I assume you are talking about the patches in the future we will push?
to drop the "meson".

I'm confused here, as the above two paragraphs conflict with each other

> Kevin
> 
> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 
> .
> 

Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver

[Yixun Lan]

HI Kevin

just want to clarify..

On 07/16/18 21:38, Kevin Hilman wrote:
> Jerome Brunet  writes:
> 
>> On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
>>>
>>> On 07/10/18 05:53, Martin Blumenstingl wrote:
>>>> On Mon, Jul 9, 2018 at 1:14 PM Jian Hu  wrote:
> 
> [...]
> 
>>>>> +
>>>>> +static const struct of_device_id clkc_match_table[] = {
>>>>> +   { .compatible = "amlogic,g12a-clkc" },
>>>>
>>>> I wonder if that should be "amlogic,meson-g12a-clkc" (I know that AXG
>>>> and GXBB/GXL/GXM omit the "meson-" prefix, but I am not sure if that's
>>>> correct - I'll CC Rob Herring on the dt-bindings patch)
>>>>
>>>
>>> we're fine with either way, since the g12a is recently new added SoC.
>>>
>>> but I guess those old compatibles which already exist won't be changed,
>>> as it will break the DT
>>
>> Yes, I doubt we are going to change the compatibles. With or without the 
>> meson
>> prefix, I suppose it going to stay that way.
> 
> Correct, we will not change existing compatibles.  Adding new ones for
> clarity is fine though.
> 
fine

>> It is worth thinking about it for new drivers though.
>> We already have the "amlogic,", so do we really to prefix even more with 
>> "meson-
>> "
>>
>> Also, if we were really strict about that scheme, should meson8b compatible 
>> be
>>
>> "amlogic,meson-meson8b-foo-bar" ... the SoC is meson8b, not just 8b after 
>> all ?
>>
>> For the particular case of the clock controller, I don't care very much, as 
>> long
>> as the compatible is coherent with documentation.
>>
>> I might have a preference for the current compatible ... just for consistency
>> with the other clock controllers.
> 
> In hindsight, I think using the "meson" prefix was a mistake.  It's
> redunant, IMO, but it's how we've been doing things for all the drivers,
> except for drivers/clk, which, honestly, I hadn't even noticed until
> now.
> 
> As Jerome said, I think consistency is an important goal, so leaving off
> the "meson-" for drivers/clk is fine with me.
> 
ok

> Also for consistency, for the rest of the drivers, keeping "meson-" is
> probably the right thing to do.
> 
ok, for the above, you are talking about the already exist compatible
names? or the patches we will push in the future?

> However, patches would be welcome to add compatibles without the "meson"
> for the rest of the drivers & documentation as well, but please do not
> remove any compatibles.
> 
I assume you are talking about the patches in the future we will push?
to drop the "meson".

I'm confused here, as the above two paragraphs conflict with each other

> Kevin
> 
> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 
> .
> 

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

Hi Jerome

thanks for the review, see my comments below

On 07/16/18 00:16, Jerome Brunet wrote:
> On Sat, 2018-07-14 at 23:27 +0000, Yixun Lan wrote:
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
>>
>> Starting from Meson-AXG SoC, the pinctrl controller block use 4
>> continues register bits to specific the pin mux function, while comparing
>> to old generation SoC which using variable length register bits for
>> the pin mux definition. The new design greatly simplify the software model.
>>
>> For the detail example, one 32bit register can be divided into 8 parts,
>> each has 4 bits whose value start from 0 - 7, each can describe one pin,
>> the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
>> the mux pin function.
>>
>> Please note, the GPIOE is actually located at AO (always on) bank.
>>
>> Acked-by: Martin Blumenstingl 
>> Signed-off-by: Xingyu Chen 
>> Signed-off-by: Yixun Lan 
>> ---
>>  drivers/pinctrl/meson/Kconfig  |6 +
>>  drivers/pinctrl/meson/Makefile |1 +
>>  drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1433 
>>  3 files changed, 1440 insertions(+)
>>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
>>
>> diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
>> index c80951d6caff..9ab537eb78a3 100644
>> --- a/drivers/pinctrl/meson/Kconfig
>> +++ b/drivers/pinctrl/meson/Kconfig
>> @@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
>>  config PINCTRL_MESON_AXG_PMX
>>  bool
>>  
>> +config PINCTRL_MESON_G12A
>> +bool "Meson g12a Soc pinctrl driver"
>> +depends on ARM64
>> +select PINCTRL_MESON_AXG_PMX
>> +default y
>> +
>>  endif
>> diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
>> index 3c6580c2d9d7..cf283f48f9d8 100644
>> --- a/drivers/pinctrl/meson/Makefile
>> +++ b/drivers/pinctrl/meson/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
>>  obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
>> +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
>> diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
>> b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> new file mode 100644
>> index ..ca5cec40ac34
>> --- /dev/null
>> +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> @@ -0,0 +1,1433 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +/*
>> + * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
>> + *
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + * Author: Xingyu Chen 
>> + * Author: Yixun Lan 
>> + */
>> +
>> +#include 
>> +#include "pinctrl-meson.h"
>> +#include "pinctrl-meson-axg-pmx.h"
>> +
>>
> 
> [...]
> 
>> +/* uart_ao_a_ee */
>> +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
>> +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
> 
> Same comment as Martin about naming consistency ... drop c2 and c3 here.
> 

there is already uart_ao_rx_a_pins[]  uart_ao_tx_a_pins[] , see

 794 static const unsigned int uart_ao_tx_a_pins[]   = {
GPIOAO_0 };
 795 static const unsigned int uart_ao_rx_a_pins[]   = {
GPIOAO_1 };

in the G12A ASIC design, some AO device (from function perspective)
route the pin to EE domain, for maximize pin mux utilization.

if you don't like this naming scheme, I could rename it into
  uart_ao_rx_a_ee_pins[]
  uart_ao_tx_a_ee_pins[]

which mean uart_ao rx pin at port A route to EE domain's physical pin.


>> +
>> +/* iso7816 */
>> +static const unsigned int iso7816_clk_c_pins[]  = { GPIOC_5 };
>> +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
>> +
>> +static const unsigned int iso7816_clk_x_pins[]  = { GPIOX_8 };
>> +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 };
>> +
>> +static const unsigned int iso7816_clk_h_pins[]  = { GPIOH_6 };
>> +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 };
>> +
>> +static const unsigned int iso7816_clk_z_pins[]  = { GPIOZ_0 };
>> +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 };
>> +
>> +/* eth */
>> +static const unsigned in

Re: [PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

Hi Jerome

thanks for the review, see my comments below

On 07/16/18 00:16, Jerome Brunet wrote:
> On Sat, 2018-07-14 at 23:27 +0000, Yixun Lan wrote:
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
>>
>> Starting from Meson-AXG SoC, the pinctrl controller block use 4
>> continues register bits to specific the pin mux function, while comparing
>> to old generation SoC which using variable length register bits for
>> the pin mux definition. The new design greatly simplify the software model.
>>
>> For the detail example, one 32bit register can be divided into 8 parts,
>> each has 4 bits whose value start from 0 - 7, each can describe one pin,
>> the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
>> the mux pin function.
>>
>> Please note, the GPIOE is actually located at AO (always on) bank.
>>
>> Acked-by: Martin Blumenstingl 
>> Signed-off-by: Xingyu Chen 
>> Signed-off-by: Yixun Lan 
>> ---
>>  drivers/pinctrl/meson/Kconfig  |6 +
>>  drivers/pinctrl/meson/Makefile |1 +
>>  drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1433 
>>  3 files changed, 1440 insertions(+)
>>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
>>
>> diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
>> index c80951d6caff..9ab537eb78a3 100644
>> --- a/drivers/pinctrl/meson/Kconfig
>> +++ b/drivers/pinctrl/meson/Kconfig
>> @@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
>>  config PINCTRL_MESON_AXG_PMX
>>  bool
>>  
>> +config PINCTRL_MESON_G12A
>> +bool "Meson g12a Soc pinctrl driver"
>> +depends on ARM64
>> +select PINCTRL_MESON_AXG_PMX
>> +default y
>> +
>>  endif
>> diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
>> index 3c6580c2d9d7..cf283f48f9d8 100644
>> --- a/drivers/pinctrl/meson/Makefile
>> +++ b/drivers/pinctrl/meson/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
>>  obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
>>  obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
>> +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
>> diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
>> b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> new file mode 100644
>> index ..ca5cec40ac34
>> --- /dev/null
>> +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
>> @@ -0,0 +1,1433 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +/*
>> + * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
>> + *
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + * Author: Xingyu Chen 
>> + * Author: Yixun Lan 
>> + */
>> +
>> +#include 
>> +#include "pinctrl-meson.h"
>> +#include "pinctrl-meson-axg-pmx.h"
>> +
>>
> 
> [...]
> 
>> +/* uart_ao_a_ee */
>> +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
>> +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
> 
> Same comment as Martin about naming consistency ... drop c2 and c3 here.
> 

there is already uart_ao_rx_a_pins[]  uart_ao_tx_a_pins[] , see

 794 static const unsigned int uart_ao_tx_a_pins[]   = {
GPIOAO_0 };
 795 static const unsigned int uart_ao_rx_a_pins[]   = {
GPIOAO_1 };

in the G12A ASIC design, some AO device (from function perspective)
route the pin to EE domain, for maximize pin mux utilization.

if you don't like this naming scheme, I could rename it into
  uart_ao_rx_a_ee_pins[]
  uart_ao_tx_a_ee_pins[]

which mean uart_ao rx pin at port A route to EE domain's physical pin.


>> +
>> +/* iso7816 */
>> +static const unsigned int iso7816_clk_c_pins[]  = { GPIOC_5 };
>> +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
>> +
>> +static const unsigned int iso7816_clk_x_pins[]  = { GPIOX_8 };
>> +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 };
>> +
>> +static const unsigned int iso7816_clk_h_pins[]  = { GPIOH_6 };
>> +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 };
>> +
>> +static const unsigned int iso7816_clk_z_pins[]  = { GPIOZ_0 };
>> +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 };
>> +
>> +/* eth */
>> +static const unsigned in

[PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC.

Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.

For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.

Please note, the GPIOE is actually located at AO (always on) bank.

Acked-by: Martin Blumenstingl 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 drivers/pinctrl/meson/Kconfig  |6 +
 drivers/pinctrl/meson/Makefile |1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1433 
 3 files changed, 1440 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index c80951d6caff..9ab537eb78a3 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
 config PINCTRL_MESON_AXG_PMX
bool
 
+config PINCTRL_MESON_G12A
+   bool "Meson g12a Soc pinctrl driver"
+   depends on ARM64
+   select PINCTRL_MESON_AXG_PMX
+   default y
+
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 3c6580c2d9d7..cf283f48f9d8 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
 obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
+obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
new file mode 100644
index ..ca5cec40ac34
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -0,0 +1,1433 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+static const struct pinctrl_pin_desc meson_g12a_periphs_pins[] = {
+   MESON_PIN(GPIOZ_0),
+   MESON_PIN(GPIOZ_1),
+   MESON_PIN(GPIOZ_2),
+   MESON_PIN(GPIOZ_3),
+   MESON_PIN(GPIOZ_4),
+   MESON_PIN(GPIOZ_5),
+   MESON_PIN(GPIOZ_6),
+   MESON_PIN(GPIOZ_7),
+   MESON_PIN(GPIOZ_8),
+   MESON_PIN(GPIOZ_9),
+   MESON_PIN(GPIOZ_10),
+   MESON_PIN(GPIOZ_11),
+   MESON_PIN(GPIOZ_12),
+   MESON_PIN(GPIOZ_13),
+   MESON_PIN(GPIOZ_14),
+   MESON_PIN(GPIOZ_15),
+   MESON_PIN(GPIOH_0),
+   MESON_PIN(GPIOH_1),
+   MESON_PIN(GPIOH_2),
+   MESON_PIN(GPIOH_3),
+   MESON_PIN(GPIOH_4),
+   MESON_PIN(GPIOH_5),
+   MESON_PIN(GPIOH_6),
+   MESON_PIN(GPIOH_7),
+   MESON_PIN(GPIOH_8),
+   MESON_PIN(BOOT_0),
+   MESON_PIN(BOOT_1),
+   MESON_PIN(BOOT_2),
+   MESON_PIN(BOOT_3),
+   MESON_PIN(BOOT_4),
+   MESON_PIN(BOOT_5),
+   MESON_PIN(BOOT_6),
+   MESON_PIN(BOOT_7),
+   MESON_PIN(BOOT_8),
+   MESON_PIN(BOOT_9),
+   MESON_PIN(BOOT_10),
+   MESON_PIN(BOOT_11),
+   MESON_PIN(BOOT_12),
+   MESON_PIN(BOOT_13),
+   MESON_PIN(BOOT_14),
+   MESON_PIN(BOOT_15),
+   MESON_PIN(GPIOC_0),
+   MESON_PIN(GPIOC_1),
+   MESON_PIN(GPIOC_2),
+   MESON_PIN(GPIOC_3),
+   MESON_PIN(GPIOC_4),
+   MESON_PIN(GPIOC_5),
+   MESON_PIN(GPIOC_6),
+   MESON_PIN(GPIOC_7),
+   MESON_PIN(GPIOA_0),
+   MESON_PIN(GPIOA_1),
+   MESON_PIN(GPIOA_2),
+   MESON_PIN(GPIOA_3),
+   MESON_PIN(GPIOA_4),
+   MESON_PIN(GPIOA_5),
+   MESON_PIN(GPIOA_6),
+   MESON_PIN(GPIOA_7),
+   MESON_PIN(GPIOA_8),
+   MESON_PIN(GPIOA_9),
+   MESON_PIN(GPIOA_10),
+   MESON_PIN(GPIOA_11),
+   MESON_PIN(GPIOA_12),
+   MESON_PIN(GPIOA_13),
+   MESON_PIN(GPIOA_14),
+   MESON_PIN(GPIOA_15),
+   MESON_PIN(GPIOX_0),
+   MESON_PIN(GPIOX_1),
+   MESON_PIN(GPIOX_2),
+   MESON_PIN(GPIOX_3),
+   MESON_PIN(GPIOX_4),
+   MESON_PIN(GPIOX_5),
+   MESON_PIN(GPIOX_6),
+   MESON_PIN(GPIOX_7),
+   MESON_PIN(GPIOX_8),
+   MESON_PIN(GPIOX_9),
+   MESON_PIN(GPIOX_10),
+   MESON_PIN(GPIOX_11),
+   MESON_PIN(GPIOX_12),
+   MESON_PIN(GPIOX_13),
+   MESON_PIN(GPIOX_14),
+   MESON_PIN(GPIOX_15),
+   MESON_PIN(GPIOX_16),
+   MESON_PIN(GPIOX_17),
+   MESON_PIN(GPIOX_1

[PATCH v2 2/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC.

Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.

For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.

Please note, the GPIOE is actually located at AO (always on) bank.

Acked-by: Martin Blumenstingl 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 drivers/pinctrl/meson/Kconfig  |6 +
 drivers/pinctrl/meson/Makefile |1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1433 
 3 files changed, 1440 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index c80951d6caff..9ab537eb78a3 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
 config PINCTRL_MESON_AXG_PMX
bool
 
+config PINCTRL_MESON_G12A
+   bool "Meson g12a Soc pinctrl driver"
+   depends on ARM64
+   select PINCTRL_MESON_AXG_PMX
+   default y
+
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 3c6580c2d9d7..cf283f48f9d8 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
 obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
+obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c 
b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
new file mode 100644
index ..ca5cec40ac34
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -0,0 +1,1433 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+static const struct pinctrl_pin_desc meson_g12a_periphs_pins[] = {
+   MESON_PIN(GPIOZ_0),
+   MESON_PIN(GPIOZ_1),
+   MESON_PIN(GPIOZ_2),
+   MESON_PIN(GPIOZ_3),
+   MESON_PIN(GPIOZ_4),
+   MESON_PIN(GPIOZ_5),
+   MESON_PIN(GPIOZ_6),
+   MESON_PIN(GPIOZ_7),
+   MESON_PIN(GPIOZ_8),
+   MESON_PIN(GPIOZ_9),
+   MESON_PIN(GPIOZ_10),
+   MESON_PIN(GPIOZ_11),
+   MESON_PIN(GPIOZ_12),
+   MESON_PIN(GPIOZ_13),
+   MESON_PIN(GPIOZ_14),
+   MESON_PIN(GPIOZ_15),
+   MESON_PIN(GPIOH_0),
+   MESON_PIN(GPIOH_1),
+   MESON_PIN(GPIOH_2),
+   MESON_PIN(GPIOH_3),
+   MESON_PIN(GPIOH_4),
+   MESON_PIN(GPIOH_5),
+   MESON_PIN(GPIOH_6),
+   MESON_PIN(GPIOH_7),
+   MESON_PIN(GPIOH_8),
+   MESON_PIN(BOOT_0),
+   MESON_PIN(BOOT_1),
+   MESON_PIN(BOOT_2),
+   MESON_PIN(BOOT_3),
+   MESON_PIN(BOOT_4),
+   MESON_PIN(BOOT_5),
+   MESON_PIN(BOOT_6),
+   MESON_PIN(BOOT_7),
+   MESON_PIN(BOOT_8),
+   MESON_PIN(BOOT_9),
+   MESON_PIN(BOOT_10),
+   MESON_PIN(BOOT_11),
+   MESON_PIN(BOOT_12),
+   MESON_PIN(BOOT_13),
+   MESON_PIN(BOOT_14),
+   MESON_PIN(BOOT_15),
+   MESON_PIN(GPIOC_0),
+   MESON_PIN(GPIOC_1),
+   MESON_PIN(GPIOC_2),
+   MESON_PIN(GPIOC_3),
+   MESON_PIN(GPIOC_4),
+   MESON_PIN(GPIOC_5),
+   MESON_PIN(GPIOC_6),
+   MESON_PIN(GPIOC_7),
+   MESON_PIN(GPIOA_0),
+   MESON_PIN(GPIOA_1),
+   MESON_PIN(GPIOA_2),
+   MESON_PIN(GPIOA_3),
+   MESON_PIN(GPIOA_4),
+   MESON_PIN(GPIOA_5),
+   MESON_PIN(GPIOA_6),
+   MESON_PIN(GPIOA_7),
+   MESON_PIN(GPIOA_8),
+   MESON_PIN(GPIOA_9),
+   MESON_PIN(GPIOA_10),
+   MESON_PIN(GPIOA_11),
+   MESON_PIN(GPIOA_12),
+   MESON_PIN(GPIOA_13),
+   MESON_PIN(GPIOA_14),
+   MESON_PIN(GPIOA_15),
+   MESON_PIN(GPIOX_0),
+   MESON_PIN(GPIOX_1),
+   MESON_PIN(GPIOX_2),
+   MESON_PIN(GPIOX_3),
+   MESON_PIN(GPIOX_4),
+   MESON_PIN(GPIOX_5),
+   MESON_PIN(GPIOX_6),
+   MESON_PIN(GPIOX_7),
+   MESON_PIN(GPIOX_8),
+   MESON_PIN(GPIOX_9),
+   MESON_PIN(GPIOX_10),
+   MESON_PIN(GPIOX_11),
+   MESON_PIN(GPIOX_12),
+   MESON_PIN(GPIOX_13),
+   MESON_PIN(GPIOX_14),
+   MESON_PIN(GPIOX_15),
+   MESON_PIN(GPIOX_16),
+   MESON_PIN(GPIOX_17),
+   MESON_PIN(GPIOX_1

[PATCH v2 0/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

This patch series try to add pinctrl driver support for
the Meson-G12A SoC.

Changes since v1 at [1]
 - add Martin's Ack, Xingyu's Signed-off
 - squash patch 1,2 (documentation & header file)
 - explain pinctrl IP
 - notice GPIOE located in AO bank

[1] https://lkml.kernel.org/r/20180704224511.29350-1-yixun@amlogic.com

Yixun Lan (2):
  documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin
controllers
  pinctrl: meson-g12a: add pinctrl driver support

 .../bindings/pinctrl/meson,pinctrl.txt|2 +
 drivers/pinctrl/meson/Kconfig |6 +
 drivers/pinctrl/meson/Makefile|1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c| 1433 +
 include/dt-bindings/gpio/meson-g12a-gpio.h|  114 ++
 5 files changed, 1556 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
 create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h

-- 
2.18.0

[PATCH v2 1/2] documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin controllers

[Yixun Lan]

Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.

Acked-by: Martin Blumenstingl 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 .../bindings/pinctrl/meson,pinctrl.txt|   2 +
 include/dt-bindings/gpio/meson-g12a-gpio.h| 114 ++
 2 files changed, 116 insertions(+)
 create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 54ecb8ab7788..82ead40311f6 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -13,6 +13,8 @@ Required properties for the root node:
  "amlogic,meson-gxl-aobus-pinctrl"
  "amlogic,meson-axg-periphs-pinctrl"
  "amlogic,meson-axg-aobus-pinctrl"
+ "amlogic,meson-g12a-periphs-pinctrl"
+ "amlogic,meson-g12a-aobus-pinctrl"
  - reg: address and size of registers controlling irq functionality
 
 === GPIO sub-nodes ===
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h 
b/include/dt-bindings/gpio/meson-g12a-gpio.h
new file mode 100644
index ..f7bd69350d18
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ */
+
+#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
+#define _DT_BINDINGS_MESON_G12A_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0   0
+#define GPIOAO_1   1
+#define GPIOAO_2   2
+#define GPIOAO_3   3
+#define GPIOAO_4   4
+#define GPIOAO_5   5
+#define GPIOAO_6   6
+#define GPIOAO_7   7
+#define GPIOAO_8   8
+#define GPIOAO_9   9
+#define GPIOAO_10  10
+#define GPIOAO_11  11
+#define GPIOE_012
+#define GPIOE_113
+#define GPIOE_214
+
+/* Second GPIO chip */
+#define GPIOZ_00
+#define GPIOZ_11
+#define GPIOZ_22
+#define GPIOZ_33
+#define GPIOZ_44
+#define GPIOZ_55
+#define GPIOZ_66
+#define GPIOZ_77
+#define GPIOZ_88
+#define GPIOZ_99
+#define GPIOZ_10   10
+#define GPIOZ_11   11
+#define GPIOZ_12   12
+#define GPIOZ_13   13
+#define GPIOZ_14   14
+#define GPIOZ_15   15
+#define GPIOH_016
+#define GPIOH_117
+#define GPIOH_218
+#define GPIOH_319
+#define GPIOH_420
+#define GPIOH_521
+#define GPIOH_622
+#define GPIOH_723
+#define GPIOH_824
+#define BOOT_0 25
+#define BOOT_1 26
+#define BOOT_2 27
+#define BOOT_3 28
+#define BOOT_4 29
+#define BOOT_5 30
+#define BOOT_6 31
+#define BOOT_7 32
+#define BOOT_8 33
+#define BOOT_9 34
+#define BOOT_1035
+#define BOOT_1136
+#define BOOT_1237
+#define BOOT_1338
+#define BOOT_1439
+#define BOOT_1540
+#define GPIOC_041
+#define GPIOC_142
+#define GPIOC_243
+#define GPIOC_344
+#define GPIOC_445
+#define GPIOC_546
+#define GPIOC_647
+#define GPIOC_748
+#define GPIOA_049
+#define GPIOA_150
+#define GPIOA_251
+#define GPIOA_352
+#define GPIOA_453
+#define GPIOA_554
+#define GPIOA_655
+#define GPIOA_756
+#define GPIOA_857
+#define GPIOA_958
+#define GPIOA_10   59
+#define GPIOA_11   60
+#define GPIOA_12   61
+#define GPIOA_13   62
+#define GPIOA_14   63
+#define GPIOA_15   64
+#define GPIOX_065
+#define GPIOX_166
+#define GPIOX_267
+#define GPIOX_368
+#define GPIOX_469
+#define GPIOX_570
+#define GPIOX_671
+#define GPIOX_772
+#define GPIOX_873
+#define GPIOX_974
+#define GPIOX_10   75
+#define GPIOX_11   76
+#define GPIOX_12   77
+#define GPIOX_13   78
+#define GPIOX_14   79
+#define GPIOX_15   80
+#define GPIOX_16   81
+#define GPIOX_17   82
+#define GPIOX_18   83
+#define GPIOX_19   84
+
+#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
-- 
2.18.0

[PATCH v2 0/2] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

This patch series try to add pinctrl driver support for
the Meson-G12A SoC.

Changes since v1 at [1]
 - add Martin's Ack, Xingyu's Signed-off
 - squash patch 1,2 (documentation & header file)
 - explain pinctrl IP
 - notice GPIOE located in AO bank

[1] https://lkml.kernel.org/r/20180704224511.29350-1-yixun@amlogic.com

Yixun Lan (2):
  documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin
controllers
  pinctrl: meson-g12a: add pinctrl driver support

 .../bindings/pinctrl/meson,pinctrl.txt|2 +
 drivers/pinctrl/meson/Kconfig |6 +
 drivers/pinctrl/meson/Makefile|1 +
 drivers/pinctrl/meson/pinctrl-meson-g12a.c| 1433 +
 include/dt-bindings/gpio/meson-g12a-gpio.h|  114 ++
 5 files changed, 1556 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
 create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h

-- 
2.18.0

[PATCH v2 1/2] documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin controllers

[Yixun Lan]

Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.

Acked-by: Martin Blumenstingl 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
---
 .../bindings/pinctrl/meson,pinctrl.txt|   2 +
 include/dt-bindings/gpio/meson-g12a-gpio.h| 114 ++
 2 files changed, 116 insertions(+)
 create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 54ecb8ab7788..82ead40311f6 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -13,6 +13,8 @@ Required properties for the root node:
  "amlogic,meson-gxl-aobus-pinctrl"
  "amlogic,meson-axg-periphs-pinctrl"
  "amlogic,meson-axg-aobus-pinctrl"
+ "amlogic,meson-g12a-periphs-pinctrl"
+ "amlogic,meson-g12a-aobus-pinctrl"
  - reg: address and size of registers controlling irq functionality
 
 === GPIO sub-nodes ===
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h 
b/include/dt-bindings/gpio/meson-g12a-gpio.h
new file mode 100644
index ..f7bd69350d18
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen 
+ */
+
+#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
+#define _DT_BINDINGS_MESON_G12A_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0   0
+#define GPIOAO_1   1
+#define GPIOAO_2   2
+#define GPIOAO_3   3
+#define GPIOAO_4   4
+#define GPIOAO_5   5
+#define GPIOAO_6   6
+#define GPIOAO_7   7
+#define GPIOAO_8   8
+#define GPIOAO_9   9
+#define GPIOAO_10  10
+#define GPIOAO_11  11
+#define GPIOE_012
+#define GPIOE_113
+#define GPIOE_214
+
+/* Second GPIO chip */
+#define GPIOZ_00
+#define GPIOZ_11
+#define GPIOZ_22
+#define GPIOZ_33
+#define GPIOZ_44
+#define GPIOZ_55
+#define GPIOZ_66
+#define GPIOZ_77
+#define GPIOZ_88
+#define GPIOZ_99
+#define GPIOZ_10   10
+#define GPIOZ_11   11
+#define GPIOZ_12   12
+#define GPIOZ_13   13
+#define GPIOZ_14   14
+#define GPIOZ_15   15
+#define GPIOH_016
+#define GPIOH_117
+#define GPIOH_218
+#define GPIOH_319
+#define GPIOH_420
+#define GPIOH_521
+#define GPIOH_622
+#define GPIOH_723
+#define GPIOH_824
+#define BOOT_0 25
+#define BOOT_1 26
+#define BOOT_2 27
+#define BOOT_3 28
+#define BOOT_4 29
+#define BOOT_5 30
+#define BOOT_6 31
+#define BOOT_7 32
+#define BOOT_8 33
+#define BOOT_9 34
+#define BOOT_1035
+#define BOOT_1136
+#define BOOT_1237
+#define BOOT_1338
+#define BOOT_1439
+#define BOOT_1540
+#define GPIOC_041
+#define GPIOC_142
+#define GPIOC_243
+#define GPIOC_344
+#define GPIOC_445
+#define GPIOC_546
+#define GPIOC_647
+#define GPIOC_748
+#define GPIOA_049
+#define GPIOA_150
+#define GPIOA_251
+#define GPIOA_352
+#define GPIOA_453
+#define GPIOA_554
+#define GPIOA_655
+#define GPIOA_756
+#define GPIOA_857
+#define GPIOA_958
+#define GPIOA_10   59
+#define GPIOA_11   60
+#define GPIOA_12   61
+#define GPIOA_13   62
+#define GPIOA_14   63
+#define GPIOA_15   64
+#define GPIOX_065
+#define GPIOX_166
+#define GPIOX_267
+#define GPIOX_368
+#define GPIOX_469
+#define GPIOX_570
+#define GPIOX_671
+#define GPIOX_772
+#define GPIOX_873
+#define GPIOX_974
+#define GPIOX_10   75
+#define GPIOX_11   76
+#define GPIOX_12   77
+#define GPIOX_13   78
+#define GPIOX_14   79
+#define GPIOX_15   80
+#define GPIOX_16   81
+#define GPIOX_17   82
+#define GPIOX_18   83
+#define GPIOX_19   84
+
+#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
-- 
2.18.0

Re: [PATCH 2/3] dt-bindings: pinctrl: meson-g12a: document pin name

[Yixun Lan]

HI Martin

thanks for the comments

On 07/14/2018 10:47 PM, Martin Blumenstingl wrote:
> Hi Yixun,
> 
> On Wed, Jul 4, 2018 at 4:49 PM Yixun Lan  wrote:
>>
>> Document the pins for Amlogic's Meson-G12A SoC.
> I suggest to combine patch 1 (adding the compatible string) and 2 (this one)
> 
> as discussed in the cover letter: it would be great if you could add a
> comment (at least to the commit message) stating that GPIOE is
> actually located (checked with the ASIC / hardware team) in the AO
> bank
> 
sure, I will state this in commit message, and will also put a note in code.

>> Signed-off-by: Yixun Lan 
> with that:
> Acked-by: Martin Blumenstingl 
> 
thanks, I assume I can add your Ack to this whole patch series
(dt-binding patch and pinctrl driver patch)?

>> ---
>>  include/dt-bindings/gpio/meson-g12a-gpio.h | 114 +
>>  1 file changed, 114 insertions(+)
>>  create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h
>>
>> diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h 
>> b/include/dt-bindings/gpio/meson-g12a-gpio.h
>> new file mode 100644
>> index ..f7bd69350d18
>> --- /dev/null
>> +++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
>> @@ -0,0 +1,114 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
>> +/*
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + * Author: Xingyu Chen 
> (since I'm not sure about all the licensing bits:) do we also need a
> "Signed-off-by" from Xingyu Chen?
> 
sure, this pinctrl driver is mostly Xingyu's work, I will add this.
> 
> Regards
> Martin
> 
> .
> 

Re: [PATCH 2/3] dt-bindings: pinctrl: meson-g12a: document pin name

[Yixun Lan]

HI Martin

thanks for the comments

On 07/14/2018 10:47 PM, Martin Blumenstingl wrote:
> Hi Yixun,
> 
> On Wed, Jul 4, 2018 at 4:49 PM Yixun Lan  wrote:
>>
>> Document the pins for Amlogic's Meson-G12A SoC.
> I suggest to combine patch 1 (adding the compatible string) and 2 (this one)
> 
> as discussed in the cover letter: it would be great if you could add a
> comment (at least to the commit message) stating that GPIOE is
> actually located (checked with the ASIC / hardware team) in the AO
> bank
> 
sure, I will state this in commit message, and will also put a note in code.

>> Signed-off-by: Yixun Lan 
> with that:
> Acked-by: Martin Blumenstingl 
> 
thanks, I assume I can add your Ack to this whole patch series
(dt-binding patch and pinctrl driver patch)?

>> ---
>>  include/dt-bindings/gpio/meson-g12a-gpio.h | 114 +
>>  1 file changed, 114 insertions(+)
>>  create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h
>>
>> diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h 
>> b/include/dt-bindings/gpio/meson-g12a-gpio.h
>> new file mode 100644
>> index ..f7bd69350d18
>> --- /dev/null
>> +++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
>> @@ -0,0 +1,114 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
>> +/*
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + * Author: Xingyu Chen 
> (since I'm not sure about all the licensing bits:) do we also need a
> "Signed-off-by" from Xingyu Chen?
> 
sure, this pinctrl driver is mostly Xingyu's work, I will add this.
> 
> Regards
> Martin
> 
> .
> 

Re: [PATCH 0/3] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

Hi Martin

see my comments

On 07/14/2018 10:36 PM, Martin Blumenstingl wrote:
> On Tue, Jul 10, 2018 at 12:07 AM Martin Blumenstingl
>  wrote:
>>
>> Hi Linus,
>>
>> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij  
>> wrote:
>>>
>>> On Wed, Jul 4, 2018 at 4:48 PM Yixun Lan  wrote:
>>>>
>>>> This patch series try to add pinctrl driver support for
>>>> the Meson-G12A SoC.
>>>>
>>>>
>>>> Yixun Lan (3):
>>>>   documentation: Add compatibles for Amlogic Meson G12A pin controllers
>>>>   dt-bindings: pinctrl: meson-g12a: document pin name
>>>>   pinctrl: meson-g12a: add pinctrl driver support
>>>
>>> Overall this looks good to me, could we get some review or ACKs
>>> from Beniamino, Martin and/or Carlo as an indication that everything
>>> seems all right before I apply the series?
>> I do not have any documentation for this hardware (I'm not even sure
>> if this is the successor to AXG/"the Audio SoCs" or rather a successor
>> of GXL or GXM/"the OTT/STB SoCs"
> for those who are interested: according to [0] the marketing name of
> this SoC will be "A311D" - specs from the linked PDF:
A311D is the G12B SoC series
This pinctrl patch is target for G12A for now, but can be very easily
extend to support G12B..
> - CPU: Quad Cortex-A73 + Dual Cortex-A53 (max frequency: TBD)
> - GPU: ARM G52 MP4 (4ppc)
> - Memory: DDR3/4 LPDDR3/4
> - Video decoding: 4K H265
> - Video Encoding: 1080P H264 H265
> - HDMI-Tx: 4K2K
> - Ethernet: 10/100M/1000M
> - AV output: CVBS
> - IP License: Dolby, DTS
> 
> W400 is the reference board for this SoC, it comes with:
> - EMMC
> - WIFI AP6398S
> - DDR 2GB
> 
yes, W400 for G12B, and U200 for G12A

> if I had to guess then I would say it's the successor of the GXL (or
> GXM?) family
> 
Yes, successor of GXL

> 
> Regards
> Martin
> 
> 
> [0] 
> http://openlinux.amlogic.com:8000/download/doc/Amlogic_A311D_Buildroot_Preview_Release_Notes_V20180706.pdf
> 
> .
> 

Re: [PATCH 0/3] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

Hi Martin

see my comments

On 07/14/2018 10:36 PM, Martin Blumenstingl wrote:
> On Tue, Jul 10, 2018 at 12:07 AM Martin Blumenstingl
>  wrote:
>>
>> Hi Linus,
>>
>> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij  
>> wrote:
>>>
>>> On Wed, Jul 4, 2018 at 4:48 PM Yixun Lan  wrote:
>>>>
>>>> This patch series try to add pinctrl driver support for
>>>> the Meson-G12A SoC.
>>>>
>>>>
>>>> Yixun Lan (3):
>>>>   documentation: Add compatibles for Amlogic Meson G12A pin controllers
>>>>   dt-bindings: pinctrl: meson-g12a: document pin name
>>>>   pinctrl: meson-g12a: add pinctrl driver support
>>>
>>> Overall this looks good to me, could we get some review or ACKs
>>> from Beniamino, Martin and/or Carlo as an indication that everything
>>> seems all right before I apply the series?
>> I do not have any documentation for this hardware (I'm not even sure
>> if this is the successor to AXG/"the Audio SoCs" or rather a successor
>> of GXL or GXM/"the OTT/STB SoCs"
> for those who are interested: according to [0] the marketing name of
> this SoC will be "A311D" - specs from the linked PDF:
A311D is the G12B SoC series
This pinctrl patch is target for G12A for now, but can be very easily
extend to support G12B..
> - CPU: Quad Cortex-A73 + Dual Cortex-A53 (max frequency: TBD)
> - GPU: ARM G52 MP4 (4ppc)
> - Memory: DDR3/4 LPDDR3/4
> - Video decoding: 4K H265
> - Video Encoding: 1080P H264 H265
> - HDMI-Tx: 4K2K
> - Ethernet: 10/100M/1000M
> - AV output: CVBS
> - IP License: Dolby, DTS
> 
> W400 is the reference board for this SoC, it comes with:
> - EMMC
> - WIFI AP6398S
> - DDR 2GB
> 
yes, W400 for G12B, and U200 for G12A

> if I had to guess then I would say it's the successor of the GXL (or
> GXM?) family
> 
Yes, successor of GXL

> 
> Regards
> Martin
> 
> 
> [0] 
> http://openlinux.amlogic.com:8000/download/doc/Amlogic_A311D_Buildroot_Preview_Release_Notes_V20180706.pdf
> 
> .
> 

Re: [PATCH v2 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Hi Rob, Jerome, Kevin

see my comments

On 07/13/18 08:15, Rob Herring wrote:
> On Thu, Jul 12, 2018 at 5:29 PM Yixun Lan  wrote:
>>
>> HI Rob
>>
>> see my comments
>>
>> On 07/12/2018 10:17 PM, Rob Herring wrote:
>>> On Wed, Jul 11, 2018 at 8:47 PM Yixun Lan  wrote:
>>>>
>>>> Hi Rob
>>>>
>>>> see my comments
>>>>
>>>> On 07/12/18 03:43, Rob Herring wrote:
>>>>> On Tue, Jul 10, 2018 at 04:36:56PM +, Yixun Lan wrote:
>>>>>> Document the MMC sub clock controller driver, the potential consumer
>>>>>> of this driver is MMC or NAND.
>>>>>
>>>>> So you all have decided to properly model this now?
>>>>>
>>>> Yes, ;-)
>>>>
>>>>>>
>>>>>> Signed-off-by: Yixun Lan 
>>>>>> ---
>>>>>>  .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
>>>>>>  1 file changed, 31 insertions(+)
>>>>>>  create mode 100644 
>>>>>> Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>>>>
>>>>>> diff --git 
>>>>>> a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
>>>>>> b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>>>> new file mode 100644
>>>>>> index ..ff6b4bf3ecf9
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>>>> @@ -0,0 +1,31 @@
>>>>>> +* Amlogic MMC Sub Clock Controller Driver
>>>>>> +
>>>>>> +The Amlogic MMC clock controller generates and supplies clock to support
>>>>>> +MMC and NAND controller
>>>>>> +
>>>>>> +Required Properties:
>>>>>> +
>>>>>> +- compatible: should be:
>>>>>> +"amlogic,meson-gx-mmc-clkc"
>>>>>> +"amlogic,meson-axg-mmc-clkc"
>>>>>> +
>>>>>> +- #clock-cells: should be 1.
>>>>>> +- clocks: phandles to clocks corresponding to the clock-names property
>>>>>> +- clock-names: list of parent clock names
>>>>>> +- "clkin0", "clkin1"
>>>>>> +
>>>>>> +Parent node should have the following properties :
>>>>>> +- compatible: "syscon", "simple-mfd, and "amlogic,meson-axg-mmc-clkc"
>>>>>
>>>>> You don't need "simple-mfd" and probably not syscon either. The order is
>>>>> wrong too. Most specific first.
>>>>>
>>>> Ok, I will drop "simple-mfd"..
>>>>
>>>> but the syscon is a must, since this mmc clock model access registers
>>>> via the regmap interface
>>>
>>> A syscon compatible should not be the only way to get a regmap.
>> do you have any suggestion about other function that I can use? is
>> devm_regmap_init_mmio() feasible
>>
>>> Removing lines 56/57 of drivers/mfd/syscon.c should be sufficient.
>>>
>> I'm not sure what's the valid point of removing compatible 'syscon' in
>> driver/mfd/syscon.c, sounds this will break a lot DT/or need to fix?
>> will you propose a patch for this? then I can certainly adjust here
> 
> Removing the 2 lines will simply allow any node to be a syscon. If
> there's a specific driver for a node, then that makes sense to allow
> that.
> 
>>
>>> Why do you need a regmap in the first place? What else needs to access
>>> this register directly?
>> Yes, the SD_EMMC_CLOCK register contain several bits which not fit well
>> into common clock model, and they need to be access in the NAND or eMMC
>> driver itself, Martin had explained this in early thread[1]
>>
>> In this register
>> Bit[31] select NAND or eMMC function
>> Bit[25] enable SDIO IRQ
>> Bit[24] Clock always on
>> Bit[15:14] SRAM Power down
>>
>> [1]
>> https://lkml.kernel.org/r/CAFBinCBeyXf6LNaZzAw6WnsxzDAv8E=yp2eem0xcpwmeui6...@mail.gmail.com
>>
>>> Don't you need a patch removing the clock code
>>> from within the emmc driver? It's not even using regmap, so using
>>> regmap here doesn't help.
>>>
>> No, and current eMMC driver still use iomap to access the register
> 
> Which means a read-modify-write can corrupt the reg

Re: [PATCH v2 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Hi Rob, Jerome, Kevin

see my comments

On 07/13/18 08:15, Rob Herring wrote:
> On Thu, Jul 12, 2018 at 5:29 PM Yixun Lan  wrote:
>>
>> HI Rob
>>
>> see my comments
>>
>> On 07/12/2018 10:17 PM, Rob Herring wrote:
>>> On Wed, Jul 11, 2018 at 8:47 PM Yixun Lan  wrote:
>>>>
>>>> Hi Rob
>>>>
>>>> see my comments
>>>>
>>>> On 07/12/18 03:43, Rob Herring wrote:
>>>>> On Tue, Jul 10, 2018 at 04:36:56PM +, Yixun Lan wrote:
>>>>>> Document the MMC sub clock controller driver, the potential consumer
>>>>>> of this driver is MMC or NAND.
>>>>>
>>>>> So you all have decided to properly model this now?
>>>>>
>>>> Yes, ;-)
>>>>
>>>>>>
>>>>>> Signed-off-by: Yixun Lan 
>>>>>> ---
>>>>>>  .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
>>>>>>  1 file changed, 31 insertions(+)
>>>>>>  create mode 100644 
>>>>>> Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>>>>
>>>>>> diff --git 
>>>>>> a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
>>>>>> b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>>>> new file mode 100644
>>>>>> index ..ff6b4bf3ecf9
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>>>> @@ -0,0 +1,31 @@
>>>>>> +* Amlogic MMC Sub Clock Controller Driver
>>>>>> +
>>>>>> +The Amlogic MMC clock controller generates and supplies clock to support
>>>>>> +MMC and NAND controller
>>>>>> +
>>>>>> +Required Properties:
>>>>>> +
>>>>>> +- compatible: should be:
>>>>>> +"amlogic,meson-gx-mmc-clkc"
>>>>>> +"amlogic,meson-axg-mmc-clkc"
>>>>>> +
>>>>>> +- #clock-cells: should be 1.
>>>>>> +- clocks: phandles to clocks corresponding to the clock-names property
>>>>>> +- clock-names: list of parent clock names
>>>>>> +- "clkin0", "clkin1"
>>>>>> +
>>>>>> +Parent node should have the following properties :
>>>>>> +- compatible: "syscon", "simple-mfd, and "amlogic,meson-axg-mmc-clkc"
>>>>>
>>>>> You don't need "simple-mfd" and probably not syscon either. The order is
>>>>> wrong too. Most specific first.
>>>>>
>>>> Ok, I will drop "simple-mfd"..
>>>>
>>>> but the syscon is a must, since this mmc clock model access registers
>>>> via the regmap interface
>>>
>>> A syscon compatible should not be the only way to get a regmap.
>> do you have any suggestion about other function that I can use? is
>> devm_regmap_init_mmio() feasible
>>
>>> Removing lines 56/57 of drivers/mfd/syscon.c should be sufficient.
>>>
>> I'm not sure what's the valid point of removing compatible 'syscon' in
>> driver/mfd/syscon.c, sounds this will break a lot DT/or need to fix?
>> will you propose a patch for this? then I can certainly adjust here
> 
> Removing the 2 lines will simply allow any node to be a syscon. If
> there's a specific driver for a node, then that makes sense to allow
> that.
> 
>>
>>> Why do you need a regmap in the first place? What else needs to access
>>> this register directly?
>> Yes, the SD_EMMC_CLOCK register contain several bits which not fit well
>> into common clock model, and they need to be access in the NAND or eMMC
>> driver itself, Martin had explained this in early thread[1]
>>
>> In this register
>> Bit[31] select NAND or eMMC function
>> Bit[25] enable SDIO IRQ
>> Bit[24] Clock always on
>> Bit[15:14] SRAM Power down
>>
>> [1]
>> https://lkml.kernel.org/r/CAFBinCBeyXf6LNaZzAw6WnsxzDAv8E=yp2eem0xcpwmeui6...@mail.gmail.com
>>
>>> Don't you need a patch removing the clock code
>>> from within the emmc driver? It's not even using regmap, so using
>>> regmap here doesn't help.
>>>
>> No, and current eMMC driver still use iomap to access the register
> 
> Which means a read-modify-write can corrupt the reg

Re: [PATCH v2 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

HI Rob

see my comments

On 07/12/2018 10:17 PM, Rob Herring wrote:
> On Wed, Jul 11, 2018 at 8:47 PM Yixun Lan  wrote:
>>
>> Hi Rob
>>
>> see my comments
>>
>> On 07/12/18 03:43, Rob Herring wrote:
>>> On Tue, Jul 10, 2018 at 04:36:56PM +, Yixun Lan wrote:
>>>> Document the MMC sub clock controller driver, the potential consumer
>>>> of this driver is MMC or NAND.
>>>
>>> So you all have decided to properly model this now?
>>>
>> Yes, ;-)
>>
>>>>
>>>> Signed-off-by: Yixun Lan 
>>>> ---
>>>>  .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
>>>>  1 file changed, 31 insertions(+)
>>>>  create mode 100644 
>>>> Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
>>>> b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>> new file mode 100644
>>>> index ..ff6b4bf3ecf9
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>> @@ -0,0 +1,31 @@
>>>> +* Amlogic MMC Sub Clock Controller Driver
>>>> +
>>>> +The Amlogic MMC clock controller generates and supplies clock to support
>>>> +MMC and NAND controller
>>>> +
>>>> +Required Properties:
>>>> +
>>>> +- compatible: should be:
>>>> +"amlogic,meson-gx-mmc-clkc"
>>>> +"amlogic,meson-axg-mmc-clkc"
>>>> +
>>>> +- #clock-cells: should be 1.
>>>> +- clocks: phandles to clocks corresponding to the clock-names property
>>>> +- clock-names: list of parent clock names
>>>> +- "clkin0", "clkin1"
>>>> +
>>>> +Parent node should have the following properties :
>>>> +- compatible: "syscon", "simple-mfd, and "amlogic,meson-axg-mmc-clkc"
>>>
>>> You don't need "simple-mfd" and probably not syscon either. The order is
>>> wrong too. Most specific first.
>>>
>> Ok, I will drop "simple-mfd"..
>>
>> but the syscon is a must, since this mmc clock model access registers
>> via the regmap interface
> 
> A syscon compatible should not be the only way to get a regmap.
do you have any suggestion about other function that I can use? is
devm_regmap_init_mmio() feasible

> Removing lines 56/57 of drivers/mfd/syscon.c should be sufficient.
> 
I'm not sure what's the valid point of removing compatible 'syscon' in
driver/mfd/syscon.c, sounds this will break a lot DT/or need to fix?
will you propose a patch for this? then I can certainly adjust here

> Why do you need a regmap in the first place? What else needs to access
> this register directly?
Yes, the SD_EMMC_CLOCK register contain several bits which not fit well
into common clock model, and they need to be access in the NAND or eMMC
driver itself, Martin had explained this in early thread[1]

In this register
Bit[31] select NAND or eMMC function
Bit[25] enable SDIO IRQ
Bit[24] Clock always on
Bit[15:14] SRAM Power down

[1]
https://lkml.kernel.org/r/CAFBinCBeyXf6LNaZzAw6WnsxzDAv8E=yp2eem0xcpwmeui6...@mail.gmail.com

> Don't you need a patch removing the clock code
> from within the emmc driver? It's not even using regmap, so using
> regmap here doesn't help.
>
No, and current eMMC driver still use iomap to access the register

I think we probably would like to take two steps approach.
first, from the hardware perspective, the NAND and eMMC(port C) driver
can't exist at same time, since they share the pins, clock, internal
ram, So we have to only enable one of NAND or eMMC in DT, not enable
both of them.
Second, we might like to convert eMMC driver to also use mmc-clkc model.


Yixun

Re: [PATCH v2 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

HI Rob

see my comments

On 07/12/2018 10:17 PM, Rob Herring wrote:
> On Wed, Jul 11, 2018 at 8:47 PM Yixun Lan  wrote:
>>
>> Hi Rob
>>
>> see my comments
>>
>> On 07/12/18 03:43, Rob Herring wrote:
>>> On Tue, Jul 10, 2018 at 04:36:56PM +, Yixun Lan wrote:
>>>> Document the MMC sub clock controller driver, the potential consumer
>>>> of this driver is MMC or NAND.
>>>
>>> So you all have decided to properly model this now?
>>>
>> Yes, ;-)
>>
>>>>
>>>> Signed-off-by: Yixun Lan 
>>>> ---
>>>>  .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
>>>>  1 file changed, 31 insertions(+)
>>>>  create mode 100644 
>>>> Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
>>>> b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>> new file mode 100644
>>>> index ..ff6b4bf3ecf9
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>>> @@ -0,0 +1,31 @@
>>>> +* Amlogic MMC Sub Clock Controller Driver
>>>> +
>>>> +The Amlogic MMC clock controller generates and supplies clock to support
>>>> +MMC and NAND controller
>>>> +
>>>> +Required Properties:
>>>> +
>>>> +- compatible: should be:
>>>> +"amlogic,meson-gx-mmc-clkc"
>>>> +"amlogic,meson-axg-mmc-clkc"
>>>> +
>>>> +- #clock-cells: should be 1.
>>>> +- clocks: phandles to clocks corresponding to the clock-names property
>>>> +- clock-names: list of parent clock names
>>>> +- "clkin0", "clkin1"
>>>> +
>>>> +Parent node should have the following properties :
>>>> +- compatible: "syscon", "simple-mfd, and "amlogic,meson-axg-mmc-clkc"
>>>
>>> You don't need "simple-mfd" and probably not syscon either. The order is
>>> wrong too. Most specific first.
>>>
>> Ok, I will drop "simple-mfd"..
>>
>> but the syscon is a must, since this mmc clock model access registers
>> via the regmap interface
> 
> A syscon compatible should not be the only way to get a regmap.
do you have any suggestion about other function that I can use? is
devm_regmap_init_mmio() feasible

> Removing lines 56/57 of drivers/mfd/syscon.c should be sufficient.
> 
I'm not sure what's the valid point of removing compatible 'syscon' in
driver/mfd/syscon.c, sounds this will break a lot DT/or need to fix?
will you propose a patch for this? then I can certainly adjust here

> Why do you need a regmap in the first place? What else needs to access
> this register directly?
Yes, the SD_EMMC_CLOCK register contain several bits which not fit well
into common clock model, and they need to be access in the NAND or eMMC
driver itself, Martin had explained this in early thread[1]

In this register
Bit[31] select NAND or eMMC function
Bit[25] enable SDIO IRQ
Bit[24] Clock always on
Bit[15:14] SRAM Power down

[1]
https://lkml.kernel.org/r/CAFBinCBeyXf6LNaZzAw6WnsxzDAv8E=yp2eem0xcpwmeui6...@mail.gmail.com

> Don't you need a patch removing the clock code
> from within the emmc driver? It's not even using regmap, so using
> regmap here doesn't help.
>
No, and current eMMC driver still use iomap to access the register

I think we probably would like to take two steps approach.
first, from the hardware perspective, the NAND and eMMC(port C) driver
can't exist at same time, since they share the pins, clock, internal
ram, So we have to only enable one of NAND or eMMC in DT, not enable
both of them.
Second, we might like to convert eMMC driver to also use mmc-clkc model.


Yixun

[PATCH v3 2/2] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.

Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.

To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
can be used in the device tree sources.

Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Kconfig|   9 +
 drivers/clk/meson/Makefile   |   1 +
 drivers/clk/meson/mmc-clkc.c | 367 +++
 3 files changed, 377 insertions(+)
 create mode 100644 drivers/clk/meson/mmc-clkc.c

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f682b4..edc18e65c89b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
 
+config COMMON_CLK_MMC_MESON
+   tristate "Meson MMC Sub Clock Controller Driver"
+   depends on COMMON_CLK_AMLOGIC
+   select MFD_SYSCON
+   select REGMAP
+   help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ Say Y if you want this clock enabled.
+
 config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c40d848..4b3817f80ba1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index ..36c4c7cd69a6
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+#define CLKID_MMC_MUX  0
+#define CLKID_MMC_PHASE_CORE   2
+
+#define SD_EMMC_CLOCK  0
+#define   CLK_DIV_MASK GENMASK(5, 0)
+#define   CLK_SRC_MASK GENMASK(7, 6)
+#define   CLK_CORE_PHASE_MASK  GENMASK(9, 8)
+#define   CLK_TX_PHASE_MASKGENMASK(11, 10)
+#define   CLK_RX_PHASE_MASKGENMASK(13, 12)
+#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define   CLK_V2_ALWAYS_ON BIT(24)
+
+#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define   CLK_V3_ALWAYS_ON BIT(28)
+
+#define   CLK_DELAY_STEP_PS200
+#define   CLK_PHASE_STEP   30
+#define   CLK_PHASE_POINT_NUM  (360 / CLK_PHASE_STEP)
+
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS   5
+
+struct clk_phase_delay_data {
+   unsigned long   phase_mask;
+   unsigned long   delay_mask;
+   unsigned intdelay_step_ps;
+};
+
+struct mmc_clkc_data {
+   struct clk_phase_delay_data tx;
+   struct clk_phase_delay_data rx;
+};
+
+static inline struct clk_phase_delay_data *
+clk_get_regmap_phase_data(struct clk_regmap *clk)
+{
+   return (struct clk_phase_delay_data *)clk->data;
+}
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+   .offset = SD_EMMC_CLOCK,
+   .mask   = 0x3,
+   .shift  = 6,
+   .flags  = CLK_DIVIDER_ROUND_CLOSEST,
+};
+
+static struct clk_regmap_div_data mmc_clkc_div_data = {
+   .offset = SD_EMMC_CLOCK,
+   .shift  = 0,
+   .width  = 6,
+   .flags  = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED,
+};
+
+static struct clk_phase_delay_data mmc_clkc_core_delay_phase = {
+   .phase_mask = CLK_CORE_PHASE_MASK,
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_MASK,
+   .delay_mask = CLK_V2_TX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+   {
+   .phase_mask = CLK_RX_PHASE_MASK,
+   .delay_mask = CLK_V2_RX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+};
+
+

[PATCH v3 2/2] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.

Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.

To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
can be used in the device tree sources.

Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Kconfig|   9 +
 drivers/clk/meson/Makefile   |   1 +
 drivers/clk/meson/mmc-clkc.c | 367 +++
 3 files changed, 377 insertions(+)
 create mode 100644 drivers/clk/meson/mmc-clkc.c

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f682b4..edc18e65c89b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
 
+config COMMON_CLK_MMC_MESON
+   tristate "Meson MMC Sub Clock Controller Driver"
+   depends on COMMON_CLK_AMLOGIC
+   select MFD_SYSCON
+   select REGMAP
+   help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ Say Y if you want this clock enabled.
+
 config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c40d848..4b3817f80ba1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index ..36c4c7cd69a6
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+#define CLKID_MMC_MUX  0
+#define CLKID_MMC_PHASE_CORE   2
+
+#define SD_EMMC_CLOCK  0
+#define   CLK_DIV_MASK GENMASK(5, 0)
+#define   CLK_SRC_MASK GENMASK(7, 6)
+#define   CLK_CORE_PHASE_MASK  GENMASK(9, 8)
+#define   CLK_TX_PHASE_MASKGENMASK(11, 10)
+#define   CLK_RX_PHASE_MASKGENMASK(13, 12)
+#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define   CLK_V2_ALWAYS_ON BIT(24)
+
+#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define   CLK_V3_ALWAYS_ON BIT(28)
+
+#define   CLK_DELAY_STEP_PS200
+#define   CLK_PHASE_STEP   30
+#define   CLK_PHASE_POINT_NUM  (360 / CLK_PHASE_STEP)
+
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS   5
+
+struct clk_phase_delay_data {
+   unsigned long   phase_mask;
+   unsigned long   delay_mask;
+   unsigned intdelay_step_ps;
+};
+
+struct mmc_clkc_data {
+   struct clk_phase_delay_data tx;
+   struct clk_phase_delay_data rx;
+};
+
+static inline struct clk_phase_delay_data *
+clk_get_regmap_phase_data(struct clk_regmap *clk)
+{
+   return (struct clk_phase_delay_data *)clk->data;
+}
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+   .offset = SD_EMMC_CLOCK,
+   .mask   = 0x3,
+   .shift  = 6,
+   .flags  = CLK_DIVIDER_ROUND_CLOSEST,
+};
+
+static struct clk_regmap_div_data mmc_clkc_div_data = {
+   .offset = SD_EMMC_CLOCK,
+   .shift  = 0,
+   .width  = 6,
+   .flags  = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED,
+};
+
+static struct clk_phase_delay_data mmc_clkc_core_delay_phase = {
+   .phase_mask = CLK_CORE_PHASE_MASK,
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_MASK,
+   .delay_mask = CLK_V2_TX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+   {
+   .phase_mask = CLK_RX_PHASE_MASK,
+   .delay_mask = CLK_V2_RX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+};
+
+

[PATCH v3 1/2] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add three clock bindings IDs which
provided by this driver.

Signed-off-by: Yixun Lan 
---
 .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
 .../clock/amlogic,meson-mmc-clkc.h| 16 ++
 2 files changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index ..91018221df1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,31 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+   "amlogic,meson-gx-mmc-clkc"
+   "amlogic,meson-axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+   - "clkin0", "clkin1"
+
+Parent node should have the following properties :
+- compatible: "amlogic,meson-axg-mmc-clkc", "syscon".
+- reg: base address and size of the MMC control register space.
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+   compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+   reg = <0x0 0x7000 0x0 0x4>;
+   #clock-cells = <1>;
+
+   clock-names = "clkin0", "clkin1";
+   clocks = < CLKID_SD_MMC_C_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h 
b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
new file mode 100644
index ..2ae988ebc3ae
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan 
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV  1
+#define CLKID_MMC_PHASE_TX 3
+#define CLKID_MMC_PHASE_RX 4
+
+#endif
-- 
2.18.0

[PATCH v3 1/2] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add three clock bindings IDs which
provided by this driver.

Signed-off-by: Yixun Lan 
---
 .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
 .../clock/amlogic,meson-mmc-clkc.h| 16 ++
 2 files changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index ..91018221df1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,31 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+   "amlogic,meson-gx-mmc-clkc"
+   "amlogic,meson-axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+   - "clkin0", "clkin1"
+
+Parent node should have the following properties :
+- compatible: "amlogic,meson-axg-mmc-clkc", "syscon".
+- reg: base address and size of the MMC control register space.
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+   compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+   reg = <0x0 0x7000 0x0 0x4>;
+   #clock-cells = <1>;
+
+   clock-names = "clkin0", "clkin1";
+   clocks = < CLKID_SD_MMC_C_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h 
b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
new file mode 100644
index ..2ae988ebc3ae
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan 
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV  1
+#define CLKID_MMC_PHASE_TX 3
+#define CLKID_MMC_PHASE_RX 4
+
+#endif
-- 
2.18.0

[PATCH v3 0/2] clk: meson: add a sub EMMC clock controller support

[Yixun Lan]

This driver will add a MMC clock controller driver support.
The original idea about adding a clock controller is during the
discussion in the NAND driver mainline effort[1].

I've tested this in the S400 board (AXG platform) by using NAND driver.

Changes since v2 [3]:
 - squash dt-binding clock-id patch
 - update license
 - fix alignment
 - construct a clk register helper() function

Changes since v1 [2]:
 - implement phase clock
 - update compatible name
 - adjust file name
 - divider probe() into small functions, and re-use them

[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com
[3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com


Yixun Lan (2):
  clk: meson: add DT documentation for emmc clock controller
  clk: meson: add sub MMC clock controller driver

 .../bindings/clock/amlogic,mmc-clkc.txt   |  31 ++
 drivers/clk/meson/Kconfig |   9 +
 drivers/clk/meson/Makefile|   1 +
 drivers/clk/meson/mmc-clkc.c  | 367 ++
 .../clock/amlogic,meson-mmc-clkc.h|  16 +
 5 files changed, 424 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 drivers/clk/meson/mmc-clkc.c
 create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h

-- 
2.18.0

[PATCH v3 0/2] clk: meson: add a sub EMMC clock controller support

[Yixun Lan]

This driver will add a MMC clock controller driver support.
The original idea about adding a clock controller is during the
discussion in the NAND driver mainline effort[1].

I've tested this in the S400 board (AXG platform) by using NAND driver.

Changes since v2 [3]:
 - squash dt-binding clock-id patch
 - update license
 - fix alignment
 - construct a clk register helper() function

Changes since v1 [2]:
 - implement phase clock
 - update compatible name
 - adjust file name
 - divider probe() into small functions, and re-use them

[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com
[3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com


Yixun Lan (2):
  clk: meson: add DT documentation for emmc clock controller
  clk: meson: add sub MMC clock controller driver

 .../bindings/clock/amlogic,mmc-clkc.txt   |  31 ++
 drivers/clk/meson/Kconfig |   9 +
 drivers/clk/meson/Makefile|   1 +
 drivers/clk/meson/mmc-clkc.c  | 367 ++
 .../clock/amlogic,meson-mmc-clkc.h|  16 +
 5 files changed, 424 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 drivers/clk/meson/mmc-clkc.c
 create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h

-- 
2.18.0

Re: [PATCH v2 3/3] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

Hi Jerome

thanks for the review

On 07/12/18 17:09, Jerome Brunet wrote:
> On Tue, 2018-07-10 at 16:36 +0000, Yixun Lan wrote:
>> The patch will add a MMC clock controller driver which used by MMC or NAND,
>> It provide a mux and divider clock, and three phase clocks - core, tx, tx.
>>
>> Two clocks are provided as the parent of MMC clock controller from
>> upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.
>>
>> To specify which clock the MMC or NAND driver may consume,
>> the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
>> can be used in the device tree sources.
>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  drivers/clk/meson/Kconfig|   9 +
>>  drivers/clk/meson/Makefile   |   1 +
>>  drivers/clk/meson/mmc-clkc.c | 419 +++
>>  3 files changed, 429 insertions(+)
>>  create mode 100644 drivers/clk/meson/mmc-clkc.c
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index efaa70f682b4..edc18e65c89b 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO
>>  select COMMON_CLK_REGMAP_MESON
>>  select RESET_CONTROLLER
>>  
>> +config COMMON_CLK_MMC_MESON
>> +tristate "Meson MMC Sub Clock Controller Driver"
>> +depends on COMMON_CLK_AMLOGIC
>> +select MFD_SYSCON
>> +select REGMAP
>> +help
>> +  Support for the MMC sub clock controller on Amlogic Meson Platform,
>> +  Say Y if you want this clock enabled.
>> +
>>  config COMMON_CLK_REGMAP_MESON
>>  bool
>>  select REGMAP
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 72ec8c40d848..4b3817f80ba1 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>>  obj-$(CONFIG_COMMON_CLK_GXBB)+= gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>>  obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
>>  obj-$(CONFIG_COMMON_CLK_AXG_AUDIO)  += axg-audio.o
>> +obj-$(CONFIG_COMMON_CLK_MMC_MESON)  += mmc-clkc.o
>>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)   += clk-regmap.o
>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>> new file mode 100644
>> index ..43b7a376746d
>> --- /dev/null
>> +++ b/drivers/clk/meson/mmc-clkc.c
>> @@ -0,0 +1,419 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Amlogic Meson MMC Sub Clock Controller Driver
> 
>  * Copyright (c) 2017 Baylibre SAS.
>  * Author: Jerome Brunet 
> 
> Considering that a fair share of the code below has been copied from the clock
> portion of the eMMC driver, which I wrote last year.
> 
Ok, fair enough, will fix in next version

>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Yixun Lan 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "clkc.h"
>> +
>> +/* clock ID used by internal driver */
>> +#define CLKID_MMC_MUX   0
>> +#define CLKID_MMC_PHASE_CORE2
>> +
>> +#define SD_EMMC_CLOCK   0
>> +#define   CLK_DIV_MASK GENMASK(5, 0)
>> +#define   CLK_SRC_MASK GENMASK(7, 6)
>> +#define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
>> +#define   CLK_TX_PHASE_MASK GENMASK(11, 10)
>> +#define   CLK_RX_PHASE_MASK GENMASK(13, 12)
>> +#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
>> +#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
>> +#define   CLK_V2_ALWAYS_ON BIT(24)
>> +
>> +#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
>> +#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
>> +#define   CLK_V3_ALWAYS_ON BIT(28)
>> +
>> +#define   CLK_DELAY_STEP_PS 200
>> +#define   CLK_PHASE_STEP 30
>> +#define   CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
>> +
>> +#define MUX_CLK_NUM_PARENTS 2
>> +#define MMC_MAX_CLKS5
> 
> Some defines are aligned, some aren't. please be consistent about it.
> I personally prefer when things are aligned but it is just a preference.  
> 
sounds good to me, I can fix this in next version

>> +
>> +struct clk_regmap_phase_data {
> 
> Considering the recent addition of clk_phase in clk/meson, it is not the best
> name to choose.
> 
> clk_phase_delay_data ?
> 
ok

>> +u

Re: [PATCH v2 3/3] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

Hi Jerome

thanks for the review

On 07/12/18 17:09, Jerome Brunet wrote:
> On Tue, 2018-07-10 at 16:36 +0000, Yixun Lan wrote:
>> The patch will add a MMC clock controller driver which used by MMC or NAND,
>> It provide a mux and divider clock, and three phase clocks - core, tx, tx.
>>
>> Two clocks are provided as the parent of MMC clock controller from
>> upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.
>>
>> To specify which clock the MMC or NAND driver may consume,
>> the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
>> can be used in the device tree sources.
>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  drivers/clk/meson/Kconfig|   9 +
>>  drivers/clk/meson/Makefile   |   1 +
>>  drivers/clk/meson/mmc-clkc.c | 419 +++
>>  3 files changed, 429 insertions(+)
>>  create mode 100644 drivers/clk/meson/mmc-clkc.c
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index efaa70f682b4..edc18e65c89b 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO
>>  select COMMON_CLK_REGMAP_MESON
>>  select RESET_CONTROLLER
>>  
>> +config COMMON_CLK_MMC_MESON
>> +tristate "Meson MMC Sub Clock Controller Driver"
>> +depends on COMMON_CLK_AMLOGIC
>> +select MFD_SYSCON
>> +select REGMAP
>> +help
>> +  Support for the MMC sub clock controller on Amlogic Meson Platform,
>> +  Say Y if you want this clock enabled.
>> +
>>  config COMMON_CLK_REGMAP_MESON
>>  bool
>>  select REGMAP
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 72ec8c40d848..4b3817f80ba1 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>>  obj-$(CONFIG_COMMON_CLK_GXBB)+= gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>>  obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
>>  obj-$(CONFIG_COMMON_CLK_AXG_AUDIO)  += axg-audio.o
>> +obj-$(CONFIG_COMMON_CLK_MMC_MESON)  += mmc-clkc.o
>>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)   += clk-regmap.o
>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>> new file mode 100644
>> index ..43b7a376746d
>> --- /dev/null
>> +++ b/drivers/clk/meson/mmc-clkc.c
>> @@ -0,0 +1,419 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Amlogic Meson MMC Sub Clock Controller Driver
> 
>  * Copyright (c) 2017 Baylibre SAS.
>  * Author: Jerome Brunet 
> 
> Considering that a fair share of the code below has been copied from the clock
> portion of the eMMC driver, which I wrote last year.
> 
Ok, fair enough, will fix in next version

>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Yixun Lan 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "clkc.h"
>> +
>> +/* clock ID used by internal driver */
>> +#define CLKID_MMC_MUX   0
>> +#define CLKID_MMC_PHASE_CORE2
>> +
>> +#define SD_EMMC_CLOCK   0
>> +#define   CLK_DIV_MASK GENMASK(5, 0)
>> +#define   CLK_SRC_MASK GENMASK(7, 6)
>> +#define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
>> +#define   CLK_TX_PHASE_MASK GENMASK(11, 10)
>> +#define   CLK_RX_PHASE_MASK GENMASK(13, 12)
>> +#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
>> +#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
>> +#define   CLK_V2_ALWAYS_ON BIT(24)
>> +
>> +#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
>> +#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
>> +#define   CLK_V3_ALWAYS_ON BIT(28)
>> +
>> +#define   CLK_DELAY_STEP_PS 200
>> +#define   CLK_PHASE_STEP 30
>> +#define   CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
>> +
>> +#define MUX_CLK_NUM_PARENTS 2
>> +#define MMC_MAX_CLKS5
> 
> Some defines are aligned, some aren't. please be consistent about it.
> I personally prefer when things are aligned but it is just a preference.  
> 
sounds good to me, I can fix this in next version

>> +
>> +struct clk_regmap_phase_data {
> 
> Considering the recent addition of clk_phase in clk/meson, it is not the best
> name to choose.
> 
> clk_phase_delay_data ?
> 
ok

>> +u

Re: [PATCH v2 2/3] clk: meson: add sub MMC clock dt-bindings IDs

[Yixun Lan]

Hi Rob

On 07/12/18 03:45, Rob Herring wrote:
> On Tue, Jul 10, 2018 at 04:36:57PM +0000, Yixun Lan wrote:
>> Add two clock bindings IDs which provided by the MMC clock controller,
>> These two clocks will be used by MMC or NAND driver.
> 
> I count 3 ids.
I will update this

> 
>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  .../dt-bindings/clock/amlogic,meson-mmc-clkc.h   | 16 
>>  1 file changed, 16 insertions(+)
>>  create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
> 
> This can go with the binding patch.
> 
sure

.

Re: [PATCH v2 2/3] clk: meson: add sub MMC clock dt-bindings IDs

[Yixun Lan]

Hi Rob

On 07/12/18 03:45, Rob Herring wrote:
> On Tue, Jul 10, 2018 at 04:36:57PM +0000, Yixun Lan wrote:
>> Add two clock bindings IDs which provided by the MMC clock controller,
>> These two clocks will be used by MMC or NAND driver.
> 
> I count 3 ids.
I will update this

> 
>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  .../dt-bindings/clock/amlogic,meson-mmc-clkc.h   | 16 
>>  1 file changed, 16 insertions(+)
>>  create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
> 
> This can go with the binding patch.
> 
sure

.

Re: [PATCH v2 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Hi Rob

see my comments

On 07/12/18 03:43, Rob Herring wrote:
> On Tue, Jul 10, 2018 at 04:36:56PM +0000, Yixun Lan wrote:
>> Document the MMC sub clock controller driver, the potential consumer
>> of this driver is MMC or NAND.
> 
> So you all have decided to properly model this now?
> 
Yes, ;-)

>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
>>  1 file changed, 31 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
>> b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>> new file mode 100644
>> index ..ff6b4bf3ecf9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>> @@ -0,0 +1,31 @@
>> +* Amlogic MMC Sub Clock Controller Driver
>> +
>> +The Amlogic MMC clock controller generates and supplies clock to support
>> +MMC and NAND controller
>> +
>> +Required Properties:
>> +
>> +- compatible: should be:
>> +"amlogic,meson-gx-mmc-clkc"
>> +"amlogic,meson-axg-mmc-clkc"
>> +
>> +- #clock-cells: should be 1.
>> +- clocks: phandles to clocks corresponding to the clock-names property
>> +- clock-names: list of parent clock names
>> +- "clkin0", "clkin1"
>> +
>> +Parent node should have the following properties :
>> +- compatible: "syscon", "simple-mfd, and "amlogic,meson-axg-mmc-clkc"
> 
> You don't need "simple-mfd" and probably not syscon either. The order is 
> wrong too. Most specific first.
> 
Ok, I will drop "simple-mfd"..

but the syscon is a must, since this mmc clock model access registers
via the regmap interface

I will fix the order, thanks for pointing this out

>> +- reg: base address and size of the MMC control register space.
>> +
>> +Example: Clock controller node:
>> +
>> +sd_mmc_c_clkc: clock-controller@7000 {
>> +compatible = "amlogic,mmc-clkc", "syscon", "simple-mfd";
> 
> Doesn't match the binding...
> 
oops, I will update this

>> +reg = <0x0 0x7000 0x0 0x4>;
>> +#clock-cells = <1>;
>> +
>> +clock-names = "clkin0", "clkin1";
>> +clocks = < CLKID_SD_MMC_C_CLK0>,
>> +< CLKID_FCLK_DIV2>;
>> +};
>> -- 
>> 2.18.0
>>
> 
> .
> 

Re: [PATCH v2 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Hi Rob

see my comments

On 07/12/18 03:43, Rob Herring wrote:
> On Tue, Jul 10, 2018 at 04:36:56PM +0000, Yixun Lan wrote:
>> Document the MMC sub clock controller driver, the potential consumer
>> of this driver is MMC or NAND.
> 
> So you all have decided to properly model this now?
> 
Yes, ;-)

>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  .../bindings/clock/amlogic,mmc-clkc.txt   | 31 +++
>>  1 file changed, 31 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt 
>> b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>> new file mode 100644
>> index ..ff6b4bf3ecf9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>> @@ -0,0 +1,31 @@
>> +* Amlogic MMC Sub Clock Controller Driver
>> +
>> +The Amlogic MMC clock controller generates and supplies clock to support
>> +MMC and NAND controller
>> +
>> +Required Properties:
>> +
>> +- compatible: should be:
>> +"amlogic,meson-gx-mmc-clkc"
>> +"amlogic,meson-axg-mmc-clkc"
>> +
>> +- #clock-cells: should be 1.
>> +- clocks: phandles to clocks corresponding to the clock-names property
>> +- clock-names: list of parent clock names
>> +- "clkin0", "clkin1"
>> +
>> +Parent node should have the following properties :
>> +- compatible: "syscon", "simple-mfd, and "amlogic,meson-axg-mmc-clkc"
> 
> You don't need "simple-mfd" and probably not syscon either. The order is 
> wrong too. Most specific first.
> 
Ok, I will drop "simple-mfd"..

but the syscon is a must, since this mmc clock model access registers
via the regmap interface

I will fix the order, thanks for pointing this out

>> +- reg: base address and size of the MMC control register space.
>> +
>> +Example: Clock controller node:
>> +
>> +sd_mmc_c_clkc: clock-controller@7000 {
>> +compatible = "amlogic,mmc-clkc", "syscon", "simple-mfd";
> 
> Doesn't match the binding...
> 
oops, I will update this

>> +reg = <0x0 0x7000 0x0 0x4>;
>> +#clock-cells = <1>;
>> +
>> +clock-names = "clkin0", "clkin1";
>> +clocks = < CLKID_SD_MMC_C_CLK0>,
>> +< CLKID_FCLK_DIV2>;
>> +};
>> -- 
>> 2.18.0
>>
> 
> .
> 

Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver

[Yixun Lan]

Hi Jerome:

just one comment

On 07/10/2018 05:54 PM, Jerome Brunet wrote:
> On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
>> HI Martin
>>
>>
>> On 07/10/18 05:53, Martin Blumenstingl wrote:
>>> On Mon, Jul 9, 2018 at 1:14 PM Jian Hu  wrote:
>>>>
>>>> Add a Clock driver for the Everyting-Else part
>>>> of the Amlogic Meson-G12A SoC.
>>>>
>>>> Signed-off-by: Jian Hu 
> 
> This patch does not apply against g...@github.com:BayLibre/clk-meson.git
> 
> Please rebase on top of the "next/drivers" branch.
> Also please review the Kconfig part as changes have happened there.
> 
>>>> ---
>>>>  drivers/clk/meson/Kconfig  |  10 +
>>>>  drivers/clk/meson/Makefile |   1 +
>>>>  drivers/clk/meson/g12a.c   | 992 
>>>> +
>>>>  drivers/clk/meson/g12a.h   | 123 ++
>>>>  4 files changed, 1126 insertions(+)
>>>>  create mode 100644 drivers/clk/meson/g12a.c
>>>>  create mode 100644 drivers/clk/meson/g12a.h
>>>>
>>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>>>> index d5cbec5..94a82f73 100644
>>>> --- a/drivers/clk/meson/Kconfig
>>>> +++ b/drivers/clk/meson/Kconfig
>>>> @@ -36,3 +36,13 @@ config COMMON_CLK_AXG
>>>> help
>>>>   Support for the clock controller on AmLogic A113D devices, aka 
>>>> axg.
>>>>   Say Y if you want peripherals and CPU frequency scaling to work.
>>>> +
>>>> +config COMMON_CLK_G12A
>>>> +   bool
>>>> +   depends on COMMON_CLK_AMLOGIC
>>>> +   select RESET_CONTROLLER
>>>> +   select COMMON_CLK_REGMAP_MESON
>>>> +   select MFD_SYSCON
>>>> +   help
>>>> + Support for the clock controller on AmLogic U400 devices, aka 
>>>> g12a.
> 
> I suppose U400 is the designation of the ref design board, not the SoC, right 
> ?
> If this is case, please provide the SoC reference instead.
> 
>>>> + Say Y if you want peripherals and CPU frequency scaling to work.
>>>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>>>> index fa6d1e3..45d107c 100644
>>>> --- a/drivers/clk/meson/Makefile
>>>> +++ b/drivers/clk/meson/Makefile
>>>> @@ -6,4 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o 
>>>> clk-audio-divider.o
>>>>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>>>>  obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o meson-aoclk.o gxbb-aoclk.o 
>>>> gxbb-aoclk-32k.o
>>>>  obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o meson-aoclk.o axg-aoclk.o
>>>> +obj-$(CONFIG_COMMON_CLK_G12A)   += g12a.o
>>>>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
>>>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>>>> new file mode 100644
>>>> index 000..3675697
>>>> --- /dev/null
>>>> +++ b/drivers/clk/meson/g12a.c
>>>> @@ -0,0 +1,992 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +/*
>>>> + * AmLogic Meson-G12A Clock Controller Driver
> 
> I thought you guys stopped writing amlogic with this camel case.
> Please be consistent about it
> 
>>>> + *
>>>> + * Copyright (c) 2016 Baylibre SAS.
>>>> + * Author: Michael Turquette 
>>>> + *
>>>> + * Copyright (c) 2018 Amlogic, inc.
>>>> + * Author: Jian Hu 
>>>> + * Author: Qiufang Dai 
>>>> + */
>>>> +
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +
>>>> +#include "clkc.h"
>>>> +#include "g12a.h"
>>>> +
>>>> +static DEFINE_SPINLOCK(meson_clk_lock);
>>>> +
>>>> +static struct clk_regmap g12a_fixed_pll = {
>>>> +   .data = &(struct meson_clk_pll_data){
>>>> +   .m = {
>>>> +   .reg_off = HHI_FIX_PLL_CNTL0,
>>>> +   .shift   = 0,
>>>> +   .width   = 8,
>>>> +   },
>>>> +   .n = {
>>>> +   .reg_off = HHI_FIX_PLL_CNTL0,
>>>> +   .shift   = 10,
>>

Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver

[Yixun Lan]

Hi Jerome:

just one comment

On 07/10/2018 05:54 PM, Jerome Brunet wrote:
> On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
>> HI Martin
>>
>>
>> On 07/10/18 05:53, Martin Blumenstingl wrote:
>>> On Mon, Jul 9, 2018 at 1:14 PM Jian Hu  wrote:
>>>>
>>>> Add a Clock driver for the Everyting-Else part
>>>> of the Amlogic Meson-G12A SoC.
>>>>
>>>> Signed-off-by: Jian Hu 
> 
> This patch does not apply against g...@github.com:BayLibre/clk-meson.git
> 
> Please rebase on top of the "next/drivers" branch.
> Also please review the Kconfig part as changes have happened there.
> 
>>>> ---
>>>>  drivers/clk/meson/Kconfig  |  10 +
>>>>  drivers/clk/meson/Makefile |   1 +
>>>>  drivers/clk/meson/g12a.c   | 992 
>>>> +
>>>>  drivers/clk/meson/g12a.h   | 123 ++
>>>>  4 files changed, 1126 insertions(+)
>>>>  create mode 100644 drivers/clk/meson/g12a.c
>>>>  create mode 100644 drivers/clk/meson/g12a.h
>>>>
>>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>>>> index d5cbec5..94a82f73 100644
>>>> --- a/drivers/clk/meson/Kconfig
>>>> +++ b/drivers/clk/meson/Kconfig
>>>> @@ -36,3 +36,13 @@ config COMMON_CLK_AXG
>>>> help
>>>>   Support for the clock controller on AmLogic A113D devices, aka 
>>>> axg.
>>>>   Say Y if you want peripherals and CPU frequency scaling to work.
>>>> +
>>>> +config COMMON_CLK_G12A
>>>> +   bool
>>>> +   depends on COMMON_CLK_AMLOGIC
>>>> +   select RESET_CONTROLLER
>>>> +   select COMMON_CLK_REGMAP_MESON
>>>> +   select MFD_SYSCON
>>>> +   help
>>>> + Support for the clock controller on AmLogic U400 devices, aka 
>>>> g12a.
> 
> I suppose U400 is the designation of the ref design board, not the SoC, right 
> ?
> If this is case, please provide the SoC reference instead.
> 
>>>> + Say Y if you want peripherals and CPU frequency scaling to work.
>>>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>>>> index fa6d1e3..45d107c 100644
>>>> --- a/drivers/clk/meson/Makefile
>>>> +++ b/drivers/clk/meson/Makefile
>>>> @@ -6,4 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o 
>>>> clk-audio-divider.o
>>>>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>>>>  obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o meson-aoclk.o gxbb-aoclk.o 
>>>> gxbb-aoclk-32k.o
>>>>  obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o meson-aoclk.o axg-aoclk.o
>>>> +obj-$(CONFIG_COMMON_CLK_G12A)   += g12a.o
>>>>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
>>>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>>>> new file mode 100644
>>>> index 000..3675697
>>>> --- /dev/null
>>>> +++ b/drivers/clk/meson/g12a.c
>>>> @@ -0,0 +1,992 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +/*
>>>> + * AmLogic Meson-G12A Clock Controller Driver
> 
> I thought you guys stopped writing amlogic with this camel case.
> Please be consistent about it
> 
>>>> + *
>>>> + * Copyright (c) 2016 Baylibre SAS.
>>>> + * Author: Michael Turquette 
>>>> + *
>>>> + * Copyright (c) 2018 Amlogic, inc.
>>>> + * Author: Jian Hu 
>>>> + * Author: Qiufang Dai 
>>>> + */
>>>> +
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +
>>>> +#include "clkc.h"
>>>> +#include "g12a.h"
>>>> +
>>>> +static DEFINE_SPINLOCK(meson_clk_lock);
>>>> +
>>>> +static struct clk_regmap g12a_fixed_pll = {
>>>> +   .data = &(struct meson_clk_pll_data){
>>>> +   .m = {
>>>> +   .reg_off = HHI_FIX_PLL_CNTL0,
>>>> +   .shift   = 0,
>>>> +   .width   = 8,
>>>> +   },
>>>> +   .n = {
>>>> +   .reg_off = HHI_FIX_PLL_CNTL0,
>>>> +   .shift   = 10,
>>

Re: [PATCH 0/3] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

HI Martin

On 07/10/18 06:07, Martin Blumenstingl wrote:
> Hi Linus,
> 
> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij  wrote:
>>
>> On Wed, Jul 4, 2018 at 4:48 PM Yixun Lan  wrote:
>>>
>>> This patch series try to add pinctrl driver support for
>>> the Meson-G12A SoC.
>>>
>>>
>>> Yixun Lan (3):
>>>   documentation: Add compatibles for Amlogic Meson G12A pin controllers
>>>   dt-bindings: pinctrl: meson-g12a: document pin name
>>>   pinctrl: meson-g12a: add pinctrl driver support
>>
>> Overall this looks good to me, could we get some review or ACKs
>> from Beniamino, Martin and/or Carlo as an indication that everything
>> seems all right before I apply the series?
> I do not have any documentation for this hardware (I'm not even sure
> if this is the successor to AXG/"the Audio SoCs" or rather a successor
> of GXL or GXM/"the OTT/STB SoCs" - I assume it's their new OTT/STB
> SoCs since G12A is mentioned here and it seems to have a GPU: [0])
> 
yes, it's more like a new generation of OTT/STB SoCs..

> I will try to have a look in the next few days and see if I can spot
> anything obvious

generally the pinctrl IP hasn't changed, so only pinctrl data need to be
updated (the pin mux IP is same as AXG SoC which already explain in
another thread).

> not sure if Neil or Kevin have access to the documentation, so it'd be
> great if they could give feedback as well
> 
we are preparing documention to baylibre guys..

I think there is not many boards available in the public?

> 
> Regards
> Martin
> 
> 
> [0] 
> http://openlinux.amlogic.com:8000/download/doc/Linux_BSP_Kernel4.9_Buildroot_OpenLinux_Release_Notes_V20180330.pdf
> 
> .
> 

Re: [PATCH 0/3] pinctrl: meson-g12a: add pinctrl driver support

[Yixun Lan]

HI Martin

On 07/10/18 06:07, Martin Blumenstingl wrote:
> Hi Linus,
> 
> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij  wrote:
>>
>> On Wed, Jul 4, 2018 at 4:48 PM Yixun Lan  wrote:
>>>
>>> This patch series try to add pinctrl driver support for
>>> the Meson-G12A SoC.
>>>
>>>
>>> Yixun Lan (3):
>>>   documentation: Add compatibles for Amlogic Meson G12A pin controllers
>>>   dt-bindings: pinctrl: meson-g12a: document pin name
>>>   pinctrl: meson-g12a: add pinctrl driver support
>>
>> Overall this looks good to me, could we get some review or ACKs
>> from Beniamino, Martin and/or Carlo as an indication that everything
>> seems all right before I apply the series?
> I do not have any documentation for this hardware (I'm not even sure
> if this is the successor to AXG/"the Audio SoCs" or rather a successor
> of GXL or GXM/"the OTT/STB SoCs" - I assume it's their new OTT/STB
> SoCs since G12A is mentioned here and it seems to have a GPU: [0])
> 
yes, it's more like a new generation of OTT/STB SoCs..

> I will try to have a look in the next few days and see if I can spot
> anything obvious

generally the pinctrl IP hasn't changed, so only pinctrl data need to be
updated (the pin mux IP is same as AXG SoC which already explain in
another thread).

> not sure if Neil or Kevin have access to the documentation, so it'd be
> great if they could give feedback as well
> 
we are preparing documention to baylibre guys..

I think there is not many boards available in the public?

> 
> Regards
> Martin
> 
> 
> [0] 
> http://openlinux.amlogic.com:8000/download/doc/Linux_BSP_Kernel4.9_Buildroot_OpenLinux_Release_Notes_V20180330.pdf
> 
> .
> 

[PATCH v2 3/3] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.

Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.

To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
can be used in the device tree sources.

Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Kconfig|   9 +
 drivers/clk/meson/Makefile   |   1 +
 drivers/clk/meson/mmc-clkc.c | 419 +++
 3 files changed, 429 insertions(+)
 create mode 100644 drivers/clk/meson/mmc-clkc.c

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f682b4..edc18e65c89b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
 
+config COMMON_CLK_MMC_MESON
+   tristate "Meson MMC Sub Clock Controller Driver"
+   depends on COMMON_CLK_AMLOGIC
+   select MFD_SYSCON
+   select REGMAP
+   help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ Say Y if you want this clock enabled.
+
 config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c40d848..4b3817f80ba1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index ..43b7a376746d
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+#define CLKID_MMC_MUX  0
+#define CLKID_MMC_PHASE_CORE   2
+
+#define SD_EMMC_CLOCK  0
+#define   CLK_DIV_MASK GENMASK(5, 0)
+#define   CLK_SRC_MASK GENMASK(7, 6)
+#define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
+#define   CLK_TX_PHASE_MASK GENMASK(11, 10)
+#define   CLK_RX_PHASE_MASK GENMASK(13, 12)
+#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define   CLK_V2_ALWAYS_ON BIT(24)
+
+#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define   CLK_V3_ALWAYS_ON BIT(28)
+
+#define   CLK_DELAY_STEP_PS 200
+#define   CLK_PHASE_STEP 30
+#define   CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
+
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS   5
+
+struct clk_regmap_phase_data {
+   unsigned long   phase_mask;
+   unsigned long   delay_mask;
+   unsigned intdelay_step_ps;
+};
+
+struct mmc_clkc_data {
+   struct clk_regmap_phase_datatx;
+   struct clk_regmap_phase_datarx;
+};
+
+struct mmc_clkc_info {
+   struct device   *dev;
+   struct regmap   *map;
+   struct mmc_clkc_data*data;
+};
+
+static inline struct clk_regmap_phase_data *
+clk_get_regmap_phase_data(struct clk_regmap *clk)
+{
+   return (struct clk_regmap_phase_data *)clk->data;
+}
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+   .offset = SD_EMMC_CLOCK,
+   .mask = 0x3,
+   .shift = 6,
+   .flags = CLK_DIVIDER_ROUND_CLOSEST,
+};
+
+static struct clk_regmap_div_data mmc_clkc_div_data = {
+   .offset = SD_EMMC_CLOCK,
+   .shift = 0,
+   .width = 6,
+   .flags = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED,
+};
+
+static struct clk_regmap_phase_data mmc_clkc_core_phase = {
+   .phase_mask = CLK_CORE_PHASE_MASK,
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_MASK,
+   .delay_mask = CLK_V2_TX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+   {
+   .phase_mask = CLK_RX_PHASE_MASK,
+   .delay_mask = CLK_V2_RX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_

[PATCH v2 0/3] clk: meson: add a sub EMMC clock controller support

[Yixun Lan]

This driver will add a MMC clock controller driver support.
The original idea about adding a clock controller is during the
discussion in the NAND driver mainline effort[1].

I've tested this in the S400 board (AXG platform) by using NAND driver.

Changes since v1 [2]:
 - implement phase clock
 - update compatible name
 - adjust file name
 - divider probe() into small functions, and re-use them

[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com

Yixun Lan (3):
  clk: meson: add DT documentation for emmc clock controller
  clk: meson: add sub MMC clock dt-bindings IDs
  clk: meson: add sub MMC clock controller driver

 .../bindings/clock/amlogic,mmc-clkc.txt   |  31 ++
 drivers/clk/meson/Kconfig |   9 +
 drivers/clk/meson/Makefile|   1 +
 drivers/clk/meson/mmc-clkc.c  | 419 ++
 .../clock/amlogic,meson-mmc-clkc.h|  16 +
 5 files changed, 476 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 drivers/clk/meson/mmc-clkc.c
 create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h

-- 
2.18.0

[PATCH v2 2/3] clk: meson: add sub MMC clock dt-bindings IDs

[Yixun Lan]

Add two clock bindings IDs which provided by the MMC clock controller,
These two clocks will be used by MMC or NAND driver.

Signed-off-by: Yixun Lan 
---
 .../dt-bindings/clock/amlogic,meson-mmc-clkc.h   | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h

diff --git a/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h 
b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
new file mode 100644
index ..2ae988ebc3ae
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan 
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV  1
+#define CLKID_MMC_PHASE_TX 3
+#define CLKID_MMC_PHASE_RX 4
+
+#endif
-- 
2.18.0

[PATCH v2 3/3] clk: meson: add sub MMC clock controller driver

[Yixun Lan]

The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.

Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.

To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
can be used in the device tree sources.

Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Kconfig|   9 +
 drivers/clk/meson/Makefile   |   1 +
 drivers/clk/meson/mmc-clkc.c | 419 +++
 3 files changed, 429 insertions(+)
 create mode 100644 drivers/clk/meson/mmc-clkc.c

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f682b4..edc18e65c89b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
 
+config COMMON_CLK_MMC_MESON
+   tristate "Meson MMC Sub Clock Controller Driver"
+   depends on COMMON_CLK_AMLOGIC
+   select MFD_SYSCON
+   select REGMAP
+   help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ Say Y if you want this clock enabled.
+
 config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c40d848..4b3817f80ba1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index ..43b7a376746d
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+#define CLKID_MMC_MUX  0
+#define CLKID_MMC_PHASE_CORE   2
+
+#define SD_EMMC_CLOCK  0
+#define   CLK_DIV_MASK GENMASK(5, 0)
+#define   CLK_SRC_MASK GENMASK(7, 6)
+#define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
+#define   CLK_TX_PHASE_MASK GENMASK(11, 10)
+#define   CLK_RX_PHASE_MASK GENMASK(13, 12)
+#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define   CLK_V2_ALWAYS_ON BIT(24)
+
+#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define   CLK_V3_ALWAYS_ON BIT(28)
+
+#define   CLK_DELAY_STEP_PS 200
+#define   CLK_PHASE_STEP 30
+#define   CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
+
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS   5
+
+struct clk_regmap_phase_data {
+   unsigned long   phase_mask;
+   unsigned long   delay_mask;
+   unsigned intdelay_step_ps;
+};
+
+struct mmc_clkc_data {
+   struct clk_regmap_phase_datatx;
+   struct clk_regmap_phase_datarx;
+};
+
+struct mmc_clkc_info {
+   struct device   *dev;
+   struct regmap   *map;
+   struct mmc_clkc_data*data;
+};
+
+static inline struct clk_regmap_phase_data *
+clk_get_regmap_phase_data(struct clk_regmap *clk)
+{
+   return (struct clk_regmap_phase_data *)clk->data;
+}
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+   .offset = SD_EMMC_CLOCK,
+   .mask = 0x3,
+   .shift = 6,
+   .flags = CLK_DIVIDER_ROUND_CLOSEST,
+};
+
+static struct clk_regmap_div_data mmc_clkc_div_data = {
+   .offset = SD_EMMC_CLOCK,
+   .shift = 0,
+   .width = 6,
+   .flags = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED,
+};
+
+static struct clk_regmap_phase_data mmc_clkc_core_phase = {
+   .phase_mask = CLK_CORE_PHASE_MASK,
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_MASK,
+   .delay_mask = CLK_V2_TX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+   {
+   .phase_mask = CLK_RX_PHASE_MASK,
+   .delay_mask = CLK_V2_RX_DELAY_MASK,
+   .delay_step_ps  = CLK_DELAY_STEP_PS,
+   },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+   {
+   .phase_mask = CLK_TX_PHASE_