[RESEND PATCH] usb: dwc2: Add reset control to dwc2

[dinguyen]

From: Dinh Nguyen 

Allow for platforms that have a reset controller driver in place to bring
the USB IP out of reset.

Signed-off-by: Dinh Nguyen 
Acked-by: John Youn 
Tested-by: Stefan Wahren 
Acked-by: Felipe Balbi 
---
v7: Use devm_reset_control_get_optional()
v6: fix 80 line checkpatch warning in dev_err print
v5: updated error conditions for not finding the reset property
v4: use dev_dbg() if not a -EPROBE_DEFER
v3: fix compile error
v2: move to lowlevel_hw_init()
---
 drivers/usb/dwc2/core.h |1 +
 drivers/usb/dwc2/platform.c |   22 ++
 2 files changed, 23 insertions(+)

diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 3c58d63..f748132 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -837,6 +837,7 @@ struct dwc2_hsotg {
void *priv;
int irq;
struct clk *clk;
+   struct reset_control *reset;
 
unsigned int queuing_high_bandwidth:1;
unsigned int srp_success:1;
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 88629be..d34f169 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -337,6 +338,24 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 {
int i, ret;
 
+   hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
+   if (IS_ERR(hsotg->reset)) {
+   ret = PTR_ERR(hsotg->reset);
+   switch (ret) {
+   case -ENOENT:
+   case -ENOTSUPP:
+   hsotg->reset = NULL;
+   break;
+   default:
+   dev_err(hsotg->dev, "error getting reset control %d\n",
+   ret);
+   return ret;
+   }
+   }
+
+   if (hsotg->reset)
+   reset_control_deassert(hsotg->reset);
+
/* Set default UTMI width */
hsotg->phyif = GUSBCFG_PHYIF16;
 
@@ -434,6 +453,9 @@ static int dwc2_driver_remove(struct platform_device *dev)
if (hsotg->ll_hw_enabled)
dwc2_lowlevel_hw_disable(hsotg);
 
+   if (hsotg->reset)
+   reset_control_assert(hsotg->reset);
+
return 0;
 }
 
-- 
1.7.9.5

[PATCHv2] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[dinguyen]

From: Dinh Nguyen 

There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.

Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.

Signed-off-by: Dinh Nguyen 
---
v2: fix compile warnings
---
 drivers/clk/socfpga/clk-gate-a10.c   | 6 +-
 drivers/clk/socfpga/clk-periph-a10.c | 7 +++
 2 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
index 1cebf25..c2d5727 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -115,7 +115,6 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
-   int i = 0;
 
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk))
@@ -167,12 +166,9 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
 
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
-   init.num_parents = i;
socfpga_clk->hw.hw.init = &init;
 
clk = clk_register(NULL, &socfpga_clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-periph-a10.c 
b/drivers/clk/socfpga/clk-periph-a10.c
index 1f397cb..70993f1 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -74,7 +74,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
struct clk *clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
-   const char *parent_name;
+   const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
@@ -109,9 +109,8 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
init.ops = ops;
init.flags = 0;
 
-   parent_name = of_clk_get_parent_name(node, 0);
-   init.num_parents = 1;
-   init.parent_names = &parent_name;
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
+   init.parent_names = parent_name;
 
periph_clk->hw.hw.init = &init;
 
-- 
2.6.2

[PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[dinguyen]

From: Dinh Nguyen 

There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.

Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/clk-gate-a10.c   | 5 +
 drivers/clk/socfpga/clk-periph-a10.c | 5 ++---
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
index 1cebf25..0b6ee7b 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -167,12 +167,9 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
 
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
-   init.num_parents = i;
socfpga_clk->hw.hw.init = &init;
 
clk = clk_register(NULL, &socfpga_clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-periph-a10.c 
b/drivers/clk/socfpga/clk-periph-a10.c
index 1f397cb..2b7e215 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -74,7 +74,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
struct clk *clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
-   const char *parent_name;
+   const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
@@ -109,8 +109,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
init.ops = ops;
init.flags = 0;
 
-   parent_name = of_clk_get_parent_name(node, 0);
-   init.num_parents = 1;
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = &parent_name;
 
periph_clk->hw.hw.init = &init;
-- 
2.6.2

[PATCH] Doc: Micrel-ksz90x1.txt: Update the Micrel phy documentation for ksz9031

[dinguyen]

From: Dinh Nguyen 

Update the Micrel phy documentation for the KSZ9031 PHY to represent how
the actual values are calculated from the code.

Signed-off-by: Dinh Nguyen 
---
 .../devicetree/bindings/net/micrel-ksz90x1.txt | 73 ++
 1 file changed, 73 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt 
b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
index f9c32ad..9535b2b 100644
--- a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
+++ b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
@@ -36,6 +36,71 @@ KSZ9031:
   value is 0, and the maximum is property-dependent. The increment
   step is 60ps.
 
+  The KSZ9031 hardware supports a range of skew values from negative to
+  positive, where the specific range is property dependent. All values
+  specified in the devicetree are offset by the minimum value so they
+  can be represented as positive integers in the devicetree since it's
+  difficult to represent a negative number in the devictree.
+
+  The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.
+
+  Pad Skew Value   Delay (ps)  Devicetree Value
+  --
+  0_   -900ps  0
+  0_0001   -840ps  60
+  0_0010   -780ps  120
+  0_0011   -720ps  180
+  0_0100   -660ps  240
+  0_0101   -600ps  300
+  0_0110   -540ps  360
+  0_0111   -480ps  420
+  0_1000   -420ps  480
+  0_1001   -360ps  540
+  0_1010   -300ps  600
+  0_1011   -240ps  660
+  0_1100   -180ps  720
+  0_1101   -120ps  780
+  0_1110   -60ps   840
+  0_   0ps 900
+  1_   60ps960
+  1_0001   120ps   1020
+  1_0010   180ps   1080
+  1_0011   240ps   1140
+  1_0100   300ps   1200
+  1_0101   360ps   1260
+  1_0110   420ps   1320
+  1_0111   480ps   1380
+  1_1000   540ps   1440
+  1_1001   600ps   1500
+  1_1010   660ps   1560
+  1_1011   720ps   1620
+  1_1100   780ps   1680
+  1_1101   840ps   1740
+  1_1110   900ps   1800
+  1_   960ps   1860
+
+  The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps
+  data pads, and the rxdv-skew-ps, txen-skew-ps control pads.
+
+  Pad Skew Value   Delay (ps)  Devicetree Value
+  --
+   -420ps  0
+  0001 -360ps  60
+  0010 -300ps  120
+  0011 -240ps  180
+  0100 -180ps  240
+  0101 -120ps  300
+  0110 -60ps   360
+  0111 0ps 420
+  1000 60ps480
+  1001 120ps   540
+  1010 180ps   600
+  1011 240ps   660
+  1100 300ps   720
+  1101 360ps   780
+  1110 420ps   840
+   480ps   900
+
   Optional properties:
 
 Maximum value of 1860:
@@ -72,3 +137,11 @@ Examples:
phy = <&phy0>;
phy-mode = "rgmii-id";
};
+
+References
+
+  Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
+  http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
+
+  Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
+  http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
-- 
2.6.2

[PATCH] arm: socfpga_defconfig: enable USB dual-role and cleanup

[dinguyen]

From: Dinh Nguyen 

Enable USB OTG dual-role and a bit of clean up by using make savedefconfig.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/configs/socfpga_defconfig | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/configs/socfpga_defconfig 
b/arch/arm/configs/socfpga_defconfig
index 8128b93e..f7f4e2e 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -36,7 +36,6 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
-CONFIG_IPV6=y
 CONFIG_NETWORK_PHY_TIMESTAMPING=y
 CONFIG_VLAN_8021Q=y
 CONFIG_VLAN_8021Q_GVRP=y
@@ -57,7 +56,6 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_STMMAC_ETH=y
-CONFIG_DWMAC_SOCFPGA=y
 CONFIG_MICREL_PHY=y
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_SERPORT is not set
@@ -83,7 +81,8 @@ CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_USB_DWC2_HOST=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_FPGA=y
@@ -92,7 +91,6 @@ CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT3_FS=y
-CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_NTFS_FS=y
 CONFIG_NTFS_RW=y
-- 
2.6.2

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[PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

[dinguyen]

From: Thor Thayer 

Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device  model. The SDRAM
controller is using the Memory Controller model.

Each type of ECC is individually configurable.

The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation can take almost 2 seconds on boot and some
customers need a faster boot time.
2) the SDRAM has an ECC initialization dependency on the preloader
which is outside the kernel. It is desirable to be able to turn the
SDRAM on & off separately.

Signed-off-by: Thor Thayer 
Signed-off-by: Dinh Nguyen 
---
v7: s/of_get_named_gen_pool/of_gen_pool_get
Remove #ifdef for EDAC_DEBUG
Use -ENODEV instead of EPROBE_DEFER

v6: Convert to nested EDAC in device tree. Force L2 cache
on for L2Cache ECC & remove L2 cache syscon for checking
enable bit. Update year in header.

v5: No Change

v4: Change mask defines to use BIT().
Fix comment style to agree with kernel coding style.
Better printk description for read != write in trigger.
Remove SysFS debugging message.
Better dci->mod_name
Move gen_pool pointer assignment to end of function.
Invert logic to reduce indent in ocram depenency check.
Change from dev_err() to edac_printk()
Replace magic numbers with defines & comments.
Improve error injection test.
Change Makefile intermediary name to altr (from alt)

v3: Move OCRAM and L2 cache EDAC functions into altera_edac.c
instead of separate files.

v2: Fix L2 dependency comments.
---
 drivers/edac/Kconfig   |  16 ++
 drivers/edac/Makefile  |   5 +-
 drivers/edac/altera_edac.c | 488 -
 3 files changed, 507 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index ef25000..b80b4ad 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -376,6 +376,22 @@ config EDAC_ALTERA_MC
  preloader must initialize the SDRAM before loading
  the kernel.
 
+config EDAC_ALTERA_L2C
+   bool "Altera L2 Cache EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
+   select CACHE_L2X0
+   help
+ Support for error detection and correction on the
+ Altera L2 cache Memory for Altera SoCs. This option
+  requires L2 cache so it will force that selection.
+
+config EDAC_ALTERA_OCRAM
+   bool "Altera On-Chip RAM EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA && SRAM && GENERIC_ALLOCATOR
+   help
+ Support for error detection and correction on the
+ Altera On-Chip RAM Memory for Altera SoCs.
+
 config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index dbf53e0..8f1c6fc 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -67,6 +67,9 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
 
-obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
+altr_edac-y:= altera_edac.o
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altr_edac.o
+obj-$(CONFIG_EDAC_ALTERA_L2C)  += altr_edac.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM)+= altr_edac.o
 obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o
 obj-$(CONFIG_EDAC_XGENE)   += xgene_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 9296409..154ac8c 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -17,8 +17,10 @@
  * Adapted from the highbank_mc_edac driver.
  */
 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -34,6 +36,7 @@
 
 #define EDAC_MOD_STR   "altera_edac"
 #define EDAC_VERSION   "1"
+#define EDAC_DEVICE"ALTR_MEM"
 
 static const struct altr_sdram_prv_data c5_data = {
.ecc_ctrl_offset= CV_CTLCFG_OFST,
@@ -75,6 +78,33 @@ static const struct altr_sdram_prv_data a10_data = {
.ue_set_mask= A10_DIAGINT_TDERRA_MASK,
 };
 
+/** EDAC Device Defines **/
+
+/* OCRAM ECC Management Group Defines */
+#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04
+#define ALTR_OCR_ECC_EN_MASKBIT(0)
+#define ALTR_OCR_ECC_INJS_MASK  BIT(1)
+#define ALTR_OCR_ECC_INJD_MASK  BIT(2)
+#define ALTR_OCR_ECC_SERR_MASK  BIT(3)
+#define ALTR_OCR_ECC_DERR_MASK  BIT(4)
+
+/* L2 ECC Management Group Defines */
+#define ALTR_MAN_GRP_L2_ECC_OFFSET  0x00
+#define ALTR_L2_ECC_EN_MASK BIT(0)
+#define ALTR_L2_ECC_INJS_MASK   BIT(1)
+#define ALTR_L2_ECC_INJD_MASK   BIT(2)
+
+#define ALTR_UE_TRIGGER_CHAR'U'   /* Trigger for UE */
+#define ALTR_TRIGGER_READ_WRD_CNT   32/* Line size x 4 */
+#define ALTR_TRIG_OCRAM_BYTE_SIZE   

[PATCH] EDAC, altera: SoCFPGA EDAC should not look for ECC_CORR_EN

[dinguyen]

From: Dinh Nguyen 

The bootloader may or may not enable the ECC_CORR_EN bit. By not enabling
ECC_CORR_EN, when error happens, it is the user's responsibility to perform
a full SDRAM scrub.

Remove the check for ECC_CORR_EN.

Signed-off-by: Dinh Nguyen 
---
 drivers/edac/altera_edac.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 7b64dc7..7a52585 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -30,8 +30,7 @@
 #define CV_CTLCFG_GEN_SB_ERR   0x2000
 #define CV_CTLCFG_GEN_DB_ERR   0x4000
 
-#define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN | \
-  CV_CTLCFG_ECC_CORR_EN)
+#define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN)
 
 /* SDRAM Controller Address Width Register */
 #define CV_DRAMADDRW_OFST  0x2C
-- 
2.4.5

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[PATCHv4] arm64: dts: Add base stratix 10 dtsi

[dinguyen]

From: Dinh Nguyen 

Add the base DTS for Altera's SoCFPGA Stratix 10 platform.

Signed-off-by: Dinh Nguyen 
---
v4: Add a non-zero ranges property for /soc node
v3: change #address-cells and #size-cells to <2>
change the GIC address to 0xfffc1000
update the GIC virtual CPU reg length to 0x2000
v2: use interrupt-affinity for pmu node
---
 arch/arm64/Kconfig.platforms   |   5 +
 arch/arm64/boot/dts/Makefile   |   1 +
 arch/arm64/boot/dts/altera/Makefile|   5 +
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  | 358 +
 .../boot/dts/altera/socfpga_stratix10_socdk.dts|  39 +++
 arch/arm64/configs/defconfig   |   1 +
 6 files changed, 409 insertions(+)
 create mode 100644 arch/arm64/boot/dts/altera/Makefile
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 23800a1..36303c8 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -66,6 +66,11 @@ config ARCH_SEATTLE
help
  This enables support for AMD Seattle SOC Family
 
+config ARCH_STRATIX10
+   bool "Altera's Stratix 10 SoCFPGA Family"
+   help
+ This enables support for Altera's Stratix 10 SoCFPGA Family.
+
 config ARCH_TEGRA
bool "NVIDIA Tegra SoC Family"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index d9f8833..f585606 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dts-dirs += altera
 dts-dirs += amd
 dts-dirs += apm
 dts-dirs += arm
diff --git a/arch/arm64/boot/dts/altera/Makefile 
b/arch/arm64/boot/dts/altera/Makefile
new file mode 100644
index 000..d7a6416
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
+
+always := $(dtb-y)
+subdir-y   := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
new file mode 100644
index 000..445aa67
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -0,0 +1,358 @@
+/*
+ * Copyright Altera Corporation (C) 2015. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+/dts-v1/;
+
+/ {
+   compatible = "altr,socfpga-stratix10";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x0>;
+   };
+
+   cpu1: cpu@1 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x1>;
+   };
+
+   cpu2: cpu@2 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x2>;
+   };
+
+   cpu3: cpu@3 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x3>;
+   };
+   };
+
+   pmu {
+   compatible = "arm,armv8-pmuv3";
+   interrupts = <0 120 8>,
+<0 121 8>,
+<0 122 8>,
+<0 123 8>;
+   interrupt-affinity = <&cpu0>,
+<&cpu1>,
+<&cpu2>,
+<&cpu3>;
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   intc: intc@fffc1000 {
+   compatible = "arm,gic-400", "arm,cortex-a15-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0x0 0

[PATCv3] arm64: dts: Add base stratix 10 dtsi

[dinguyen]

From: Dinh Nguyen 

Add the base DTS for Altera's SoCFPGA Stratix 10 platform.

Signed-off-by: Dinh Nguyen 
---
v3: change #address-cells and #size-cells to <2>
change the GIC address to 0xfffc1000
update the GIC virtual CPU reg length to 0x2000
v2: use interrupt-affinity for pmu node
---
 arch/arm64/Kconfig |   5 +
 arch/arm64/boot/dts/Makefile   |   1 +
 arch/arm64/boot/dts/altera/Makefile|   5 +
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  | 358 +
 .../boot/dts/altera/socfpga_stratix10_socdk.dts|  38 +++
 arch/arm64/configs/defconfig   |   1 +
 6 files changed, 408 insertions(+)
 create mode 100644 arch/arm64/boot/dts/altera/Makefile
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 318175f..0f8ab2b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -207,6 +207,11 @@ config ARCH_SEATTLE
help
  This enables support for AMD Seattle SOC Family
 
+config ARCH_STRATIX10
+   bool "Altera's Stratix 10 SoCFPGA Family"
+   help
+ This enables support for Altera's Stratix 10 SoCFPGA Family
+
 config ARCH_TEGRA
bool "NVIDIA Tegra SoC Family"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 38913be..7fb421a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dts-dirs += altera
 dts-dirs += amd
 dts-dirs += apm
 dts-dirs += arm
diff --git a/arch/arm64/boot/dts/altera/Makefile 
b/arch/arm64/boot/dts/altera/Makefile
new file mode 100644
index 000..d7a6416
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
+
+always := $(dtb-y)
+subdir-y   := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
new file mode 100644
index 000..d5f51a5
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -0,0 +1,358 @@
+/*
+ * Copyright Altera Corporation (C) 2015. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+/dts-v1/;
+
+/ {
+   compatible = "altr,socfpga-stratix10";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x0>;
+   };
+
+   cpu1: cpu@1 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x1>;
+   };
+
+   cpu2: cpu@2 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x2>;
+   };
+
+   cpu3: cpu@3 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x3>;
+   };
+   };
+
+   pmu {
+   compatible = "arm,armv8-pmuv3";
+   interrupts = <0 120 8>,
+<0 121 8>,
+<0 122 8>,
+<0 123 8>;
+   interrupt-affinity = <&cpu0>,
+<&cpu1>,
+<&cpu2>,
+<&cpu3>;
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   intc: intc@fffc1000 {
+   compatible = "arm,gic-400", "arm,cortex-a15-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0x0 0xfffc1000 0x1000>,
+ <0x0 0xfffc2000 0x2000>,
+ 

[PATCHv2] arm64: dts: Add base stratix 10 dtsi

[dinguyen]

From: Dinh Nguyen 

Add the base DTS for Altera's SoCFPGA Stratix 10 platform.

Signed-off-by: Dinh Nguyen 
---
v2: use interrupt-affinity for pmu node
---
 arch/arm64/Kconfig |   5 +
 arch/arm64/boot/dts/Makefile   |   1 +
 arch/arm64/boot/dts/altera/Makefile|   5 +
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  | 358 +
 .../boot/dts/altera/socfpga_stratix10_socdk.dts|  38 +++
 arch/arm64/configs/defconfig   |   1 +
 6 files changed, 408 insertions(+)
 create mode 100644 arch/arm64/boot/dts/altera/Makefile
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 318175f..0f8ab2b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -207,6 +207,11 @@ config ARCH_SEATTLE
help
  This enables support for AMD Seattle SOC Family
 
+config ARCH_STRATIX10
+   bool "Altera's Stratix 10 SoCFPGA Family"
+   help
+ This enables support for Altera's Stratix 10 SoCFPGA Family
+
 config ARCH_TEGRA
bool "NVIDIA Tegra SoC Family"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 38913be..7fb421a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dts-dirs += altera
 dts-dirs += amd
 dts-dirs += apm
 dts-dirs += arm
diff --git a/arch/arm64/boot/dts/altera/Makefile 
b/arch/arm64/boot/dts/altera/Makefile
new file mode 100644
index 000..d7a6416
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
+
+always := $(dtb-y)
+subdir-y   := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
new file mode 100644
index 000..d67de22
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -0,0 +1,358 @@
+/*
+ * Copyright Altera Corporation (C) 2015. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+/dts-v1/;
+
+/ {
+   compatible = "altr,socfpga-stratix10";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x0>;
+   };
+
+   cpu1: cpu@1 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x1>;
+   };
+
+   cpu2: cpu@2 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x2>;
+   };
+
+   cpu3: cpu@3 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x3>;
+   };
+   };
+
+   pmu {
+   compatible = "arm,armv8-pmuv3";
+   interrupts = <0 120 8>,
+<0 121 8>,
+<0 122 8>,
+<0 123 8>;
+   interrupt-affinity = <&cpu0>,
+<&cpu1>,
+<&cpu2>,
+<&cpu3>;
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   intc: intc@8000 {
+   compatible = "arm,gic-400", "arm,cortex-a15-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0x0 0x9000 0x1000>,
+ <0x0 0xa000 0x2000>,
+ <0x0 0xc000 0x1000>,
+ <0x0 0xd000 0x1000>;
+   };
+
+   soc {
+   #address-cells = <1>;
+

[PATCH] arm64: dts: Add base stratix 10 dtsi

[dinguyen]

From: Dinh Nguyen 

Add the base DTS for Altera's SoCFPGA Stratix 10 platform.

Signed-off-by: Dinh Nguyen 
---
 arch/arm64/Kconfig |   5 +
 arch/arm64/boot/dts/Makefile   |   1 +
 arch/arm64/boot/dts/altera/Makefile|   5 +
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  | 354 +
 .../boot/dts/altera/socfpga_stratix10_socdk.dts|  38 +++
 arch/arm64/configs/defconfig   |   1 +
 6 files changed, 404 insertions(+)
 create mode 100644 arch/arm64/boot/dts/altera/Makefile
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 318175f..0f8ab2b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -207,6 +207,11 @@ config ARCH_SEATTLE
help
  This enables support for AMD Seattle SOC Family
 
+config ARCH_STRATIX10
+   bool "Altera's Stratix 10 SoCFPGA Family"
+   help
+ This enables support for Altera's Stratix 10 SoCFPGA Family
+
 config ARCH_TEGRA
bool "NVIDIA Tegra SoC Family"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 38913be..7fb421a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dts-dirs += altera
 dts-dirs += amd
 dts-dirs += apm
 dts-dirs += arm
diff --git a/arch/arm64/boot/dts/altera/Makefile 
b/arch/arm64/boot/dts/altera/Makefile
new file mode 100644
index 000..d7a6416
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
+
+always := $(dtb-y)
+subdir-y   := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
new file mode 100644
index 000..34f6dc3
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -0,0 +1,354 @@
+/*
+ * Copyright Altera Corporation (C) 2015. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+/dts-v1/;
+
+/ {
+   compatible = "altr,socfpga-stratix10";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x3>;
+   };
+   };
+
+   pmu {
+   compatible = "arm,armv8-pmuv3";
+   interrupts = <0 120 8>,
+<0 121 8>,
+<0 122 8>,
+<0 123 8>;
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   intc: intc@8000 {
+   compatible = "arm,gic-400", "arm,cortex-a15-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0x0 0x9000 0x1000>,
+ <0x0 0xa000 0x2000>,
+ <0x0 0xc000 0x1000>,
+ <0x0 0xd000 0x1000>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <&intc>;
+   ranges;
+
+   clkmgr@ffd1000 {
+   compatible = "a

[PATCHv2 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

[dinguyen]

From: Dinh Nguyen 

In order for the Arria10 to be able to re-use the reset driver for SoCFPGA
Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the
device tree entry. The 'altr,modrst-offset' property is the first register
into the reset manager that is used for bringing peripherals out of reset.

The driver assumes a modrst-offset of 0x10 in order to support legacy
Cyclone5/Arria5 hardware.

Signed-off-by: Dinh Nguyen 
---
v2: assume a modrst-offset of 0x10 if the property is not specified in order
to support legacy boards that do not have the property.
---
 drivers/reset/reset-socfpga.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 0a8def3..1a6c5d6 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -24,11 +24,11 @@
 #include 
 
 #define NR_BANKS   4
-#define OFFSET_MODRST  0x10
 
 struct socfpga_reset_data {
spinlock_t  lock;
void __iomem*membase;
+   u32 modrst_offset;
struct reset_controller_dev rcdev;
 };
 
@@ -45,8 +45,8 @@ static int socfpga_reset_assert(struct reset_controller_dev 
*rcdev,
 
spin_lock_irqsave(&data->lock, flags);
 
-   reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
-   writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
+   reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
+   writel(reg | BIT(offset), data->membase + data->modrst_offset +
 (bank * NR_BANKS));
spin_unlock_irqrestore(&data->lock, flags);
 
@@ -67,8 +67,8 @@ static int socfpga_reset_deassert(struct reset_controller_dev 
*rcdev,
 
spin_lock_irqsave(&data->lock, flags);
 
-   reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
-   writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
+   reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
+   writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
  (bank * NR_BANKS));
 
spin_unlock_irqrestore(&data->lock, flags);
@@ -85,7 +85,7 @@ static int socfpga_reset_status(struct reset_controller_dev 
*rcdev,
int offset = id % BITS_PER_LONG;
u32 reg;
 
-   reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
+   reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
 
return !(reg & BIT(offset));
 }
@@ -100,6 +100,8 @@ static int socfpga_reset_probe(struct platform_device *pdev)
 {
struct socfpga_reset_data *data;
struct resource *res;
+   struct device *dev = &pdev->dev;
+   struct device_node *np = dev->of_node;
 
/*
 * The binding was mainlined without the required property.
@@ -120,6 +122,11 @@ static int socfpga_reset_probe(struct platform_device 
*pdev)
if (IS_ERR(data->membase))
return PTR_ERR(data->membase);
 
+   if (of_property_read_u32(np, "altr,modrst-offset", 
&data->modrst_offset)) {
+   dev_warn(dev, "missing altr,modrst-offset property, assuming 
0x10!\n");
+   data->modrst_offset = 0x10;
+   }
+
spin_lock_init(&data->lock);
 
data->rcdev.owner = THIS_MODULE;
-- 
2.4.5

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[PATCHv2 0/4] reset: socfpga: Add reset driver support for Arria10 platform

[dinguyen]

From: Dinh Nguyen 

v2: For the reset driver, assume a modrst-offset of 0x10 in order to support
legacy boards that do have the property..

v1:
This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The
reset manager on the Arria10 is very similar to the one on Cyclone5/Arria5,
thus I think it's best to try to re-use the same reset driver.

The biggest difference between the reset manager on Arria10 and Cyclone is
the addition of security features. Since the driver does not support these
security features, it winds down to just a driver that will release IPs from
reset.

The other difference between Arria10 and Cyclone5 are register offsets, and
register bits for different IPs. For the register offset, the main register
offset is the very first register that is needed by the driver for releasing
IPs from reset. To handle this difference, I've introduced a new DTS property,
"altr,modrst-offset", that will represent this register.

The register bits for all the resets are in a new file:

include/dt-bindings/reset/altr,rst-mgr-a10.h

Thanks,

Dinh Nguyen (4):
  dt-bindings: Add reset manager offsets for Arria10
  ARM: socfpga: dts: add "altr,modrst-offset" property
  reset: socfpga: Update reset-socfpga to read the altr,modrst-offset
property
  ARM: socfpga: dts: Add resets for EMACs on Arria10

 .../devicetree/bindings/reset/socfpga-reset.txt|   2 +
 arch/arm/boot/dts/socfpga.dtsi |   1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi |   6 ++
 drivers/reset/reset-socfpga.c  |  19 ++--
 include/dt-bindings/reset/altr,rst-mgr-a10.h   | 110 +
 5 files changed, 132 insertions(+), 6 deletions(-)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

-- 
2.4.5

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[PATCHv2 1/4] dt-bindings: Add reset manager offsets for Arria10

[dinguyen]

From: Dinh Nguyen 

The reset manager for is pretty similar to the one for SoCFPGA
cyclone5/arria5 except for a few offsets. This patch adds those offsets.

Signed-off-by: Dinh Nguyen 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 +++
 1 file changed, 110 insertions(+)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..acb0bbf
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
2.4.5

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[PATCHv2 2/4] ARM: socfpga: dts: add "altr,modrst-offset" property

[dinguyen]

From: Dinh Nguyen 

The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.

Signed-off-by: Dinh Nguyen 
---
 Documentation/devicetree/bindings/reset/socfpga-reset.txt | 2 ++
 arch/arm/boot/dts/socfpga.dtsi| 1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi| 1 +
 3 files changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt 
b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
index 32c1c8b..98c9f56 100644
--- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt
+++ b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
@@ -3,6 +3,7 @@ Altera SOCFPGA Reset Manager
 Required properties:
 - compatible : "altr,rst-mgr"
 - reg : Should contain 1 register ranges(address and length)
+- altr,modrst-offset : Should contain the offset of the first modrst register.
 - #reset-cells: 1
 
 Example:
@@ -10,4 +11,5 @@ Example:
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
+   altr,modrst-offset = <0x10>;
};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 86e0fb6..0bda96a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -783,6 +783,7 @@
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
+   altr,modrst-offset = <0x10>;
};
 
usbphy0: usbphy@0 {
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a252905..22e7d82 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -593,6 +593,7 @@
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x100>;
+   altr,modrst-offset = <0x20>;
};
 
scu: snoop-control-unit@c000 {
-- 
2.4.5

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[PATCHv2 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

[dinguyen]

From: Dinh Nguyen 

Add the reset property for the EMAC controllers on Arria10.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 22e7d82..2340fcb 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -16,6 +16,7 @@
 
 #include "skeleton.dtsi"
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -414,6 +415,8 @@
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
+   resets = <&rst EMAC0_RESET>;
+   reset-names = "stmmaceth";
status = "disabled";
};
 
@@ -431,6 +434,8 @@
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
+   resets = <&rst EMAC1_RESET>;
+   reset-names = "stmmaceth";
status = "disabled";
};
 
-- 
2.4.5

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[PATCH 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

[dinguyen]

From: Dinh Nguyen 

In order for the Arria10 to be able to re-use the reset driver for SoCFPGA
Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the
device tree entry. The 'altr,modrst-offset' property is the first register
into the reset manager that is used for bringing peripherals out of reset.

Signed-off-by: Dinh Nguyen 
---
 drivers/reset/reset-socfpga.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 0a8def3..9074d41 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -24,11 +24,11 @@
 #include 
 
 #define NR_BANKS   4
-#define OFFSET_MODRST  0x10
 
 struct socfpga_reset_data {
spinlock_t  lock;
void __iomem*membase;
+   u32 modrst_offset;
struct reset_controller_dev rcdev;
 };
 
@@ -45,8 +45,8 @@ static int socfpga_reset_assert(struct reset_controller_dev 
*rcdev,
 
spin_lock_irqsave(&data->lock, flags);
 
-   reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
-   writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
+   reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
+   writel(reg | BIT(offset), data->membase + data->modrst_offset +
 (bank * NR_BANKS));
spin_unlock_irqrestore(&data->lock, flags);
 
@@ -67,8 +67,8 @@ static int socfpga_reset_deassert(struct reset_controller_dev 
*rcdev,
 
spin_lock_irqsave(&data->lock, flags);
 
-   reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
-   writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
+   reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
+   writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
  (bank * NR_BANKS));
 
spin_unlock_irqrestore(&data->lock, flags);
@@ -85,7 +85,7 @@ static int socfpga_reset_status(struct reset_controller_dev 
*rcdev,
int offset = id % BITS_PER_LONG;
u32 reg;
 
-   reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
+   reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
 
return !(reg & BIT(offset));
 }
@@ -100,6 +100,8 @@ static int socfpga_reset_probe(struct platform_device *pdev)
 {
struct socfpga_reset_data *data;
struct resource *res;
+   struct device *dev = &pdev->dev;
+   struct device_node *np = dev->of_node;
 
/*
 * The binding was mainlined without the required property.
@@ -120,6 +122,11 @@ static int socfpga_reset_probe(struct platform_device 
*pdev)
if (IS_ERR(data->membase))
return PTR_ERR(data->membase);
 
+   if (of_property_read_u32(np, "altr,modrst-offset", 
&data->modrst_offset)) {
+   dev_err(dev, "no altr,modrst-offset specified in device 
tree\n");
+   return -ENODEV;
+   }
+
spin_lock_init(&data->lock);
 
data->rcdev.owner = THIS_MODULE;
-- 
2.4.5

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 2/4] ARM: socfpga: dts: add "altr,modrst-offset" property

[dinguyen]

From: Dinh Nguyen 

The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.

Signed-off-by: Dinh Nguyen 
---
 Documentation/devicetree/bindings/reset/socfpga-reset.txt | 2 ++
 arch/arm/boot/dts/socfpga.dtsi| 1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi| 1 +
 3 files changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt 
b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
index 32c1c8b..98c9f56 100644
--- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt
+++ b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
@@ -3,6 +3,7 @@ Altera SOCFPGA Reset Manager
 Required properties:
 - compatible : "altr,rst-mgr"
 - reg : Should contain 1 register ranges(address and length)
+- altr,modrst-offset : Should contain the offset of the first modrst register.
 - #reset-cells: 1
 
 Example:
@@ -10,4 +11,5 @@ Example:
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
+   altr,modrst-offset = <0x10>;
};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 86e0fb6..0bda96a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -783,6 +783,7 @@
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
+   altr,modrst-offset = <0x10>;
};
 
usbphy0: usbphy@0 {
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a252905..22e7d82 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -593,6 +593,7 @@
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x100>;
+   altr,modrst-offset = <0x20>;
};
 
scu: snoop-control-unit@c000 {
-- 
2.4.5

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[PATCH 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

[dinguyen]

From: Dinh Nguyen 

Add the reset property for the EMAC controllers on Arria10.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 22e7d82..2340fcb 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -16,6 +16,7 @@
 
 #include "skeleton.dtsi"
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -414,6 +415,8 @@
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
+   resets = <&rst EMAC0_RESET>;
+   reset-names = "stmmaceth";
status = "disabled";
};
 
@@ -431,6 +434,8 @@
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
+   resets = <&rst EMAC1_RESET>;
+   reset-names = "stmmaceth";
status = "disabled";
};
 
-- 
2.4.5

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[PATCH 0/4] reset: socfpga: Add reset driver support for Arria10 platform

[dinguyen]

From: Dinh Nguyen 

Hi,

This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The
reset manager on the Arria10 is very similar to the one on Cyclone5/Arria5,
thus I think it's best to try to re-use the same reset driver.

The biggest difference between the reset manager on Arria10 and Cyclone is
the addition of security features. Since the driver does not support these
security features, it winds down to just a driver that will release IPs from
reset.

The other difference between Arria10 and Cyclone5 are register offsets, and
register bits for different IPs. For the register offset, the main register
offset is the very first register that is needed by the driver for releasing
IPs from reset. To handle this difference, I've introduced a new DTS property,
"altr,modrst-offset", that will represent this register.

The register bits for all the resets are in a new file:

include/dt-bindings/reset/altr,rst-mgr-a10.h

Thanks,

Dinh Nguyen (4):
  dt-bindings: Add reset manager offsets for Arria10
  ARM: socfpga: dts: add "altr,modrst-offset" property
  reset: socfpga: Update reset-socfpga to read the altr,modrst-offset
property
  ARM: socfpga: dts: Add resets for EMACs on Arria10

 .../devicetree/bindings/reset/socfpga-reset.txt|   2 +
 arch/arm/boot/dts/socfpga.dtsi |   1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi |   6 ++
 drivers/reset/reset-socfpga.c  |  19 ++--
 include/dt-bindings/reset/altr,rst-mgr-a10.h   | 110 +
 5 files changed, 132 insertions(+), 6 deletions(-)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

-- 
2.4.5

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[PATCH 1/4] dt-bindings: Add reset manager offsets for Arria10

[dinguyen]

From: Dinh Nguyen 

The reset manager for is pretty similar to the one for SoCFPGA
cyclone5/arria5 except for a few offsets. This patch adds those offsets.

Signed-off-by: Dinh Nguyen 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 +++
 1 file changed, 110 insertions(+)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..acb0bbf
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
2.4.5

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[PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk

[dinguyen]

From: Dinh Nguyen 

The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.

Signed-off-by: Dinh Nguyen 
---
v2: remove changes to socfpga.dtsi
---
 drivers/clk/socfpga/clk-periph.c | 18 ++
 drivers/clk/socfpga/clk.h|  1 +
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 0c66863..52c883e 100644
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -44,8 +44,17 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw 
*hwclk,
return parent_rate / div;
 }
 
+static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
+{
+   u32 clk_src;
+
+   clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);
+   return clk_src & 0x1;
+}
+
 static const struct clk_ops periclk_ops = {
.recalc_rate = clk_periclk_recalc_rate,
+   .get_parent = clk_periclk_get_parent,
 };
 
 static __init void __socfpga_periph_init(struct device_node *node,
@@ -55,7 +64,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
struct clk *clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
-   const char *parent_name;
+   const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
@@ -89,9 +98,10 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   parent_name = of_clk_get_parent_name(node, 0);
-   init.parent_names = &parent_name;
-   init.num_parents = 1;
+
+   init.num_parents = of_clk_parent_fill(node, parent_name,
+ SOCFPGA_MAX_PARENTS);
+   init.parent_names = parent_name;
 
periph_clk->hw.hw.init = &init;
 
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index aa2741d..814c724 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -22,6 +22,7 @@
 /* Clock Manager offsets */
 #define CLKMGR_CTRL0x0
 #define CLKMGR_BYPASS  0x4
+#define CLKMGR_DBCTRL  0x10
 #define CLKMGR_L4SRC   0x70
 #define CLKMGR_PERPLL_SRC  0xAC
 
-- 
2.4.5

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[PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk

[dinguyen]

From: Dinh Nguyen 

The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga.dtsi   |  2 +-
 drivers/clk/socfpga/clk-periph.c | 18 ++
 drivers/clk/socfpga/clk.h|  1 +
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 80f924d..7d5db54 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -164,7 +164,7 @@
dbg_base_clk: dbg_base_clk {
#clock-cells = <0>;
compatible = 
"altr,socfpga-perip-clk";
-   clocks = <&main_pll>;
+   clocks = <&main_pll>, 
<&osc1>;
div-reg = <0xe8 0 9>;
reg = <0x50>;
};
diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 0c66863..52c883e 100644
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -44,8 +44,17 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw 
*hwclk,
return parent_rate / div;
 }
 
+static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
+{
+   u32 clk_src;
+
+   clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);
+   return clk_src & 0x1;
+}
+
 static const struct clk_ops periclk_ops = {
.recalc_rate = clk_periclk_recalc_rate,
+   .get_parent = clk_periclk_get_parent,
 };
 
 static __init void __socfpga_periph_init(struct device_node *node,
@@ -55,7 +64,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
struct clk *clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
-   const char *parent_name;
+   const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
@@ -89,9 +98,10 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   parent_name = of_clk_get_parent_name(node, 0);
-   init.parent_names = &parent_name;
-   init.num_parents = 1;
+
+   init.num_parents = of_clk_parent_fill(node, parent_name,
+ SOCFPGA_MAX_PARENTS);
+   init.parent_names = parent_name;
 
periph_clk->hw.hw.init = &init;
 
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index aa2741d..814c724 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -22,6 +22,7 @@
 /* Clock Manager offsets */
 #define CLKMGR_CTRL0x0
 #define CLKMGR_BYPASS  0x4
+#define CLKMGR_DBCTRL  0x10
 #define CLKMGR_L4SRC   0x70
 #define CLKMGR_PERPLL_SRC  0xAC
 
-- 
2.4.5

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[PATCH] ARM: socfpga: add reset for the Arria 10 platform

[dinguyen]

From: Dinh Nguyen 

Since the Arria10's reset register offset is different from the Cyclone/Arria 5,
it's best to add a new DT_MACHINE_START() for the Arria10.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/core.h|  1 +
 arch/arm/mach-socfpga/socfpga.c | 26 ++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 7259c37..5bc6ea8 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -25,6 +25,7 @@
 #define SOCFPGA_RSTMGR_MODPERRST   0x14
 #define SOCFPGA_RSTMGR_BRGMODRST   0x1c
 
+#define SOCFPGA_A10_RSTMGR_CTRL0xC
 #define SOCFPGA_A10_RSTMGR_MODMPURST   0x20
 
 /* System Manager bits */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 19643a7..48c82af 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -74,6 +74,19 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, 
const char *cmd)
writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 }
 
+static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
+{
+   u32 temp;
+
+   temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
+
+   if (mode == REBOOT_HARD)
+   temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
+   else
+   temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+   writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
+}
+
 static const char *altera_dt_match[] = {
"altr,socfpga",
NULL
@@ -86,3 +99,16 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
.restart= socfpga_cyclone5_restart,
.dt_compat  = altera_dt_match,
 MACHINE_END
+
+static const char *altera_a10_dt_match[] = {
+   "altr,socfpga-arria10",
+   NULL
+};
+
+DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
+   .l2c_aux_val= 0,
+   .l2c_aux_mask   = ~0,
+   .init_irq   = socfpga_init_irq,
+   .restart= socfpga_arria10_restart,
+   .dt_compat  = altera_dt_match,
+MACHINE_END
-- 
2.4.5

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[PATCHv2 6/6] clk: ti: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Cc: Tero Kristo 
---
 drivers/clk/ti/apll.c  |4 +---
 drivers/clk/ti/composite.c |4 +---
 drivers/clk/ti/dpll.c  |4 +---
 drivers/clk/ti/fapll.c |3 +--
 drivers/clk/ti/mux.c   |4 +---
 5 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 49baf38..523880e 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -170,7 +170,6 @@ static void __init of_dra7_apll_setup(struct device_node 
*node)
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
-   int i;
 
ad = kzalloc(sizeof(*ad), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
@@ -195,8 +194,7 @@ static void __init of_dra7_apll_setup(struct device_node 
*node)
if (!parent_names)
goto cleanup;
 
-   for (i = 0; i < init->num_parents; i++)
-   parent_names[i] = of_clk_get_parent_name(node, i);
+   of_clk_parent_fill(node, parent_names, init->num_parents);
 
init->parent_names = parent_names;
 
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 96f83ce..dbef218 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -276,7 +276,6 @@ int __init ti_clk_add_component(struct device_node *node, 
struct clk_hw *hw,
int num_parents;
const char **parent_names;
struct component_clk *clk;
-   int i;
 
num_parents = of_clk_get_parent_count(node);
 
@@ -289,8 +288,7 @@ int __init ti_clk_add_component(struct device_node *node, 
struct clk_hw *hw,
if (!parent_names)
return -ENOMEM;
 
-   for (i = 0; i < num_parents; i++)
-   parent_names[i] = of_clk_get_parent_name(node, i);
+   of_clk_parent_fill(node, parent_names, num_parents);
 
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk) {
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 2aacf7a..49acdf2 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -341,7 +341,6 @@ static void __init of_ti_dpll_setup(struct device_node 
*node,
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
struct dpll_data *dd = NULL;
-   int i;
u8 dpll_mode = 0;
 
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
@@ -370,8 +369,7 @@ static void __init of_ti_dpll_setup(struct device_node 
*node,
if (!parent_names)
goto cleanup;
 
-   for (i = 0; i < init->num_parents; i++)
-   parent_names[i] = of_clk_get_parent_name(node, i);
+   of_clk_parent_fill(node, parent_names, init->num_parents);
 
init->parent_names = parent_names;
 
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 730aa62..b1c741b 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -558,8 +558,7 @@ static void __init ti_fapll_setup(struct device_node *node)
goto free;
}
 
-   parent_name[0] = of_clk_get_parent_name(node, 0);
-   parent_name[1] = of_clk_get_parent_name(node, 1);
+   of_clk_parent_fill(node, parent_name, 2);
init->parent_names = parent_name;
 
fd->clk_ref = of_clk_get(node, 0);
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 5cdeed5..99fe27e 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -190,7 +190,6 @@ static void of_mux_clk_setup(struct device_node *node)
void __iomem *reg;
int num_parents;
const char **parent_names;
-   int i;
u8 clk_mux_flags = 0;
u32 mask = 0;
u32 shift = 0;
@@ -205,8 +204,7 @@ static void of_mux_clk_setup(struct device_node *node)
if (!parent_names)
goto cleanup;
 
-   for (i = 0; i < num_parents; i++)
-   parent_names[i] = of_clk_get_parent_name(node, i);
+   of_clk_parent_fill(node, parent_names, num_parents);
 
reg = ti_clk_get_reg_addr(node, 0);
 
-- 
1.7.9.5

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[PATCHv2 0/6] clk: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Hello,

This is v2 of the patchset that makes use of of_clk_parent_fill helper function
on various platforms.

Thanks,

Dinh Nguyen (6):
  clk: at91: make use of of_clk_parent_fill helper function
  clk: qoriq: make use of of_clk_parent_fill helper function
  clk: keystone: make use of of_clk_parent_fill helper function
  clk: st: make use of of_clk_parent_fill helper function
  clk: sunxi: make use of of_clk_parent_fill helper function
  clk: ti: make use of of_clk_parent_fill helper function

 drivers/clk/at91/clk-main.c |7 +--
 drivers/clk/at91/clk-master.c   |7 +--
 drivers/clk/at91/clk-programmable.c |7 +--
 drivers/clk/at91/clk-slow.c |   14 ++
 drivers/clk/at91/clk-smd.c  |7 +--
 drivers/clk/at91/clk-usb.c  |7 +--
 drivers/clk/clk-qoriq.c |5 ++---
 drivers/clk/keystone/pll.c  |3 +--
 drivers/clk/st/clk-flexgen.c|6 ++
 drivers/clk/st/clkgen-mux.c |7 ++-
 drivers/clk/sunxi/clk-a20-gmac.c|4 +---
 drivers/clk/sunxi/clk-factors.c |4 +---
 drivers/clk/sunxi/clk-sun6i-ar100.c |3 +--
 drivers/clk/sunxi/clk-sunxi.c   |   10 ++
 drivers/clk/ti/apll.c   |4 +---
 drivers/clk/ti/composite.c  |4 +---
 drivers/clk/ti/dpll.c   |4 +---
 drivers/clk/ti/fapll.c  |3 +--
 drivers/clk/ti/mux.c|4 +---
 19 files changed, 24 insertions(+), 86 deletions(-)

-- 
1.7.9.5

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[PATCHv2 1/6] clk: at91: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Cc: Boris Brezillon 
---
 drivers/clk/at91/clk-main.c |7 +--
 drivers/clk/at91/clk-master.c   |7 +--
 drivers/clk/at91/clk-programmable.c |7 +--
 drivers/clk/at91/clk-slow.c |   14 ++
 drivers/clk/at91/clk-smd.c  |7 +--
 drivers/clk/at91/clk-usb.c  |7 +--
 6 files changed, 7 insertions(+), 42 deletions(-)

diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index c240045..13f481b 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -612,17 +612,12 @@ void __init of_at91sam9x5_clk_main_setup(struct 
device_node *np,
int num_parents;
unsigned int irq;
const char *name = np->name;
-   int i;
 
num_parents = of_clk_get_parent_count(np);
if (num_parents <= 0 || num_parents > 2)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
of_property_read_string(np, "clock-output-names", &name);
 
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index f98eafe..38f646d 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -218,7 +218,6 @@ of_at91_clk_master_setup(struct device_node *np, struct 
at91_pmc *pmc,
 {
struct clk *clk;
int num_parents;
-   int i;
unsigned int irq;
const char *parent_names[MASTER_SOURCE_MAX];
const char *name = np->name;
@@ -228,11 +227,7 @@ of_at91_clk_master_setup(struct device_node *np, struct 
at91_pmc *pmc,
if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
of_property_read_string(np, "clock-output-names", &name);
 
diff --git a/drivers/clk/at91/clk-programmable.c 
b/drivers/clk/at91/clk-programmable.c
index 8c86c0f..21492ac 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -230,7 +230,6 @@ of_at91_clk_prog_setup(struct device_node *np, struct 
at91_pmc *pmc,
 {
int num;
u32 id;
-   int i;
struct clk *clk;
int num_parents;
const char *parent_names[PROG_SOURCE_MAX];
@@ -241,11 +240,7 @@ of_at91_clk_prog_setup(struct device_node *np, struct 
at91_pmc *pmc,
if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
num = of_get_child_count(np);
if (!num || num > (PROG_ID_MAX + 1))
diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
index 98a84a8..84c19d7 100644
--- a/drivers/clk/at91/clk-slow.c
+++ b/drivers/clk/at91/clk-slow.c
@@ -371,17 +371,12 @@ void __init of_at91sam9x5_clk_slow_setup(struct 
device_node *np,
const char *parent_names[2];
int num_parents;
const char *name = np->name;
-   int i;
 
num_parents = of_clk_get_parent_count(np);
if (num_parents <= 0 || num_parents > 2)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
of_property_read_string(np, "clock-output-names", &name);
 
@@ -449,17 +444,12 @@ void __init of_at91sam9260_clk_slow_setup(struct 
device_node *np,
const char *parent_names[2];
int num_parents;
const char *name = np->name;
-   int i;
 
num_parents = of_clk_get_parent_count(np);
if (num_parents != 2)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
of_property_read_string(np, "clock-output-names", &name);
 
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
index 3817ea8..a7f8501 100644
--- a/drivers/clk/at91/clk-smd.c
+++ b/drivers/clk/at91/clk-smd.c
@@ -145,7 +145,6 @@ void __init of_at91sam9x5_clk_smd_setup(struct device_node 
*np,
struct at91_pmc *pmc)
 {
s

[PATCHv2 4/6] clk: st: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Tested-by Gabriel Fernandez 
Cc: Peter Griffin 
---
 drivers/clk/st/clk-flexgen.c |6 ++
 drivers/clk/st/clkgen-mux.c  |7 ++-
 2 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 657ca14..ed0696c 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -243,7 +243,7 @@ static const char ** __init flexgen_get_parents(struct 
device_node *np,
   int *num_parents)
 {
const char **parents;
-   int nparents, i;
+   int nparents;
 
nparents = of_clk_get_parent_count(np);
if (WARN_ON(nparents <= 0))
@@ -253,10 +253,8 @@ static const char ** __init flexgen_get_parents(struct 
device_node *np,
if (!parents)
return NULL;
 
-   for (i = 0; i < nparents; i++)
-   parents[i] = of_clk_get_parent_name(np, i);
+   *num_parents = of_clk_parent_fill(np, parents, nparents);
 
-   *num_parents = nparents;
return parents;
 }
 
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 4fbe6e0..b83654a 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -24,7 +24,7 @@ static const char ** __init clkgen_mux_get_parents(struct 
device_node *np,
   int *num_parents)
 {
const char **parents;
-   int nparents, i;
+   int nparents;
 
nparents = of_clk_get_parent_count(np);
if (WARN_ON(nparents <= 0))
@@ -34,10 +34,7 @@ static const char ** __init clkgen_mux_get_parents(struct 
device_node *np,
if (!parents)
return ERR_PTR(-ENOMEM);
 
-   for (i = 0; i < nparents; i++)
-   parents[i] = of_clk_get_parent_name(np, i);
-
-   *num_parents = nparents;
+   *num_parents = of_clk_parent_fill(np, parents, nparents);
return parents;
 }
 
-- 
1.7.9.5

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[PATCHv2 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Cc: Maxime Ripard 
Cc: "Emilio López" 
---
v2: Add if (of_clk_parent_fill(node, parents, 2) != 2) to clk-a20-gmac.c
---
 drivers/clk/sunxi/clk-a20-gmac.c|4 +---
 drivers/clk/sunxi/clk-factors.c |4 +---
 drivers/clk/sunxi/clk-sun6i-ar100.c |3 +--
 drivers/clk/sunxi/clk-sunxi.c   |   10 ++
 4 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c
index 0dcf4f2..1611b03 100644
--- a/drivers/clk/sunxi/clk-a20-gmac.c
+++ b/drivers/clk/sunxi/clk-a20-gmac.c
@@ -80,9 +80,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct 
device_node *node)
goto free_mux;
 
/* gmac clock requires exactly 2 parents */
-   parents[0] = of_clk_get_parent_name(node, 0);
-   parents[1] = of_clk_get_parent_name(node, 1);
-   if (!parents[0] || !parents[1])
+   if (of_clk_parent_fill(node, parents, 2) != 2)
goto free_gate;
 
reg = of_iomap(node, 0);
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 8c20190..2589457 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -174,9 +174,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
int i = 0;
 
/* if we have a mux, we will have >1 parents */
-   while (i < FACTORS_MAX_PARENTS &&
-  (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-   i++;
+   i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS);
 
/*
 * some factor clocks, such as pll5 and pll6, may have multiple
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c 
b/drivers/clk/sunxi/clk-sun6i-ar100.c
index 63cf149..6f229ff 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -195,8 +195,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device 
*pdev)
if (nparents > SUN6I_AR100_MAX_PARENTS)
nparents = SUN6I_AR100_MAX_PARENTS;
 
-   for (i = 0; i < nparents; i++)
-   parents[i] = of_clk_get_parent_name(np, i);
+   of_clk_parent_fill(np, parents, nparents);
 
of_property_read_string(np, "clock-output-names", &clk_name);
 
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 9a82f17..eed66f8 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -202,10 +202,7 @@ static void __init sun6i_ahb1_clk_setup(struct device_node 
*node)
return;
 
/* we have a mux, we will have >1 parents */
-   while (i < SUN6I_AHB1_MAX_PARENTS &&
-  (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-   i++;
-
+   of_clk_parent_fill(node, parents, SUN6I_AHB1_MAX_PARENTS);
of_property_read_string(node, "clock-output-names", &clk_name);
 
ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
@@ -790,10 +787,7 @@ static void __init sunxi_mux_clk_setup(struct device_node 
*node,
 
reg = of_iomap(node, 0);
 
-   while (i < SUNXI_MAX_PARENTS &&
-  (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-   i++;
-
+   of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
of_property_read_string(node, "clock-output-names", &clk_name);
 
clk = clk_register_mux(NULL, clk_name, parents, i,
-- 
1.7.9.5

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[PATCHv2 3/6] clk: keystone: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Acked-by: Santosh Shilimkar 
---
 drivers/clk/keystone/pll.c |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
index 4a375ea..d6ef063 100644
--- a/drivers/clk/keystone/pll.c
+++ b/drivers/clk/keystone/pll.c
@@ -309,8 +309,7 @@ static void __init of_pll_mux_clk_init(struct device_node 
*node)
return;
}
 
-   parents[0] = of_clk_get_parent_name(node, 0);
-   parents[1] = of_clk_get_parent_name(node, 1);
+   of_clk_parent_fill(node, parents, 2);
if (!parents[0] || !parents[1]) {
pr_err("%s: missing parent clocks\n", __func__);
return;
-- 
1.7.9.5

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[PATCHv2 2/6] clk: qoriq: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/clk-qoriq.c |5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index cda90a9..d3f4570 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -70,7 +70,7 @@ static void __init core_mux_init(struct device_node *np)
struct clk_init_data init;
struct cmux_clk *cmux_clk;
struct device_node *node;
-   int rc, count, i;
+   int rc, count;
u32 offset;
const char *clk_name;
const char **parent_names;
@@ -92,8 +92,7 @@ static void __init core_mux_init(struct device_node *np)
if (!parent_names)
return;
 
-   for (i = 0; i < count; i++)
-   parent_names[i] = of_clk_get_parent_name(np, i);
+   of_clk_parent_fill(np, parent_names, count);
 
cmux_clk = kzalloc(sizeof(*cmux_clk), GFP_KERNEL);
if (!cmux_clk)
-- 
1.7.9.5

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[PATCH 3/6] clk: keystone: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Cc: Santosh Shilimkar 
---
 drivers/clk/keystone/pll.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
index 0dd8a4b..d885372 100644
--- a/drivers/clk/keystone/pll.c
+++ b/drivers/clk/keystone/pll.c
@@ -293,8 +293,7 @@ static void __init of_pll_mux_clk_init(struct device_node 
*node)
return;
}
 
-   parents[0] = of_clk_get_parent_name(node, 0);
-   parents[1] = of_clk_get_parent_name(node, 1);
+   of_clk_parent_fill(node, parents, 2);
if (!parents[0] || !parents[1]) {
pr_err("%s: missing parent clocks\n", __func__);
return;
-- 
2.2.1

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[PATCH 4/6] clk: st: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Cc: Peter Griffin 
Cc: Gabriel FERNANDEZ 
---
 drivers/clk/st/clk-flexgen.c | 6 ++
 drivers/clk/st/clkgen-mux.c  | 7 ++-
 2 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 657ca14..ed0696c 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -243,7 +243,7 @@ static const char ** __init flexgen_get_parents(struct 
device_node *np,
   int *num_parents)
 {
const char **parents;
-   int nparents, i;
+   int nparents;
 
nparents = of_clk_get_parent_count(np);
if (WARN_ON(nparents <= 0))
@@ -253,10 +253,8 @@ static const char ** __init flexgen_get_parents(struct 
device_node *np,
if (!parents)
return NULL;
 
-   for (i = 0; i < nparents; i++)
-   parents[i] = of_clk_get_parent_name(np, i);
+   *num_parents = of_clk_parent_fill(np, parents, nparents);
 
-   *num_parents = nparents;
return parents;
 }
 
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 4fbe6e0..b83654a 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -24,7 +24,7 @@ static const char ** __init clkgen_mux_get_parents(struct 
device_node *np,
   int *num_parents)
 {
const char **parents;
-   int nparents, i;
+   int nparents;
 
nparents = of_clk_get_parent_count(np);
if (WARN_ON(nparents <= 0))
@@ -34,10 +34,7 @@ static const char ** __init clkgen_mux_get_parents(struct 
device_node *np,
if (!parents)
return ERR_PTR(-ENOMEM);
 
-   for (i = 0; i < nparents; i++)
-   parents[i] = of_clk_get_parent_name(np, i);
-
-   *num_parents = nparents;
+   *num_parents = of_clk_parent_fill(np, parents, nparents);
return parents;
 }
 
-- 
2.2.1

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[PATCH 6/6] clk: ti: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Cc: Tero Kristo 
---
 drivers/clk/ti/apll.c  | 4 +---
 drivers/clk/ti/composite.c | 4 +---
 drivers/clk/ti/dpll.c  | 4 +---
 drivers/clk/ti/fapll.c | 3 +--
 drivers/clk/ti/mux.c   | 4 +---
 5 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 49baf38..523880e 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -170,7 +170,6 @@ static void __init of_dra7_apll_setup(struct device_node 
*node)
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
-   int i;
 
ad = kzalloc(sizeof(*ad), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
@@ -195,8 +194,7 @@ static void __init of_dra7_apll_setup(struct device_node 
*node)
if (!parent_names)
goto cleanup;
 
-   for (i = 0; i < init->num_parents; i++)
-   parent_names[i] = of_clk_get_parent_name(node, i);
+   of_clk_parent_fill(node, parent_names, init->num_parents);
 
init->parent_names = parent_names;
 
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 96f83ce..dbef218 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -276,7 +276,6 @@ int __init ti_clk_add_component(struct device_node *node, 
struct clk_hw *hw,
int num_parents;
const char **parent_names;
struct component_clk *clk;
-   int i;
 
num_parents = of_clk_get_parent_count(node);
 
@@ -289,8 +288,7 @@ int __init ti_clk_add_component(struct device_node *node, 
struct clk_hw *hw,
if (!parent_names)
return -ENOMEM;
 
-   for (i = 0; i < num_parents; i++)
-   parent_names[i] = of_clk_get_parent_name(node, i);
+   of_clk_parent_fill(node, parent_names, num_parents);
 
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk) {
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 2aacf7a..49acdf2 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -341,7 +341,6 @@ static void __init of_ti_dpll_setup(struct device_node 
*node,
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
struct dpll_data *dd = NULL;
-   int i;
u8 dpll_mode = 0;
 
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
@@ -370,8 +369,7 @@ static void __init of_ti_dpll_setup(struct device_node 
*node,
if (!parent_names)
goto cleanup;
 
-   for (i = 0; i < init->num_parents; i++)
-   parent_names[i] = of_clk_get_parent_name(node, i);
+   of_clk_parent_fill(node, parent_names, init->num_parents);
 
init->parent_names = parent_names;
 
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 730aa62..b1c741b 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -558,8 +558,7 @@ static void __init ti_fapll_setup(struct device_node *node)
goto free;
}
 
-   parent_name[0] = of_clk_get_parent_name(node, 0);
-   parent_name[1] = of_clk_get_parent_name(node, 1);
+   of_clk_parent_fill(node, parent_name, 2);
init->parent_names = parent_name;
 
fd->clk_ref = of_clk_get(node, 0);
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 5cdeed5..99fe27e 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -190,7 +190,6 @@ static void of_mux_clk_setup(struct device_node *node)
void __iomem *reg;
int num_parents;
const char **parent_names;
-   int i;
u8 clk_mux_flags = 0;
u32 mask = 0;
u32 shift = 0;
@@ -205,8 +204,7 @@ static void of_mux_clk_setup(struct device_node *node)
if (!parent_names)
goto cleanup;
 
-   for (i = 0; i < num_parents; i++)
-   parent_names[i] = of_clk_get_parent_name(node, i);
+   of_clk_parent_fill(node, parent_names, num_parents);
 
reg = ti_clk_get_reg_addr(node, 0);
 
-- 
2.2.1

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[PATCH 1/6] clk: at91: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Cc: Boris Brezillon 
---
 drivers/clk/at91/clk-main.c |  7 +--
 drivers/clk/at91/clk-master.c   |  7 +--
 drivers/clk/at91/clk-programmable.c |  7 +--
 drivers/clk/at91/clk-slow.c | 14 ++
 drivers/clk/at91/clk-smd.c  |  7 +--
 drivers/clk/at91/clk-usb.c  |  7 +--
 6 files changed, 7 insertions(+), 42 deletions(-)

diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index c240045..13f481b 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -612,17 +612,12 @@ void __init of_at91sam9x5_clk_main_setup(struct 
device_node *np,
int num_parents;
unsigned int irq;
const char *name = np->name;
-   int i;
 
num_parents = of_clk_get_parent_count(np);
if (num_parents <= 0 || num_parents > 2)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
of_property_read_string(np, "clock-output-names", &name);
 
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index f98eafe..38f646d 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -218,7 +218,6 @@ of_at91_clk_master_setup(struct device_node *np, struct 
at91_pmc *pmc,
 {
struct clk *clk;
int num_parents;
-   int i;
unsigned int irq;
const char *parent_names[MASTER_SOURCE_MAX];
const char *name = np->name;
@@ -228,11 +227,7 @@ of_at91_clk_master_setup(struct device_node *np, struct 
at91_pmc *pmc,
if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
of_property_read_string(np, "clock-output-names", &name);
 
diff --git a/drivers/clk/at91/clk-programmable.c 
b/drivers/clk/at91/clk-programmable.c
index 8c86c0f..21492ac 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -230,7 +230,6 @@ of_at91_clk_prog_setup(struct device_node *np, struct 
at91_pmc *pmc,
 {
int num;
u32 id;
-   int i;
struct clk *clk;
int num_parents;
const char *parent_names[PROG_SOURCE_MAX];
@@ -241,11 +240,7 @@ of_at91_clk_prog_setup(struct device_node *np, struct 
at91_pmc *pmc,
if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
num = of_get_child_count(np);
if (!num || num > (PROG_ID_MAX + 1))
diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
index 98a84a8..84c19d7 100644
--- a/drivers/clk/at91/clk-slow.c
+++ b/drivers/clk/at91/clk-slow.c
@@ -371,17 +371,12 @@ void __init of_at91sam9x5_clk_slow_setup(struct 
device_node *np,
const char *parent_names[2];
int num_parents;
const char *name = np->name;
-   int i;
 
num_parents = of_clk_get_parent_count(np);
if (num_parents <= 0 || num_parents > 2)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
of_property_read_string(np, "clock-output-names", &name);
 
@@ -449,17 +444,12 @@ void __init of_at91sam9260_clk_slow_setup(struct 
device_node *np,
const char *parent_names[2];
int num_parents;
const char *name = np->name;
-   int i;
 
num_parents = of_clk_get_parent_count(np);
if (num_parents != 2)
return;
 
-   for (i = 0; i < num_parents; ++i) {
-   parent_names[i] = of_clk_get_parent_name(np, i);
-   if (!parent_names[i])
-   return;
-   }
+   of_clk_parent_fill(np, parent_names, num_parents);
 
of_property_read_string(np, "clock-output-names", &name);
 
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
index 3817ea8..a7f8501 100644
--- a/drivers/clk/at91/clk-smd.c
+++ b/drivers/clk/at91/clk-smd.c
@@ -145,7 +145,6 @@ void __init of_at91sam9x5_clk_smd_setup(struct device_node 
*np,
struct at91_pmc *pmc)
 {
struct clk *c

[PATCH 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
Cc: Maxime Ripard 
Cc: "Emilio López" 
---
 drivers/clk/sunxi/clk-a20-gmac.c|  3 +--
 drivers/clk/sunxi/clk-factors.c |  4 +---
 drivers/clk/sunxi/clk-sun6i-ar100.c |  3 +--
 drivers/clk/sunxi/clk-sunxi.c   | 10 ++
 4 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c
index 0dcf4f2..a432edd 100644
--- a/drivers/clk/sunxi/clk-a20-gmac.c
+++ b/drivers/clk/sunxi/clk-a20-gmac.c
@@ -80,8 +80,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct 
device_node *node)
goto free_mux;
 
/* gmac clock requires exactly 2 parents */
-   parents[0] = of_clk_get_parent_name(node, 0);
-   parents[1] = of_clk_get_parent_name(node, 1);
+   of_clk_parent_fill(node, parents, 2);
if (!parents[0] || !parents[1])
goto free_gate;
 
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 8c20190..2589457 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -174,9 +174,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
int i = 0;
 
/* if we have a mux, we will have >1 parents */
-   while (i < FACTORS_MAX_PARENTS &&
-  (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-   i++;
+   i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS);
 
/*
 * some factor clocks, such as pll5 and pll6, may have multiple
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c 
b/drivers/clk/sunxi/clk-sun6i-ar100.c
index 63cf149..6f229ff 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -195,8 +195,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device 
*pdev)
if (nparents > SUN6I_AR100_MAX_PARENTS)
nparents = SUN6I_AR100_MAX_PARENTS;
 
-   for (i = 0; i < nparents; i++)
-   parents[i] = of_clk_get_parent_name(np, i);
+   of_clk_parent_fill(np, parents, nparents);
 
of_property_read_string(np, "clock-output-names", &clk_name);
 
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7e1e2bd..ebea294 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -200,10 +200,7 @@ static void __init sun6i_ahb1_clk_setup(struct device_node 
*node)
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 
/* we have a mux, we will have >1 parents */
-   while (i < SUN6I_AHB1_MAX_PARENTS &&
-  (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-   i++;
-
+   of_clk_parent_fill(node, parents, SUN6I_AHB1_MAX_PARENTS);
of_property_read_string(node, "clock-output-names", &clk_name);
 
ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
@@ -788,10 +785,7 @@ static void __init sunxi_mux_clk_setup(struct device_node 
*node,
 
reg = of_iomap(node, 0);
 
-   while (i < SUNXI_MAX_PARENTS &&
-  (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-   i++;
-
+   of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
of_property_read_string(node, "clock-output-names", &clk_name);
 
clk = clk_register_mux(NULL, clk_name, parents, i,
-- 
2.2.1

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[PATCH 2/6] clk: qoriq: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/clk-qoriq.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index cda90a9..d3f4570 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -70,7 +70,7 @@ static void __init core_mux_init(struct device_node *np)
struct clk_init_data init;
struct cmux_clk *cmux_clk;
struct device_node *node;
-   int rc, count, i;
+   int rc, count;
u32 offset;
const char *clk_name;
const char **parent_names;
@@ -92,8 +92,7 @@ static void __init core_mux_init(struct device_node *np)
if (!parent_names)
return;
 
-   for (i = 0; i < count; i++)
-   parent_names[i] = of_clk_get_parent_name(np, i);
+   of_clk_parent_fill(np, parent_names, count);
 
cmux_clk = kzalloc(sizeof(*cmux_clk), GFP_KERNEL);
if (!cmux_clk)
-- 
2.2.1

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[PATCH 0/6] clk: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Hello,

This patch series makes use of the new of_clk_parent_fill() helper function.
This patch series is not intended for v4.2, as I think it's a bit late, but
I just wanted to make sure people have time to test it. The series is based
on git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git#clk-next.

Thank,

Dinh Nguyen (6):
  clk: at91: make use of of_clk_parent_fill helper function
  clk: qoriq: make use of of_clk_parent_fill helper function
  clk: keystone: make use of of_clk_parent_fill helper function
  clk: st: make use of of_clk_parent_fill helper function
  clk: sunxi: make use of of_clk_parent_fill helper function
  clk: ti: make use of of_clk_parent_fill helper function

 drivers/clk/at91/clk-main.c |  7 +--
 drivers/clk/at91/clk-master.c   |  7 +--
 drivers/clk/at91/clk-programmable.c |  7 +--
 drivers/clk/at91/clk-slow.c | 14 ++
 drivers/clk/at91/clk-smd.c  |  7 +--
 drivers/clk/at91/clk-usb.c  |  7 +--
 drivers/clk/clk-qoriq.c |  5 ++---
 drivers/clk/keystone/pll.c  |  3 +--
 drivers/clk/st/clk-flexgen.c|  6 ++
 drivers/clk/st/clkgen-mux.c |  7 ++-
 drivers/clk/sunxi/clk-a20-gmac.c|  3 +--
 drivers/clk/sunxi/clk-factors.c |  4 +---
 drivers/clk/sunxi/clk-sun6i-ar100.c |  3 +--
 drivers/clk/sunxi/clk-sunxi.c   | 10 ++
 drivers/clk/ti/apll.c   |  4 +---
 drivers/clk/ti/composite.c  |  4 +---
 drivers/clk/ti/dpll.c   |  4 +---
 drivers/clk/ti/fapll.c  |  3 +--
 drivers/clk/ti/mux.c|  4 +---
 19 files changed, 24 insertions(+), 85 deletions(-)
---
Cc: Tero Kristo 
Cc: Maxime Ripard 
Cc: "Emilio López" 
Cc: Peter Griffin 
Cc: Gabriel FERNANDEZ 
Cc: Santosh Shilimkar 
Cc: Boris Brezillon 

-- 
2.2.1

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[PATCHv3 1/2] clk: of: helper for filling parent clock array and return num of parents

[dinguyen]

From: Dinh Nguyen 

Sprinkled all through the platform clock drivers are code like this to
fill the clock parent array:

for (i = 0; i < num_parents; ++i)
parent_names[i] = of_clk_get_parent_name(np, i);

The of_clk_parent_fill() will do the same as the code above, and while
at it, return the number of parents as well since the logic of the
function is to the walk the clock node to look for the parent.

Signed-off-by: Dinh Nguyen 
---
v3: shorten and clean up function comment, use EXPORT_SYMBOL_GPL
v2: use unsigned int for size
---
 drivers/clk/clk.c| 20 
 include/linux/clk-provider.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 459ce9d..5130622 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3060,6 +3060,26 @@ const char *of_clk_get_parent_name(struct device_node 
*np, int index)
 }
 EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
 
+/**
+ * of_clk_parent_fill(): Fill @parents with names of @np's parents and return
+ * number of parents.
+ * @np: Device node pointer associated with clock provider
+ * @parents: pointer to char array that hold the parents' name
+ * @size: size of the parents array
+ *
+ * Returns number of parents for the clock node.
+ */
+int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned 
int size)
+{
+   unsigned int i = 0;
+
+   while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
+   i++;
+
+   return i;
+}
+EXPORT_SYMBOL_GPL(of_clk_parent_fill);
+
 struct clock_provider {
of_clk_init_cb_t clk_init_cb;
struct device_node *np;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index df69531..3ab66d3 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -624,6 +624,7 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args 
*clkspec,
  void *data);
 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void 
*data);
 int of_clk_get_parent_count(struct device_node *np);
+int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned 
int size);
 const char *of_clk_get_parent_name(struct device_node *np, int index);
 
 void of_clk_init(const struct of_device_id *matches);
-- 
2.2.1

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[PATCHv3 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock's array.

Signed-off-by: Dinh Nguyen 
---
v3: none
v2: none
---
 drivers/clk/socfpga/clk-gate.c | 6 +-
 drivers/clk/socfpga/clk-pll.c  | 7 +--
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index dd3a78c..fb5a5d7 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -194,7 +194,6 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
-   int i = 0;
 
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk))
@@ -238,12 +237,9 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
 
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
-   init.num_parents = i;
socfpga_clk->hw.hw.init = &init;
 
clk = clk_register(NULL, &socfpga_clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index de6da95..8f26b52 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -92,7 +92,6 @@ static __init struct clk *__socfpga_pll_init(struct 
device_node *node,
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
-   int i = 0;
 
of_property_read_u32(node, "reg", ®);
 
@@ -111,11 +110,7 @@ static __init struct clk *__socfpga_pll_init(struct 
device_node *node,
init.ops = ops;
init.flags = 0;
 
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
-
-   init.num_parents = i;
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
pll_clk->hw.hw.init = &init;
 
-- 
2.2.1

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[PATCHv3 0/2] clk: of: add helper function to fill parent clock array

[dinguyen]

From: Dinh Nguyen 

Hi,

As suggested by Stephen Boyd, this patch adds a helper function that will fill
the parent clock array.

Since the following code is sprinkled all over the platform clock drivers:

for (i = 0; i < num_parents; ++i)
parent_names[i] = of_clk_get_parent_name(np, i);

The above code can be replace by of_clk_parent_fill(). And since the logic
of the of_clk_parent_fill is to walk the clock node to find the parent, it is
easy to just return the number of parents as well.

The second patch makes use of the new helper function in the SoCFPGA platform.
If this patch is accepted, I can go through and replace the other platforms
after that.

v3: shorten and clean up function comment, use EXPORT_SYMBOL_GPL
v2: use unsigned int for size

Thanks,

Dinh Nguyen (2):
  clk: of: helper for filling parent clock array and return num of
parents
  clk: socfpga: make use of of_clk_parent_fill helper function

 drivers/clk/clk.c  | 20 
 drivers/clk/socfpga/clk-gate.c |  6 +-
 drivers/clk/socfpga/clk-pll.c  |  7 +--
 include/linux/clk-provider.h   |  1 +
 4 files changed, 23 insertions(+), 11 deletions(-)

-- 
2.2.1

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[PATCH] EDAC, altera: wrap edac pm with a CONFIG_PM

[dinguyen]

From: Alan Tull 

Suspend-to-RAM and EDAC support are mutually exclusive on
SOCFPGA.  If the EDAC is enabled, it will prevent the
platform from going into suspend.

Signed-off-by: Alan Tull 
Signed-off-by: Dinh Nguyen 
Acked-by: Borislav Petkov 
---
Hi Boris,

Please apply this patch to your for-next? This was part of Alan Tull's
suspend-to-ram patch that I was going to take through arm-soc. But if
I left the patch as it was, it would have caused a merge conflict for
v4.2.

Thanks,
Dinh
---
 drivers/edac/altera_edac.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 182c741..23ef091 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -477,11 +477,31 @@ static int altr_sdram_remove(struct platform_device *pdev)
return 0;
 }
 
+/*
+ * If you want to suspend, need to disable EDAC by removing it
+ * from the device tree or defconfig.
+ */
+#ifdef CONFIG_PM
+static int altr_sdram_prepare(struct device *dev)
+{
+   pr_err("Suspend not allowed when EDAC is enabled.\n");
+
+   return -EPERM;
+}
+
+static const struct dev_pm_ops altr_sdram_pm_ops = {
+   .prepare = altr_sdram_prepare,
+};
+#endif
+
 static struct platform_driver altr_sdram_edac_driver = {
.probe = altr_sdram_probe,
.remove = altr_sdram_remove,
.driver = {
.name = "altr_sdram_edac",
+#ifdef CONFIG_PM
+   .pm = &altr_sdram_pm_ops,
+#endif
.of_match_table = altr_sdram_ctrl_of_match,
},
 };
-- 
2.2.1

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[RFC/PATCHv2 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock's array.

Signed-off-by: Dinh Nguyen 
---
v2: none
---
 drivers/clk/socfpga/clk-gate.c | 6 +-
 drivers/clk/socfpga/clk-pll.c  | 7 +--
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index dd3a78c..fb5a5d7 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -194,7 +194,6 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
-   int i = 0;
 
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk))
@@ -238,12 +237,9 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
 
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
-   init.num_parents = i;
socfpga_clk->hw.hw.init = &init;
 
clk = clk_register(NULL, &socfpga_clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index de6da95..8f26b52 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -92,7 +92,6 @@ static __init struct clk *__socfpga_pll_init(struct 
device_node *node,
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
-   int i = 0;
 
of_property_read_u32(node, "reg", ®);
 
@@ -111,11 +110,7 @@ static __init struct clk *__socfpga_pll_init(struct 
device_node *node,
init.ops = ops;
init.flags = 0;
 
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
-
-   init.num_parents = i;
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
pll_clk->hw.hw.init = &init;
 
-- 
2.2.1

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[RFC/PATCHv2 0/2] clk: of: add helper function to fill parent clock array

[dinguyen]

From: Dinh Nguyen 

Hi,

As suggested by Stephen Boyd, this patch adds a helper function that will fill
the parent clock array.

Since the following code is sprinkled all over the platform clock drivers:

for (i = 0; i < num_parents; ++i)
parent_names[i] = of_clk_get_parent_name(np, i);

The above code can be replace by of_clk_parent_fill(). And since the logic
of the of_clk_parent_fill is to walk the clock node to find the parent, it is
easy to just return the number of parents as well.

The second patch makes use of the new helper function in the SoCFPGA platform.
If this patch is accepted, I can go through and replace the other platforms
after that.

v2: use unsigned int for 'size'

Thanks,

Dinh Nguyen (2):
  clk: of: helper for filling parent clock array and return num of
parents
  clk: socfpga: make use of of_clk_parent_fill helper function

 drivers/clk/clk.c  | 20 
 drivers/clk/socfpga/clk-gate.c |  6 +-
 drivers/clk/socfpga/clk-pll.c  |  7 +--
 include/linux/clk-provider.h   |  1 +
 4 files changed, 23 insertions(+), 11 deletions(-)

-- 
2.2.1

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[RFC/PATCHv2 1/2] clk: of: helper for filling parent clock array and return num of parents

[dinguyen]

From: Dinh Nguyen 

Sprinkled all through the platform clock drivers are code like this to
fill the clock parent array:

for (i = 0; i < num_parents; ++i)
parent_names[i] = of_clk_get_parent_name(np, i);

The of_clk_parent_fill() will do the same as the code above, and while
at it, return the number of parents as well since the logic of the
function is to the walk the clock node to look for the parent.

Signed-off-by: Dinh Nguyen 
---
v2: use unsigned int for size
---
 drivers/clk/clk.c| 20 
 include/linux/clk-provider.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 459ce9d..778bebd 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3060,6 +3060,26 @@ const char *of_clk_get_parent_name(struct device_node 
*np, int index)
 }
 EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
 
+/*
+ * of_clk_parent_fill(): Helper clock function that will fill the parent
+ * clock's array and return the number of parents it found.
+ * @np: Device node pointer associated with clock provider
+ * @parents: pointer to char array that hold the parent's name
+ * @size: size of the parents array
+ *
+ * Returns number of parents for the clock node.
+ */
+int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned 
int size)
+{
+   unsigned int i = 0;
+
+   while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
+   i++;
+
+   return i;
+}
+EXPORT_SYMBOL(of_clk_parent_fill);
+
 struct clock_provider {
of_clk_init_cb_t clk_init_cb;
struct device_node *np;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index df69531..3ab66d3 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -624,6 +624,7 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args 
*clkspec,
  void *data);
 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void 
*data);
 int of_clk_get_parent_count(struct device_node *np);
+int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned 
int size);
 const char *of_clk_get_parent_name(struct device_node *np, int index);
 
 void of_clk_init(const struct of_device_id *matches);
-- 
2.2.1

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[RFC/PATCHv1 1/2] clk: of: helper for filling parent clock array and return num of parents

[dinguyen]

From: Dinh Nguyen 

Sprinkled all through the platform clock drivers are code like this to
fill the clock parent array:

for (i = 0; i < num_parents; ++i)
parent_names[i] = of_clk_get_parent_name(np, i);

The of_clk_parent_fill() will do the same as the code above, and while
at it, return the number of parents as well since the logic of the
function is to the walk the clock node to look for the parent.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/clk.c| 20 
 include/linux/clk-provider.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 459ce9d..b75616f 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3060,6 +3060,26 @@ const char *of_clk_get_parent_name(struct device_node 
*np, int index)
 }
 EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
 
+/*
+ * of_clk_parent_fill(): Helper clock function that will fill the parent
+ * clock's array and return the number of parents it found.
+ * @np: Device node pointer associated with clock provider
+ * @parents: pointer to char array that hold the parent's name
+ * @size: size of the parents array
+ *
+ * Returns number of parents for the clock node.
+ */
+int of_clk_parent_fill(struct device_node *np, const char **parents, int size)
+{
+   int i = 0;
+
+   while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
+   i++;
+
+   return i;
+}
+EXPORT_SYMBOL(of_clk_parent_fill);
+
 struct clock_provider {
of_clk_init_cb_t clk_init_cb;
struct device_node *np;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index df69531..36e56c4 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -624,6 +624,7 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args 
*clkspec,
  void *data);
 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void 
*data);
 int of_clk_get_parent_count(struct device_node *np);
+int of_clk_parent_fill(struct device_node *np, const char **parents, int size);
 const char *of_clk_get_parent_name(struct device_node *np, int index);
 
 void of_clk_init(const struct of_device_id *matches);
-- 
2.2.1

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[RFC/PATCHv1 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

[dinguyen]

From: Dinh Nguyen 

Use of_clk_parent_fill to fill in the parent clock's array.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/clk-gate.c | 6 +-
 drivers/clk/socfpga/clk-pll.c  | 7 +--
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index dd3a78c..fb5a5d7 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -194,7 +194,6 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
-   int i = 0;
 
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk))
@@ -238,12 +237,9 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
 
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
-   init.num_parents = i;
socfpga_clk->hw.hw.init = &init;
 
clk = clk_register(NULL, &socfpga_clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index de6da95..8f26b52 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -92,7 +92,6 @@ static __init struct clk *__socfpga_pll_init(struct 
device_node *node,
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
-   int i = 0;
 
of_property_read_u32(node, "reg", ®);
 
@@ -111,11 +110,7 @@ static __init struct clk *__socfpga_pll_init(struct 
device_node *node,
init.ops = ops;
init.flags = 0;
 
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
-
-   init.num_parents = i;
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
pll_clk->hw.hw.init = &init;
 
-- 
2.2.1

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[RFC/PATCHv1 0/2] clk: of: add helper function to fill parent clock array

[dinguyen]

From: Dinh Nguyen 

Hi,

As suggested by Stephen Boyd, this patch adds a helper function that will fill
the parent clock array.

Since this kind of code is sprinkled all over the platform clock drivers:

for (i = 0; i < num_parents; ++i)
parent_names[i] = of_clk_get_parent_name(np, i);

The above code can be replace by of_clk_parent_fill(). And since the logic
of the of_clk_parent_fill is to walk the clock node to find the parent, it is
easy to just return the number of parents as well.

The second patch makes use of the new helper function in the SoCFPGA platform.
If this patch is accepted, I can go through and replace the other platforms
after that.

Thanks,

Dinh Nguyen (2):
  clk: of: helper for filling parent clock array and return num of
parents
  clk: socfpga: make use of of_clk_parent_fill helper function

 drivers/clk/clk.c  | 20 
 drivers/clk/socfpga/clk-gate.c |  6 +-
 drivers/clk/socfpga/clk-pll.c  |  7 +--
 include/linux/clk-provider.h   |  1 +
 4 files changed, 23 insertions(+), 11 deletions(-)

-- 
2.2.1

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[PATCH] usb: dwc2: fix unnecessary USB overcurrent condition

[dinguyen]

From: Dinh Nguyen 

For platforms that use a ULPI phy, we should enable the external VbusValid
signal instead.

Signed-off-by: Dinh Nguyen 
Cc: Gregory Herrero 
Cc: Mian Yousaf Kaukab 
Cc: Felipe Balbi 
---
 drivers/usb/dwc2/core.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index e5b546f..08ffdc6 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -807,6 +807,11 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool 
select_phy, int irq)
if (hsotg->core_params->ts_dline > 0)
usbcfg |= GUSBCFG_TERMSELDLPULSE;
 
+   /* Set external VBUS indicator as needed. */
+   if (hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_ULPI)
+   usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
+  GUSBCFG_INDICATORPASSTHROUGH);
+
writel(usbcfg, hsotg->regs + GUSBCFG);
 
/* Reset the Controller */
-- 
2.2.1

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[PATCH 1/3] ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5

[dinguyen]

From: Dinh Nguyen 

Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/platsmp.c | 2 ++
 arch/arm/mach-socfpga/socfpga.c | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 7886eae..08250c8 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -90,3 +90,5 @@ struct smp_operations socfpga_smp_ops __initdata = {
.cpu_die= socfpga_cpu_die,
 #endif
 };
+
+CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index b63dec6..a154920 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -78,7 +78,6 @@ static const char *altera_dt_match[] = {
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
.l2c_aux_val= 0,
.l2c_aux_mask   = ~0,
-   .smp= smp_ops(socfpga_smp_ops),
.init_irq   = socfpga_init_irq,
.restart= socfpga_cyclone5_restart,
.dt_compat  = altera_dt_match,
-- 
2.2.1

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[PATCH 2/3] ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10

[dinguyen]

From: Dinh Nguyen 

Add boot_secondary implementation for the Arria10 platform. Bringing up
the secondary core on the Arria 10 platform is pretty similar to the
Cyclone/Arria 5 platform, with the exception of the following differences:

- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/core.h|  2 ++
 arch/arm/mach-socfpga/platsmp.c | 30 ++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 5913bbb..7637b7f 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -25,6 +25,8 @@
 #define SOCFPGA_RSTMGR_MODPERRST   0x14
 #define SOCFPGA_RSTMGR_BRGMODRST   0x1c
 
+#define SOCFPGA_A10_RSTMGR_MODMPURST   0x20
+
 /* System Manager bits */
 #define RSTMGR_CTRL_SWCOLDRSTREQ   0x1 /* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ   0x2 /* Warm Reset */
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 08250c8..bcc7ce8 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -54,6 +54,27 @@ static int socfpga_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
return 0;
 }
 
+static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct 
*idle)
+{
+   int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+   if (socfpga_cpu1start_addr) {
+   memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+   writel(virt_to_phys(socfpga_secondary_startup),
+  sys_manager_base_addr + (socfpga_cpu1start_addr & 
0x0fff));
+
+   flush_cache_all();
+   smp_wmb();
+   outer_clean_range(0, trampoline_size);
+
+   /* This will release CPU #1 out of reset. */
+   writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
+   }
+
+   return 0;
+}
+
 static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
 {
struct device_node *np;
@@ -91,4 +112,13 @@ struct smp_operations socfpga_smp_ops __initdata = {
 #endif
 };
 
+struct smp_operations socfpga_a10_smp_ops __initdata = {
+   .smp_prepare_cpus   = socfpga_smp_prepare_cpus,
+   .smp_boot_secondary = socfpga_a10_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+   .cpu_die= socfpga_cpu_die,
+#endif
+};
+
 CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
+CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", 
&socfpga_a10_smp_ops);
-- 
2.2.1

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[PATCH 3/3] ARM: socfpga: dts: add enable-method property for cpu nodes

[dinguyen]

From: Dinh Nguyen 

Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga.dtsi | 1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 9b653ed..80f924d 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -36,6 +36,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "altr,socfpga-smp";
 
cpu@0 {
compatible = "arm,cortex-a9";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index d025f77..6ceb26e 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -24,6 +24,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "altr,socfpga-a10-smp";
 
cpu@0 {
compatible = "arm,cortex-a9";
-- 
2.2.1

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[PATCH 0/3] ARM: socfpga: enable SMP for Arria10

[dinguyen]

From: Dinh Nguyen 

Hi,

The goal of these 3 patches is to enable SMP on the Arria10 platform. During
the process, I found it would be much cleaner to convert the Cyclone5/Arria5
platform to use CPU_METHOD_OF_DECLARE instead of the machine descriptor.

The procedure to enable SMP on the Arria10 platform is similar to the Cyclone5/
Arria5 with the exception of a few differences in the register offset of the
reset manager designed to bring the secondary core out of reset. So instead of
littering the code with machine lookups, just use CPU_METHOD_OF_DECLARE.

Thanks,

Dinh Nguyen (3):
  ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
  ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
  ARM: socfpga: dts: add enable-method property for cpu nodes

 arch/arm/boot/dts/socfpga.dtsi |  1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi |  1 +
 arch/arm/mach-socfpga/core.h   |  2 ++
 arch/arm/mach-socfpga/platsmp.c| 32 
 arch/arm/mach-socfpga/socfpga.c|  1 -
 5 files changed, 36 insertions(+), 1 deletion(-)

-- 
2.2.1

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[PATCHv4 1/2] clk: socfpga: update clk.h so for Arria10 platform to use

[dinguyen]

From: Dinh Nguyen 

There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define
SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver
can use.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/clk-gate.c | 4 
 drivers/clk/socfpga/clk.h  | 6 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index dd3a78c..607ab35 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -32,14 +32,10 @@
 #define SOCFPGA_MMC_CLK"sdmmc_clk"
 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
 
-#define streq(a, b) (strcmp((a), (b)) == 0)
-
 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
 /* SDMMC Group for System Manager defines */
 #define SYSMGR_SDMMCGRP_CTRL_OFFSET0x108
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
-   smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
 
 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d291f60..b09a5d5 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -26,9 +26,13 @@
 #define CLKMGR_L4SRC   0x70
 #define CLKMGR_PERPLL_SRC  0xAC
 
-#define SOCFPGA_MAX_PARENTS3
+#define SOCFPGA_MAX_PARENTS5
 #define div_mask(width) ((1 << (width)) - 1)
 
+#define streq(a, b) (strcmp((a), (b)) == 0)
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+   smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
 extern void __iomem *clk_mgr_base_addr;
 
 void __init socfpga_pll_init(struct device_node *node);
-- 
2.2.1

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[PATCHv4 0/2] clk: socfpga: Add clock driver for Arria10

[dinguyen]

From: Dinh Nguyen 

Hi,

This patch series add the clock driver for the Arria10 platform. Although the
Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the
differences are enough to warrant it's own driver, rather than polluting the
existing driver with platform lookups.

v4:
- Move syscon regmap lookup to gate_clk_init().
- Remove unused includes(linux/clk.h and linux/clkdev.h)
- Check return value of of_clk_add_provider
- Clean ups to address Stephen's comments

v3:
- Fix sparse warning of assigning an integer 0 instead of NULL to a pointer.

v2:
- Update the DTS bindings doucment to have the new Arria10 clocks.
- Add an l4_sys_free_clk node. The l4_sys_free_clk is similar to the
  l4_sp_clk, but cannot be gated.

Thanks,

Dinh Nguyen (2):
  clk: socfpga: update clk.h so for Arria10 platform to use
  clk: socfpga: add a clock driver for the Arria 10 platform

 drivers/clk/socfpga/Makefile |   1 +
 drivers/clk/socfpga/clk-gate-a10.c   | 188 +++
 drivers/clk/socfpga/clk-gate.c   |   4 -
 drivers/clk/socfpga/clk-periph-a10.c | 138 +
 drivers/clk/socfpga/clk-pll-a10.c| 129 
 drivers/clk/socfpga/clk.c|   7 +-
 drivers/clk/socfpga/clk.h|  11 +-
 7 files changed, 472 insertions(+), 6 deletions(-)
 create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-a10.c

-- 
2.2.1

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[PATCHv4 2/2] clk: socfpga: add a clock driver for the Arria 10 platform

[dinguyen]

From: Dinh Nguyen 

The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5
platform that it should just have it's own driver.

Signed-off-by: Dinh Nguyen 
---
v4: Move lookup of syscon for clk_phase to gate_clk_init()
Remove unused includes
v3: Assign pointer to NULL instead of integer 0 per sparse check
---
 drivers/clk/socfpga/Makefile |   1 +
 drivers/clk/socfpga/clk-gate-a10.c   | 188 +++
 drivers/clk/socfpga/clk-periph-a10.c | 138 +
 drivers/clk/socfpga/clk-pll-a10.c| 129 
 drivers/clk/socfpga/clk.c|   7 +-
 drivers/clk/socfpga/clk.h|   5 +
 6 files changed, 467 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-a10.c

diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 7e2d15a..d8bb239 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -2,3 +2,4 @@ obj-y += clk.o
 obj-y += clk-gate.o
 obj-y += clk-pll.o
 obj-y += clk-periph.o
+obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
new file mode 100644
index 000..01fee80
--- /dev/null
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define streq(a, b) (strcmp((a), (b)) == 0)
+
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
+
+/* SDMMC Group for System Manager defines */
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET0x28
+
+static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
+   unsigned long parent_rate)
+{
+   struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+   u32 div = 1, val;
+
+   if (socfpgaclk->fixed_div)
+   div = socfpgaclk->fixed_div;
+   else if (socfpgaclk->div_reg) {
+   val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+   val &= div_mask(socfpgaclk->width);
+   div = (1 << val);
+   }
+
+   return parent_rate / div;
+}
+
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
+{
+   struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+   int i;
+   u32 hs_timing;
+   u32 clk_phase[2];
+
+   if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
+   for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
+   switch (socfpgaclk->clk_phase[i]) {
+   case 0:
+   clk_phase[i] = 0;
+   break;
+   case 45:
+   clk_phase[i] = 1;
+   break;
+   case 90:
+   clk_phase[i] = 2;
+   break;
+   case 135:
+   clk_phase[i] = 3;
+   break;
+   case 180:
+   clk_phase[i] = 4;
+   break;
+   case 225:
+   clk_phase[i] = 5;
+   break;
+   case 270:
+   clk_phase[i] = 6;
+   break;
+   case 315:
+   clk_phase[i] = 7;
+   break;
+   default:
+   clk_phase[i] = 0;
+   break;
+   }
+   }
+
+   hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
+   if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
+   regmap_write(socfpgaclk->sys_mgr_base_addr,
+SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
+   else
+   pr_err("%s: cannot set clk_phase because 
sys_mgr_base_addr\
+   is not available!\n", __func__);
+   }
+   return 0;
+}
+
+stat

[PATCHv3 1/4] clk: socfpga: update clk.h so for Arria10 platform to use

[dinguyen]

From: Dinh Nguyen 

There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define
SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver
can use.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/clk-gate.c | 4 
 drivers/clk/socfpga/clk.h  | 6 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index dd3a78c..607ab35 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -32,14 +32,10 @@
 #define SOCFPGA_MMC_CLK"sdmmc_clk"
 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
 
-#define streq(a, b) (strcmp((a), (b)) == 0)
-
 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
 /* SDMMC Group for System Manager defines */
 #define SYSMGR_SDMMCGRP_CTRL_OFFSET0x108
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
-   smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
 
 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d291f60..b09a5d5 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -26,9 +26,13 @@
 #define CLKMGR_L4SRC   0x70
 #define CLKMGR_PERPLL_SRC  0xAC
 
-#define SOCFPGA_MAX_PARENTS3
+#define SOCFPGA_MAX_PARENTS5
 #define div_mask(width) ((1 << (width)) - 1)
 
+#define streq(a, b) (strcmp((a), (b)) == 0)
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+   smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
 extern void __iomem *clk_mgr_base_addr;
 
 void __init socfpga_pll_init(struct device_node *node);
-- 
2.2.1

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[PATCHv3 2/4] clk: socfpga: add a clock driver for the Arria 10 platform

[dinguyen]

From: Dinh Nguyen 

The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5
platform that it should just have it's own driver.

Signed-off-by: Dinh Nguyen 
---
v3: Assign pointer to NULL instead of integer 0 per sparse check
---
 drivers/clk/socfpga/Makefile |   1 +
 drivers/clk/socfpga/clk-gate-a10.c   | 187 +++
 drivers/clk/socfpga/clk-periph-a10.c | 131 
 drivers/clk/socfpga/clk-pll-a10.c| 132 +
 drivers/clk/socfpga/clk.c|   7 +-
 drivers/clk/socfpga/clk.h|   4 +
 6 files changed, 461 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-a10.c

diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 7e2d15a..d8bb239 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -2,3 +2,4 @@ obj-y += clk.o
 obj-y += clk-gate.o
 obj-y += clk-pll.o
 obj-y += clk-periph.o
+obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
new file mode 100644
index 000..fadf6f7
--- /dev/null
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define streq(a, b) (strcmp((a), (b)) == 0)
+
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
+
+/* SDMMC Group for System Manager defines */
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET0x28
+
+static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
+   unsigned long parent_rate)
+{
+   struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+   u32 div = 1, val;
+
+   if (socfpgaclk->fixed_div)
+   div = socfpgaclk->fixed_div;
+   else if (socfpgaclk->div_reg) {
+   val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+   val &= div_mask(socfpgaclk->width);
+   div = (1 << val);
+   }
+
+   return parent_rate / div;
+}
+
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
+{
+   struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+   struct regmap *sys_mgr_base_addr;
+   int i;
+   u32 hs_timing;
+   u32 clk_phase[2];
+
+   if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
+   sys_mgr_base_addr = 
syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+   if (IS_ERR(sys_mgr_base_addr)) {
+   pr_err("%s: failed to find altr,sys-mgr regmap!\n", 
__func__);
+   return -EINVAL;
+   }
+
+   for (i = 0; i < 2; i++) {
+   switch (socfpgaclk->clk_phase[i]) {
+   case 0:
+   clk_phase[i] = 0;
+   break;
+   case 45:
+   clk_phase[i] = 1;
+   break;
+   case 90:
+   clk_phase[i] = 2;
+   break;
+   case 135:
+   clk_phase[i] = 3;
+   break;
+   case 180:
+   clk_phase[i] = 4;
+   break;
+   case 225:
+   clk_phase[i] = 5;
+   break;
+   case 270:
+   clk_phase[i] = 6;
+   break;
+   case 315:
+   clk_phase[i] = 7;
+   break;
+   default:
+   clk_phase[i] = 0;
+   break;
+   }
+   }
+
+   hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
+   regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
+hs_timing);
+   }
+   return 0;
+}
+
+static struct clk_o

[PATCHv3 4/4] Documentation: DT bindings: document the clocks for Arria10

[dinguyen]

From: Dinh Nguyen 

Update the bindings document for the clocks on the SoCFPGA Arria10 platform.
Also fix up a spelling error for the "altr,socfpga-perip-clk".

Signed-off-by: Dinh Nguyen 
---
 .../devicetree/bindings/clock/altr_socfpga.txt  | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt 
b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index f72e80e..317e9cc 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -7,11 +7,15 @@ This binding uses the common clock binding[1].
 Required properties:
 - compatible : shall be one of the following:
"altr,socfpga-pll-clock" - for a PLL clock
-   "altr,socfpga-perip-clock" - The peripheral clock divided from the
+   "altr,socfpga-perip-clk" - The peripheral clock divided from the
PLL clock.
"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
can get gated.
-
+   "altr,socfpga-a10-pll-clock" - for a PLL clock on the Arria10.
+   "altr,socfpga-a10-perip-clk" - The peripheral clock divided from the
+   PLL clock on the Arria10.
+   "altr,socfpga-a10-gate-clk" - Clocks that directly feed peripherals and
+   can be gated.
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the 
clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
@@ -19,10 +23,11 @@ Required properties:
 
 Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
-- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
-and the bit index.
-- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
-   the divider register, bit shift, and width.
+- clk-gate : For "socfpga-gate-clk" and "altr,socfpga-a10-gate-clk", clk-gate
+   contains the gating register and the bit index.
+- div-reg : For "socfpga-gate-clk", "socfpga-perip-clk",
+   "altr,socfpga-a10-gate-clk", and "altr,socfpga-a10-perip-clk", div-reg
+   contains the divider register, bit shift, and width.
 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that 
controls
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the 
second
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the 
correct
-- 
2.2.1

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[PATCHv3 0/4] clk: socfpga: Add clock driver for Arria10

[dinguyen]

From: Dinh Nguyen 

Hi,

This patch series add the clock driver for the Arria10 platform. Although the
Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the
differences are enough to warrant it's own driver, rather than polluting the
existing driver with platform lookups.

v3:
- Fix sparse warning of assigning an integer 0 instead of NULL to a pointer.

v2:
- Update the DTS bindings doucment to have the new Arria10 clocks.
- Add an l4_sys_free_clk node. The l4_sys_free_clk is similar to the
  l4_sp_clk, but cannot be gated.

*** BLURB HERE ***

Dinh Nguyen (4):
  clk: socfpga: update clk.h so for Arria10 platform to use
  clk: socfpga: add a clock driver for the Arria 10 platform
  ARM: socfpga: dts: add clocks to the Arria10 platform
  Documentation: DT bindings: document the clocks for Arria10

 .../devicetree/bindings/clock/altr_socfpga.txt |  17 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi | 309 -
 drivers/clk/socfpga/Makefile   |   1 +
 drivers/clk/socfpga/clk-gate-a10.c | 187 +
 drivers/clk/socfpga/clk-gate.c |   4 -
 drivers/clk/socfpga/clk-periph-a10.c   | 131 +
 drivers/clk/socfpga/clk-pll-a10.c  | 132 +
 drivers/clk/socfpga/clk.c  |   7 +-
 drivers/clk/socfpga/clk.h  |  10 +-
 9 files changed, 782 insertions(+), 16 deletions(-)
 create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-a10.c

-- 
2.2.1

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[PATCHv3 3/4] ARM: socfpga: dts: add clocks to the Arria10 platform

[dinguyen]

From: Dinh Nguyen 

Add all the clock nodes for the Arria10 platform. At the same time, update
the peripherals with their respective clocks property.

Signed-off-by: Dinh Nguyen 
---
v2: Add the l4_sys_free_clk node
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 309 -
 1 file changed, 305 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 6c3ad92..ef2c946 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -86,6 +86,21 @@
#address-cells = <1>;
#size-cells = <0>;
 
+   cb_intosc_hs_div2_clk: 
cb_intosc_hs_div2_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
+   cb_intosc_ls_clk: cb_intosc_ls_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
+   f2s_free_clk: f2s_free_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -95,16 +110,286 @@
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
-   compatible = 
"altr,socfpga-pll-clock";
-   clocks = <&osc1>;
+   compatible = 
"altr,socfpga-a10-pll-clock";
+   clocks = <&osc1>, 
<&cb_intosc_ls_clk>,
+<&f2s_free_clk>;
+   reg = <0x40>;
+
+   main_mpu_base_clk: 
main_mpu_base_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   div-reg = <0x140 0 11>;
+   };
+
+   main_noc_base_clk: 
main_noc_base_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   div-reg = <0x144 0 11>;
+   };
+
+   main_emaca_clk: main_emaca_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x68>;
+   };
+
+   main_emacb_clk: main_emacb_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x6C>;
+   };
+
+   main_emac_ptp_clk: 
main_emac_ptp_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x70>;
+   };
+
+   main_gpio_db_clk: 
main_gpio_db_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+

[PATCH] dmaengine: pl300: enable the clock to PL330 dma

[dinguyen]

From: Dinh Nguyen 

Turn on the clock to the PL330 DMA if there is a clock node provided.

Signed-off-by: Dinh Nguyen 
---
 drivers/dma/pl330.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 0e1f567..82eb641 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2894,6 +2894,10 @@ pl330_probe(struct amba_device *adev, const struct 
amba_id *id)
 
adev->dev.dma_parms = &pl330->dma_parms;
 
+   adev->pclk = devm_clk_get(&adev->dev, "apb_pclk");
+   if (adev->pclk)
+   clk_prepare_enable(adev->pclk);
+
/*
 * This is the limit for transfers with a buswidth of 1, larger
 * buswidths will have larger limits.
-- 
2.2.1

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[PATCHv2 4/4] Documentation: DT bindings: document the clocks for Arria10

[dinguyen]

From: Dinh Nguyen 

Update the bindings document for the clocks on the SoCFPGA Arria10 platform.
Also fix up a spelling error for the "altr,socfpga-perip-clk".

Signed-off-by: Dinh Nguyen 
---
 .../devicetree/bindings/clock/altr_socfpga.txt  | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt 
b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index f72e80e..317e9cc 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -7,11 +7,15 @@ This binding uses the common clock binding[1].
 Required properties:
 - compatible : shall be one of the following:
"altr,socfpga-pll-clock" - for a PLL clock
-   "altr,socfpga-perip-clock" - The peripheral clock divided from the
+   "altr,socfpga-perip-clk" - The peripheral clock divided from the
PLL clock.
"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
can get gated.
-
+   "altr,socfpga-a10-pll-clock" - for a PLL clock on the Arria10.
+   "altr,socfpga-a10-perip-clk" - The peripheral clock divided from the
+   PLL clock on the Arria10.
+   "altr,socfpga-a10-gate-clk" - Clocks that directly feed peripherals and
+   can be gated.
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the 
clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
@@ -19,10 +23,11 @@ Required properties:
 
 Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
-- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
-and the bit index.
-- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
-   the divider register, bit shift, and width.
+- clk-gate : For "socfpga-gate-clk" and "altr,socfpga-a10-gate-clk", clk-gate
+   contains the gating register and the bit index.
+- div-reg : For "socfpga-gate-clk", "socfpga-perip-clk",
+   "altr,socfpga-a10-gate-clk", and "altr,socfpga-a10-perip-clk", div-reg
+   contains the divider register, bit shift, and width.
 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that 
controls
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the 
second
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the 
correct
-- 
2.2.1

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[PATCHv2 1/4] clk: socfpga: update clk.h so for Arria10 platform to use

[dinguyen]

From: Dinh Nguyen 

There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define
SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver
can use.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/clk-gate.c | 4 
 drivers/clk/socfpga/clk.h  | 6 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index dd3a78c..607ab35 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -32,14 +32,10 @@
 #define SOCFPGA_MMC_CLK"sdmmc_clk"
 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
 
-#define streq(a, b) (strcmp((a), (b)) == 0)
-
 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
 /* SDMMC Group for System Manager defines */
 #define SYSMGR_SDMMCGRP_CTRL_OFFSET0x108
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
-   smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
 
 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d291f60..b09a5d5 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -26,9 +26,13 @@
 #define CLKMGR_L4SRC   0x70
 #define CLKMGR_PERPLL_SRC  0xAC
 
-#define SOCFPGA_MAX_PARENTS3
+#define SOCFPGA_MAX_PARENTS5
 #define div_mask(width) ((1 << (width)) - 1)
 
+#define streq(a, b) (strcmp((a), (b)) == 0)
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+   smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
 extern void __iomem *clk_mgr_base_addr;
 
 void __init socfpga_pll_init(struct device_node *node);
-- 
2.2.1

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[PATCHv2 2/4] clk: socfpga: add a clock driver for the Arria 10 platform

[dinguyen]

From: Dinh Nguyen 

The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5
platform that it should just have it's own driver.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/Makefile |   1 +
 drivers/clk/socfpga/clk-gate-a10.c   | 187 +++
 drivers/clk/socfpga/clk-periph-a10.c | 131 
 drivers/clk/socfpga/clk-pll-a10.c| 132 +
 drivers/clk/socfpga/clk.c|   7 +-
 drivers/clk/socfpga/clk.h|   4 +
 6 files changed, 461 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-a10.c

diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 7e2d15a..d8bb239 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -2,3 +2,4 @@ obj-y += clk.o
 obj-y += clk-gate.o
 obj-y += clk-pll.o
 obj-y += clk-periph.o
+obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
new file mode 100644
index 000..7329657
--- /dev/null
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define streq(a, b) (strcmp((a), (b)) == 0)
+
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
+
+/* SDMMC Group for System Manager defines */
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET0x28
+
+static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
+   unsigned long parent_rate)
+{
+   struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+   u32 div = 1, val;
+
+   if (socfpgaclk->fixed_div)
+   div = socfpgaclk->fixed_div;
+   else if (socfpgaclk->div_reg) {
+   val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+   val &= div_mask(socfpgaclk->width);
+   div = (1 << val);
+   }
+
+   return parent_rate / div;
+}
+
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
+{
+   struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+   struct regmap *sys_mgr_base_addr;
+   int i;
+   u32 hs_timing;
+   u32 clk_phase[2];
+
+   if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
+   sys_mgr_base_addr = 
syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+   if (IS_ERR(sys_mgr_base_addr)) {
+   pr_err("%s: failed to find altr,sys-mgr regmap!\n", 
__func__);
+   return -EINVAL;
+   }
+
+   for (i = 0; i < 2; i++) {
+   switch (socfpgaclk->clk_phase[i]) {
+   case 0:
+   clk_phase[i] = 0;
+   break;
+   case 45:
+   clk_phase[i] = 1;
+   break;
+   case 90:
+   clk_phase[i] = 2;
+   break;
+   case 135:
+   clk_phase[i] = 3;
+   break;
+   case 180:
+   clk_phase[i] = 4;
+   break;
+   case 225:
+   clk_phase[i] = 5;
+   break;
+   case 270:
+   clk_phase[i] = 6;
+   break;
+   case 315:
+   clk_phase[i] = 7;
+   break;
+   default:
+   clk_phase[i] = 0;
+   break;
+   }
+   }
+
+   hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
+   regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
+hs_timing);
+   }
+   return 0;
+}
+
+static struct clk_ops gateclk_ops = {
+   .prepare = socfpga_clk_prepare,
+   .r

[PATCHv2 3/4] ARM: socfpga: dts: add clocks to the Arria10 platform

[dinguyen]

From: Dinh Nguyen 

Add all the clock nodes for the Arria10 platform. At the same time, update
the peripherals with their respective clocks property.

Signed-off-by: Dinh Nguyen 
---
v2: Add the l4_sys_free_clk node
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 309 -
 1 file changed, 305 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 6c3ad92..ef2c946 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -86,6 +86,21 @@
#address-cells = <1>;
#size-cells = <0>;
 
+   cb_intosc_hs_div2_clk: 
cb_intosc_hs_div2_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
+   cb_intosc_ls_clk: cb_intosc_ls_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
+   f2s_free_clk: f2s_free_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -95,16 +110,286 @@
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
-   compatible = 
"altr,socfpga-pll-clock";
-   clocks = <&osc1>;
+   compatible = 
"altr,socfpga-a10-pll-clock";
+   clocks = <&osc1>, 
<&cb_intosc_ls_clk>,
+<&f2s_free_clk>;
+   reg = <0x40>;
+
+   main_mpu_base_clk: 
main_mpu_base_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   div-reg = <0x140 0 11>;
+   };
+
+   main_noc_base_clk: 
main_noc_base_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   div-reg = <0x144 0 11>;
+   };
+
+   main_emaca_clk: main_emaca_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x68>;
+   };
+
+   main_emacb_clk: main_emacb_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x6C>;
+   };
+
+   main_emac_ptp_clk: 
main_emac_ptp_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x70>;
+   };
+
+   main_gpio_db_clk: 
main_gpio_db_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+

[PATCHv2 0/4] clk: socfpga: Add clock driver for Arria10

[dinguyen]

From: Dinh Nguyen 

Hi,

This patch series add the clock driver for the Arria10 platform. Although the
Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the
differences are enough to warrant it's own driver, rather than polluting the
existing driver with platform lookups.

v2:
- Update the DTS bindings doucment to have the new Arria10 clocks.
- Add an l4_sys_free_clk node. The l4_sys_free_clk is similar to the
  l4_sp_clk, but cannot be gated.

Thanks,

Dinh Nguyen (4):
  clk: socfpga: update clk.h so for Arria10 platform to use
  clk: socfpga: add a clock driver for the Arria 10 platform
  ARM: socfpga: dts: add clocks to the Arria10 platform
  Documentation: DT bindings: document the clocks for Arria10

 .../devicetree/bindings/clock/altr_socfpga.txt |  17 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi | 309 -
 drivers/clk/socfpga/Makefile   |   1 +
 drivers/clk/socfpga/clk-gate-a10.c | 187 +
 drivers/clk/socfpga/clk-gate.c |   4 -
 drivers/clk/socfpga/clk-periph-a10.c   | 131 +
 drivers/clk/socfpga/clk-pll-a10.c  | 132 +
 drivers/clk/socfpga/clk.c  |   7 +-
 drivers/clk/socfpga/clk.h  |  10 +-
 9 files changed, 782 insertions(+), 16 deletions(-)
 create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-a10.c

-- 
2.2.1

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[PATCH] MAINTAINERS: socfpga: update the git repo for SoCFPGA

[dinguyen]

From: Dinh Nguyen 

The git tree at rocketboards.org is going away. Update the entry to reflect
the address of the new location. Also add an entry for all the socfpga_*
dts files.

Signed-off-by: Dinh Nguyen 
---
 MAINTAINERS | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index db335f9..b939fc9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1447,9 +1447,10 @@ ARM/SOCFPGA ARCHITECTURE
 M: Dinh Nguyen 
 S: Maintained
 F: arch/arm/mach-socfpga/
+F: arch/arm/boot/dts/socfpga*
+F: arch/arm/configs/socfpga_defconfig
 W: http://www.rocketboards.org
-T: git://git.rocketboards.org/linux-socfpga.git
-T: git://git.rocketboards.org/linux-socfpga-next.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
 
 ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
 M: Dinh Nguyen 
-- 
2.2.1

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[PATCHv2 2/4] ARM: socfpga: disable the sdmmc, and uart nodes in the base arria10

[dinguyen]

From: Dinh Nguyen 

Add status = "disabled" in the base DTSI for Arria10.  The SDMMC and uart
nodes should be enabled in the appropriate board file.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 69d616a..d843609 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -268,6 +268,7 @@
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
+   status = "disabled";
};
 
ocram: sram@ffe0 {
@@ -324,6 +325,7 @@
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+   status = "disabled";
};
 
uart1: serial1@ffc02100 {
@@ -332,6 +334,7 @@
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+   status = "disabled";
};
 
usbphy0: usbphy@0 {
-- 
2.2.1

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[PATCHv2 4/4] ARM: socfpga: rename socdk board file to socdk_sdmmc

[dinguyen]

From: Dinh Nguyen 

Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc
as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus
we will need to have 2 separate board files, one for SDMMC and one for
QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi
so that we use common peripherals for each flavor of the devkits.

Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/Makefile|  2 +-
 arch/arm/boot/dts/socfpga_arria10_socdk.dts   | 48 ---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi  | 46 ++
 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 26 
 4 files changed, 73 insertions(+), 49 deletions(-)
 delete mode 100755 arch/arm/boot/dts/socfpga_arria10_socdk.dts
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b..e50441a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -485,7 +485,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7794-alt.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
-   socfpga_arria10_socdk.dtb \
+   socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts 
b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
deleted file mode 100755
index 811a61c..000
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dts
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2014 Altera Corporation 
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see .
- */
-
-/dts-v1/;
-#include "socfpga_arria10.dtsi"
-
-/ {
-   model = "Altera SOCFPGA Arria 10";
-   compatible = "altr,socfpga-arria10", "altr,socfpga";
-
-   chosen {
-   bootargs = "console=ttyS0,115200 rootwait";
-   };
-
-   memory {
-   name = "memory";
-   device_type = "memory";
-   reg = <0x0 0x4000>; /* 1GB */
-   };
-
-   soc {
-   clkmgr@ffd04000 {
-   clocks {
-   osc1 {
-   clock-frequency = <2500>;
-   };
-   };
-   };
-   };
-};
-
-&uart1 {
-   status = "okay";
-};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi 
b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
new file mode 100644
index 000..347ca4e
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+#include "socfpga_arria10.dtsi"
+
+/ {
+   model = "Altera SOCFPGA Arria 10";
+   compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+   chosen {
+   bootargs = "console=ttyS0,115200 rootwait";
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   soc {
+   clkmgr@ffd04000 {
+   clocks {
+   osc1 {
+   clock-frequency = <2500>;
+   };
+   };
+   };
+   };
+};
+
+&uart1 {
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts 
b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
new file mode 10

[PATCHv2 1/4] ARM: socfpga: add cpu1-start-addr for Arria 10

[dinguyen]

From: Dinh Nguyen 

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 8a05c47..69d616a 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -284,6 +284,7 @@
sysmgr: sysmgr@ffd06000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd06000 0x300>;
+   cpu1-start-addr = <0xffd06230>;
};
 
/* Local timer */
-- 
2.2.1

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[PATCHv2 3/4] ARM: socfpga: dts: enable UART1 for the debug uart

[dinguyen]

From: Dinh Nguyen 

Arria10 devkit is using UART1 for the debug uart port. Remove
unused aliases.

Signed-off-by: Dinh Nguyen 
---
v2: Add removal of unused aliases
---
 arch/arm/boot/dts/socfpga_arria10.dtsi  | 12 
 arch/arm/boot/dts/socfpga_arria10_socdk.dts |  8 
 2 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index d843609..6c3ad92 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -21,18 +21,6 @@
#address-cells = <1>;
#size-cells = <1>;
 
-   aliases {
-   ethernet0 = &gmac0;
-   ethernet1 = &gmac1;
-   ethernet2 = &gmac2;
-   serial0 = &uart0;
-   serial1 = &uart1;
-   timer0 = &timer0;
-   timer1 = &timer1;
-   timer2 = &timer2;
-   timer3 = &timer3;
-   };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts 
b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
index 3015ce8..811a61c 100755
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
@@ -40,9 +40,9 @@
};
};
};
-
-   serial0@ffc02000 {
-   status = "okay";
-   };
};
 };
+
+&uart1 {
+   status = "okay";
+};
-- 
2.2.1

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[PATCHv2 0/4] Add support for Arria10 devkit

[dinguyen]

From: Dinh Nguyen 

Hi,

This patchset enables and tidy up support for the Arria10 devkit. Along with
this patchset and the patchset for enabling clocks on the Arria10, the devkit
can boot Linux.

V2:
- Patch "ARM: socfpga: dts: enable UART1 for the debug uart" adds the removal
  of unused aliases in the dts file.

- Split out the "Documentation: DT bindings: add doc for Altera's SoCFPGA
  platform" patch.

- Split out the 2 patches for early printk uart.

Thanks,

Dinh Nguyen (4):
  ARM: socfpga: add cpu1-start-addr for Arria 10
  ARM: socfpga: disable the sdmmc, and uart nodes in the base arria10
  ARM: socfpga: dts: enable UART1 for the debug uart
  ARM: socfpga: rename socdk board file to socdk_sdmmc

 arch/arm/boot/dts/Makefile|  2 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi| 16 ++--
 arch/arm/boot/dts/socfpga_arria10_socdk.dts   | 48 ---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi  | 46 ++
 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 26 
 5 files changed, 77 insertions(+), 61 deletions(-)
 delete mode 100755 arch/arm/boot/dts/socfpga_arria10_socdk.dts
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts

-- 
2.2.1

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[PATCH RESEND 1/2] ARM: socfpga: Add support for UART1 debug uart for earlyprintk

[dinguyen]

From: Dinh Nguyen 

Add support for hardware uart1 for earlyprintk support on Arria10 devkit.

Signed-off-by: Dinh Nguyen 
CC: Russell King 
---
 arch/arm/Kconfig.debug | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 970de75..0e52b92 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -920,13 +920,22 @@ choice
  on SA-11x0 UART ports. The kernel will check for the first
  enabled UART in a sequence 3-1-2.
 
-   config DEBUG_SOCFPGA_UART
+   config DEBUG_SOCFPGA_UART0
depends on ARCH_SOCFPGA
-   bool "Use SOCFPGA UART for low-level debug"
+   bool "Use SOCFPGA UART0 for low-level debug"
select DEBUG_UART_8250
help
  Say Y here if you want kernel low-level debugging support
- on SOCFPGA based platforms.
+ on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
+
+   config DEBUG_SOCFPGA_UART1
+   depends on ARCH_SOCFPGA
+   bool "Use SOCFPGA UART1 for low-level debug"
+   select DEBUG_UART_8250
+   help
+ Say Y here if you want kernel low-level debugging support
+ on SOCFPGA(Arria 10) based platforms.
+
 
config DEBUG_SUN9I_UART0
bool "Kernel low-level debugging messages via sun9i UART0"
@@ -1419,7 +1428,8 @@ config DEBUG_UART_PHYS
default 0xfcb0 if DEBUG_HI3620_UART
default 0xfe80 if ARCH_IOP32X
default 0xff69 if DEBUG_RK32_UART2
-   default 0xffc02000 if DEBUG_SOCFPGA_UART
+   default 0xffc02000 if DEBUG_SOCFPGA_UART0
+   default 0xffc02100 if DEBUG_SOCFPGA_UART1
default 0xffd82340 if ARCH_IOP13XX
default 0xffe4 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
@@ -1497,7 +1507,8 @@ config DEBUG_UART_VIRT
default 0xfeb26000 if DEBUG_RK3X_UART1
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
-   default 0xfec02000 if DEBUG_SOCFPGA_UART
+   default 0xfec02000 if DEBUG_SOCFPGA_UART0
+   default 0xfec02100 if DEBUG_SOCFPGA_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec1 if DEBUG_SIRFATLAS7_UART0
@@ -1542,8 +1553,8 @@ config DEBUG_UART_8250_WORD
bool "Use 32-bit accesses for 8250 UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
depends on DEBUG_UART_8250_SHIFT >= 2
-   default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
-   ARCH_KEYSTONE || \
+   default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART0 || \
+   DEBUG_SOCFPGA_UART1 || ARCH_KEYSTONE || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || \
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \
-- 
2.2.1

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[PATCH RESEND 2/2] ARM: socfpga: remove the need to map uart_io_desc

[dinguyen]

From: Dinh Nguyen 

All the necessary debug uart mapping is already being done in
debug_ll_io_init, there's no need for it here.

Signed-off-by: Dinh Nguyen 
Cc: Russell King 
---
 arch/arm/mach-socfpga/socfpga.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index f5e597c..358f2c7 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -39,13 +39,6 @@ static struct map_desc scu_io_desc __initdata = {
.type   = MT_DEVICE,
 };
 
-static struct map_desc uart_io_desc __initdata = {
-   .virtual= 0xfec02000,
-   .pfn= __phys_to_pfn(0xffc02000),
-   .length = SZ_8K,
-   .type   = MT_DEVICE,
-};
-
 static void __init socfpga_scu_map_io(void)
 {
unsigned long base;
@@ -60,8 +53,6 @@ static void __init socfpga_scu_map_io(void)
 static void __init socfpga_map_io(void)
 {
socfpga_scu_map_io();
-   iotable_init(&uart_io_desc, 1);
-   early_printk("Early printk initialized\n");
 }
 
 void __init socfpga_sysmgr_init(void)
-- 
2.2.1

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[PATCH RESEND] Documentation: DT bindings: add doc for Altera's SoCFPGA platform

[dinguyen]

From: Dinh Nguyen 

Document "altr,socfpga-cyclone5", "altr,socfpga-arria5", and
"altr,socfpga-arria10".

Signed-off-by: Dinh Nguyen 
---
 Documentation/devicetree/bindings/arm/altera.txt | 14 ++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/altera.txt

diff --git a/Documentation/devicetree/bindings/arm/altera.txt 
b/Documentation/devicetree/bindings/arm/altera.txt
new file mode 100644
index 000..558735a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera.txt
@@ -0,0 +1,14 @@
+Altera's SoCFPGA platform device tree bindings
+-
+
+Boards with Cyclone 5 SoC:
+Required root node properties:
+compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+Boards with Arria 5 SoC:
+Required root node properties:
+compatible = "altr,socfpga-arria5", "altr,socfpga";
+
+Boards with Arria 10 SoC:
+Required root node properties:
+compatible = "altr,socfpga-arria10", "altr,socfpga";
-- 
2.2.1

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[PATCH 3/7] ARM: socfpga: dts: enable UART1 for the debug uart

[dinguyen]

From: Dinh Nguyen 

Arria10 devkit is using UART1 for the debug uart port.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts 
b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
index 3015ce8..addec61 100755
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
@@ -41,7 +41,7 @@
};
};
 
-   serial0@ffc02000 {
+   serial1@ffc02100 {
status = "okay";
};
};
-- 
2.2.1

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[PATCH 0/3] clk: socfpga: Add clock driver for Arria10

[dinguyen]

From: Dinh Nguyen 

Hi,

This patch series add the clock driver for the Arria10 platform. Although the
Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the
differences are enough to warrant it's own driver, rather than polluting the
existing driver with platform lookups.

Dinh Nguyen (3):
  clk: socfpga: update clk.h so for Arria10 platform to use
  clk: socfpga: add a clock driver for the Arria 10 platform
  ARM: socfpga: dts: add clocks to the Arria10 platform

 arch/arm/boot/dts/socfpga_arria10.dtsi | 298 -
 drivers/clk/socfpga/Makefile   |   1 +
 drivers/clk/socfpga/clk-gate-a10.c | 187 +
 drivers/clk/socfpga/clk-gate.c |   4 -
 drivers/clk/socfpga/clk-periph-a10.c   | 131 +++
 drivers/clk/socfpga/clk-pll-a10.c  | 132 +++
 drivers/clk/socfpga/clk.c  |   7 +-
 drivers/clk/socfpga/clk.h  |  10 +-
 8 files changed, 760 insertions(+), 10 deletions(-)
 create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-a10.c

-- 
2.2.1

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[PATCH 0/7] ARM: socfpga: Add support for Arria10 devkit

[dinguyen]

From: Dinh Nguyen 

Hi,

This patchset enables and tidy up support for the Arria10 devkit. Along with
this patchset and the patch for enabling clocks on the Arria10, the devkit
can boot Linux.

Dinh Nguyen (7):
  ARM: socfpga: add cpu1-start-addr for Arria 10
  ARM: socfpga: disable the sdmmc, and uart nodes in the base arria10
  ARM: socfpga: dts: enable UART1 for the debug uart
  ARM: socfpga: rename socdk board file to socdk_sdmmc
  ARM: socfpga: Add support for UART1 debug uart for earlyprintk
  ARM: socfpga: remove the need to map uart_io_desc
  Documentation: DT bindings: add doc for Altera's SoCFPGA platform

 Documentation/devicetree/bindings/arm/altera.txt   | 14 
 arch/arm/Kconfig.debug | 25 +++--
 arch/arm/boot/dts/Makefile |  2 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi |  4 
 ...rria10_socdk.dts => socfpga_arria10_socdk.dtsi} |  6 ++---
 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts  | 26 ++
 arch/arm/mach-socfpga/socfpga.c|  9 
 7 files changed, 65 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/altera.txt
 rename arch/arm/boot/dts/{socfpga_arria10_socdk.dts => 
socfpga_arria10_socdk.dtsi} (92%)
 mode change 100755 => 100644
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts

-- 
2.2.1

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[PATCH 7/7] Documentation: DT bindings: add doc for Altera's SoCFPGA platform

[dinguyen]

From: Dinh Nguyen 

Document "altr,socfpga-cyclone5", "altr,socfpga-arria5", and
"altr,socfpga-arria10".

Signed-off-by: Dinh Nguyen 
---
 Documentation/devicetree/bindings/arm/altera.txt | 14 ++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/altera.txt

diff --git a/Documentation/devicetree/bindings/arm/altera.txt 
b/Documentation/devicetree/bindings/arm/altera.txt
new file mode 100644
index 000..558735a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera.txt
@@ -0,0 +1,14 @@
+Altera's SoCFPGA platform device tree bindings
+-
+
+Boards with Cyclone 5 SoC:
+Required root node properties:
+compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+Boards with Arria 5 SoC:
+Required root node properties:
+compatible = "altr,socfpga-arria5", "altr,socfpga";
+
+Boards with Arria 10 SoC:
+Required root node properties:
+compatible = "altr,socfpga-arria10", "altr,socfpga";
-- 
2.2.1

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[PATCH 2/3] clk: socfpga: add a clock driver for the Arria 10 platform

[dinguyen]

From: Dinh Nguyen 

The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5
platform that it should just have it's own driver.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/Makefile |   1 +
 drivers/clk/socfpga/clk-gate-a10.c   | 187 +++
 drivers/clk/socfpga/clk-periph-a10.c | 131 
 drivers/clk/socfpga/clk-pll-a10.c| 132 +
 drivers/clk/socfpga/clk.c|   7 +-
 drivers/clk/socfpga/clk.h|   4 +
 6 files changed, 461 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
 create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
 create mode 100644 drivers/clk/socfpga/clk-pll-a10.c

diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 7e2d15a..d8bb239 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -2,3 +2,4 @@ obj-y += clk.o
 obj-y += clk-gate.o
 obj-y += clk-pll.o
 obj-y += clk-periph.o
+obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
new file mode 100644
index 000..7329657
--- /dev/null
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define streq(a, b) (strcmp((a), (b)) == 0)
+
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
+
+/* SDMMC Group for System Manager defines */
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET0x28
+
+static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
+   unsigned long parent_rate)
+{
+   struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+   u32 div = 1, val;
+
+   if (socfpgaclk->fixed_div)
+   div = socfpgaclk->fixed_div;
+   else if (socfpgaclk->div_reg) {
+   val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+   val &= div_mask(socfpgaclk->width);
+   div = (1 << val);
+   }
+
+   return parent_rate / div;
+}
+
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
+{
+   struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+   struct regmap *sys_mgr_base_addr;
+   int i;
+   u32 hs_timing;
+   u32 clk_phase[2];
+
+   if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
+   sys_mgr_base_addr = 
syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+   if (IS_ERR(sys_mgr_base_addr)) {
+   pr_err("%s: failed to find altr,sys-mgr regmap!\n", 
__func__);
+   return -EINVAL;
+   }
+
+   for (i = 0; i < 2; i++) {
+   switch (socfpgaclk->clk_phase[i]) {
+   case 0:
+   clk_phase[i] = 0;
+   break;
+   case 45:
+   clk_phase[i] = 1;
+   break;
+   case 90:
+   clk_phase[i] = 2;
+   break;
+   case 135:
+   clk_phase[i] = 3;
+   break;
+   case 180:
+   clk_phase[i] = 4;
+   break;
+   case 225:
+   clk_phase[i] = 5;
+   break;
+   case 270:
+   clk_phase[i] = 6;
+   break;
+   case 315:
+   clk_phase[i] = 7;
+   break;
+   default:
+   clk_phase[i] = 0;
+   break;
+   }
+   }
+
+   hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
+   regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
+hs_timing);
+   }
+   return 0;
+}
+
+static struct clk_ops gateclk_ops = {
+   .prepare = socfpga_clk_prepare,
+   .r

[PATCH 4/7] ARM: socfpga: rename socdk board file to socdk_sdmmc

[dinguyen]

From: Dinh Nguyen 

Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc
as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus
we will need to have 2 separate board files, one for SDMMC and one for
QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi
so that we use common peripherals for each flavor of the devkits.

Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/Makefile |  2 +-
 ...rria10_socdk.dts => socfpga_arria10_socdk.dtsi} |  4 +---
 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts  | 26 ++
 3 files changed, 28 insertions(+), 4 deletions(-)
 rename arch/arm/boot/dts/{socfpga_arria10_socdk.dts => 
socfpga_arria10_socdk.dtsi} (94%)
 mode change 100755 => 100644
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b..e50441a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -485,7 +485,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7794-alt.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
-   socfpga_arria10_socdk.dtb \
+   socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts 
b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
old mode 100755
new mode 100644
similarity index 94%
rename from arch/arm/boot/dts/socfpga_arria10_socdk.dts
rename to arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index addec61..2791f09
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2015 Altera Corporation 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,8 +14,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see .
  */
-
-/dts-v1/;
 #include "socfpga_arria10.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts 
b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
new file mode 100644
index 000..dbbb751
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2014-2015 Altera Corporation 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_socdk.dtsi"
+
+&mmc {
+   status = "okay";
+   num-slots = <1>;
+   broken-cd;
+   bus-width = <4>;
+};
-- 
2.2.1

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[PATCH 1/3] clk: socfpga: update clk.h so for Arria10 platform to use

[dinguyen]

From: Dinh Nguyen 

There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define
SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver
can use.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/clk-gate.c | 4 
 drivers/clk/socfpga/clk.h  | 6 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index dd3a78c..607ab35 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -32,14 +32,10 @@
 #define SOCFPGA_MMC_CLK"sdmmc_clk"
 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
 
-#define streq(a, b) (strcmp((a), (b)) == 0)
-
 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
 /* SDMMC Group for System Manager defines */
 #define SYSMGR_SDMMCGRP_CTRL_OFFSET0x108
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
-   smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
 
 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d291f60..b09a5d5 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -26,9 +26,13 @@
 #define CLKMGR_L4SRC   0x70
 #define CLKMGR_PERPLL_SRC  0xAC
 
-#define SOCFPGA_MAX_PARENTS3
+#define SOCFPGA_MAX_PARENTS5
 #define div_mask(width) ((1 << (width)) - 1)
 
+#define streq(a, b) (strcmp((a), (b)) == 0)
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+   smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
 extern void __iomem *clk_mgr_base_addr;
 
 void __init socfpga_pll_init(struct device_node *node);
-- 
2.2.1

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[PATCH 6/7] ARM: socfpga: remove the need to map uart_io_desc

[dinguyen]

From: Dinh Nguyen 

All the necessary debug uart mapping is already being done in
debug_ll_io_init, there's no need for it here.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/socfpga.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index f5e597c..358f2c7 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -39,13 +39,6 @@ static struct map_desc scu_io_desc __initdata = {
.type   = MT_DEVICE,
 };
 
-static struct map_desc uart_io_desc __initdata = {
-   .virtual= 0xfec02000,
-   .pfn= __phys_to_pfn(0xffc02000),
-   .length = SZ_8K,
-   .type   = MT_DEVICE,
-};
-
 static void __init socfpga_scu_map_io(void)
 {
unsigned long base;
@@ -60,8 +53,6 @@ static void __init socfpga_scu_map_io(void)
 static void __init socfpga_map_io(void)
 {
socfpga_scu_map_io();
-   iotable_init(&uart_io_desc, 1);
-   early_printk("Early printk initialized\n");
 }
 
 void __init socfpga_sysmgr_init(void)
-- 
2.2.1

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[PATCH 3/3] ARM: socfpga: dts: add clocks to the Arria10 platform

[dinguyen]

From: Dinh Nguyen 

Add all the clock nodes for the Arria10 platform. At the same time, update
the peripherals with their respective clocks property.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 298 -
 1 file changed, 294 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 8a05c47..341cb28 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -98,6 +98,21 @@
#address-cells = <1>;
#size-cells = <0>;
 
+   cb_intosc_hs_div2_clk: 
cb_intosc_hs_div2_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
+   cb_intosc_ls_clk: cb_intosc_ls_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
+   f2s_free_clk: f2s_free_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   };
+
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -107,16 +122,279 @@
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
-   compatible = 
"altr,socfpga-pll-clock";
-   clocks = <&osc1>;
+   compatible = 
"altr,socfpga-a10-pll-clock";
+   clocks = <&osc1>, 
<&cb_intosc_ls_clk>,
+<&f2s_free_clk>;
+   reg = <0x40>;
+
+   main_mpu_base_clk: 
main_mpu_base_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   div-reg = <0x140 0 11>;
+   };
+
+   main_noc_base_clk: 
main_noc_base_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   div-reg = <0x144 0 11>;
+   };
+
+   main_emaca_clk: main_emaca_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x68>;
+   };
+
+   main_emacb_clk: main_emacb_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x6C>;
+   };
+
+   main_emac_ptp_clk: 
main_emac_ptp_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+   clocks = <&main_pll>;
+   reg = <0x70>;
+   };
+
+   main_gpio_db_clk: 
main_gpio_db_clk {
+   #clock-cells = <0>;
+   compatible = 
"altr,socfpga-a10-perip-clk";
+

[PATCH 5/7] ARM: socfpga: Add support for UART1 debug uart for earlyprintk

[dinguyen]

From: Dinh Nguyen 

Add support for hardware uart1 for earlyprintk support on Arria10 devkit.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig.debug | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 970de75..0e52b92 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -920,13 +920,22 @@ choice
  on SA-11x0 UART ports. The kernel will check for the first
  enabled UART in a sequence 3-1-2.
 
-   config DEBUG_SOCFPGA_UART
+   config DEBUG_SOCFPGA_UART0
depends on ARCH_SOCFPGA
-   bool "Use SOCFPGA UART for low-level debug"
+   bool "Use SOCFPGA UART0 for low-level debug"
select DEBUG_UART_8250
help
  Say Y here if you want kernel low-level debugging support
- on SOCFPGA based platforms.
+ on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
+
+   config DEBUG_SOCFPGA_UART1
+   depends on ARCH_SOCFPGA
+   bool "Use SOCFPGA UART1 for low-level debug"
+   select DEBUG_UART_8250
+   help
+ Say Y here if you want kernel low-level debugging support
+ on SOCFPGA(Arria 10) based platforms.
+
 
config DEBUG_SUN9I_UART0
bool "Kernel low-level debugging messages via sun9i UART0"
@@ -1419,7 +1428,8 @@ config DEBUG_UART_PHYS
default 0xfcb0 if DEBUG_HI3620_UART
default 0xfe80 if ARCH_IOP32X
default 0xff69 if DEBUG_RK32_UART2
-   default 0xffc02000 if DEBUG_SOCFPGA_UART
+   default 0xffc02000 if DEBUG_SOCFPGA_UART0
+   default 0xffc02100 if DEBUG_SOCFPGA_UART1
default 0xffd82340 if ARCH_IOP13XX
default 0xffe4 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
@@ -1497,7 +1507,8 @@ config DEBUG_UART_VIRT
default 0xfeb26000 if DEBUG_RK3X_UART1
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
-   default 0xfec02000 if DEBUG_SOCFPGA_UART
+   default 0xfec02000 if DEBUG_SOCFPGA_UART0
+   default 0xfec02100 if DEBUG_SOCFPGA_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec1 if DEBUG_SIRFATLAS7_UART0
@@ -1542,8 +1553,8 @@ config DEBUG_UART_8250_WORD
bool "Use 32-bit accesses for 8250 UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
depends on DEBUG_UART_8250_SHIFT >= 2
-   default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
-   ARCH_KEYSTONE || \
+   default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART0 || \
+   DEBUG_SOCFPGA_UART1 || ARCH_KEYSTONE || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || \
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \
-- 
2.2.1

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[PATCH 2/7] ARM: socfpga: disable the sdmmc, and uart nodes in the base arria10

[dinguyen]

From: Dinh Nguyen 

Add status = "disabled" in the base DTSI for Arria10.  The SDMMC and uart
nodes should be enabled in the appropriate board file.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 69d616a..d843609 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -268,6 +268,7 @@
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
+   status = "disabled";
};
 
ocram: sram@ffe0 {
@@ -324,6 +325,7 @@
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+   status = "disabled";
};
 
uart1: serial1@ffc02100 {
@@ -332,6 +334,7 @@
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+   status = "disabled";
};
 
usbphy0: usbphy@0 {
-- 
2.2.1

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[PATCH 1/7] ARM: socfpga: add cpu1-start-addr for Arria 10

[dinguyen]

From: Dinh Nguyen 

Signed-off-by: Dinh Nguyen 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 8a05c47..69d616a 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -284,6 +284,7 @@
sysmgr: sysmgr@ffd06000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd06000 0x300>;
+   cpu1-start-addr = <0xffd06230>;
};
 
/* Local timer */
-- 
2.2.1

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[PATCHv2 net-next] net: stmmac: make reset control an optional requirement

[dinguyen]

From: Dinh Nguyen 

Not having a reset control line to the ethernet controller should not be a
hard failure. Instead, add support for deferred probing and just print out
a debug statement.

Signed-off-by: Dinh Nguyen 
Cc: Vince Bridgers 
CC: David S. Miller 
---
v2: return EPROBE_DEFER directly as 'ret' is not used as return variable
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 3aad413..9987b34 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -89,7 +89,9 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac 
*dwmac, struct device *
  STMMAC_RESOURCE_NAME);
if (IS_ERR(dwmac->stmmac_rst)) {
dev_info(dev, "Could not get reset control!\n");
-   return -EINVAL;
+   if (PTR_ERR(dwmac->stmmac_rst) == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   dwmac->stmmac_rst = NULL;
}
 
dwmac->interface = of_get_phy_mode(np);
-- 
2.2.1

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[PATCH] net: stmmac: make reset control an optional requirement

[dinguyen]

From: Dinh Nguyen 

Not having a reset control line to the ethernet controller should not be a
hard failure. Instead, add support for deferred probing and just print out
a debug statement.

Signed-off-by: Dinh Nguyen 
Cc: Vince Bridgers 
CC: David S. Miller 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index e97074c..ecb0b9b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -91,7 +91,9 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac 
*dwmac, struct device *
  STMMAC_RESOURCE_NAME);
if (IS_ERR(dwmac->stmmac_rst)) {
dev_info(dev, "Could not get reset control!\n");
-   return -EINVAL;
+   if (PTR_ERR(dwmac->stmmac_rst) == -EPROBE_DEFER)
+   ret = -EPROBE_DEFER;
+   dwmac->stmmac_rst = NULL;
}
 
dwmac->interface = of_get_phy_mode(np);
-- 
2.2.1

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[RESEND PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

[dinguyen]

From: Dinh Nguyen 

By not having bit 22 set in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/socfpga.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index a5f1fda..4ce2100 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -105,7 +105,8 @@ static const char *altera_dt_match[] = {
 
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
.l2c_aux_val= L310_AUX_CTRL_DATA_PREFETCH |
- L310_AUX_CTRL_INSTR_PREFETCH,
+ L310_AUX_CTRL_INSTR_PREFETCH |
+ L2C_AUX_CTRL_SHARED_OVERRIDE,
.l2c_aux_mask   = ~0,
.smp= smp_ops(socfpga_smp_ops),
.map_io = socfpga_map_io,
-- 
2.2.1

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[RESEND PATCH 1/2] arm: socfpga: update l2 cache settings

[dinguyen]

From: Dinh Nguyen 

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/socfpga.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 383d61e..a5f1fda 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -104,7 +104,8 @@ static const char *altera_dt_match[] = {
 };
 
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
-   .l2c_aux_val= 0,
+   .l2c_aux_val= L310_AUX_CTRL_DATA_PREFETCH |
+ L310_AUX_CTRL_INSTR_PREFETCH,
.l2c_aux_mask   = ~0,
.smp= smp_ops(socfpga_smp_ops),
.map_io = socfpga_map_io,
-- 
2.2.1

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[RFC PATCH] arm: cti: fix up cti pmu build

[dinguyen]

From: Dinh Nguyen 

commit "184901a06a36 ARM: removing support for etb/etm in "arch/arm/kernel/"
removed arch/arm/include/asm/hardware/coresight.h

then

commit "a06ae8609b3d coresight: add CoreSight core layer framework" added
include/linux/coresight.h

Update cti.h to use thew new coresight.h and replace CS_LAR_KEY with
CORESIGHT_UNLOCK.

Signed-off-by: Dinh Nguyen 
Cc: Pratik Patel 
Cc: Mathieu Poirier 
Cc: Greg Kroah-Hartman 
Cc: Will Deacon 
---
 arch/arm/include/asm/cti.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
index 2381199..044fda8 100644
--- a/arch/arm/include/asm/cti.h
+++ b/arch/arm/include/asm/cti.h
@@ -2,7 +2,7 @@
 #define __ASMARM_CTI_H
 
 #include   
-#include   
+#include   
 
 /* The registers' definition is from section 3.2 of
  * Embedded Cross Trigger Revision: r0p0
@@ -142,7 +142,7 @@ static inline void cti_irq_ack(struct cti *cti)
  */
 static inline void cti_unlock(struct cti *cti)
 {
-   __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
+   __raw_writel(CORESIGHT_UNLOCK, cti->base + LOCKACCESS);
 }
 
 /**
@@ -154,6 +154,6 @@ static inline void cti_unlock(struct cti *cti)
  */
 static inline void cti_lock(struct cti *cti)
 {
-   __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
+   __raw_writel(~CORESIGHT_UNLOCK, cti->base + LOCKACCESS);
 }
 #endif
-- 
2.2.1

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[RFC PATCH] arm: cti: fix build for cti.h

[dinguyen]

From: Dinh Nguyen 

Hi,

I would to like check to see if this is right thing to do for cti.h. Our
downstream kernel's PMU support is using cti.h. But I don't see any other
upstream driver using cti.h, so I'm not sure if this file should be removed?

Thanks,

Dinh Nguyen (1):
  arm: cti: fix up cti pmu build

 arch/arm/include/asm/cti.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

-- 
Cc: Pratik Patel 
Cc: Mathieu Poirier 
Cc: Greg Kroah-Hartman 
Cc: Will Deacon 
--
2.2.1

--
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[PATCH] mtd: denali: Disable sub-page writes in Denali NAND driver

[dinguyen]

From: Graham Moore 

The Denali Controller IP does not support sub-page writes.

Signed-off-by: Graham Moore 
Signed-off-by: Dinh Nguyen 
---
 drivers/mtd/nand/denali.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index b3b7ca1..b16b040 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -1565,6 +1565,9 @@ int denali_init(struct denali_nand_info *denali)
denali->nand.options |= NAND_SKIP_BBTSCAN;
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
 
+   /* no subpage writes on denali */
+   denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
+
/*
 * Denali Controller only support 15bit and 8bit ECC in MRST,
 * so just let controller do 15bit ECC for MLC and 8bit ECC for
-- 
2.2.1

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[PATCH] mtd: denali: fix incorrect bitmask error in denali_setup_dma

[dinguyen]

From: Graham Moore 

commit "3157d1ed2309 mtd: denali: remove unnecessary casts" introduced
an error by using a wrong bitmask.

A uint16_t cast was replaced with & 0xff, should be & 0x.

Signed-off-by: Graham Moore 
Signed-off-by: Dinh Nguyen 
---
 drivers/mtd/nand/denali.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index b3b7ca1..5e397fb 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -1041,7 +1041,7 @@ static void denali_setup_dma(struct denali_nand_info 
*denali, int op)
index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
 
/* 3. set memory low address bits 23:8 */
-   index_addr(denali, mode | ((addr & 0xff) << 8), 0x2300);
+   index_addr(denali, mode | ((addr & 0x) << 8), 0x2300);
 
/* 4. interrupt when complete, burst len = 64 bytes */
index_addr(denali, mode | 0x14000, 0x2400);
-- 
1.7.9.5

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[PATCH] stmmac: platform: fix stmmac probe failure

[dinguyen]

From: Dinh Nguyen 

The commit 571dcfde23712b ("stmmac: platform: fix default values of the filter
bins setting") broke support for stmmac probe for all CONFIG_OF platforms.

[0.743567] Unable to handle kernel NULL pointer dereference at virtual 
address 0048
[0.751679] pgd = c0004000
[0.754384] [0048] *pgd=
[0.757983] Internal error: Oops: 805 [#1] SMP ARM
[0.762774] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.18.0-rc7 #1
[0.769034] task: ee86c000 ti: ee87 task.ti: ee87
[0.774429] PC is at stmmac_pltfr_probe+0x40/0x5d0
[0.779217] LR is at devm_ioremap_nocache+0x54/0x74
...
[0.951644] [] (stmmac_pltfr_probe) from [] 
(platform_drv_probe+0x44/0xa4)
[0.960250] [] (platform_drv_probe) from [] 
(driver_probe_device+0x10c/0x240)
[0.969113] [] (driver_probe_device) from [] 
(__driver_attach+0x8c/0x90)
[0.977544] [] (__driver_attach) from [] 
(bus_for_each_dev+0x6c/0xa0)

The reason is that in stmmac_pltfr_probe(), the plat_dat on a CONFIG_OF
platform is NULL until devm_kzalloc() is called to allocate plat_dat.

Signed-off-by: Dinh Nguyen 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 5b0da39..62c9e75 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -265,12 +265,6 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
 
plat_dat = dev_get_platdata(&pdev->dev);
 
-   /* Set default value for multicast hash bins */
-   plat_dat->multicast_filter_bins = HASH_TABLE_SIZE;
-
-   /* Set default value for unicast filter entries */
-   plat_dat->unicast_filter_entries = 1;
-
if (pdev->dev.of_node) {
if (!plat_dat)
plat_dat = devm_kzalloc(&pdev->dev,
@@ -288,6 +282,12 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
}
}
 
+   /* Set default value for multicast hash bins */
+   plat_dat->multicast_filter_bins = HASH_TABLE_SIZE;
+
+   /* Set default value for unicast filter entries */
+   plat_dat->unicast_filter_entries = 1;
+
/* Custom setup (if needed) */
if (plat_dat->setup) {
plat_dat->bsp_priv = plat_dat->setup(pdev);
-- 
2.0.3

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[PATCH] usb: dwc2: remove early return on clock query

[dinguyen]

From: Dinh Nguyen 

Since we have assigned clk=NULL, which is a valid clk, we should not
be returning when a clock node is not provide. Instead, we should return
only when we cannot enable the clock.

Signed-off-by: Dinh Nguyen 
---
 drivers/usb/dwc2/gadget.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 05b0522..407f55c 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3451,8 +3451,7 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
hsotg->clk = devm_clk_get(dev, "otg");
if (IS_ERR(hsotg->clk)) {
hsotg->clk = NULL;
-   dev_err(dev, "cannot get otg clock\n");
-   return PTR_ERR(hsotg->clk);
+   dev_dbg(dev, "cannot get otg clock\n");
}
 
hsotg->gadget.max_speed = USB_SPEED_HIGH;
@@ -3461,7 +3460,12 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
 
/* reset the system */
 
-   clk_prepare_enable(hsotg->clk);
+   ret = clk_prepare_enable(hsotg->clk);
+   if (ret) {
+   dev_err(dev, "failed to enable otg clk\n");
+   goto err_clk;
+   }
+
 
/* regulators */
 
-- 
2.0.3

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[PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

[dinguyen]

From: Dinh Nguyen 

By not having bit 22 set in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/socfpga.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 13b1858..afc009f 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -105,7 +105,8 @@ static const char *altera_dt_match[] = {
 
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
.l2c_aux_val= L310_AUX_CTRL_DATA_PREFETCH |
- L310_AUX_CTRL_INSTR_PREFETCH,
+ L310_AUX_CTRL_INSTR_PREFETCH |
+ L2C_AUX_CTRL_SHARED_OVERRIDE,
.l2c_aux_mask   = ~0,
.smp= smp_ops(socfpga_smp_ops),
.map_io = socfpga_map_io,
-- 
2.0.3

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[PATCH 1/2] arm: socfpga: update l2 cache settings

[dinguyen]

From: Dinh Nguyen 

Enable D and I prefetch helps improve SDRAM preformance.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/socfpga.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf383..13b1858 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -104,7 +104,8 @@ static const char *altera_dt_match[] = {
 };
 
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
-   .l2c_aux_val= 0,
+   .l2c_aux_val= L310_AUX_CTRL_DATA_PREFETCH |
+ L310_AUX_CTRL_INSTR_PREFETCH,
.l2c_aux_mask   = ~0,
.smp= smp_ops(socfpga_smp_ops),
.map_io = socfpga_map_io,
-- 
2.0.3

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