[PATCH v3 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu

[Icenowy Zheng]

From: Icenowy Zheng 

Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .

The mux 3 of R_CCU is still the internal oscillator, which is said to be
16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two
H3 boards and one H5 board.

Signed-off-by: Icenowy Zheng 
---
Changes in v3:
- Change osc32000 to iosc.

 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 47 +-
 1 file changed, 16 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 6640ebfa6419..a7e858a82c90 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -41,8 +41,10 @@
  */
 
 #include 
+#include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -68,31 +70,12 @@
clock-output-names = "osc32k";
};
 
-   apb0: apb0_clk {
-   compatible = "fixed-factor-clock";
+   iosc: internal-osc-clk {
#clock-cells = <0>;
-   clock-div = <1>;
-   clock-mult = <1>;
-   clocks = <>;
-   clock-output-names = "apb0";
-   };
-
-   apb0_gates: clk@01f01428 {
-   compatible = "allwinner,sun8i-h3-apb0-gates-clk",
-"allwinner,sun4i-a10-gates-clk";
-   reg = <0x01f01428 0x4>;
-   #clock-cells = <1>;
-   clocks = <>;
-   clock-indices = <0>, <1>;
-   clock-output-names = "apb0_pio", "apb0_ir";
-   };
-
-   ir_clk: ir_clk@01f01454 {
-   compatible = "allwinner,sun4i-a10-mod0-clk";
-   reg = <0x01f01454 0x4>;
-   #clock-cells = <0>;
-   clocks = <>, <>;
-   clock-output-names = "ir";
+   compatible = "fixed-clock";
+   clock-frequency = <1600>;
+   clock-accuracy = <3>;
+   clock-output-names = "iosc";
};
};
 
@@ -576,9 +559,12 @@
 ;
};
 
-   apb0_reset: reset@01f014b0 {
-   reg = <0x01f014b0 0x4>;
-   compatible = "allwinner,sun6i-a31-clock-reset";
+   r_ccu: clock@1f01400 {
+   compatible = "allwinner,sun50i-a64-r-ccu";
+   reg = <0x01f01400 0x100>;
+   clocks = <>, <>, <>;
+   clock-names = "hosc", "losc", "iosc";
+   #clock-cells = <1>;
#reset-cells = <1>;
};
 
@@ -589,9 +575,9 @@
 
ir: ir@01f02000 {
compatible = "allwinner,sun5i-a13-ir";
-   clocks = <_gates 1>, <_clk>;
+   clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
clock-names = "apb", "ir";
-   resets = <_reset 1>;
+   resets = <_ccu RST_APB0_IR>;
interrupts = ;
reg = <0x01f02000 0x40>;
status = "disabled";
@@ -601,9 +587,8 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = ;
-   clocks = <_gates 0>, <>, <>;
+   clocks = <_ccu CLK_APB0_PIO>, <>, <>;
clock-names = "apb", "hosc", "losc";
-   resets = <_reset 0>;
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
-- 
2.12.0

[PATCH v3 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu

[Icenowy Zheng]

From: Icenowy Zheng 

Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .

The mux 3 of R_CCU is still the internal oscillator, which is said to be
16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two
H3 boards and one H5 board.

Signed-off-by: Icenowy Zheng 
---
Changes in v3:
- Change osc32000 to iosc.

 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 47 +-
 1 file changed, 16 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 6640ebfa6419..a7e858a82c90 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -41,8 +41,10 @@
  */
 
 #include 
+#include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -68,31 +70,12 @@
clock-output-names = "osc32k";
};
 
-   apb0: apb0_clk {
-   compatible = "fixed-factor-clock";
+   iosc: internal-osc-clk {
#clock-cells = <0>;
-   clock-div = <1>;
-   clock-mult = <1>;
-   clocks = <>;
-   clock-output-names = "apb0";
-   };
-
-   apb0_gates: clk@01f01428 {
-   compatible = "allwinner,sun8i-h3-apb0-gates-clk",
-"allwinner,sun4i-a10-gates-clk";
-   reg = <0x01f01428 0x4>;
-   #clock-cells = <1>;
-   clocks = <>;
-   clock-indices = <0>, <1>;
-   clock-output-names = "apb0_pio", "apb0_ir";
-   };
-
-   ir_clk: ir_clk@01f01454 {
-   compatible = "allwinner,sun4i-a10-mod0-clk";
-   reg = <0x01f01454 0x4>;
-   #clock-cells = <0>;
-   clocks = <>, <>;
-   clock-output-names = "ir";
+   compatible = "fixed-clock";
+   clock-frequency = <1600>;
+   clock-accuracy = <3>;
+   clock-output-names = "iosc";
};
};
 
@@ -576,9 +559,12 @@
 ;
};
 
-   apb0_reset: reset@01f014b0 {
-   reg = <0x01f014b0 0x4>;
-   compatible = "allwinner,sun6i-a31-clock-reset";
+   r_ccu: clock@1f01400 {
+   compatible = "allwinner,sun50i-a64-r-ccu";
+   reg = <0x01f01400 0x100>;
+   clocks = <>, <>, <>;
+   clock-names = "hosc", "losc", "iosc";
+   #clock-cells = <1>;
#reset-cells = <1>;
};
 
@@ -589,9 +575,9 @@
 
ir: ir@01f02000 {
compatible = "allwinner,sun5i-a13-ir";
-   clocks = <_gates 1>, <_clk>;
+   clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
clock-names = "apb", "ir";
-   resets = <_reset 1>;
+   resets = <_ccu RST_APB0_IR>;
interrupts = ;
reg = <0x01f02000 0x40>;
status = "disabled";
@@ -601,9 +587,8 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = ;
-   clocks = <_gates 0>, <>, <>;
+   clocks = <_ccu CLK_APB0_PIO>, <>, <>;
clock-names = "apb", "hosc", "losc";
-   resets = <_reset 0>;
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
-- 
2.12.0