Re: [PATCH v5 5/9] phy: Move Allwinner A31 D-PHY driver to drivers/phy/
Hi, On Mon, 2019-01-21 at 16:45 +0100, Maxime Ripard wrote: > Now that our MIPI D-PHY driver has been converted to the phy framework, > let's move it into the drivers/phy directory. > > Signed-off-by: Maxime Ripard Reviewed-by: Paul Kocialkowski Cheers, Paul > --- > drivers/gpu/drm/sun4i/Kconfig | 10 +- > drivers/gpu/drm/sun4i/Makefile | 1 +- > drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c | 318 +- > drivers/phy/allwinner/Kconfig | 12 +- > drivers/phy/allwinner/Makefile | 1 +- > drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 318 +- > 6 files changed, 332 insertions(+), 328 deletions(-) > delete mode 100644 drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c > create mode 100644 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c > > diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig > index 2b8db82c4bab..1dbbc3a1b763 100644 > --- a/drivers/gpu/drm/sun4i/Kconfig > +++ b/drivers/gpu/drm/sun4i/Kconfig > @@ -45,20 +45,12 @@ config DRM_SUN6I_DSI > default MACH_SUN8I > select CRC_CCITT > select DRM_MIPI_DSI > - select DRM_SUN6I_DPHY > + select PHY_SUN6I_MIPI_DPHY > help > Choose this option if you want have an Allwinner SoC with > MIPI-DSI support. If M is selected the module will be called > sun6i_mipi_dsi. > > -config DRM_SUN6I_DPHY > - tristate "Allwinner A31 MIPI D-PHY Support" > - select GENERIC_PHY_MIPI_DPHY > - help > - Choose this option if you have an Allwinner SoC with > - MIPI-DSI support. If M is selected, the module will be > - called sun6i_mipi_dphy. > - > config DRM_SUN8I_DW_HDMI > tristate "Support for Allwinner version of DesignWare HDMI" > depends on DRM_SUN4I > diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile > index 1e2320d824b5..0d04f2447b01 100644 > --- a/drivers/gpu/drm/sun4i/Makefile > +++ b/drivers/gpu/drm/sun4i/Makefile > @@ -34,7 +34,6 @@ ifdef CONFIG_DRM_SUN4I_BACKEND > obj-$(CONFIG_DRM_SUN4I) += sun4i-frontend.o > endif > obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o > -obj-$(CONFIG_DRM_SUN6I_DPHY) += sun6i_mipi_dphy.o > obj-$(CONFIG_DRM_SUN6I_DSI) += sun6i_mipi_dsi.o > obj-$(CONFIG_DRM_SUN8I_DW_HDMI) += sun8i-drm-hdmi.o > obj-$(CONFIG_DRM_SUN8I_MIXER)+= sun8i-mixer.o > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c > b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c > deleted file mode 100644 > index 79c8af5c7c1d.. > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c > +++ /dev/null > @@ -1,318 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright (c) 2016 Allwinnertech Co., Ltd. > - * Copyright (C) 2017-2018 Bootlin > - * > - * Maxime Ripard > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > -#include > - > -#include > -#include > - > -#define SUN6I_DPHY_GCTL_REG 0x00 > -#define SUN6I_DPHY_GCTL_LANE_NUM(n) n) - 1) & 3) << 4) > -#define SUN6I_DPHY_GCTL_EN BIT(0) > - > -#define SUN6I_DPHY_TX_CTL_REG0x04 > -#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28) > - > -#define SUN6I_DPHY_TX_TIME0_REG 0x10 > -#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24) > -#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n)(((n) & 0xff) << 16) > -#define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n)((n) & 0xff) > - > -#define SUN6I_DPHY_TX_TIME1_REG 0x14 > -#define SUN6I_DPHY_TX_TIME1_CLK_POST(n) (((n) & 0xff) << 24) > -#define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16) > -#define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n) (((n) & 0xff) << 8) > -#define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) > - > -#define SUN6I_DPHY_TX_TIME2_REG 0x18 > -#define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) > - > -#define SUN6I_DPHY_TX_TIME3_REG 0x1c > - > -#define SUN6I_DPHY_TX_TIME4_REG 0x20 > -#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n)(((n) & 0xff) << 8) > -#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n)((n) & 0xff) > - > -#define SUN6I_DPHY_ANA0_REG 0x4c > -#define SUN6I_DPHY_ANA0_REG_PWS BIT(31) > -#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28) > -#define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24) > -#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12) > -#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8) > - > -#define SUN6I_DPHY_ANA1_REG 0x50 > -#define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31) > -#define SUN6I_DPHY_ANA1_REG_CSMPS(n) (((n) & 3) << 28) > -#define SUN6I_DPHY_ANA1_REG_SVTT(n) (((n) & 0xf) << 24) > - > -#define SUN6I_DPHY_ANA2_REG 0x54 > -#define SUN6I_DPHY_ANA2_EN_P2S_CPU(n)(((n) & 0xf) << 24) > -#define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK
[PATCH v5 5/9] phy: Move Allwinner A31 D-PHY driver to drivers/phy/
Now that our MIPI D-PHY driver has been converted to the phy framework, let's move it into the drivers/phy directory. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/Kconfig | 10 +- drivers/gpu/drm/sun4i/Makefile | 1 +- drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c | 318 +- drivers/phy/allwinner/Kconfig | 12 +- drivers/phy/allwinner/Makefile | 1 +- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 318 +- 6 files changed, 332 insertions(+), 328 deletions(-) delete mode 100644 drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c create mode 100644 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig index 2b8db82c4bab..1dbbc3a1b763 100644 --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -45,20 +45,12 @@ config DRM_SUN6I_DSI default MACH_SUN8I select CRC_CCITT select DRM_MIPI_DSI - select DRM_SUN6I_DPHY + select PHY_SUN6I_MIPI_DPHY help Choose this option if you want have an Allwinner SoC with MIPI-DSI support. If M is selected the module will be called sun6i_mipi_dsi. -config DRM_SUN6I_DPHY - tristate "Allwinner A31 MIPI D-PHY Support" - select GENERIC_PHY_MIPI_DPHY - help - Choose this option if you have an Allwinner SoC with - MIPI-DSI support. If M is selected, the module will be - called sun6i_mipi_dphy. - config DRM_SUN8I_DW_HDMI tristate "Support for Allwinner version of DesignWare HDMI" depends on DRM_SUN4I diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index 1e2320d824b5..0d04f2447b01 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -34,7 +34,6 @@ ifdef CONFIG_DRM_SUN4I_BACKEND obj-$(CONFIG_DRM_SUN4I)+= sun4i-frontend.o endif obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o -obj-$(CONFIG_DRM_SUN6I_DPHY) += sun6i_mipi_dphy.o obj-$(CONFIG_DRM_SUN6I_DSI)+= sun6i_mipi_dsi.o obj-$(CONFIG_DRM_SUN8I_DW_HDMI)+= sun8i-drm-hdmi.o obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c deleted file mode 100644 index 79c8af5c7c1d.. --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c +++ /dev/null @@ -1,318 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2016 Allwinnertech Co., Ltd. - * Copyright (C) 2017-2018 Bootlin - * - * Maxime Ripard - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define SUN6I_DPHY_GCTL_REG0x00 -#define SUN6I_DPHY_GCTL_LANE_NUM(n)n) - 1) & 3) << 4) -#define SUN6I_DPHY_GCTL_EN BIT(0) - -#define SUN6I_DPHY_TX_CTL_REG 0x04 -#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28) - -#define SUN6I_DPHY_TX_TIME0_REG0x10 -#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24) -#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16) -#define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff) - -#define SUN6I_DPHY_TX_TIME1_REG0x14 -#define SUN6I_DPHY_TX_TIME1_CLK_POST(n)(((n) & 0xff) << 24) -#define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16) -#define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n)(((n) & 0xff) << 8) -#define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) - -#define SUN6I_DPHY_TX_TIME2_REG0x18 -#define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) - -#define SUN6I_DPHY_TX_TIME3_REG0x1c - -#define SUN6I_DPHY_TX_TIME4_REG0x20 -#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8) -#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff) - -#define SUN6I_DPHY_ANA0_REG0x4c -#define SUN6I_DPHY_ANA0_REG_PWSBIT(31) -#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28) -#define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24) -#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12) -#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8) - -#define SUN6I_DPHY_ANA1_REG0x50 -#define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31) -#define SUN6I_DPHY_ANA1_REG_CSMPS(n) (((n) & 3) << 28) -#define SUN6I_DPHY_ANA1_REG_SVTT(n)(((n) & 0xf) << 24) - -#define SUN6I_DPHY_ANA2_REG0x54 -#define SUN6I_DPHY_ANA2_EN_P2S_CPU(n) (((n) & 0xf) << 24) -#define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASKGENMASK(27, 24) -#define SUN6I_DPHY_ANA2_EN_CK_CPU BIT(4) -#define SUN6I_DPHY_ANA2_REG_ENIB BIT(1) - -#define SUN6I_DPHY_ANA3_REG0x58 -#define SUN6I_DPHY_ANA3_EN_VTTD(n) (((n) & 0xf) << 28) -#define SUN6I_DPHY_ANA3_EN_V
