[PATCH 3/5] usb: dwc3: of-simple: Add compatible for Allwinner H6 platform
Add compatible string to use this generic glue layer to support
Allwinner H6 platform's dwc3 controller.
Signed-off-by: Icenowy Zheng
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c
b/drivers/usb/dwc3/dwc3-of-simple.c
index cb2ee96fd3e8..a92a8e4c6b92 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -215,6 +215,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
{ .compatible = "sprd,sc9860-dwc3" },
{ .compatible = "amlogic,meson-axg-dwc3" },
{ .compatible = "amlogic,meson-gxl-dwc3" },
+ { .compatible = "allwinner,sun50i-h6-dwc3" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
--
2.17.0
[PATCH 4/5] arm64: allwinner: h6: add USB3 device nodes
Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.
Add device tree nodes for them.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index c72da8cd9ef5..9564c938717c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -174,6 +174,44 @@
status = "disabled";
};
+ usb3: usb@520 {
+ compatible = "allwinner,sun50i-h6-dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = < CLK_BUS_XHCI>;
+ clock-names = "bus";
+ resets = < RST_BUS_XHCI>;
+ reset-names = "bus";
+ status = "disabled";
+
+ dwc3: dwc3 {
+ compatible = "snps,dwc3";
+ reg = <0x520 0x1>;
+ interrupts = ;
+ /*
+* According to Wink from Allwinner, the
+* USB3 port on H6 is not capable of OTG;
+* the datasheet doesn't mention OTG at all
+* either, so the dr_mode is default to
+* "host" here.
+*/
+ dr_mode = "host";
+ phys = <>;
+ phy-names = "usb3-phy";
+ status = "disabled";
+ };
+ };
+
+ usb3phy: phy@521 {
+ compatible = "allwinner,sun50i-h6-usb3-phy";
+ reg = <0x521 0x1>;
+ clocks = < CLK_USB_PHY1>;
+ resets = < RST_USB_PHY1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
r_ccu: clock@701 {
compatible = "allwinner,sun50i-h6-r-ccu";
reg = <0x0701 0x400>;
--
2.17.0
[PATCH 5/5] arm64: allwinner: h6: enable USB3 port on Pine H64
Pine H64 board have a USB3 port, which is connected to the USB3 pins of
the H6 SoC, and the 5V power supply is controlled via GPIO (shared with
the power USB ports).
Enable this port.
Signed-off-by: Icenowy Zheng
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index b6f2d6b2ecae..e2e262b4e3d8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -20,6 +20,20 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_usb_vbus: vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ startup-delay-us = <10>;
+ gpio = <_pio 0 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+ {
+ status = "okay";
};
_i2c {
@@ -37,3 +51,12 @@
pinctrl-0 = <_ph_pins>;
status = "okay";
};
+
+ {
+ status = "okay";
+};
+
+ {
+ phy-supply = <_usb_vbus>;
+ status = "okay";
+};
--
2.17.0
Re: [linux-sunxi] Re: [PATCH 02/21] arm64: dts: allwinner: a64: Add DE2 CCU
于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard 写到:
>On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
>> DE2 in A64 has clock control unit and behavior is
>> same like H3/H5, so reuse the same in A64.
>>
>> Signed-off-by: Jagan Teki
>> ---
>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> index 1b2ef28c42bd..67b80bbe5bf5 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> @@ -43,9 +43,11 @@
>> */
>>
>> #include
>> +#include
>> #include
>> #include
>> #include
>> +#include
>>
>> / {
>> interrupt-parent = <>;
>> @@ -168,6 +170,19 @@
>> #size-cells = <1>;
>> ranges;
>>
>> +display_clocks: clock@100 {
>> +compatible = "allwinner,sun50i-a64-de2-clk",
>> + "allwinner,sun50i-h5-de2-clk";
>
>The A64 was released before the H5, so that should be the other way
>around.
>
>> +reg = <0x0100 0x10>;
>> +clocks = < CLK_DE>,
>> + < CLK_BUS_DE>;
>> +clock-names = "mod",
>> + "bus";
>> +resets = < RST_BUS_DE>;
>> +#clock-cells = <1>;
>> +#reset-cells = <1>;
>> +};
>> +
>
>So it turns out we don't need the SRAM to access the CCU driver?
As now U-Boot claims SRAM, people may forget thus :-(
>
>Maxime
Re: [PATCH 15/21] drm: sun4i: add support for HVCC regulator for DWC HDMI glue
于 2018年5月2日 GMT+08:00 下午7:48:43, Maxime Ripard 写到:
>On Mon, Apr 30, 2018 at 05:10:52PM +0530, Jagan Teki wrote:
>> From: Icenowy Zheng
>>
>> Allwinner SoCs with DWC HDMI controller have a "HVCC" power pin for
>the
>> HDMI part, and on some boards it's connected to a dedicated regulator
>> rather than the main 3.3v.
>>
>> Add support for optional HVCC regulator. For boards that doesn't use
>a
>> dedicated regulator to power it, the default dummy regulator is used.
>>
>> Signed-off-by: Icenowy Zheng
>> Signed-off-by: Jagan Teki
>> ---
>> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 ++
>> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++
>> 2 files changed, 16 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>> index 9f40a44b456b..7c33faff7ad4 100644
>> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>> @@ -73,6 +73,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev,
>struct device *master,
>> if (encoder->possible_crtcs == 0)
>> return -EPROBE_DEFER;
>>
>> +hdmi->vcc_hdmi = devm_regulator_get(dev, "hvcc");
>> +if (IS_ERR(hdmi->vcc_hdmi)) {
>> +dev_err(dev, "Could not get HDMI power supply\n");
>> +return PTR_ERR(hdmi->vcc_hdmi);
>> +}
>> +
>
>You're not making it optional here, unlike what your commit log
>says. Not that I'm fine with both, but we need to be consistent :)
If it's not set, regulator subsystem will generate a dummy
regulator as a spaceholder, except using the exclusive variant
of the function.
The word "optional" is from DT perspectove, as it's possible that
it's bound to some critical regulators.
>
>> hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
>> if (IS_ERR(hdmi->rst_ctrl)) {
>> dev_err(dev, "Could not get ctrl reset control\n");
>> @@ -91,6 +97,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev,
>struct device *master,
>> return ret;
>> }
>>
>> +ret = regulator_enable(hdmi->vcc_hdmi);
>> +if (ret) {
>> +dev_err(dev, "Cannot enable HDMI power supply\n");
>> +goto err_disable_vcc;
>> +}
>> +
>> ret = clk_prepare_enable(hdmi->clk_tmds);
>> if (ret) {
>> dev_err(dev, "Could not enable tmds clock\n");
>> @@ -143,6 +155,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev,
>struct device *master,
>> clk_disable_unprepare(hdmi->clk_tmds);
>> err_assert_ctrl_reset:
>> reset_control_assert(hdmi->rst_ctrl);
>> +err_disable_vcc:
>> +regulator_disable(hdmi->vcc_hdmi);
>
>
>The err_disable_vcc label will disable the regulator, but if there's
>an error in regulator_enable, it will disable it while it wasn't
>enabled in the first place, which is not really something we want to
>do.
>
>Maxime
Re: [linux-sunxi] Re: [PATCH 02/21] arm64: dts: allwinner: a64: Add DE2 CCU
于 2018年5月2日 GMT+08:00 下午7:50:19, Jagan Teki 写到:
>On Wed, May 2, 2018 at 5:04 PM, Icenowy Zheng wrote:
>>
>>
>> 于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard
> 写到:
>>>On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
>>>> DE2 in A64 has clock control unit and behavior is
>>>> same like H3/H5, so reuse the same in A64.
>>>>
>>>> Signed-off-by: Jagan Teki
>>>> ---
>>>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++
>>>> 1 file changed, 15 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> index 1b2ef28c42bd..67b80bbe5bf5 100644
>>>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> @@ -43,9 +43,11 @@
>>>> */
>>>>
>>>> #include
>>>> +#include
>>>> #include
>>>> #include
>>>> #include
>>>> +#include
>>>>
>>>> / {
>>>> interrupt-parent = <>;
>>>> @@ -168,6 +170,19 @@
>>>> #size-cells = <1>;
>>>> ranges;
>>>>
>>>> +display_clocks: clock@100 {
>>>> +compatible = "allwinner,sun50i-a64-de2-clk",
>>>> + "allwinner,sun50i-h5-de2-clk";
>>>
>>>The A64 was released before the H5, so that should be the other way
>>>around.
>>>
>>>> +reg = <0x0100 0x10>;
>>>> +clocks = < CLK_DE>,
>>>> + < CLK_BUS_DE>;
>>>> +clock-names = "mod",
>>>> + "bus";
>>>> +resets = < RST_BUS_DE>;
>>>> +#clock-cells = <1>;
>>>> +#reset-cells = <1>;
>>>> +};
>>>> +
>>>
>>>So it turns out we don't need the SRAM to access the CCU driver?
>>
>> As now U-Boot claims SRAM, people may forget thus :-(
>
>I've sent few mails about how we represent de2 with sram_c [1] but
>none response after. Can I get further inputs so-that we can include
>sram_c in proper manner.
Please wait for the SRAMC driver sent by Chen-Yu (and commited
by me) and the DE2 bus driver pending for the SRAMC part.
>
>[1] https://patchwork.kernel.org/patch/10289737/
>
>Jagan.
>
>___
>linux-arm-kernel mailing list
>linux-arm-ker...@lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
[PATCH 0/7] Allwinner H6 R_{PIO,INTC,I2C} support
This patchset adds support for Allwinner H6's R_{PIO,INTC,I2C}
peripherals. They are in the "CPUS" power domain, powered by VDD-CPUS
rather than VDD-SYS.
R_PIO controls the PL/PM GPIO banks, R_INTC controls NMI, and R_I2C
controls the I2C at PL0/1.
A PCF8563 RTC is attached on R_I2C on Pine H64, which is added to the
device tree. An AXP805 (a variation of AXP806 with different default
value customization) is attached on the bus too, however as its driver
currently lacks self-work mode support, it will be activated in another
patchset.
In order to support R_{PIO,I2C}, a PRCM CCU driver is introduced. As the
PRCM clock part is totally different with older SoCs (from A31 to H5),
the driver for H6 is a new one, not reusing the old code.
Icenowy Zheng (7):
clk: sunxi-ng: add support for H6 PRCM CCU
arm64: allwinner: h6: add PRCM CCU device node
pinctrl: sunxi: add support for H6 R_PIO pin controller
arm64: allwinner: h6: add node for R_PIO pin controller
arm64: allwinner: h6: add R_INTC interrupt controller
arm64: allwinner: h6: add R_I2C controller
arm64: allwinner: h6: add PCF8563 RTC on Pine H64 board
.../devicetree/bindings/clock/sunxi-ccu.txt| 3 +-
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 +
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 52 ++
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 207 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 19 ++
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c| 128 +
include/dt-bindings/clock/sun50i-h6-r-ccu.h| 24 +++
include/dt-bindings/reset/sun50i-h6-r-ccu.h| 17 ++
13 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h
--
2.15.1
[PATCH 1/7] clk: sunxi-ng: add support for H6 PRCM CCU
The H6 has clock/reset controls in PRCM part, like old SoCs such as H3
and A64. However, the PRCM CCU is rearranged; the register arragement
is now similar to the main CCU of H6, and the PRCM now has two APB
buses to control -- one is clocked from AHB clock derivde from AR100
clock, the other is clocked from the same mux with AR100 clock.
Therefore a new driver is written for it.
As there's no official document about the PRCM in H6, all the information
are indirectly collected from BSP and parts of the document, and the
information source is noted as comments in the driver's source code. If
reliable information is provided furtherly, the driver needs to be
rechecked.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-ccu.txt| 3 +-
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 207 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 19 ++
include/dt-bindings/clock/sun50i-h6-r-ccu.h| 24 +++
include/dt-bindings/reset/sun50i-h6-r-ccu.h| 17 ++
7 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 460ef27b1008..47d2e902ced4 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -21,6 +21,7 @@ Required properties :
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
+ - "allwinner,sun50i-h6-r-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@@ -35,7 +36,7 @@ Required properties :
For the main CCU on H6, one more clock is needed:
- "iosc": the SoC's internal frequency oscillator
-For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
+For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 79dfd296c3d1..826674d090fd 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -16,6 +16,11 @@ config SUN50I_H6_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_H6_R_CCU
+ bool "Support for the Allwinner H6 PRCM CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN4I_A10_CCU
bool "Support for the Allwinner A10/A20 CCU"
default MACH_SUN4I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 9ac0fb948101..49454700f2e5 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,7 @@ obj-y += ccu_mp.o
# SoC support
obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
+obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
new file mode 100644
index ..27554eaf6929
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-h6-r.h"
+
+/*
+ * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
+ * clock definitions in the BSP source code.
+ */
+
+static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
+"pll-periph0", "iosc" };
+static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
+ { .index = 2, .shift = 0, .width = 5 },
+};
+
+static struct ccu_div ar100_clk = {
+ .div= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux= {
+ .shift = 24,
+ .wid
[PATCH 2/7] arm64: allwinner: h6: add PRCM CCU device node
Allwinner H6 has also a PRCM CCU.
Add its device node into the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 4debc3962830..db9da343ba46 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -173,5 +173,15 @@
resets = < RST_BUS_UART3>;
status = "disabled";
};
+
+ r_ccu: clock@701 {
+ compatible = "allwinner,sun50i-h6-r-ccu";
+ reg = <0x0701 0x400>;
+ clocks = <>, <>, <>,
+< CLK_PLL_PERIPH0>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
--
2.15.1
[PATCH 3/7] pinctrl: sunxi: add support for H6 R_PIO pin controller
Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.
Add support for it.
Signed-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c| 128 +
4 files changed, 134 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 64bc5c2a76da..258a4648ab81 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -28,6 +28,7 @@ Required properties:
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
"allwinner,sun50i-h6-pinctrl"
+ "allwinner,sun50i-h6-r-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 5de1f63b07bb..95282cda6cee 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -81,4 +81,8 @@ config PINCTRL_SUN50I_H6
def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H6_R
+ def_bool ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 3c4aec6611e9..adb8443aa55c 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S)+= pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5)+= pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6)+= pinctrl-sun50i-h6.o
+obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
new file mode 100644
index ..4557e18d5989
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H6 R_PIO pin controller driver
+ *
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * Based on pinctrl-sun6i-a31-r.c, which is:
+ * Copyright (C) 2014 Boris Brezillon
+ * Boris Brezillon
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_h6_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+
[PATCH 4/7] arm64: allwinner: h6: add node for R_PIO pin controller
Allwinner H6 SoC has a R_PIO pin controller which controls PL and PM
GPIO banks.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index db9da343ba46..a18b78fb4850 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -183,5 +183,18 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl@7022000 {
+ compatible = "allwinner,sun50i-h6-r-pinctrl";
+ reg = <0x07022000 0x400>;
+ interrupts = ,
+;
+ clocks = <_ccu CLK_R_APB1>, <>, <>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.15.1
[PATCH 5/7] arm64: allwinner: h6: add R_INTC interrupt controller
Allwinner H6 SoC has also a R_INTC interrupt controller like Allwinner
A64 SoC, but has its base address changed due to the memory map change
in H6.
Add it into the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index a18b78fb4850..b0b342c8c189 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -184,6 +184,15 @@
#reset-cells = <1>;
};
+ r_intc: interrupt-controller@7021000 {
+ compatible = "allwinner,sun50i-h6-r-intc",
+"allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x07021000 0x400>;
+ interrupts = ;
+ };
+
r_pio: pinctrl@7022000 {
compatible = "allwinner,sun50i-h6-r-pinctrl";
reg = <0x07022000 0x400>;
--
2.15.1
[PATCH 7/7] arm64: allwinner: h6: add PCF8563 RTC on Pine H64 board
Pine H64 board has a PCF8563 dedicated RTC connected to its R_I2C bus.
Enable the R_I2C bus and add the RTC to the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index d36de5eb81f3..b6f2d6b2ecae 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -22,6 +22,16 @@
};
};
+_i2c {
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_ph_pins>;
--
2.15.1
[PATCH 6/7] arm64: allwinner: h6: add R_I2C controller
Allwinner H6 SoC has a R_I2C controller wired to the PL0/PL1 pins, which
are used in the reference design to connect AXP805 PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index b0b342c8c189..37c2e11fca2e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -5,7 +5,9 @@
#include
#include
+#include
#include
+#include
/ {
interrupt-parent = <>;
@@ -204,6 +206,24 @@
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+
+ r_i2c_pins: r-i2c {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ };
+ };
+
+ r_i2c: i2c@7081400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07081400 0x400>;
+ interrupts = ;
+ clocks = <_ccu CLK_R_APB2_I2C>;
+ resets = <_ccu RST_R_APB2_I2C>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
--
2.15.1
[PATCH] ARM: sun8i: a33: add dts for Q8 tablets with different resolution
Q8 tablets with Allwinner A33 SoC now come with two kind of LCD, either
800x480 or 1024x600.
In order for sun4i-drm to be able to choose correct LCD configuration,
two different device trees should be present, one for a resolution.
Add stub device trees for two resolutions.
As the sun4i-drm driver still has some problems to support the LCDs, the
real LCD device nodes are not added to the device tree files.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts | 49 ++
arch/arm/boot/dts/sun8i-a33-q8-tablet-800x480.dts | 49 ++
3 files changed, 100 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts
create mode 100644 arch/arm/boot/dts/sun8i-a33-q8-tablet-800x480.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 570e107bf702..eeb9d9591cf0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -908,6 +908,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
+ sun8i-a33-q8-tablet-800x480.dtb \
+ sun8i-a33-q8-tablet-1024x600.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts
b/arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts
new file mode 100644
index ..6f8ebd6c90ee
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-a33-q8-tablet.dts"
+
+/ {
+ model = "Q8 A33 Tablet with 1024x600 LCD";
+ compatible = "allwinner,q8-a33-1024x600", "allwinner,q8-a33",
+"allwinner,sun8i-a33";
+};
diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet-800x480.dts
b/arch/arm/boot/dts/sun8i-a33-q8-tablet-800x480.dts
new file mode 100644
index ..ad84b94dee53
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet-800x480.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more detail
Re: [linux-sunxi] [PATCH 2/4] drivers: soc: sunxi: fix error processing on base address when claiming
于 2017年8月18日 GMT+08:00 下午2:21:07, Chen-Yu Tsai 写到: >Hi, > >On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote: >> When claiming SRAM, if the base is set to an error, it means that the >> SRAM controller has been probed, but failed to remap the controller >> memory zone. If the base is zero, thus the SRAM controller should be >not >> probed at all, and it should return -EPROBE_DEFER. However, currently >we >> returned -EPROBE_DEFER in the former situation, and ignored the >latter >> situation (which will lead to the kernel to panic). >> >> Fix the behavior on abnormal base address processing when claiming. > >Could you describe how you actually ran into this? The failure seems >unlikely for a properly written device tree. In fact it's possible, as the probe defering used to be broken. On the A64 situation, the SRAM is referenced by the DE2 CCU driver, which will be probed very early -- before SRAM is probed, and the problem happens. > >Thanks >ChenYu
[PATCH v2 2/5] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
On newer revisions of the Banana Pi M2 Ultra boards, the 5V power output
(used by HDMI, SATA and USB) is controller via a GPIO.
Add the regulator node for it.
Older revisions just have the 5V power output always on, and the GPIO is
reserved on these boards. So it won't affect the older revisions.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -78,6 +78,15 @@
};
};
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
--
2.13.6
[PATCH v2 3/5] ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.
Add regulator node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index 8a69be2a0842..fe16fc0eb518 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -72,6 +72,15 @@
};
};
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
--
2.13.6
[PATCH v2 0/5] Allwinner R40 USB host support (DT part)
This patchset adds support for the USB host ports on Allwiner R40, and enable them on Banana Pi M2 Ultra and Berry boards. The first patch adds USB PHY and EHCI/OHCI nodes to the R40 DTSI. The second and third patch adds 5V regulator for the two boards, and the fourth and fifth patch finally adds USB host ports support. Icenowy Zheng (5): ARM: sun8i: r40: add USB host port nodes for R40 ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 31 ++ arch/arm/boot/dts/sun8i-r40.dtsi | 72 +++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 22 +++ 3 files changed, 125 insertions(+) -- 2.13.6
[PATCH v2 4/5] ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
From: Icenowy Zheng
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 035599d870b9..8c5efe2a9881 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -93,6 +93,14 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
status = "okay";
@@ -180,8 +188,22 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pb_pins>;
status = "okay";
};
+
+ {
+ usb1_vbus-supply = <_vcc5v0>;
+ usb2_vbus-supply = <_vcc5v0>;
+ status = "okay";
+};
--
2.13.6
[PATCH v2 5/5] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.
Enable it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index fe16fc0eb518..45c17c8c5915 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -87,6 +87,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
@@ -98,6 +102,10 @@
};
};
+ {
+ status = "okay";
+};
+
#include "axp22x.dtsi"
_aldo3 {
@@ -171,3 +179,8 @@
pinctrl-0 = <_pb_pins>;
status = "okay";
};
+
+ {
+ usb1_vbus-supply = <_vcc5v0>;
+ status = "okay";
+};
--
2.13.6
[PATCH v2 1/5] ARM: sun8i: r40: add USB host port nodes for R40
From: Icenowy Zheng
Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
Add support for the host ports in the DTSI file.
The OTG controller still cannot work with existing compatibles, and needs
more investigation. So it's not added yet.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the bogus OHCI resources in EHCI device node.
arch/arm/boot/dts/sun8i-r40.dtsi | 72
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5a6745409ae..19f270a9f3b1 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -173,6 +173,78 @@
#size-cells = <0>;
};
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,sun8i-r40-usb-phy";
+ reg = <0x01c13400 0x14>,
+ <0x01c14800 0x4>,
+ <0x01c19800 0x4>,
+ <0x01c1c800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2";
+ clocks = < CLK_USB_PHY0>,
+< CLK_USB_PHY1>,
+< CLK_USB_PHY2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy";
+ resets = < RST_USB_PHY0>,
+< RST_USB_PHY1>,
+< RST_USB_PHY2>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb@1c19000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c19000 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_EHCI1>;
+ resets = < RST_BUS_EHCI1>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@1c19400 {
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+ reg = <0x01c19400 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI1>,
+< CLK_USB_OHCI1>;
+ resets = < RST_BUS_OHCI1>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@1c1c000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_EHCI2>;
+ resets = < RST_BUS_EHCI2>;
+ phys = < 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@1c1c400 {
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI2>,
+< CLK_USB_OHCI2>;
+ resets = < RST_BUS_OHCI2>;
+ phys = < 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
ccu: clock@1c2 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c2 0x400>;
--
2.13.6
[PATCH v2 1/3] arm64: allwinner: a64: enable USB host controller for BPi M64
Banana Pi M64 connects the USB host-only controller on A64 SoC to a USB
hub, which provided the two USB Type-A ports on the board.
Enable the USB host controller.
The OTG function of the Micro-USB port needs the drivevbus function of
the AXP803 driver implemented, so it's not enabled now.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v2:
- Added Chen-Yu's review tag.
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index ba2fde2909f9..a4a7b9cb59b9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -68,6 +68,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
@@ -123,6 +127,10 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
@@ -134,3 +142,7 @@
pinctrl-0 = <_pins>, <_rts_cts_pins>;
status = "okay";
};
+
+ {
+ status = "okay";
+};
--
2.13.0
[PATCH v2 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64
Banana Pi M64 board uses an AXP803 PMIC.
Enable the PMIC and its regulators.
As we have now proper regulators support, missing or dummy regulators
are changed to the correct ones.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Changed vdd-cpux constraints.
- Added vcc-1v2-hsic regulator.
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 122 +++--
1 file changed, 112 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index a4a7b9cb59b9..ec72ca8c8b30 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -59,13 +59,6 @@
chosen {
stdout-path = "serial0:115200n8";
};
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- };
};
{
@@ -77,6 +70,7 @@
pinctrl-0 = <_pins>;
phy-mode = "rgmii";
phy-handle = <_rgmii_phy>;
+ phy-supply = <_dc1sw>;
status = "okay";
};
@@ -100,7 +94,7 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- vmmc-supply = <_vcc3v3>;
+ vmmc-supply = <_dcdc1>;
cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
@@ -111,7 +105,8 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- vmmc-supply = <_vcc3v3>;
+ vmmc-supply = <_dldo2>;
+ vqmmc-supply = <_dldo4>;
bus-width = <4>;
non-removable;
status = "okay";
@@ -120,7 +115,7 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- vmmc-supply = <_vcc3v3>;
+ vmmc-supply = <_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
@@ -131,6 +126,113 @@
status = "okay";
};
+_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-pl";
+};
+
+_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-3v3";
+};
+
+_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <104>;
+ regulator-max-microvolt = <130>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <150>;
+ regulator-name = "vcc-dram";
+};
+
+_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <110>;
+ regulator-max-microvolt = <110>;
+ regulator-name = "vdd-sys";
+};
+
+_dldo1 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-hdmi-dsi";
+};
+
+_dldo2 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-wifi";
+};
+
+_dldo4 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-wifi-io";
+};
+
+_eldo1 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "cpvdd";
+};
+
+_fldo1 {
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <110>;
+ regulator-max-microvolt = <110>;
+ regulator-name = "vdd-cpus";
+};
+
+_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
--
2.13.0
[PATCH v2 3/3] arm64: allwinner: a64: add proper support for the Wi-Fi on BPi M64
BPi M64 has an AP6212 Wi-Fi/Bluetooth combo module, and the Wi-Fi SDIO
card is connected to the mmc1 controller.
The pwrseq of the mmc1 (used to reset the card) used to missing, and the
out-of-band interrupt line of the card is not specified.
Fix these issues for proper Wi-Fi support of BPi M64.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index ec72ca8c8b30..4a8d3f83a36e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -59,6 +59,11 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
};
{
@@ -107,9 +112,18 @@
pinctrl-0 = <_pins>;
vmmc-supply = <_dldo2>;
vqmmc-supply = <_dldo4>;
+ mmc-pwrseq = <_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+ interrupt-names = "host-wake";
+ };
};
{
--
2.13.0
Re: [PATCH 0/3] Add ethernet0 alias for several A64 boards
于 2017年7月25日 GMT+08:00 下午10:31:27, Maxime Ripard 写到: >On Tue, Jul 25, 2017 at 05:18:19AM +0200, Adam Borowski wrote: >> On Tue, Jul 25, 2017 at 11:04:24AM +0800, icen...@aosc.io wrote: >> > 在 2017-07-24 15:58，Maxime Ripard 写道： >> > > On Sat, Jul 22, 2017 at 10:28:49AM +0800, Icenowy Zheng wrote: >> > > > Allwinner A64 SoC has an EMAC which is used to provide Ethernet >> > > > function on several boards. >> > > > >> > > > The EMAC itself doesn't have a fixed MAC address, but the sunxi >> > > > mainline U-Boot have the ability to generate one based on the >eFUSE >> > > > SID in the chip, and add the generated MAC address to the >device >> > > > tree when booting. >> > > > >> > > > The MAC address setting step is based on the device tree's >aliases, >> > > > and device tree nodes prefixed "ethernet" will get the MAC >address >> > > > added. However, in several A64 boards' device tree, the alias >is not >> > > > set up, so that the U-Boot won't set the MAC address. >> > > > >> > > > Add the ethernet0 aliases to these boards. >> > > > >> > > > I hope this patchset can be queued in 4.13, otherwise 4.13 >kernels >> > > > won't get non-volatile MAC addresses, and will use random ones >> > > > instead, which is annoying to many users. >> > > > >> > > > Icenowy Zheng (3): >> > > > arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC >node >> > > > arm64: allwinner: a64: add ethernet0 alias for Pine64 EMAC >node >> > > > arm64: allwinner: a64: add ethernet0 alias for SoPine EMAC >node >> > > >> > > Applied all three, thanks! >> > >> > Sorry, but could you queue them to 4.13? >> > >> > Otherwise 4.13 kernel release will have annoying random MAC >problem, >> > which heavily affects headless usages. >> >> Perhaps it would be better to reword the commit subject as "fix >missing >> ethernet0 alias ..."? That'd convey that the previous behaviour is a >defect >> that needs these patches as a fix. > >Yes, definitely. > >That and having a fixes: tag. Should I resend them with different commit message? > >Maxime
[PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register
In the CCU of the Allwinner R40 SoC, there's a GMAC configuration register, which is intended to be accessed by the dwmac-sun8i driver. On SoCs already supported by the driver the register is placed in the syscon rather than the CCU. As CCU is a critical part of the SoC, so write to it should be strictly limited. A regmap with restricted write permission is created by the R40 CCU driver, and can be get with dev_get_regmap. In order to tie the regmap to the CCU device, the R40 CCU is now a platform driver, so a platform device is created for it (and then tied with the regmap). The first patch does the conversion of the driver to a platform driver, and the second patch adds the regmap. Icenowy Zheng (2): clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: r40: export a regmap to access the GMAC register drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 69 ++-- 1 file changed, 59 insertions(+), 10 deletions(-) -- 2.13.6
[PATCH 2/2] clk: sunxi-ng: r40: export a regmap to access the GMAC register
There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in
the syscon part, in the CCU of R40 SoC.
Export a regmap of the CCU.
Read access is not restricted to all registers, but only the GMAC
register is allowed to be written.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index bb94e2c44e86..df752bf77ff1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include "ccu_common.h"
#include "ccu_reset.h"
@@ -1251,9 +1252,35 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = {
.bypass_index = 1, /* index of 24 MHz oscillator */
};
+/*
+ * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
+ * GMAC configuration register.
+ * Only this register is allowed to be written, in order to
+ * prevent overriding critical clock configuration.
+ */
+
+#define SUN8I_R40_GMAC_CFG_REG 0x164
+static bool sun8i_r40_ccu_regmap_writeable_reg(struct device *dev,
+ unsigned int reg)
+{
+ if (reg == SUN8I_R40_GMAC_CFG_REG)
+ return true;
+ return false;
+}
+
+static struct regmap_config sun8i_r40_ccu_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x320, /* PLL_LOCK_CTRL_REG */
+
+ .writeable_reg = sun8i_r40_ccu_regmap_writeable_reg,
+};
+
static int sun8i_r40_ccu_probe(struct platform_device *pdev)
{
struct resource *res;
+ struct regmap *regmap;
void __iomem *reg;
u32 val;
int ret;
@@ -1278,6 +1305,11 @@ static int sun8i_r40_ccu_probe(struct platform_device
*pdev)
val &= ~GENMASK(25, 20);
writel(val, reg + SUN8I_R40_USB_CLK_REG);
+ regmap = devm_regmap_init_mmio(>dev, reg,
+ _r40_ccu_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _r40_ccu_desc);
if (ret)
return ret;
--
2.13.6
[PATCH 1/2] clk: sunxi-ng: r40: rewrite init code to a platform driver
As we need to register a regmap on the R40 CCU, there needs to be a
device structure bound to the CCU device node.
Rewrite the R40 CCU driver initial code to make it a proper platform
driver, thus we will have a platform device bound to it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..bb94e2c44e86 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -12,6 +12,7 @@
*/
#include
+#include
#include
#include "ccu_common.h"
@@ -1250,17 +1251,17 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = {
.bypass_index = 1, /* index of 24 MHz oscillator */
};
-static void __init sun8i_r40_ccu_setup(struct device_node *node)
+static int sun8i_r40_ccu_probe(struct platform_device *pdev)
{
+ struct resource *res;
void __iomem *reg;
u32 val;
+ int ret;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
- return;
- }
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg = devm_ioremap_resource(>dev, res);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 4 */
val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
@@ -1277,7 +1278,9 @@ static void __init sun8i_r40_ccu_setup(struct device_node
*node)
val &= ~GENMASK(25, 20);
writel(val, reg + SUN8I_R40_USB_CLK_REG);
- sunxi_ccu_probe(node, reg, _r40_ccu_desc);
+ ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _r40_ccu_desc);
+ if (ret)
+ return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(_r40_pll_cpu_nb);
@@ -1285,6 +1288,20 @@ static void __init sun8i_r40_ccu_setup(struct
device_node *node)
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
_r40_cpu_nb);
+
+ return 0;
}
-CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu",
- sun8i_r40_ccu_setup);
+
+static const struct of_device_id sun8i_r40_ccu_ids[] = {
+ { .compatible = "allwinner,sun8i-r40-ccu" },
+ { }
+};
+
+static struct platform_driver sun8i_r40_ccu_driver = {
+ .probe = sun8i_r40_ccu_probe,
+ .driver = {
+ .name = "sun8i-r40-ccu",
+ .of_match_table = sun8i_r40_ccu_ids,
+ },
+};
+builtin_platform_driver(sun8i_r40_ccu_driver);
--
2.13.6
[PATCH v3 0/3] Basical device tree parts for Allwinner R40 SoC
This patchset adds basical device tree parts for the Allwinner R40 SoC and two boards feature this SoC -- Banana Pi M2 Ultra and Berry (The BPi M2 Berry board uses V40 SoC, which is just a renamed R40). Chen-Yu Tsai (2): ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (1): ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry arch/arm/boot/dts/Makefile| 4 +- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++ arch/arm/boot/dts/sun8i-r40.dtsi | 396 ++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 + 4 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts -- 2.13.6
[PATCH v3 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
From: Chen-Yu Tsai
The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Dropped all max-frequency properties in MMC nodes.
Changes in v2:
- Change the MMC frequencies to conservative verified values.
- Add fallback R40 compatible for MMC.
arch/arm/boot/dts/sun8i-r40.dtsi | 396 +++
1 file changed, 396 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..d5a6745409ae
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,396 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai
+ * Copyright 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ soc {
+ compatible = &quo
[PATCH v3 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
The Banana Pi M2 Ultra is an SBC based on the Allwinner V40 SoC (same as
the R40 SoC). The form factor is similar to the Raspberry Pi series.
It features:
- X-Powers AXP221s PMIC connected to i2c0
- 1GiB DDR3 DRAM
- microSD slot
- MicroUSB Type-B port for power and connected to usb0
- HDMI output
- MIPI DSI connector
- 4 USB Type-A ports (connected to the usb1 controller via a hub)
- gigabit ethernet with Realtek RTL8211E transceiver
- WiFi/Bluetooth with AP6212 module, with external antenna connector
- SATA and power connectors for native SATA support
- camera sensor connector
- audio out headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 ++
2 files changed, 166 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 93b1e63a52af..da3f87b35059 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -941,7 +941,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
- sun8i-v3s-licheepi-zero-dock.dtb
+ sun8i-v3s-licheepi-zero-dock.dtb \
+ sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
new file mode 100644
index ..8a69be2a0842
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include
+
+/ {
+ model = "Banana Pi M2 Berry";
+ compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ label = "bananapi:red:pwr";
+ gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ user-led {
+ label = "bananapi:green:user";
+ gpios = < 7 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = < 6 10 GPIO_ACTIVE_LO
[PATCH v3 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
From: Chen-Yu Tsai
The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
form factor and position of various connectors, leds and buttons is
similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
as the latest Banana Pi M64.
It features:
- X-Powers AXP221s PMIC connected to i2c0
- 2 GB DDR3 DRAM
- 8 GB eMMC
- micro SD card slot
- DC power jack
- HDMI output
- MIPI DSI connector
- 2x USB 2.0 hosts
- 1x USB 2.0 OTG
- gigabit ethernet with Realtek RTL8211E transceiver
- WiFi/Bluetooth with AP6212 chip, with external antenna connector
- SATA and power connectors for native SATA support
- camera sensor connector
- consumer IR receiver
- audio out headphone jack
- onboard microphone
- red, green, and blue LEDs
- debug UART pins
- Li-Po battery connector
- Raspberry Pi B+ compatible GPIO header
- power, reset, and boot control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Added 3.3V vqmmc regulator for mmc2 (eMMC).
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++
2 files changed, 179 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9cf688d404b8..93b1e63a52af 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -939,6 +939,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-parrot.dtb \
+ sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index ..7b52608cebe6
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include
+
+/ {
+ model = "Banana Pi BPI-M2-Ultra";
+ compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ label = "bananapi:red:pwr";
+ gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ user-led-green {
+ label = "bananapi:green:user
Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
于 2017年10月5日 GMT+08:00 下午2:58:01, Kalle Valo 写到: >Icenowy Zheng writes: > >> 于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard >> 写到: >>>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote: >>>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote: >>>> > >>>> > >>>> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo > >>>写到: >>>> > > Icenowy Zheng writes: >>>> > > >>>> > > > Allwinner XR819 is a SDIO Wi-Fi chip, which has the >>>functionality to >>>> > > use >>>> > > > an out-of-band interrupt pin instead of SDIO in-band >interrupt. >>>> > > > >>>> > > > Add the device tree binding of this chip, in order to make it >>>> > > possible >>>> > > > to add this interrupt pin to device trees. >>>> > > > >>>> > > > Signed-off-by: Icenowy Zheng >>>> > > > Acked-by: Rob Herring >>>> > > > --- >>>> > > > Changes in v3: >>>> > > > - Renames the node name. >>>> > > > - Adds ACK from Rob. >>>> > > > Changes in v2: >>>> > > > - Removed status property in example. >>>> > > > - Added required property reg. >>>> > > > >>>> > > > .../bindings/net/wireless/allwinner,xr819.txt | 38 >>>> > > ++ >>>> > > > 1 file changed, 38 insertions(+) >>>> > > > create mode 100644 >>>> > > >>>Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt >>>> > > >>>> > > Like I asked already last time, AFAICS there is no upstream >xr819 >>>> > > wireless driver in drivers/net/wireless directory. Do we still >>>accept >>>> > > bindings like this for out-of-tree drivers? >>>> > >>>> > See esp8089. >>>> > >>>> > There's also no in-tree driver for it. >>>> >>>> The question is whether we should. The above might be a precedent, >>>but it >>>> may not necessarily be the way to go. The commit message for >esp8089 >>>seems >>>> to hint that there is intent to have an in-tree driver: >>>> >>>> """ >>>> Note that at this point there only is an out of tree driver for >>>this >>>> hardware, there is no clear timeline / path for merging this. >>>Still >>>> I believe it would be good to specify the binding for this in >>>tree >>>> now, so that any future migration to an in tree driver will not >>>cause >>>> compatiblity issues. >>>> >>>> Cc: Icenowy Zheng >>>> Signed-off-by: Hans de Goede >>>> Signed-off-by: Rob Herring >>>> """ >>>> >>>> Regardless the bindings are in principle independent of the kernel >>>and just >>>> describing hardware. I think there have been discussions to move >the >>>> bindings to their own repository, but apparently it was decided >>>otherwise. >>> >>>Yeah, I guess especially how it could be merged with the cw1200 >driver >>>would be very relevant to that commit log. >> >> The cw1200 driver seems to still have some legacy platform >> data. Maybe they should also be convert to DT. >> (Or maybe compatible = "allwinner,xr819" is enough, as >> xr819 is a specified variant of cw1200 family) > >Ah, so the upstream cw1200 driver supports xr819? Has anyone tested >that? Or does cw1200 more changes than just adding the DT support? I think the cw1200 driver currently lacks maintain, and the product is already discontinued by ST-E. > >-- >Kalle Valo > >___ >linux-arm-kernel mailing list >linux-arm-ker...@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH review for 4.4 14/24] dmaengine: sun6i: allow build on ARM64 platforms (sun50i)
于 2017年10月8日 GMT+08:00 上午6:37:46, "Levin, Alexander (Sasha Levin)" 写到: >From: Icenowy Zheng > >[ Upstream commit c429ceb1e18252122ba96b52e689dcf87103c186 ] > >As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA >driver should be allowed to be built for ARM64, in order to make it >work on H5. There's no H5 support in 4.4/4.9. This patch can be ignored. > >Signed-off-by: Icenowy Zheng >Acked-by: Maxime Ripard >Acked-by: Chen-Yu Tsai >Signed-off-by: Vinod Koul >Signed-off-by: Sasha Levin >--- > drivers/dma/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig >index e6cd1a32025a..27b7b3a9bdd2 100644 >--- a/drivers/dma/Kconfig >+++ b/drivers/dma/Kconfig >@@ -158,7 +158,7 @@ config DMA_SUN4I > > config DMA_SUN6I > tristate "Allwinner A31 SoCs DMA support" >- depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST >+ depends on MACH_SUN6I || MACH_SUN8I || (ARM64 && ARCH_SUNXI) || >COMPILE_TEST > depends on RESET_CONTROLLER > select DMA_ENGINE > select DMA_VIRTUAL_CHANNELS
[PATCH 1/6] phy: sun4i-usb: add support for R40 USB PHY
Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
drivers/phy/allwinner/phy-sun4i-usb.c | 12
2 files changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index cbc7847dbf6c..0f00abd40a50 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -11,6 +11,7 @@ Required properties:
* allwinner,sun8i-a33-usb-phy
* allwinner,sun8i-a83t-usb-phy
* allwinner,sun8i-h3-usb-phy
+ * allwinner,sun8i-r40-usb-phy
* allwinner,sun8i-v3s-usb-phy
* allwinner,sun50i-a64-usb-phy
- reg : a list of offset + length pairs
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 1161e11fb3cf..9df7a2c9ca75 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -112,6 +112,7 @@ enum sun4i_usb_phy_type {
sun8i_a33_phy,
sun8i_a83t_phy,
sun8i_h3_phy,
+ sun8i_r40_phy,
sun8i_v3s_phy,
sun50i_a64_phy,
};
@@ -919,6 +920,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.phy0_dual_route = true,
};
+static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
+ .num_phys = 3,
+ .type = sun8i_r40_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
+ .phy0_dual_route = true,
+};
+
static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
.num_phys = 1,
.type = sun8i_v3s_phy,
@@ -947,6 +958,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] =
{
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = _a33_cfg },
{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = _a83t_cfg
},
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = _h3_cfg },
+ { .compatible = "allwinner,sun8i-r40-usb-phy", .data = _r40_cfg },
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = _v3s_cfg },
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = _a64_cfg},
--
2.13.6
[PATCH 0/6] Allwinner R40 USB host support
This patchset adds support for the USB host ports on Allwiner R40, and enable them on Banana Pi M2 Ultra and Berry boards. The first patch adds R40 support to the USB PHY driver. The second patch adds USB PHY and EHCI/OHCI nodes to the R40 DTSI. The thrid and fourth patch adds 5V regulator for the two boards, and the fifth and sixth patch finally adds USB host ports support. Icenowy Zheng (6): phy: sun4i-usb: add support for R40 USB PHY ARM: sun8i: r40: add USB host port nodes for R40 ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 31 + arch/arm/boot/dts/sun8i-r40.dtsi | 78 ++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 22 ++ drivers/phy/allwinner/phy-sun4i-usb.c | 12 5 files changed, 144 insertions(+) -- 2.13.6
[PATCH 5/6] ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
From: Icenowy Zheng
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 035599d870b9..8c5efe2a9881 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -93,6 +93,14 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
status = "okay";
@@ -180,8 +188,22 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pb_pins>;
status = "okay";
};
+
+ {
+ usb1_vbus-supply = <_vcc5v0>;
+ usb2_vbus-supply = <_vcc5v0>;
+ status = "okay";
+};
--
2.13.6
[PATCH 2/6] ARM: sun8i: r40: add USB host port nodes for R40
From: Icenowy Zheng
Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
Add support for the host ports in the DTSI file.
The OTG controller still cannot work with existing compatibles, and needs
more investigation. So it's not added yet.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 78
1 file changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5a6745409ae..f6c917cbbaac 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -173,6 +173,84 @@
#size-cells = <0>;
};
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,sun8i-r40-usb-phy";
+ reg = <0x01c13400 0x14>,
+ <0x01c14800 0x4>,
+ <0x01c19800 0x4>,
+ <0x01c1c800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2";
+ clocks = < CLK_USB_PHY0>,
+< CLK_USB_PHY1>,
+< CLK_USB_PHY2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy";
+ resets = < RST_USB_PHY0>,
+< RST_USB_PHY1>,
+< RST_USB_PHY2>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb@1c19000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c19000 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI1>,
+< CLK_BUS_EHCI1>,
+< CLK_USB_OHCI1>;
+ resets = < RST_BUS_OHCI1>,
+< RST_BUS_EHCI1>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@1c19400 {
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+ reg = <0x01c19400 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI1>,
+< CLK_USB_OHCI1>;
+ resets = < RST_BUS_OHCI1>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@1c1c000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI2>,
+< CLK_BUS_EHCI2>,
+< CLK_USB_OHCI2>;
+ resets = < RST_BUS_OHCI2>,
+< RST_BUS_EHCI2>;
+ phys = < 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@1c1c400 {
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI2>,
+< CLK_USB_OHCI2>;
+ resets = < RST_BUS_OHCI2>;
+ phys = < 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
ccu: clock@1c2 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c2 0x400>;
--
2.13.6
[PATCH 3/6] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
On newer revisions of the Banana Pi M2 Ultra boards, the 5V power output
(used by HDMI, SATA and USB) is controller via a GPIO.
Add the regulator node for it.
Older revisions just have the 5V power output always on, and the GPIO is
reserved on these boards. So it won't affect the older revisions.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -78,6 +78,15 @@
};
};
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
--
2.13.6
[PATCH 4/6] ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.
Add regulator node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index 8a69be2a0842..fe16fc0eb518 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -72,6 +72,15 @@
};
};
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
--
2.13.6
[PATCH 6/6] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.
Enable it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index fe16fc0eb518..45c17c8c5915 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -87,6 +87,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
@@ -98,6 +102,10 @@
};
};
+ {
+ status = "okay";
+};
+
#include "axp22x.dtsi"
_aldo3 {
@@ -171,3 +179,8 @@
pinctrl-0 = <_pb_pins>;
status = "okay";
};
+
+ {
+ usb1_vbus-supply = <_vcc5v0>;
+ status = "okay";
+};
--
2.13.6
[PATCH 2/2] ata: ahci_sunxi: add support for R40 SATA controller
Allwinner R40 SoC has an AHCI SATA controller like the one in A10/A20,
but with a reset control and two dedicated VDD pins for this controller
(one 1.2v and one 2.5v).
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/ata/ahci_sunxi.c | 118 +--
1 file changed, 115 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index b26437430163..a650fd6508be 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "ahci.h"
#define DRV_NAME "ahci-sunxi"
@@ -58,6 +59,19 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
+struct ahci_sunxi_quirks {
+ bool has_reset;
+ bool has_vdd1v2;
+ bool has_vdd2v5;
+};
+
+struct ahci_sunxi_data {
+ const struct ahci_sunxi_quirks *quirks;
+ struct reset_control *reset;
+ struct regulator *vdd1v2;
+ struct regulator *vdd2v5;
+};
+
static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
{
u32 reg_val;
@@ -179,17 +193,69 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
{
struct device *dev = >dev;
struct ahci_host_priv *hpriv;
+ struct ahci_sunxi_data *data;
int rc;
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->quirks = of_device_get_match_data(dev);
+ if (!data->quirks)
+ return -EINVAL;
+
+ if (data->quirks->has_reset) {
+ data->reset = devm_reset_control_get(dev, NULL);
+ if (IS_ERR(data->reset)) {
+ dev_err(dev, "Failed to get reset\n");
+ return PTR_ERR(data->reset);
+ }
+ }
+
+ if (data->quirks->has_vdd1v2) {
+ data->vdd1v2 = devm_regulator_get(dev, "vdd1v2");
+ if (IS_ERR(data->vdd1v2)) {
+ dev_err(dev, "Failed to get 1.2v VDD regulator\n");
+ return PTR_ERR(data->vdd1v2);
+ }
+ }
+
+ if (data->quirks->has_vdd2v5) {
+ data->vdd2v5 = devm_regulator_get(dev, "vdd2v5");
+ if (IS_ERR(data->vdd2v5)) {
+ dev_err(dev, "Failed to get 2.5v VDD regulator\n");
+ return PTR_ERR(data->vdd2v5);
+ }
+ }
+
hpriv = ahci_platform_get_resources(pdev);
if (IS_ERR(hpriv))
return PTR_ERR(hpriv);
+ hpriv->plat_data = data;
hpriv->start_engine = ahci_sunxi_start_engine;
+ if (data->quirks->has_vdd1v2) {
+ rc = regulator_enable(data->vdd1v2);
+ if (rc)
+ return rc;
+ }
+
+ if (data->quirks->has_vdd2v5) {
+ rc = regulator_enable(data->vdd2v5);
+ if (rc)
+ goto disable_vdd1v2;
+ }
+
+ if (data->quirks->has_reset) {
+ rc = reset_control_deassert(data->reset);
+ if (rc)
+ goto disable_vdd2v5;
+ }
+
rc = ahci_platform_enable_resources(hpriv);
if (rc)
- return rc;
+ goto assert_reset;
rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
if (rc)
@@ -215,6 +281,35 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
disable_resources:
ahci_platform_disable_resources(hpriv);
+assert_reset:
+ if (data->quirks->has_reset)
+ reset_control_assert(data->reset);
+disable_vdd2v5:
+ if (data->quirks->has_vdd2v5)
+ regulator_disable(data->vdd2v5);
+disable_vdd1v2:
+ if (data->quirks->has_vdd1v2)
+ regulator_disable(data->vdd1v2);
+ return rc;
+}
+
+static int ahci_sunxi_remove(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct ata_host *host = dev_get_drvdata(dev);
+ struct ahci_host_priv *hpriv = host->private_data;
+ struct ahci_sunxi_data *data = hpriv->plat_data;
+ int rc;
+
+ rc = ata_platform_remove_one(pdev);
+
+ if (data->quirks->has_reset)
+ reset_control_assert(data->reset);
+ if (data->quirks->has_vdd2v5)
+ regulator_disable(data->vdd2v5);
+ if (data->quirks->has_vdd1v2)
+ regulator_disable(data->vdd1v2);
+
return rc;
}
@@ -248,15 +343,32 @@ static int ahci_sunxi_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
ahci_sunxi_resume);
+static const struct ahci_sunxi_quirks sun4i_a10_ahci_quirks = {
[PATCH 1/2] dt-bindings: add binding for Allwinner R40 SATA AHCI controller
The Allwinner R40 SoC contains a SATA AHCI controller like the one in
A10/A20 SoCs, however a reset control and two power supplies are added
to it.
Add a binding document for it.
As a dedicated binding document is needed now for the A10/A20/R40 AHCI
controller, drop the A10 compatible line from generic platform AHCI
controller binding document.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/ata/ahci-platform.txt | 1 -
.../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++
2 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644
Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index fedc213b5f1a..da6818b2c204 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -9,7 +9,6 @@ PHYs.
Required properties:
- compatible: compatible string, one of:
- - "allwinner,sun4i-a10-ahci"
- "brcm,iproc-ahci"
- "hisilicon,hisi-ahci"
- "cavium,octeon-7130-ahci"
diff --git a/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt
b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt
new file mode 100644
index ..0eea78c14ad3
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt
@@ -0,0 +1,40 @@
+Allwinner A10/A20/R40 SoC SATA AHCI Controller
+
+Required properties:
+- compatible: compatible string, one of:
+ - "allwinner,sun4i-a10-ahci"
+ - "allwinner,sun8i-r40-ahci"
+- interrupts: the SATA IRQ
+- reg : the register mapping
+- clocks: the clocks needed by SATA controller, usually contains
+ an AHB clock and a mod clock
+
+Optional properties:
+- target-supply : regulator for SATA target power
+
+Required properties for the following compatibles:
+ - "allwinner,sun8i-r40-ahci"
+- resets: the reset control needed by SATA controller
+- vdd1v2-supply : regulator for SATA controller's 1.2V VDD
+- vdd2v5-supply : regulator for SATA controller's 2.5V VDD
+
+
+Examples for A10:
+ ahci: sata@1c18000 {
+ compatible = "allwinner,sun4i-a10-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <56>;
+ clocks = < 0>, <_gates 25>;
+ target-supply = <_ahci_5v>;
+ };
+
+Examples for R40:
+ ahci: sata@1c18000 {
+ compatible = "allwinner,sun8i-r40-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_SATA>, < CLK_BUS_SATA>;
+ resets = < RST_BUS_SATA>;
+ vdd1v2-supply = <_eldo3>;
+ vdd2v5-supply = <_dldo4>;
+ };
--
2.13.6
[PATCH] pinctrl: sunxi: rename R_PIO i2c pin function name
The I2C pin functions in R_PIO used to be named "s_twi".
As we usually use the name "i2c" instead of "twi" in the mainline
kernel, change these names to "s_i2c" for consistency.
The "s_twi" functions are not yet referenced by any device trees in
mainline kernel so I think it's safe to change the name.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 4 ++--
drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 4 ++--
drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index a22bd88a1f03..c96a3610a178 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -25,12 +25,12 @@ static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
index 2292e05a397b..5789e9ecbae1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
@@ -29,13 +29,13 @@ static const struct sunxi_desc_pin sun8i_a23_r_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
- SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
- SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
index 686ec212120b..ebfd9a26628c 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
@@ -20,12 +20,12 @@ static const struct sunxi_desc_pin sun8i_h3_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
--
2.13.0
[PATCH 00/13] Allwinner H3 DE2 basical support
Allwinner H3 features a "Display Engine 2.0", which needs some support to be present in the DRM driver. This patchset is now a basical version, which dropped some features I used to submitted: - TVE support (not so high priority now) - Multi-pipeline support (also not so high priority now due to no TVE) The last 6 patches are only used for testing this patchset, and they're going to be sent by Jernej Skrabec after this patchset is applied. Icenowy Zheng (9): dt-bindings: update the binding for Allwinner H3 DE2 support drm: sun4i: add support for H3 mixers drm: sun4i: add support for H3's TCON drm: sun4i: add compatible for H3 display engine clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 clk: sunxi-ng: export CLK_PLL_DE for H3 ARM: sun8i: h3: add display engine pipeline barebone [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC Jernej Skrabec (4): [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3 .../bindings/display/sunxi/sun4i-drm.txt | 25 +- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16 + arch/arm/boot/dts/sun8i-h3.dtsi| 205 + drivers/clk/sunxi-ng/ccu-sun8i-h3.c| 4 +- drivers/clk/sunxi-ng/ccu-sun8i-h3.h| 3 +- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 9 +- drivers/gpu/drm/sun4i/Kconfig | 9 + drivers/gpu/drm/sun4i/Makefile | 1 + drivers/gpu/drm/sun4i/sun4i_drv.c | 2 + drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +- drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 462 + drivers/gpu/drm/sun4i/sun8i_mixer.c| 18 + include/drm/bridge/dw_hdmi.h | 2 + include/dt-bindings/clock/sun8i-h3-ccu.h | 2 + 15 files changed, 781 insertions(+), 21 deletions(-) create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -- 2.13.0
[PATCH 03/13] drm: sun4i: add support for H3's TCON
From: Icenowy Zheng
Allwinner H3 has two special TCONs without channel 0.
Add support for this kind of TCON.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +++---
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
3 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index ace59651892f..fd99fe8a4df7 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -188,6 +188,7 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
of_device_is_compatible(node, "allwinner,sun6i-a31-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31s-tcon") ||
of_device_is_compatible(node, "allwinner,sun8i-a33-tcon") ||
+ of_device_is_compatible(node, "allwinner,sun8i-h3-tcon") ||
of_device_is_compatible(node, "allwinner,sun8i-v3s-tcon");
}
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d9791292553e..270f09e381a5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -59,6 +59,7 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int
channel)
/* Disable the TCON's channel */
if (channel == 0) {
+ WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_TCON_ENABLE, 0);
clk_disable_unprepare(tcon->dclk);
@@ -78,6 +79,7 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int
channel)
/* Enable the TCON's channel */
if (channel == 0) {
+ WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_TCON_ENABLE,
SUN4I_TCON0_CTL_TCON_ENABLE);
@@ -157,6 +159,8 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
u8 clk_delay;
u32 val = 0;
+ WARN_ON(!tcon->quirks->has_channel_0);
+
/* Configure the dot clock */
clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
@@ -366,10 +370,12 @@ static int sun4i_tcon_init_clocks(struct device *dev,
}
clk_prepare_enable(tcon->clk);
- tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
- if (IS_ERR(tcon->sclk0)) {
- dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
- return PTR_ERR(tcon->sclk0);
+ if (tcon->quirks->has_channel_0) {
+ tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
+ if (IS_ERR(tcon->sclk0)) {
+ dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
+ return PTR_ERR(tcon->sclk0);
+ }
}
if (tcon->quirks->has_channel_1) {
@@ -551,10 +557,12 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
goto err_free_clocks;
}
- ret = sun4i_dclk_create(dev, tcon);
- if (ret) {
- dev_err(dev, "Couldn't create our TCON dot clock\n");
- goto err_free_clocks;
+ if (tcon->quirks->has_channel_0) {
+ ret = sun4i_dclk_create(dev, tcon);
+ if (ret) {
+ dev_err(dev, "Couldn't create our TCON dot clock\n");
+ goto err_free_clocks;
+ }
}
ret = sun4i_tcon_init_irq(dev, tcon);
@@ -579,7 +587,8 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
return 0;
err_free_dotclock:
- sun4i_dclk_free(tcon);
+ if (tcon->quirks->has_channel_0)
+ sun4i_dclk_free(tcon);
err_free_clocks:
sun4i_tcon_free_clocks(tcon);
err_assert_reset:
@@ -593,7 +602,9 @@ static void sun4i_tcon_unbind(struct device *dev, struct
device *master,
struct sun4i_tcon *tcon = dev_get_drvdata(dev);
list_del(>list);
- sun4i_dclk_free(tcon);
+
+ if (tcon->quirks->has_channel_0)
+ sun4i_dclk_free(tcon);
sun4i_tcon_free_clocks(tcon);
}
@@ -625,23 +636,30 @@ static int sun4i_tcon_remove(struct platform_device *pdev)
static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
.has_unknown_mux = true,
+ .has_channel_0 = true,
.has_channel_1 = true,
};
static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = true,
};
static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = tru
[PATCH 04/13] drm: sun4i: add compatible for H3 display engine
Add a compatible string for H3 display engine in sun4i_drv code.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index fd99fe8a4df7..02c80bb7b385 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -314,6 +314,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
{ .compatible = "allwinner,sun8i-a33-display-engine" },
+ { .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ }
};
--
2.13.0
[PATCH 06/13] clk: sunxi-ng: export CLK_PLL_DE for H3
The CLK_PLL_DE is needed to be referenced in device tree for H3, for both forcing the parent of PLL_DE. So export it to the device tree binding header. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +-- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h index 1b4baea37d81..add3a7c18212 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h @@ -35,9 +35,8 @@ #define CLK_PLL_PERIPH0_2X 10 #define CLK_PLL_GPU11 #define CLK_PLL_PERIPH112 -#define CLK_PLL_DE 13 -/* The CPUX clock is exported */ +/* The PLL_DE and CPUX clocks is exported */ #define CLK_AXI15 #define CLK_AHB1 16 diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index e139fe5c62ec..5345957a8c2e 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -45,6 +45,8 @@ #define CLK_PLL_PERIPH09 +#define CLK_PLL_DE 13 + #define CLK_CPUX 14 #define CLK_BUS_CE 20 -- 2.13.0
[PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.
Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.
So allow CLK_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index d1ab0d713fa6..b1127e8629d9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
-0x104, 0, 4, 24, 3, BIT(31), 0);
+0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
--
2.13.0
[PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone
As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.
The H5 pipeline has some differences and will be enabled later.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 170
1 file changed, 170 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..75ad7b65a7fc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
*/
#include "sunxi-h3-h5.dtsi"
+#include
+#include
/ {
cpus {
@@ -72,6 +74,174 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-h3-display-engine";
+ allwinner,pipelines = <>,
+ <>;
+ status = "disabled";
+ };
+
+ soc {
+ display_clocks: clock@100 {
+ compatible = "allwinner,sun8i-a83t-de2-clk";
+ reg = <0x0100 0x10>;
+ clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+ clock-names = "bus",
+ "mod";
+ resets = < RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = < CLK_DE>;
+ assigned-clock-parents = < CLK_PLL_DE>;
+ assigned-clock-rates = <43200>;
+ };
+
+ mixer0: mixer@110 {
+ compatible = "allwinner,sun8i-h3-de2-mixer0";
+ reg = <0x0110 0x10>;
+ clocks = <_clocks CLK_BUS_MIXER0>,
+<_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <_clocks RST_MIXER0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<_in_mixer0>;
+ };
+
+ mixer0_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint =
<_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@120 {
+ compatible = "allwinner,sun8i-h3-de2-mixer1";
+ reg = <0x0120 0x10>;
+ clocks = <_clocks CLK_BUS_MIXER1>,
+<_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <_clocks RST_WB>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer1_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<_in_mixer1>;
+ };
+
+ mixer1_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint =
<_in_mixer1>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-h3-tcon";
+ reg = <0x0
[PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi
From: Jernej Skrabec Some custom phys don't support hpd interrupts. Add support for polling such events. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 60faf2d2bc6b..6c6466c6297c 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1942,7 +1942,11 @@ static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) struct drm_connector *connector = >connector; connector->interlace_allowed = 1; - connector->polled = DRM_CONNECTOR_POLL_HPD; + if (hdmi->phy.ops->setup_hpd) + connector->polled = DRM_CONNECTOR_POLL_HPD; + else + connector->polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; drm_connector_helper_add(connector, _hdmi_connector_helper_funcs); -- 2.13.0
[PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver
From: Jernej Skrabec
Some platform glues of DesignWare HDMI controller require some
initialization to be performed before probing the main HDMI controller.
Add a pre_init function for this kind of work.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
include/drm/bridge/dw_hdmi.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 6c6466c6297c..1e69b7631cae 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2343,6 +2343,9 @@ __dw_hdmi_probe(struct platform_device *pdev,
goto err_isfr;
}
+ if (plat_data->pre_init)
+ plat_data->pre_init(plat_data->pre_init_data);
+
/* Product and revision IDs */
hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
| (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 182f83283e24..6e109c336ca1 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -128,6 +128,8 @@ struct dw_hdmi_plat_data {
const struct drm_display_mode *mode);
unsigned long input_bus_format;
unsigned long input_bus_encoding;
+ void (*pre_init)(void *data);
+ void *pre_init_data;
/* Vendor PHY support */
const struct dw_hdmi_phy_ops *phy_ops;
--
2.13.0
[PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
From: Jernej Skrabec
When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
Signed-off-by: Jernej Skrabec
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index b1127e8629d9..2ebb3d865b01 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk, "avs",
"osc24M",
static const char * const hdmi_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
-0x150, 0, 4, 24, 2, BIT(31), 0);
+0x150, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_ddc_clk,"hdmi-ddc", "osc24M",
0x154, BIT(31), 0);
--
2.13.0
[PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3
From: Jernej Skrabec
Allwinner H3 features DesignWare HDMI Transmitter paired with custom
PHY.
For now, only video is supported by the driver. However, audio and CEC
are also supported by the hardware.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/Kconfig | 9 +
drivers/gpu/drm/sun4i/Makefile| 1 +
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 462 ++
3 files changed, 472 insertions(+)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 06f05302ee75..589502ffe31a 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -40,6 +40,15 @@ config DRM_SUN4I_BACKEND
do some alpha blending and feed graphics to TCON. If M is
selected the module will be called sun4i-backend.
+config DRM_SUN8I_DW_HDMI
+ tristate "Support for Allwinner version of DesignWare HDMI"
+ depends on DRM_SUN4I
+ select DRM_DW_HDMI
+ help
+ Choose this option if you have an Allwinner SoC with the
+ DesignWare HDMI controller with custom HDMI PHY. If M is
+ selected the module will be called sun8i_dw_hdmi.
+
config DRM_SUN8I_MIXER
tristate "Support for Allwinner Display Engine 2.0 Mixer"
default MACH_SUN8I
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 43c753cafc88..9c56173bf140 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_DRM_SUN4I) += sun4i_tv.o
obj-$(CONFIG_DRM_SUN4I_BACKEND)+= sun4i-backend.o
obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o
obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o
+obj-$(CONFIG_DRM_SUN8I_DW_HDMI)+= sun8i_dw_hdmi.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
new file mode 100644
index ..fa1ecbcf08b8
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2017, Jernej Skrabec
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "sun4i_crtc.h"
+#include "sun4i_tcon.h"
+
+#define SUN8I_HDMI_PHY_REG_POL 0x
+
+#define SUN8I_HDMI_PHY_REG_READ_EN 0x0010
+#define SUN8I_HDMI_PHY_REG_READ_EN_MAGIC 0x54524545
+
+#define SUN8I_HDMI_PHY_REG_UNSCRAMBLE 0x0014
+#define SUN8I_HDMI_PHY_REG_UNSCRAMBLE_MAGIC0x42494E47
+
+#define SUN8I_HDMI_PHY_REG_CTRL0x0020
+#define SUN8I_HDMI_PHY_REG_UNK10x0024
+#define SUN8I_HDMI_PHY_REG_UNK20x0028
+#define SUN8I_HDMI_PHY_REG_PLL 0x002c
+#define SUN8I_HDMI_PHY_REG_CLK 0x0030
+#define SUN8I_HDMI_PHY_REG_UNK30x0034
+
+#define SUN8I_HDMI_PHY_REG_STATUS 0x0038
+#define SUN8I_HDMI_PHY_REG_STATUS_READYBIT(7)
+#define SUN8I_HDMI_PHY_REG_STATUS_HPD BIT(19)
+
+#define to_sun8i_dw_hdmi(x)container_of(x, struct sun8i_dw_hdmi, x)
+#define set_bits(p, v) writel(readl(p) | (v), p)
+
+struct sun8i_dw_hdmi {
+ struct clk *clk_ddc;
+ struct clk *clk_hdmi;
+ struct device *dev;
+ struct drm_encoder encoder;
+ void __iomem *phy_base;
+ struct dw_hdmi_plat_data plat_data;
+ struct reset_control *rst_ddc;
+ struct reset_control *rst_hdmi;
+};
+
+static u32 sun8i_dw_hdmi_get_divider(int clk_khz)
+{
+ /*
+* Due to missing documentaion of HDMI PHY, we know correct
+* settings only for following four PHY dividers. Select one
+* based on clock speed.
+*/
+ if (clk_khz <= 27000)
+ return 11;
+ else if (clk_khz <= 74250)
+ return 4;
+ else if (clk_khz <= 148500)
+ return 2;
+ else
+ return 1;
+}
+
+static void sun8i_dw_hdmi_encoder_disable(struct drm_encoder *encoder)
+{
+ struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
+ struct sun4i_tcon *tcon = crtc->tcon;
+
+ DRM_DEBUG_DRIVER("Disabling HDMI Output\n");
+
+ sun4i_tcon_channel_disable(tcon, 1);
+}
+
+static void sun8i_dw_hdmi_encoder_enable(struct drm_encoder *encoder)
+{
+ struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
+ struct sun4i_tcon *tcon = crtc->tcon;
+
+ DRM_DEBUG_DRIVER("Enabling HDMI Output\n");
+
+ sun4i_tcon_channel_enable(tcon, 1);
+}
+
+static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+
[PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller
The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific
glues.
Add the related device nodes.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 75ad7b65a7fc..cd38d7e04606 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -197,6 +197,11 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ tcon0_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint =
<_in_tcon0>;
+ };
};
};
};
@@ -240,6 +245,36 @@
};
};
};
+
+ hdmi: hdmi@1ee {
+ compatible = "allwinner,h3-dw-hdmi";
+ reg = <0x01ee 0x1>,
+ <0x01ef 0x1>;
+ reg-io-width = <1>;
+ interrupts = ;
+ clocks = < CLK_BUS_HDMI>, < CLK_HDMI>,
+< CLK_HDMI_DDC>;
+ clock-names = "iahb", "isfr", "iddc";
+ resets = < RST_BUS_HDMI0>, < RST_BUS_HDMI1>;
+ reset-names = "hdmi", "ddc";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<_out_hdmi>;
+ };
+ };
+ };
+ };
};
timer {
--
2.13.0
[PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC
Orange Pi PC board has a HDMI-A port connected to the HDMI controller of
Allwinner H3 SoC.
Enable the HDMI output in Orange Pi PC device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 998b60f8d295..0e3326399590 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -98,6 +98,10 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
};
@@ -121,12 +125,20 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin>;
@@ -177,6 +189,10 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
--
2.13.0
[PATCH 02/13] drm: sun4i: add support for H3 mixers
From: Icenowy Zheng
Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI. There's also some graphics post-process
function that is missing on mixer1, however, as we currently support
none of these functions, the only difference that is shown to us is the
channel number difference.
Add support for these two variants.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index cb193c5f1686..d658a3a8159a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -390,11 +390,29 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg =
{
.ui_num = 1,
};
+static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ .vi_num = 1,
+ .ui_num = 3,
+};
+
+static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
+ .vi_num = 1,
+ .ui_num = 1,
+};
+
static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = _v3s_mixer_cfg,
},
+ {
+ .compatible = "allwinner,sun8i-h3-de2-mixer0",
+ .data = _h3_mixer0_cfg
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-de2-mixer1",
+ .data = _h3_mixer1_cfg
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
--
2.13.0
[PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Allwinner H3 features a "Display Engine 2.0". Add device tree bindings for the following parts: - H3 TCONs - H3 Mixers - H3 Display engine Signed-off-by: Icenowy Zheng --- .../bindings/display/sunxi/sun4i-drm.txt | 25 ++ 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 2ee6ff0ef98e..92512953943e 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -87,18 +87,17 @@ Required properties: * allwinner,sun6i-a31-tcon * allwinner,sun6i-a31s-tcon * allwinner,sun8i-a33-tcon + * allwinner,sun8i-h3-tcon * allwinner,sun8i-v3s-tcon - reg: base address and size of memory-mapped region - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the TCON. Three are needed: - 'ahb': the interface clocks - - 'tcon-ch0': The clock driving the TCON channel 0 - resets: phandles to the reset controllers driving the encoder - "lcd": the reset line for the TCON channel 0 - clock-names: the clock names mentioned above - reset-names: the reset names mentioned above - - clock-output-names: Name of the pixel clock created - ports: A ports node with endpoint definitions as defined in Documentation/devicetree/bindings/media/video-interfaces.txt. The @@ -112,7 +111,23 @@ Required properties: channel the endpoint is associated to. If that property is not present, the endpoint number will be used as the channel number. -On SoCs other than the A33 and V3s, there is one more clock required: +For the following compatibles: + * allwinner,sun5i-a13-tcon + * allwinner,sun6i-a31-tcon + * allwinner,sun6i-a31s-tcon + * allwinner,sun8i-a33-tcon + * allwinner,sun8i-v3s-tcon +there is one more clock and one more property required: + - clocks: + - 'tcon-ch0': The clock driving the TCON channel 0 + - clock-output-names: Name of the pixel clock created + +For the following compatibles: + * allwinner,sun5i-a13-tcon + * allwinner,sun6i-a31-tcon + * allwinner,sun6i-a31s-tcon + * allwinner,sun8i-h3-tcon +there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 DRC @@ -207,6 +222,8 @@ supported. Required properties: - compatible: value must be one of: * allwinner,sun8i-v3s-de2-mixer +* allwinner,sun8i-h3-de2-mixer0 +* allwinner,sun8i-h3-de2-mixer1 - reg: base address and size of the memory-mapped region. - clocks: phandles to the clocks feeding the mixer * bus: the mixer interface clock @@ -218,7 +235,6 @@ Required properties: Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoints, the second one the output - Display Engine Pipeline --- @@ -233,6 +249,7 @@ Required properties: * allwinner,sun6i-a31-display-engine * allwinner,sun6i-a31s-display-engine * allwinner,sun8i-a33-display-engine +* allwinner,sun8i-h3-display-engine * allwinner,sun8i-v3s-display-engine - allwinner,pipelines: list of phandle to the display engine -- 2.13.0
[PATCH] pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when
developing the driver, which makes IRQ not working.
Fix the IRQ bank base.
Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
Cc: sta...@vger.kernel.org
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
index c86d3c42a905..496ba34e1f5f 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
@@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc
sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
+ .irq_bank_base = 1,
.irq_read_needs_mux = true
};
--
2.13.0
[PATCH v3 0/2] Allwinner XR819 SDIO Wi-Fi DT binding and OPi Zero XR819 IRQ
The Allwinner XR819 SDIO Wi-Fi chip supports an out-of-band interrupt line, and the in-band interrupt is also supported. However the current out-of-tree driver uses the out-of-band interrupt by default. This patchset adds the device tree binding for the chip as well as the out-of-band interrupt, then adds the interrupt to the device tree of Orange Pi Zero. Icenowy Zheng (1): dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi Sergey Matyukevich (1): ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero .../bindings/net/wireless/allwinner,xr819.txt | 38 ++ arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 3 ++ 2 files changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt -- 2.13.5
[PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
Changes in v3:
- Renames the node name.
- Adds ACK from Rob.
Changes in v2:
- Removed status property in example.
- Added required property reg.
.../bindings/net/wireless/allwinner,xr819.txt | 38 ++
1 file changed, 38 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt
diff --git a/Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt
b/Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt
new file mode 100644
index ..7ae40441e343
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt
@@ -0,0 +1,38 @@
+Allwinner XRadio wireless SDIO devices
+
+This node provides properties for controlling the XRadio wireless device. The
+node is expected to be specified as a child node to the SDIO controller that
+connects the device to the system.
+
+Required properties:
+
+ - reg : The SDIO function number, see "Use of function subnodes" in
+ ../../mmc/mmc.txt.
+ - compatible : Should be "allwinner,xr819".
+
+Optional properties:
+ - interrupt-parent : the phandle for the interrupt controller to which the
+ device interrupts are connected.
+ - interrupts : specifies attributes for the out-of-band interrupt (host-wake).
+ When not specified the device will use in-band SDIO interrupts.
+
+Example:
+
+mmc1: mmc@01c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_a>;
+ vmmc-supply = <_vcc_wifi>;
+ mmc-pwrseq = <_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+
+ xr819: wifi@1 {
+ reg = <1>;
+ compatible = "allwinner,xr819";
+ interrupt-parent = <>;
+ interrupts = <6 10 IRQ_TYPE_EDGE_RISING>;
+ };
+};
--
2.13.5
[PATCH v3 2/2] ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero
From: Sergey Matyukevich
The Orange Pi Zero board has Allwinner XR819 SDIO wifi chip. The board
dts file provides a node enabling mmc1 controller, and a out-of-band
interrupt line of the chip is also connected, although the chip also
supports in-band interrupt.
The current out-of-tree driver is hardcoded to use out-of-band interrupt
as default, and it needs to be modified to use the in-band interrupt.
This commit adds the out-of-band interrupt line into the device tree.
Signed-off-by: Sergey Matyukevich
[Icenowy: Changed vendor prefix to allwinner and modify commit message]
Signed-off-by: Icenowy Zheng
---
Changes in v3 by Icenowy:
- Change the compatible string vendor prefix to "allwinner".
- Modify the commit message.
Changes in v2 by Sergey:
- Adds the compatible string.
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6595617204b3 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -127,6 +127,9 @@
*/
xr819: sdio_wifi@1 {
reg = <1>;
+ compatible = "allwinner,xr819";
+ interrupt-parent = <>;
+ interrupts = <6 10 IRQ_TYPE_EDGE_RISING>;
};
};
--
2.13.5
Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo 写到: >Icenowy Zheng writes: > >> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to >use >> an out-of-band interrupt pin instead of SDIO in-band interrupt. >> >> Add the device tree binding of this chip, in order to make it >possible >> to add this interrupt pin to device trees. >> >> Signed-off-by: Icenowy Zheng >> Acked-by: Rob Herring >> --- >> Changes in v3: >> - Renames the node name. >> - Adds ACK from Rob. >> Changes in v2: >> - Removed status property in example. >> - Added required property reg. >> >> .../bindings/net/wireless/allwinner,xr819.txt | 38 >++ >> 1 file changed, 38 insertions(+) >> create mode 100644 >Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt > >Like I asked already last time, AFAICS there is no upstream xr819 >wireless driver in drivers/net/wireless directory. Do we still accept >bindings like this for out-of-tree drivers? See esp8089. There's also no in-tree driver for it.
Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard 写到: >On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote: >> On 10/4/2017 11:03 AM, Icenowy Zheng wrote: >> > >> > >> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo >写到: >> > > Icenowy Zheng writes: >> > > >> > > > Allwinner XR819 is a SDIO Wi-Fi chip, which has the >functionality to >> > > use >> > > > an out-of-band interrupt pin instead of SDIO in-band interrupt. >> > > > >> > > > Add the device tree binding of this chip, in order to make it >> > > possible >> > > > to add this interrupt pin to device trees. >> > > > >> > > > Signed-off-by: Icenowy Zheng >> > > > Acked-by: Rob Herring >> > > > --- >> > > > Changes in v3: >> > > > - Renames the node name. >> > > > - Adds ACK from Rob. >> > > > Changes in v2: >> > > > - Removed status property in example. >> > > > - Added required property reg. >> > > > >> > > > .../bindings/net/wireless/allwinner,xr819.txt | 38 >> > > ++ >> > > > 1 file changed, 38 insertions(+) >> > > > create mode 100644 >> > > >Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt >> > > >> > > Like I asked already last time, AFAICS there is no upstream xr819 >> > > wireless driver in drivers/net/wireless directory. Do we still >accept >> > > bindings like this for out-of-tree drivers? >> > >> > See esp8089. >> > >> > There's also no in-tree driver for it. >> >> The question is whether we should. The above might be a precedent, >but it >> may not necessarily be the way to go. The commit message for esp8089 >seems >> to hint that there is intent to have an in-tree driver: >> >> """ >> Note that at this point there only is an out of tree driver for >this >> hardware, there is no clear timeline / path for merging this. >Still >> I believe it would be good to specify the binding for this in >tree >> now, so that any future migration to an in tree driver will not >cause >> compatiblity issues. >> >> Cc: Icenowy Zheng >> Signed-off-by: Hans de Goede >> Signed-off-by: Rob Herring >> """ >> >> Regardless the bindings are in principle independent of the kernel >and just >> describing hardware. I think there have been discussions to move the >> bindings to their own repository, but apparently it was decided >otherwise. > >Yeah, I guess especially how it could be merged with the cw1200 driver >would be very relevant to that commit log. The cw1200 driver seems to still have some legacy platform data. Maybe they should also be convert to DT. (Or maybe compatible = "allwinner,xr819" is enough, as xr819 is a specified variant of cw1200 family) > >Maxime
[PATCH] ARM: sun8i: r40: add watchdog device node
The R40 SoC has a watchdog like the one on A20, in the timer memory zone
(which is also the same on A20).
Add the device tree node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5a6745409ae..ddcb3fff4cd4 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -229,6 +229,11 @@
};
};
+ wdt: watchdog@1c20c90 {
+ compatible = "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
--
2.13.6
[PATCH] staging: rtl8723bs: hide "nolinked power save" info when not debugging
Currently the rtl8723bs driver will print "nolinked power save enter"
and "nolinked power save leave" per minute if it's not connected to any
network.
These messages are meaningless and annoying to regular users.
Hide them when it's not debugging.
Signed-off-by: Icenowy Zheng
---
drivers/staging/rtl8723bs/core/rtw_pwrctrl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
index 820a061506cc..80cf5a8b1557 100644
--- a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
+++ b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
@@ -34,7 +34,7 @@ void _ips_enter(struct adapter *padapter)
if (rf_off == pwrpriv->change_rfpwrstate) {
pwrpriv->bpower_saving = true;
- DBG_871X_LEVEL(_drv_always_, "nolinked power save enter\n");
+ DBG_871X("nolinked power save enter\n");
if (pwrpriv->ips_mode == IPS_LEVEL_2)
pwrpriv->bkeepfwalive = true;
@@ -73,7 +73,7 @@ int _ips_leave(struct adapter *padapter)
if (result == _SUCCESS) {
pwrpriv->rf_pwrstate = rf_on;
}
- DBG_871X_LEVEL(_drv_always_, "nolinked power save leave\n");
+ DBG_871X("nolinked power save leave\n");
DBG_871X("==> ips_leave.LED(0x%08x)...\n",
rtw_read32(padapter, 0x4c));
pwrpriv->bips_processing = false;
--
2.13.6
[PATCH 2/2] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 5cdaf52669e4..2e3a3ca087f7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include "ccu_common.h"
#include "ccu_div.h"
@@ -148,6 +149,11 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc
= {
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
+static bool sunxi_de2_clk_has_sram(const struct device_node *node)
+{
+ return of_device_is_compatible(node, "allwinner,sun50i-a64-de2-clk");
+}
+
static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
struct resource *res;
@@ -191,11 +197,20 @@ static int sunxi_de2_clk_probe(struct platform_device
*pdev)
return ret;
}
+ if (sunxi_de2_clk_has_sram(pdev->dev.of_node)) {
+ ret = sunxi_sram_claim(>dev);
+ if (ret) {
+ dev_err(>dev,
+ "Error couldn't map SRAM to device\n");
+ return ret;
+ }
+ }
+
/* The clocks need to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);
if (ret) {
dev_err(>dev, "Couldn't enable bus clk: %d\n", ret);
- return ret;
+ goto err_release_sram;
}
ret = clk_prepare_enable(mod_clk);
@@ -224,6 +239,10 @@ static int sunxi_de2_clk_probe(struct platform_device
*pdev)
clk_disable_unprepare(mod_clk);
err_disable_bus_clk:
clk_disable_unprepare(bus_clk);
+err_release_sram:
+ if (sunxi_de2_clk_has_sram(pdev->dev.of_node))
+ sunxi_sram_release(>dev);
+
return ret;
}
@@ -237,16 +256,13 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.data = _v3s_de2_clk_desc,
},
{
+ .compatible = "allwinner,sun50i-a64-de2-clk",
+ .data = _a64_de2_clk_desc,
+ },
+ {
.compatible = "allwinner,sun50i-h5-de2-clk",
.data = _a64_de2_clk_desc,
},
- /*
-* The Allwinner A64 SoC needs some bit to be poke in syscon to make
-* DE2 really working.
-* So there's currently no A64 compatible here.
-* H5 shares the same reset line with A64, so here H5 is using the
-* clock description of A64.
-*/
{ }
};
--
2.13.6
[PATCH 1/2] dt-bindings: add binding for A64 DE2 CCU with SRAM section
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed.
Add binding for this.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index 631d27cd89d6..8b1f86080d3d 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -5,6 +5,7 @@ Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
+ - "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
- reg: Must contain the registers base address and length
@@ -17,6 +18,10 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
+Additional required properties for "allwinner,sun50i-a64-de2-clk" :
+- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt,
+ should be the SRAM C section on A64 SoC.
+
Example:
de2_clocks: clock@100 {
compatible = "allwinner,sun8i-a83t-de2-clk";
--
2.13.6
[PATCH v2 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
From: Chen-Yu Tsai
The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change the MMC frequencies to conservative verified values.
- Add fallback R40 compatible for MMC.
arch/arm/boot/dts/sun8i-r40.dtsi | 407 +++
1 file changed, 407 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..5d365b72b893
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,407 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai
+ * Copyright 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-ce
[PATCH v2 0/3] Basical device tree parts for Allwinner R40 SoC
This patchset adds basical device tree parts for the Allwinner R40 SoC and two boards feature this SoC -- Banana Pi M2 Ultra and Berry (The BPi M2 Berry board uses V40 SoC, which is just a renamed R40). Chen-Yu Tsai (2): ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (1): ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry arch/arm/boot/dts/Makefile| 4 +- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++ arch/arm/boot/dts/sun8i-r40.dtsi | 407 ++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 + 4 files changed, 751 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts -- 2.13.5
[PATCH v2 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
From: Chen-Yu Tsai
The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
form factor and position of various connectors, leds and buttons is
similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
as the latest Banana Pi M64.
It features:
- X-Powers AXP221s PMIC connected to i2c0
- 2 GB DDR3 DRAM
- 8 GB eMMC
- micro SD card slot
- DC power jack
- HDMI output
- MIPI DSI connector
- 2x USB 2.0 hosts
- 1x USB 2.0 OTG
- gigabit ethernet with Realtek RTL8211E transceiver
- WiFi/Bluetooth with AP6212 chip, with external antenna connector
- SATA and power connectors for native SATA support
- camera sensor connector
- consumer IR receiver
- audio out headphone jack
- onboard microphone
- red, green, and blue LEDs
- debug UART pins
- Li-Po battery connector
- Raspberry Pi B+ compatible GPIO header
- power, reset, and boot control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++
2 files changed, 178 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9cf688d404b8..93b1e63a52af 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -939,6 +939,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-parrot.dtb \
+ sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index ..148427517819
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include
+
+/ {
+ model = "Banana Pi BPI-M2-Ultra";
+ compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ label = "bananapi:red:pwr";
+ gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ user-led-green {
+ label = "bananapi:green:user";
+ gpios = < 7 21 GPIO
[PATCH v2 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
The Banana Pi M2 Ultra is an SBC based on the Allwinner V40 SoC (same as
the R40 SoC). The form factor is similar to the Raspberry Pi series.
It features:
- X-Powers AXP221s PMIC connected to i2c0
- 1GiB DDR3 DRAM
- microSD slot
- MicroUSB Type-B port for power and connected to usb0
- HDMI output
- MIPI DSI connector
- 4 USB Type-A ports (connected to the usb1 controller via a hub)
- gigabit ethernet with Realtek RTL8211E transceiver
- WiFi/Bluetooth with AP6212 module, with external antenna connector
- SATA and power connectors for native SATA support
- camera sensor connector
- audio out headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 ++
2 files changed, 166 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 93b1e63a52af..da3f87b35059 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -941,7 +941,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
- sun8i-v3s-licheepi-zero-dock.dtb
+ sun8i-v3s-licheepi-zero-dock.dtb \
+ sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
new file mode 100644
index ..8a69be2a0842
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include
+
+/ {
+ model = "Banana Pi M2 Berry";
+ compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ label = "bananapi:red:pwr";
+ gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ user-led {
+ label = "bananapi:green:user";
+ gpios = < 7 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = < 6 10 GPIO_ACTIVE_LO
Re: [PATCH v2 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
于 2017年9月28日 GMT+08:00 下午11:12:25, Maxime Ripard
写到:
>On Thu, Sep 28, 2017 at 09:25:42AM +0000, Icenowy Zheng wrote:
>> + {
>> +vmmc-supply = <_dcdc1>;
>> +bus-width = <8>;
>> +non-removable;
>> +status = "okay";
>> +};
>
>I guess it's an emmc, it doesn't have a vqmmmc regulator?
vqmmc is also 3v3.
>
>Looks good otherwise, thanks!
>Maxime
Re: [PATCH v2 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
于 2017年9月28日 GMT+08:00 下午11:11:03, Maxime Ripard
写到:
>Hi,
>
>On Thu, Sep 28, 2017 at 09:25:41AM +, Icenowy Zheng wrote:
>> +/*
>> + * The max-frequency properties in all MMC controller nodes
>> + * are conservative values proven to work on Banana Pi M2
>> + * Ultra (the first community available R40 board).
>> + * As the board doesn't wire MMC3 out, the property is not
>> + * set in MMC3.
>> + * TODO: measure the accurate max frequency of the controllers.
>> + */
>> +mmc0: mmc@1c0f000 {
>> +compatible = "allwinner,sun8i-r40-mmc",
>> + "allwinner,sun50i-a64-mmc";
>> +reg = <0x01c0f000 0x1000>;
>> +clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
>> +clock-names = "ahb", "mmc";
>> +resets = < RST_BUS_MMC0>;
>> +reset-names = "ahb";
>> +pinctrl-0 = <_pins>;
>> +pinctrl-names = "default";
>> +interrupts = ;
>> +max-frequency = <2500>;
>> +status = "disabled";
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +};
>
>Sorry if it wasn't really clear, but my point was more than you should
>just drop the max-frequency property
Then set it in the boards' DTS?
>
>Maxime
Re: [linux-sunxi] Re: [PATCH] uas: ignore UAS for Norelsys NS1068(X) chips
于 2018年1月7日 GMT+08:00 上午6:12:57, Hans de Goede 写到: >Hi, > >On 05-01-18 17:56, Icenowy Zheng wrote: >> The UAS mode of Norelsys NS1068(X) is reported to fail to work on >> several platforms with the following error message: >> >> xhci-hcd xhci-hcd.0.auto: ERROR Transfer event for unknown stream >ring slot 1 ep 8 >> xhci-hcd xhci-hcd.0.auto: @bf04a400 >1b00 01098001 >> >> And when trying to mount a partition on the disk the disk will >> disconnect from the USB controller, then after re-connecting the >device >> will be offlined and not working at all. >> >> Falling back to USB mass storage can solve this problem, so ignore >UAS >> function of this chip. >> >> Cc: sta...@vger.kernel.org >> Signed-off-by: Icenowy Zheng > >A quick internet search shows various problems with this device even >under >Windows, so yes this seems like a good idea: > >Acked-by: Hans de Goede > >> The NS1066 chip from the same vendor seems to also suffer from this >> problem (its USB ID is 2537:1066) according to the report of Armbian >> community. However I don't have such device (I have a USB HDD >enclosure >> with USB ID 2537:1066, but it doesn't report UAS function at all; as >> it's > >If it has been reported to not work in uas mode then I think adding >the same quirk for the 1066 device-id is a good idea, can you please >submit a patch for that? I don't have such devices, although as Armbian suggests the 1066 device needs also to be blacklisted. Maybe we can wait for an unforunate NS1066 user to add the 1066 ID. > >Regards, > >Hans > > > >> >> The `lsusb -v` result of my NS1068X is shown below: >> >> Bus 004 Device 002: ID 2537:1068 >> Device Descriptor: >>bLength18 >>bDescriptorType 1 >>bcdUSB 3.00 >>bDeviceClass0 >>bDeviceSubClass 0 >>bDeviceProtocol 0 >>bMaxPacketSize0 9 >>idVendor 0x2537 >>idProduct 0x1068 >>bcdDevice1.00 >>iManufacturer 1 Norelsys >>iProduct2 NS1068 >>iSerial 3 0123456789ABCDE >>bNumConfigurations 1 >>Configuration Descriptor: >> bLength 9 >> bDescriptorType 2 >> wTotalLength 121 >> bNumInterfaces 1 >> bConfigurationValue 1 >> iConfiguration 0 >> bmAttributes 0xc0 >>Self Powered >> MaxPower2mA >> Interface Descriptor: >>bLength 9 >>bDescriptorType 4 >>bInterfaceNumber0 >>bAlternateSetting 0 >>bNumEndpoints 2 >>bInterfaceClass 8 >>bInterfaceSubClass 6 >>bInterfaceProtocol 80 >>iInterface 0 >>Endpoint Descriptor: >> bLength 7 >> bDescriptorType 5 >> bEndpointAddress 0x81 EP 1 IN >> bmAttributes2 >>Transfer TypeBulk >>Synch Type None >>Usage Type Data >> wMaxPacketSize 0x0400 1x 1024 bytes >> bInterval 0 >> bMaxBurst 15 >>Endpoint Descriptor: >> bLength 7 >> bDescriptorType 5 >> bEndpointAddress 0x02 EP 2 OUT >> bmAttributes2 >>Transfer TypeBulk >>Synch Type None >>Usage Type Data >> wMaxPacketSize 0x0400 1x 1024 bytes >> bInterval 0 >> bMaxBurst 15 >> Interface Descriptor: >>bLength 9 >>bDescriptorType 4 >>bInterfaceNumber0 >>bAlternateSetting 1 >>bNumEndpoints 4 >>bInterfaceClass 8 >>bInterfaceSubClass 6 >>bInterfaceProtocol 98 >>iInterface 0 >>Endpoint Descriptor: >> bLength 7 >> bDescriptorType 5 >> bEndpointAddress 0x83 EP 3 IN >> bmAttributes2
[PATCH] clk: sunxi-ng: defaultly enable DE2 CCU for sun8i/sun50i
As DE2 support for more SoCs are introducing, there's many reports that the DE2 is not functional due to DE2 CCU code not included in kernel. Defaultly enable DE2 CCU for sun8i/sun50i to reduce this kind of problems. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 6427d0ebe2de..c2b04dcb6f18 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -60,6 +60,8 @@ config SUN8I_V3S_CCU config SUN8I_DE2_CCU bool "Support for the Allwinner SoCs DE2 CCU" + default MACH_SUN8I || (ARM64 && ARCH_SUNXI) + depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST config SUN8I_R40_CCU bool "Support for the Allwinner R40 CCU" -- 2.14.2
Re: [linux-sunxi] Re: [PATCH 0/7] Initial Allwinner H6 support
在 2018年1月11日星期四 CST 下午5:36:39，Linus Walleij 写道： > On Sat, Jan 6, 2018 at 5:18 AM, Icenowy Zheng wrote: > > This patchset adds initial support for the Allwinner H6 SoC. > > Can I apply the pin control patches without the clock patches? I think it's OK. Note: on H6 now the pin controller do not depend on the CCU at all -- it only needs two oscillators now. > > Also waiting for Maxime and/or Chen-Yu to provide some review > before merging this. > > Yours, > Linus Walleij
Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
于 2018年1月11日 GMT+08:00 下午6:08:19, Andre Przywara 写到:
>Hi,
>
>On 06/01/18 04:23, Icenowy Zheng wrote:
>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>> have no bus gate clocks.
>>
>> Add support for this kind of pin controllers.
>>
>> Signed-off-by: Icenowy Zheng
>> ---
>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30
>--
>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
>> 2 files changed, 21 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> index 4b6cb25bc796..68cd505679d9 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct
>sunxi_pinctrl *pctl,
>> unsigned int hosc_div, losc_div;
>> struct clk *hosc, *losc;
>> u8 div, src;
>> -int i, ret;
>> +int i, ret, clk_count;
>> +
>> +if (pctl->desc->without_bus_gate)
>> +clk_count = 2;
>> +else
>> +clk_count = 3;
>>
>> /* Deal with old DTs that didn't have the oscillators */
>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") !=
>3)
>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct
>platform_device *pdev,
>> goto gpiochip_error;
>> }
>>
>> -clk = devm_clk_get(>dev, NULL);
>> -if (IS_ERR(clk)) {
>> -ret = PTR_ERR(clk);
>> -goto gpiochip_error;
>> -}
>> +if (!desc->without_bus_gate) {
>
>Do we really need explicit support for that case?
>Can't we have something that works automatically?
It can be a sanity check. When a SoC comes with bus gate
support but no apb is provided, there's something wrong.
>
>if (node has clock-names property) (A)
> use clocks as enumerated and named there
>else if (node has one clock reference) (B)
> use this as gate clock, no debounce support
>else if (node has no clock property at all)(C)
> no gate clock needed, no debounce support
This should not happen in practice, as no gate clock is implemented
after debounce.
>
>On top of that we should add the clock-names property to all DTs, even
>for those with only a "apb" clock. Shouldn't hurt existing kernels.
>Possibly even add debounce support for those on the way, if applicable.
>
>So we would just support case (B) and (C) for legacy reasons.
>
>Does that make sense?
>
>Cheers,
>Andre.
>
>> +clk = devm_clk_get(>dev, NULL);
>> +if (IS_ERR(clk)) {
>> +ret = PTR_ERR(clk);
>> +goto gpiochip_error;
>> +}
>>
>> -ret = clk_prepare_enable(clk);
>> -if (ret)
>> -goto gpiochip_error;
>> +ret = clk_prepare_enable(clk);
>> +if (ret)
>> +goto gpiochip_error;
>> +} else {
>> +clk = NULL;
>> +}
>>
>> pctl->irq = devm_kcalloc(>dev,
>> pctl->desc->irq_banks,
>> @@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct
>platform_device *pdev,
>> return 0;
>>
>> clk_error:
>> -clk_disable_unprepare(clk);
>> +if (clk)
>> +clk_disable_unprepare(clk);
>> gpiochip_error:
>> gpiochip_remove(pctl->chip);
>> return ret;
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> index 11b128f54ed2..ccb6230f0bb5 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> @@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
>> unsignedirq_bank_base;
>> boolirq_read_needs_mux;
>> booldisable_strict_mode;
>> +boolwithout_bus_gate;
>> };
>>
>> struct sunxi_pinctrl_function {
>>
Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
在 2018年1月11日星期四 CST 下午6:41:00，Maxime Ripard 写道：
> On Thu, Jan 11, 2018 at 10:23:52AM +, Andre Przywara wrote:
> > Hi,
> >
> > On 11/01/18 10:14, Chen-Yu Tsai wrote:
> > > On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara
wrote:
> > >> Hi,
> > >>
> > >> On 06/01/18 04:23, Icenowy Zheng wrote:
> > >>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> > >>> have no bus gate clocks.
> > >>>
> > >>> Add support for this kind of pin controllers.
> > >>>
> > >>> Signed-off-by: Icenowy Zheng
> > >>> ---
> > >>>
> > >>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30
> > >>> --
> > >>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
> > >>> 2 files changed, 21 insertions(+), 10 deletions(-)
> > >>>
> > >>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > >>> b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index
> > >>> 4b6cb25bc796..68cd505679d9 100644
> > >>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > >>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > >>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct
> > >>> sunxi_pinctrl *pctl,> >>>
> > >>> unsigned int hosc_div, losc_div;
> > >>> struct clk *hosc, *losc;
> > >>> u8 div, src;
> > >>>
> > >>> - int i, ret;
> > >>> + int i, ret, clk_count;
> > >>> +
> > >>> + if (pctl->desc->without_bus_gate)
> > >>> + clk_count = 2;
> > >>> + else
> > >>> + clk_count = 3;
> > >>>
> > >>> /* Deal with old DTs that didn't have the oscillators */
> > >>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells")
> > >>> != 3)
> > >>>
> > >>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct
> > >>> platform_device *pdev,> >>>
> > >>> goto gpiochip_error;
> > >>>
> > >>> }
> > >>>
> > >>> - clk = devm_clk_get(>dev, NULL);
> > >>> - if (IS_ERR(clk)) {
> > >>> - ret = PTR_ERR(clk);
> > >>> - goto gpiochip_error;
> > >>> - }
> > >>> + if (!desc->without_bus_gate) {
> > >>
> > >> Do we really need explicit support for that case?
> > >> Can't we have something that works automatically?
> > >>
> > >> if (node has clock-names property) (A)
> > >>
> > >> use clocks as enumerated and named there
> > >
> > > You still need to know if the hardware has a bus gate or not.
> > > If it's missing, and it's disabled, you end up with unusable
> > > hardware.
> >
> > Yes. So what? If you have a broken DT, it will not work. Just don't do
> > it. I don't understand why we want to defend against this case.
>
> This is not the point, but rather: if we have a way to detect easily
> that the device tree is missing a property that is missing in our
> binding, why shouldn't we do it?
>
> We're already doing it for reg and interrupts for example, why not for
> the clocks?
>
> > > Unless you are fully trusting the device tree to be correct.
> >
> > Sorry, but what else do we trust?
> >
> > > IMHO that makes for hard to find bugs during SoC bringup.
> >
> > I am not sure if that is really an issue. I would expect people
> > doing SoC bringup to be able to cope with those kinds of problems.
>
> Rght, because it worked so well in the past. We definitely didn't
> overlooked some clocks used for debouncing in this particular driver,
> or some to get the timekeeping right in the RTC.
>
> The argument that "anyone who codes in the kernel should just know
> better" doesn't work, on multiple levels. Because anyone that actually
> knows better can make a mistake or overlook some feature (because you
> didn't have your morning coffee yet, or because it was undocumented)
> and because you just make someone that doesn't feel bad.
I agree it here -- when I'm doing initial trial on H6 I didn't found that apb
gate is missing ;-)
>
> So, yes, we cannot not trust the device tree. But if we have a way to
> detect simple mistakes in the binding, we should also do it.
>
> Maxime
Re: [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
于 2018年1月11日 GMT+08:00 下午7:48:40, Andre Przywara 写到:
>Hi,
>
>another take to avoid this patch at all, I just remembered this from an
>IRC discussion before:
>
>On 06/01/18 04:23, Icenowy Zheng wrote:
>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>> have no bus gate clocks.
>
>I don't think this is true. The pin controller *needs* an APB clock,
>it's just not gate-able or not exposed or documented.
>The "system bus tree" on page 90 in the manual shows that the "GPIO"
>block is located on the APB1 bus.
>So can't we just reference this apb clock directly? That would be much
>cleaner, "more" correct and require less changes: "The best patch is no
>patch":
I can accept this. (In fact I have considered this, but
I don't dare to directly use bus clock in a device, as it's not
exported before.
Maxime, Chen-Yu, can you agree the following code?
>
> clocks = < APB1>, <>, <>;
> /* or whatever this APB clock is actually called. */
> clock-names = "apb", "hosc", "losc";
>
>Cheers,
>Andre.
>
>>
>> Add support for this kind of pin controllers.
>>
>> Signed-off-by: Icenowy Zheng
>> ---
>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30
>--
>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
>> 2 files changed, 21 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> index 4b6cb25bc796..68cd505679d9 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct
>sunxi_pinctrl *pctl,
>> unsigned int hosc_div, losc_div;
>> struct clk *hosc, *losc;
>> u8 div, src;
>> -int i, ret;
>> +int i, ret, clk_count;
>> +
>> +if (pctl->desc->without_bus_gate)
>> +clk_count = 2;
>> +else
>> +clk_count = 3;
>>
>> /* Deal with old DTs that didn't have the oscillators */
>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") !=
>3)
>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct
>platform_device *pdev,
>> goto gpiochip_error;
>> }
>>
>> -clk = devm_clk_get(>dev, NULL);
>> -if (IS_ERR(clk)) {
>> -ret = PTR_ERR(clk);
>> -goto gpiochip_error;
>> -}
>> +if (!desc->without_bus_gate) {
>> +clk = devm_clk_get(>dev, NULL);
>> +if (IS_ERR(clk)) {
>> +ret = PTR_ERR(clk);
>> +goto gpiochip_error;
>> +}
>>
>> -ret = clk_prepare_enable(clk);
>> -if (ret)
>> -goto gpiochip_error;
>> +ret = clk_prepare_enable(clk);
>> +if (ret)
>> +goto gpiochip_error;
>> +} else {
>> +clk = NULL;
>> +}
>>
>> pctl->irq = devm_kcalloc(>dev,
>> pctl->desc->irq_banks,
>> @@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct
>platform_device *pdev,
>> return 0;
>>
>> clk_error:
>> -clk_disable_unprepare(clk);
>> +if (clk)
>> +clk_disable_unprepare(clk);
>> gpiochip_error:
>> gpiochip_remove(pctl->chip);
>> return ret;
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> index 11b128f54ed2..ccb6230f0bb5 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> @@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
>> unsignedirq_bank_base;
>> boolirq_read_needs_mux;
>> booldisable_strict_mode;
>> +boolwithout_bus_gate;
>> };
>>
>> struct sunxi_pinctrl_function {
>>
>
>___
>linux-arm-kernel mailing list
>linux-arm-ker...@lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
[PATCH] pinctrl: sunxi: add support for Allwinner H6 main pin controller
Allwinner H6 SoC has two pin controllers like other Allwinner SoCs with
ARISC: one main pin controller (called CPUX-PORT in user manual) and one
pin controller in the CPUs power domain (called CPUS-PORT in user
manual).
This commit adds support for the main pin controller in the H6 SoC.
Signed-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 525 +
4 files changed, 531 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 09789fdfa749..ed5eb547afc8 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -27,6 +27,7 @@ Required properties:
"allwinner,sun50i-a64-pinctrl"
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
+ "allwinner,sun50i-h6-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index bfce99d86dfc..5de1f63b07bb 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -77,4 +77,8 @@ config PINCTRL_SUN50I_H5
def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H6
+ def_bool ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 12a752e836ef..3c4aec6611e9 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3)+=
pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S)+= pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5)+= pinctrl-sun50i-h5.o
+obj-$(CONFIG_PINCTRL_SUN50I_H6)+= pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
new file mode 100644
index ..468f77baa17c
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
@@ -0,0 +1,525 @@
+/*
+ * Allwinner H6 SoC pinctrl driver.
+ *
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin h6_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* DS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RE */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
+ SUN
Re: [PATCH v2 11/18] drm/sun4i: Add A83T support
在 2017-11-28 17:02，Maxime Ripard 写道：
Hi,
On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard
napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
> drivers/gpu/drm/sun4i/sun4i_drv.c | 2 ++
> drivers/gpu/drm/sun4i/sun4i_tcon.c| 5 +
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 4
> 4 files changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
> d4259a4f5171..d6b52e5c48c0 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -93,6 +93,7 @@ Required properties:
> * allwinner,sun6i-a31s-tcon
> * allwinner,sun7i-a20-tcon
> * allwinner,sun8i-a33-tcon
> + * allwinner,sun8i-a83t-tcon-lcd
> * allwinner,sun8i-v3s-tcon
> - reg: base address and size of memory-mapped region
> - interrupts: interrupt associated to this IP
> @@ -224,6 +225,7 @@ supported.
>
> Required properties:
>- compatible: value must be one of:
> +* allwinner,sun8i-a83t-de2-mixer
What will be the name of the second mixer, once support for HDMI is
added?
Should we start directly with 0 and 1 postfix ?
What are the differences exactly without the two mixers?
I was hoping to be able to cover them all using properties, indices
are usually pretty badly received in compatibles.
1. VEP is only available on the VI channel in mixer0. (VEP may mean
Video Enhance Processor)
2. Smart Backlight is only available in mixer0's on SoCs with LCD.
3. Writeback function is only available in mixer0.
> static const struct of_device_id sun8i_mixer_of_table[] = {
>{
> + .compatible = "allwinner,sun8i-a83t-de2-mixer",
> + .data = _v3s_mixer_cfg,
> + },
> + {
Maybe you want to squash 12 patch since this works only by luck.
Yeah, I totally meant to do that :)
Thanks!
Maxime
Re: [PATCH 12/17] drm/sun4i: Add CCSC property to DE2 configuration
在 2017-11-28 04:57，Jernej Skrabec 写道：
Base addresses of channel output CSC (CCSC) depends whether mixer in
question is first or second and if it is second, if supports VEP or
not.
This new property will tell which set of base addresses to take.
0 - first mixer or second mixer with VEP support
1 - second mixer without VEP support
Maxime,
I think here the ID of the mixer matters.
P.S. I didn't found any SoC with a second mixer with VEP currently
Thanks!
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 1 +
drivers/gpu/drm/sun4i/sun8i_mixer.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 7c9c87a0535b..2276eff8798d 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -622,6 +622,7 @@ static const struct sun8i_mixer_cfg
sun8i_v3s_mixer_cfg = {
.vi_num = 2,
.ui_num = 1,
.scaler_mask = 0x3,
+ .ccsc = 0,
Jernej, the lowlevel_sun8iw8/de_feat.c in the BSP DE2 source code
claims that V3/V3s have no VEP support even for mixer0.
};
static const struct of_device_id sun8i_mixer_of_table[] = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h
b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 355a45e6cfb4..4fcf1653e345 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -136,6 +136,7 @@ struct sun8i_mixer_cfg {
int vi_num;
int ui_num;
int scaler_mask;
+ int ccsc;
};
struct sun8i_mixer {
Re: [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
于 2018年1月5日 GMT+08:00 上午2:52:10, Maxime Ripard 写到: >On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej Škrabec wrote: >> Hi Rob, >> >> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a): >> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote: >> > > This commit adds all necessary compatibles and descriptions >needed to >> > > implement A83T HDMI pipeline. >> > > >> > > Mixer is already properly described, so only compatible is added. >> > > >> > > However, A83T TCON1, which is connected to HDMI, doesn't have >channel 0, >> > > contrary to all TCONs currently described. Because of that, TCON >> > > documentation is extended. >> > > >> > > A83T features Synopsys DW HDMI controller with a custom PHY which >looks >> > > like Synopsys Gen2 PHY with few additions. Since there is no >> > > documentation, needed properties were found out through >experimentation >> > > and reading BSP code. >> > > >> > > At the end, example is added for newer SoCs, which features DE2 >and DW >> > > HDMI. >> > > >> > > Signed-off-by: Jernej Skrabec >> > > --- >> > > >> > > .../bindings/display/sunxi/sun4i-drm.txt | 188 >> > > - 1 file changed, 181 insertions(+), 7 >deletions(-) >> > > >> > > diff --git >a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >index >> > > 9f073af4c711..3eca258096a5 100644 >> > > --- >a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > > +++ >b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > > >> > > @@ -64,6 +64,40 @@ Required properties: >> > > first port should be the input endpoint. The second should >be the >> > > output, usually to an HDMI connector. >> > > >> > > +DWC HDMI TX Encoder >> > > +- >> > > + >> > > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX >controller IP >> > > +with Allwinner's own PHY IP. It supports audio and video outputs >and CEC. >> > > + >> > > +These DT bindings follow the Synopsys DWC HDMI TX bindings >defined in >> > > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt >with the >> > > +following device-specific properties. >> > > + >> > > +Required properties: >> > > + >> > > + - compatible: value must be one of: >> > > +* "allwinner,sun8i-a83t-dw-hdmi" >> > > + - reg: two pairs of base address and size of memory-mapped >region, >> > > first >> > > +for controller and second for PHY >> > > +registers. >> > >> > Seems like the phy should be a separate node and use the phy >binding. >> > You can use the phy binding even if you don't use the kernel phy >> > framework... >> >> Unfortunately, it's not so straighforward. Phy is actually accessed >through >> I2C implemented in HDMI controller. Second memory region in this case >has >> small influence on phy. However, it has big influence on controller. >For >> example, magic number has to be written in one register in second >memory >> region in order to unlock read access to any register from first >memory region >> (controller). However, they shouldn't be merged to one region, >because first >> memory region requires byte access while second memory region can be >accessed >> per byte or word. >> >> To complicate things more, later I want to add support for another >SoC which >> has same glue layer (unlocking read access, etc.) and uses memory >mapped phy >> registers in second memory region. >> >> I think current binding is the least complicated way to represent >this. > >I agree with Rob here. I did a similar thing for the DSI patches I've >sent a few monthes ago and it turned out to not be that difficult, so >I'm sure you can come up with something :) In A83T/H3/A64/H5/R40 this part is not purely a PHY. It controls the access of main controller's register (e.g. read/write lock and register obfuscation). So it should be called a "glue" with PHY part (and on A83T seems a pure glue) but not a simple PHY. > >Maxime > >-- >Maxime Ripard, Free Electrons >Embedded Linux and Kernel engineering >http://free-electrons.com > >___ >linux-arm-kernel mailing list >linux-arm-ker...@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
于 2018年1月4日 GMT+08:00 上午5:32:26, "Jernej Škrabec" 写到: >Hi Rob, > >Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a): >> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote: >> > This commit adds all necessary compatibles and descriptions needed >to >> > implement A83T HDMI pipeline. >> > >> > Mixer is already properly described, so only compatible is added. >> > >> > However, A83T TCON1, which is connected to HDMI, doesn't have >channel 0, >> > contrary to all TCONs currently described. Because of that, TCON >> > documentation is extended. >> > >> > A83T features Synopsys DW HDMI controller with a custom PHY which >looks >> > like Synopsys Gen2 PHY with few additions. Since there is no >> > documentation, needed properties were found out through >experimentation >> > and reading BSP code. >> > >> > At the end, example is added for newer SoCs, which features DE2 and >DW >> > HDMI. >> > >> > Signed-off-by: Jernej Skrabec >> > --- >> > >> > .../bindings/display/sunxi/sun4i-drm.txt | 188 >> > - 1 file changed, 181 insertions(+), 7 >deletions(-) >> > >> > diff --git >a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >index >> > 9f073af4c711..3eca258096a5 100644 >> > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > >> > @@ -64,6 +64,40 @@ Required properties: >> > first port should be the input endpoint. The second should be >the >> > output, usually to an HDMI connector. >> > >> > +DWC HDMI TX Encoder >> > +- >> > + >> > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX >controller IP >> > +with Allwinner's own PHY IP. It supports audio and video outputs >and CEC. >> > + >> > +These DT bindings follow the Synopsys DWC HDMI TX bindings defined >in >> > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with >the >> > +following device-specific properties. >> > + >> > +Required properties: >> > + >> > + - compatible: value must be one of: >> > +* "allwinner,sun8i-a83t-dw-hdmi" >> > + - reg: two pairs of base address and size of memory-mapped >region, >> > first >> > +for controller and second for PHY >> > +registers. >> >> Seems like the phy should be a separate node and use the phy binding. >> You can use the phy binding even if you don't use the kernel phy >> framework... > >Unfortunately, it's not so straighforward. Phy is actually accessed >through >I2C implemented in HDMI controller. Second memory region in this case >has >small influence on phy. However, it has big influence on controller. To be honest you used inaccurate word. Use "glue" directly here may be more accurate. >For >example, magic number has to be written in one register in second >memory >region in order to unlock read access to any register from first memory >region >(controller). However, they shouldn't be merged to one region, because >first >memory region requires byte access while second memory region can be >accessed >per byte or word. > >To complicate things more, later I want to add support for another SoC >which >has same glue layer (unlocking read access, etc.) and uses memory >mapped phy >registers in second memory region. > >I think current binding is the least complicated way to represent this. > >> >> > + - reg-io-width: See dw_hdmi.txt. Shall be 1. >> > + - interrupts: HDMI interrupt number >> > + - clocks: phandles to the clocks feeding the HDMI encoder >> > +* iahb: the HDMI bus clock >> > +* isfr: the HDMI register clock >> > +* tmds: the HDMI tmds clock >> > + - clock-names: the clock names mentioned above >> > + - resets: phandles to the reset controllers driving the encoder >> > +* ctrl: the reset line for the controller >> > +* phy: the reset line for the PHY >> > + - reset-names: the reset names mentioned above >> > + >> > + - ports: A ports node with endpoint definitions as defined in >> > +Documentation/devicetree/bindings/media/video-interfaces.txt. >The >> > +first port should be the input endpoint. The second should be >the >> > +output, usually to an HDMI connector. >> > + >> > >> > TV Encoder >> > -- >> > >> > @@ -94,18 +128,17 @@ Required properties: >> > * allwinner,sun7i-a20-tcon >> > * allwinner,sun8i-a33-tcon >> > * allwinner,sun8i-a83t-tcon-lcd >> > >> > + * allwinner,sun8i-a83t-tcon-tv >> > >> > * allwinner,sun8i-v3s-tcon >> > >> > - reg: base address and size of memory-mapped region >> > - interrupts: interrupt associated to this IP >> > >> > - - clocks: phandles to the clocks feeding the TCON. Three are >needed: >> > >> > + - clocks: phandles to the clocks feeding the TCON. One is needed: >> > - 'ahb': the interface clocks >> > >> > - - 'tcon-ch0': The clock driving the TCON channel 0
[PATCH] uas: ignore UAS for Norelsys NS1068(X) chips
The UAS mode of Norelsys NS1068(X) is reported to fail to work on several platforms with the following error message: xhci-hcd xhci-hcd.0.auto: ERROR Transfer event for unknown stream ring slot 1 ep 8 xhci-hcd xhci-hcd.0.auto: @bf04a400 1b00 01098001 And when trying to mount a partition on the disk the disk will disconnect from the USB controller, then after re-connecting the device will be offlined and not working at all. Falling back to USB mass storage can solve this problem, so ignore UAS function of this chip. Cc: sta...@vger.kernel.org Signed-off-by: Icenowy Zheng --- The NS1066 chip from the same vendor seems to also suffer from this problem (its USB ID is 2537:1066) according to the report of Armbian community. However I don't have such device (I have a USB HDD enclosure with USB ID 2537:1066, but it doesn't report UAS function at all; as it's The `lsusb -v` result of my NS1068X is shown below: Bus 004 Device 002: ID 2537:1068 Device Descriptor: bLength18 bDescriptorType 1 bcdUSB 3.00 bDeviceClass0 bDeviceSubClass 0 bDeviceProtocol 0 bMaxPacketSize0 9 idVendor 0x2537 idProduct 0x1068 bcdDevice1.00 iManufacturer 1 Norelsys iProduct2 NS1068 iSerial 3 0123456789ABCDE bNumConfigurations 1 Configuration Descriptor: bLength 9 bDescriptorType 2 wTotalLength 121 bNumInterfaces 1 bConfigurationValue 1 iConfiguration 0 bmAttributes 0xc0 Self Powered MaxPower2mA Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber0 bAlternateSetting 0 bNumEndpoints 2 bInterfaceClass 8 bInterfaceSubClass 6 bInterfaceProtocol 80 iInterface 0 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x81 EP 1 IN bmAttributes2 Transfer TypeBulk Synch Type None Usage Type Data wMaxPacketSize 0x0400 1x 1024 bytes bInterval 0 bMaxBurst 15 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x02 EP 2 OUT bmAttributes2 Transfer TypeBulk Synch Type None Usage Type Data wMaxPacketSize 0x0400 1x 1024 bytes bInterval 0 bMaxBurst 15 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber0 bAlternateSetting 1 bNumEndpoints 4 bInterfaceClass 8 bInterfaceSubClass 6 bInterfaceProtocol 98 iInterface 0 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x83 EP 3 IN bmAttributes2 Transfer TypeBulk Synch Type None Usage Type Data wMaxPacketSize 0x0400 1x 1024 bytes bInterval 0 bMaxBurst 15 MaxStreams 8 Status pipe (0x02) Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x06 EP 6 OUT bmAttributes2 Transfer TypeBulk Synch Type None Usage Type Data wMaxPacketSize 0x0400 1x 1024 bytes bInterval 0 bMaxBurst 15 Command pipe (0x01) Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x84 EP 4 IN bmAttributes2 Transfer TypeBulk Synch Type None Usage Type Data wMaxPacketSize 0x0400 1x 1024 bytes bInterval 0 bMaxBurst 15 MaxStreams 8 Data-in pipe (0x03) Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x05 EP 5 OUT bmAttributes2 Transfer TypeBulk Synch Type None Usage Type Data wMaxPacketSize 0x0400 1x 1024 bytes bInterval 0 bMaxBurst 15 MaxStreams
[PATCH 0/7] Initial Allwinner H6 support
This patchset adds initial support for the Allwinner H6 SoC. It's quite different from earlier Allwinner SoCs. For example, the memory map is refactored, and the CCU is rearranged. It's also the first Allwinner SoC with PCI Express interface, and the second one with USB 3.0 (the first one is A80). This patchset adds the most basical support for it, including the main pin controller, the main CCU and the basical device tree. Icenowy Zheng (7): pinctrl: sunxi: add support for pin controllers without bus gate pinctrl: sunxi: support pin controllers with holes among IRQ banks pinctrl: sunxi: add support for the Allwinner H6 main pin controller clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: add support for the Allwinner H6 CCU arm64: allwinner: h6: add the basical Allwinner H6 DTSI file arm64: allwinner: h6: add support for Pine H64 board .../devicetree/bindings/clock/sunxi-ccu.txt|1 + .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt |4 +- arch/arm64/boot/dts/allwinner/Makefile |1 + .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 66 ++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 214 drivers/clk/sunxi-ng/Kconfig |5 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 1206 drivers/clk/sunxi-ng/ccu-sun50i-h6.h | 63 + drivers/clk/sunxi-ng/ccu_nkmp.c| 20 +- drivers/clk/sunxi-ng/ccu_nkmp.h|2 + drivers/pinctrl/sunxi/Kconfig |4 + drivers/pinctrl/sunxi/Makefile |1 + drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 679 +++ drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c |4 +- drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c |4 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 46 +- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 42 +- include/dt-bindings/clock/sun50i-h6-ccu.h | 159 +++ include/dt-bindings/reset/sun50i-h6-ccu.h | 110 ++ 20 files changed, 2595 insertions(+), 37 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6.h create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c create mode 100644 include/dt-bindings/clock/sun50i-h6-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h6-ccu.h -- 2.14.2
[PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
The Allwinner H6 pin controllers (both the main one and the CPUs one)
have no bus gate clocks.
Add support for this kind of pin controllers.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 --
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 4b6cb25bc796..68cd505679d9 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct
sunxi_pinctrl *pctl,
unsigned int hosc_div, losc_div;
struct clk *hosc, *losc;
u8 div, src;
- int i, ret;
+ int i, ret, clk_count;
+
+ if (pctl->desc->without_bus_gate)
+ clk_count = 2;
+ else
+ clk_count = 3;
/* Deal with old DTs that didn't have the oscillators */
if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
@@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct
platform_device *pdev,
goto gpiochip_error;
}
- clk = devm_clk_get(>dev, NULL);
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
- goto gpiochip_error;
- }
+ if (!desc->without_bus_gate) {
+ clk = devm_clk_get(>dev, NULL);
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ goto gpiochip_error;
+ }
- ret = clk_prepare_enable(clk);
- if (ret)
- goto gpiochip_error;
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ goto gpiochip_error;
+ } else {
+ clk = NULL;
+ }
pctl->irq = devm_kcalloc(>dev,
pctl->desc->irq_banks,
@@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct
platform_device *pdev,
return 0;
clk_error:
- clk_disable_unprepare(clk);
+ if (clk)
+ clk_disable_unprepare(clk);
gpiochip_error:
gpiochip_remove(pctl->chip);
return ret;
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 11b128f54ed2..ccb6230f0bb5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
unsignedirq_bank_base;
boolirq_read_needs_mux;
booldisable_strict_mode;
+ boolwithout_bus_gate;
};
struct sunxi_pinctrl_function {
--
2.14.2
[PATCH 2/7] pinctrl: sunxi: support pin controllers with holes among IRQ banks
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. This
situation cannot be processed with the current pinctrl IRQ code, as it
only expects a offset to all IRQ banks.
Update the code to use a logical IRQ bank to hardware IRQ bank map, so
the new situation in H6 main pin controller can be processed. The old
special situation which uses a constant offset (on A33 and V3s, both
with a offset of 1) can be also processed with the new code.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 4 ++-
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 4 ++-
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 16 ++--
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 41 +--
4 files changed, 42 insertions(+), 23 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
index da387211a75e..f043afa1aac5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -481,11 +481,13 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = {
SUNXI_FUNCTION(0x3, "uart3")),/* CTS */
};
+static const unsigned int sun8i_a33_pinctrl_irq_bank_map[] = { 1, 2 };
+
static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
.pins = sun8i_a33_pins,
.npins = ARRAY_SIZE(sun8i_a33_pins),
.irq_banks = 2,
- .irq_bank_base = 1,
+ .irq_bank_map = sun8i_a33_pinctrl_irq_bank_map,
.disable_strict_mode = true,
};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
index 496ba34e1f5f..6704ce8e5e3d 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
@@ -293,11 +293,13 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
};
+static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 };
+
static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
- .irq_bank_base = 1,
+ .irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map,
.irq_read_needs_mux = true
};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 68cd505679d9..67ceb40fcb86 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -832,7 +832,7 @@ static void sunxi_pinctrl_irq_release_resources(struct
irq_data *d)
static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
+ u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_map);
u8 index = sunxi_irq_cfg_offset(d->hwirq);
unsigned long flags;
u32 regval;
@@ -880,7 +880,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 status_reg = sunxi_irq_status_reg(d->hwirq,
- pctl->desc->irq_bank_base);
+ pctl->desc->irq_bank_map);
u8 status_idx = sunxi_irq_status_offset(d->hwirq);
/* Clear the IRQ */
@@ -890,7 +890,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d)
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
+ u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_map);
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
unsigned long flags;
u32 val;
@@ -907,7 +907,7 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
+ u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_map);
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
unsigned long flags;
u32 val;
@@ -999,7 +999,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
if (bank == pctl->desc->irq_banks)
return;
- reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
+ reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_map);
val = readl(pctl->membase + reg);
if (val) {
@@ -1237,7 +1237,7 @@ static int sunxi_pinctrl_setup_debounce(struct
sunxi_pinctrl *pctl,
write
[PATCH 3/7] pinctrl: sunxi: add support for the Allwinner H6 main pin controller
The Allwinner H6 SoC has two pin controllers, one main controller
(called CPUX-PORT in user manual) and one controller in CPUs power
domain (called CPUS-PORT in user manual).
This commit introduces support for the main pin controller on H6.
The pin bank A and B are not wired out and hidden from the SoC's
documents, however it's shown that the "ATE" (an AC200 chip
co-packaged with the H6 die) is connected to the main SoC die via these
pin banks. The information about these banks is just copied from the BSP
pinctrl driver, but re-formatted to fit the mainline pinctrl driver
format.
Signed-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 4 +-
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 679 +
4 files changed, 687 insertions(+), 1 deletion(-)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 09789fdfa749..4523e658b9f2 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -27,6 +27,7 @@ Required properties:
"allwinner,sun50i-a64-pinctrl"
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
+ "allwinner,sun50i-h6-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
@@ -39,7 +40,8 @@ Required properties:
Note: For backward compatibility reasons, the hosc and losc clocks are only
required if you need to use the optional input-debounce property. Any new
-device tree should set them.
+device tree should set them. For the pin controllers on Allwinner H6 SoC,
+there's no APB bus gate, and the "apb" clock should be omitted.
Optional properties:
- input-debounce: Array of debouncing periods in microseconds. One period per
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index bfce99d86dfc..5de1f63b07bb 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -77,4 +77,8 @@ config PINCTRL_SUN50I_H5
def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H6
+ def_bool ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 12a752e836ef..3c4aec6611e9 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3)+=
pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S)+= pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5)+= pinctrl-sun50i-h5.o
+obj-$(CONFIG_PINCTRL_SUN50I_H6)+= pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
new file mode 100644
index ..bfc5df8719d8
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
@@ -0,0 +1,679 @@
+/*
+ * Allwinner H6 SoC pinctrl driver.
+ *
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin h6_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION
[PATCH 4/7] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.
Add fixed post divider support to the NKMP style clocks.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu_nkmp.c | 20 +---
drivers/clk/sunxi-ng/ccu_nkmp.h | 2 ++
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index e58c95787f94..497ac20deb19 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -81,7 +81,7 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
- unsigned long n, m, k, p;
+ unsigned long n, m, k, p, rate;
u32 reg;
reg = readl(nkmp->common.base + nkmp->common.reg);
@@ -107,7 +107,11 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw
*hw,
p = reg >> nkmp->p.shift;
p &= (1 << nkmp->p.width) - 1;
- return (parent_rate * n * k >> p) / m;
+ rate = (parent_rate * n * k >> p) / m;
+ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= nkmp->fixed_post_div;
+
+ return rate;
}
static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -116,6 +120,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned
long rate,
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
struct _ccu_nkmp _nkmp;
+ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate *= nkmp->fixed_post_div;
+
_nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
_nkmp.min_k = nkmp->k.min ?: 1;
@@ -127,7 +134,11 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw,
unsigned long rate,
ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
- return *parent_rate * _nkmp.n * _nkmp.k / (_nkmp.m * _nkmp.p);
+ rate = *parent_rate * _nkmp.n * _nkmp.k / (_nkmp.m * _nkmp.p);
+ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate = rate / nkmp->fixed_post_div;
+
+ return rate;
}
static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -138,6 +149,9 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned
long rate,
unsigned long flags;
u32 reg;
+ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate = rate * nkmp->fixed_post_div;
+
_nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
_nkmp.min_k = nkmp->k.min ?: 1;
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h
index a82facbc6144..6940503e7fc4 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.h
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
@@ -34,6 +34,8 @@ struct ccu_nkmp {
struct ccu_div_internal m;
struct ccu_div_internal p;
+ unsigned intfixed_post_div;
+
struct ccu_common common;
};
--
2.14.2
[PATCH 5/7] clk: sunxi-ng: add support for the Allwinner H6 CCU
The Allwinner H6 SoC has a CCU which has been largely rearranged.
Add support for it in the sunxi-ng CCU framework.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-ccu.txt|1 +
drivers/clk/sunxi-ng/Kconfig |5 +
drivers/clk/sunxi-ng/Makefile |1 +
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 1206
drivers/clk/sunxi-ng/ccu-sun50i-h6.h | 63 +
include/dt-bindings/clock/sun50i-h6-ccu.h | 159 +++
include/dt-bindings/reset/sun50i-h6-ccu.h | 110 ++
7 files changed, 1545 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6.h
create mode 100644 include/dt-bindings/clock/sun50i-h6-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h6-ccu.h
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 4ca21c3a6fc9..9ae27881c924 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -20,6 +20,7 @@ Required properties :
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
+ - "allwinner,sun50i-h6-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 6427d0ebe2de..4bc196a49b12 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -11,6 +11,11 @@ config SUN50I_A64_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_H6_CCU
+ bool "Support for the Allwinner H6 CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN4I_A10_CCU
bool "Support for the Allwinner A10/A20 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 4141c3fe08ae..128a40ee5c5e 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -22,6 +22,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o
# SoC support
obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
+obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
new file mode 100644
index ..18a1e08e7260
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -0,0 +1,1206 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-h6.h"
+
+/*
+ * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
+ * P should only be used for output frequencies lower than 288 MHz.
+ *
+ * For now we can just model it as a multiplier clock, and force P to /1.
+ *
+ * The M factor is present in the register's description, but not in the
+ * frequency formula, and it's documented as "M is only used for backdoor
+ * testing", so it's not modelled and then force to 0.
+ */
+#define SUN50I_H6_PLL_CPUX_REG 0x000
+static struct ccu_mult pll_cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .common = {
+ .reg= 0x000,
+ .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
+ _mult_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
+#define SUN50I_H6_PLL_DDR0_REG 0x010
+static struct ccu_nkmp pll_ddr0_clk = {
+ .enable
[PATCH 6/7] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.
This commit adds the basical DTSI file of it, including the clock
support and UART support.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 214 +++
1 file changed, 214 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
new file mode 100644
index ..482f5cb64d07
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ iosc: internal-osc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1600>;
+ clock-accuracy = <3>;
+ clock-output-names = "iosc";
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ psci {
+
[PATCH 7/7] arm64: allwinner: h6: add support for Pine H64 board
Pine H64 is an Allwinner H6-based SBC from Pine64, with the following
features:
- 1GiB/2GiB/4GiB LPDDR3 DRAM (in 4GiB situation only 3GiB is
accessible)
- AXP805 PMIC
- Raspberry-Pi-compatible GPIO header, "Euler" GPIO header (not
compatible with the "Euler" on Pine A64) and "Expansion" pin header
- 2 USB 2.0 ports and 1 USB 3.0 ports
- Audio jack
- MicroSD slot and eMMC module slot
- on-board SPI NOR flash
- 1Gbps Ethernet port (via RTL8211E PHY)
- HDMI port
Adds initial support for it, including the UART on the Expansion pin
header.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 66 ++
2 files changed, 67 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index f505227b0250..addf245226f6 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -10,3 +10,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
new file mode 100644
index ..0d7b294c8aa9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include
+
+/ {
+ model = "Pine H64";
+ compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_ph_pins>;
+ status = "okay";
+};
--
2.14.2
[PATCH 0/2] Add EHCI/OHCI nodes for V3s and Lichee Pi Zero
As the PHY dual-route property is added to 4.15-rc, the EHCI/OHCI nodes are now necessary. Please apply these patches to 4.15, Thanks! Icenowy Zheng (2): ARM: sun8i: v3s: add EHCI/OHCI0 device nodes ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++ 2 files changed, 27 insertions(+) -- 2.14.2
[PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 443b083c6adc..cc315dc742d2 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -264,6 +264,25 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_EHCI0>, < CLK_BUS_OHCI0>;
+ resets = < RST_BUS_EHCI0>, < RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_EHCI0>, < CLK_BUS_OHCI0>,
+< CLK_USB_OHCI0>;
+ resets = < RST_BUS_EHCI0>, < RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ccu: clock@1c2 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c2 0x400>;
--
2.14.2
[PATCH 2/2] ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 387fc2aa546d..cf2d9fe3bbb7 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -77,6 +77,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
pinctrl-0 = <_pins_a>;
pinctrl-names = "default";
@@ -86,6 +90,10 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
pinctrl-0 = <_pins_a>;
pinctrl-names = "default";
--
2.14.2
[PATCH v3 00/11] Allwinner H3/H5/A64(DE2) SimpleFB support
This patchset adds support for the SimpleFB on Allwinner SoCs with "Display Engine 2.0". PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs. PATCH 4 adds the pipeline strings for DE2 SimpleFB. PATCH 5 to 7 adds necessary device tree nodes (DE2 CCU and SimpleFB) for H3/H5 SoCs. PATCH 8 to 11 are for Allwinner A64 SoC to enable SimpleFB. Icenowy Zheng (11): dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3 clk: sunxi-ng: add support for Allwinner H3 DE2 CCU clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU dt-bindings: simplefb-sunxi: add pipelines for DE2 ARM: sun8i: h3/h5: add DE2 CCU device node for H3 arm64: allwinner: h5: add compatible string for DE2 CCU ARM: sunxi: h3/h5: add simplefb nodes dt-bindings: add binding for A64 DE2 CCU SRAM clk: sunxi-ng: add support for Allwinner A64 DE2 CCU arm64: allwinner: a64: add DE2 CCU for A64 SoC arm64: allwinner: a64: add simplefb for A64 SoC .../devicetree/bindings/clock/sun8i-de2.txt| 10 ++- .../bindings/display/simple-framebuffer-sunxi.txt | 4 + arch/arm/boot/dts/sun8i-h3.dtsi| 4 + arch/arm/boot/dts/sunxi-h3-h5.dtsi | 43 +++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 65 + arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 + drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 85 +++--- 7 files changed, 202 insertions(+), 13 deletions(-) -- 2.14.2
[PATCH v3 01/11] dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on
A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed
when I develop the DE2 CCU driver.
Fix the binding by using different compatibles for A83T and H3, adding
notes for the PLL_DE usage on A83T, and change the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).
Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index 631d27cd89d6..f2fa87c4765c 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun8i-a83t-de2-clk"
+ - "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
Three are needed:
- - "mod": the display engine module clock
+ - "mod": the display engine module clock (on A83T it's the DE PLL)
- "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
@@ -19,7 +20,7 @@ Required properties :
Example:
de2_clocks: clock@100 {
- compatible = "allwinner,sun8i-a83t-de2-clk";
+ compatible = "allwinner,sun8i-h3-de2-clk";
reg = <0x0100 0x10>;
clocks = < CLK_BUS_DE>,
< CLK_DE>;
--
2.14.2
