[RFC PATCH] ARM: OMAP4: ID: Improve features detection and check
Replaces several flags bearing the same meaning. There is no need
to set flags due to different omap types here, it can be checked
in appropriate places as well.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: linux-o...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/mach-omap2/id.c | 25 +++--
arch/arm/mach-omap2/soc.h |8 ++--
2 files changed, 9 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index cf2362c..3c47a19 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -28,6 +28,9 @@
#include soc.h
#include control.h
+#define OMAP4_SILICON_TYPE_STANDARD0x01
+#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
+
static unsigned int omap_revision;
static const char *cpu_rev;
u32 omap_features;
@@ -273,25 +276,11 @@ void __init omap4xxx_check_features(void)
{
u32 si_type;
- if (cpu_is_omap443x())
- omap_features |= OMAP4_HAS_MPU_1GHZ;
-
+ si_type =
+ (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) 16) 0x03;
- if (cpu_is_omap446x()) {
- si_type =
- read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
- switch ((si_type (3 16)) 16) {
- case 2:
- /* High performance device */
- omap_features |= OMAP4_HAS_MPU_1_5GHZ;
- break;
- case 1:
- default:
- /* Standard device */
- omap_features |= OMAP4_HAS_MPU_1_2GHZ;
- break;
- }
- }
+ if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
+ omap_features = OMAP4_HAS_PERF_SILICON;
}
void __init ti81xx_check_features(void)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 0700964..f31d907 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -435,9 +435,7 @@ extern u32 omap_features;
#define OMAP3_HAS_IO_WAKEUPBIT(6)
#define OMAP3_HAS_SDRC BIT(7)
#define OMAP3_HAS_IO_CHAIN_CTRLBIT(8)
-#define OMAP4_HAS_MPU_1GHZ BIT(9)
-#define OMAP4_HAS_MPU_1_2GHZ BIT(10)
-#define OMAP4_HAS_MPU_1_5GHZ BIT(11)
+#define OMAP4_HAS_PERF_SILICON BIT(9)
#define OMAP3_HAS_FEATURE(feat,flag) \
@@ -465,9 +463,7 @@ static inline unsigned int omap4_has_ ##feat(void) \
return omap_features OMAP4_HAS_ ##flag; \
} \
-OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
-OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
-OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+OMAP4_HAS_FEATURE(perf_silicon, PERF_SILICON)
#endif /* __ASSEMBLY__ */
--
1.7.9.5
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[PATCH] ARM: OMAP4: ID: Improve features detection and check
Replaces several flags bearing the same meaning. There is no need
to set flags due to different omap types here, it can be checked
in appropriate places as well.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: linux-o...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Nishanth Menon n...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/mach-omap2/id.c | 25 +++--
arch/arm/mach-omap2/soc.h |8 ++--
2 files changed, 9 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index cf2362c..3c47a19 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -28,6 +28,9 @@
#include soc.h
#include control.h
+#define OMAP4_SILICON_TYPE_STANDARD0x01
+#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
+
static unsigned int omap_revision;
static const char *cpu_rev;
u32 omap_features;
@@ -273,25 +276,11 @@ void __init omap4xxx_check_features(void)
{
u32 si_type;
- if (cpu_is_omap443x())
- omap_features |= OMAP4_HAS_MPU_1GHZ;
-
+ si_type =
+ (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) 16) 0x03;
- if (cpu_is_omap446x()) {
- si_type =
- read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
- switch ((si_type (3 16)) 16) {
- case 2:
- /* High performance device */
- omap_features |= OMAP4_HAS_MPU_1_5GHZ;
- break;
- case 1:
- default:
- /* Standard device */
- omap_features |= OMAP4_HAS_MPU_1_2GHZ;
- break;
- }
- }
+ if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
+ omap_features = OMAP4_HAS_PERF_SILICON;
}
void __init ti81xx_check_features(void)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 0700964..f31d907 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -435,9 +435,7 @@ extern u32 omap_features;
#define OMAP3_HAS_IO_WAKEUPBIT(6)
#define OMAP3_HAS_SDRC BIT(7)
#define OMAP3_HAS_IO_CHAIN_CTRLBIT(8)
-#define OMAP4_HAS_MPU_1GHZ BIT(9)
-#define OMAP4_HAS_MPU_1_2GHZ BIT(10)
-#define OMAP4_HAS_MPU_1_5GHZ BIT(11)
+#define OMAP4_HAS_PERF_SILICON BIT(9)
#define OMAP3_HAS_FEATURE(feat,flag) \
@@ -465,9 +463,7 @@ static inline unsigned int omap4_has_ ##feat(void) \
return omap_features OMAP4_HAS_ ##flag; \
} \
-OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
-OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
-OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+OMAP4_HAS_FEATURE(perf_silicon, PERF_SILICON)
#endif /* __ASSEMBLY__ */
--
1.7.9.5
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[RFC PATCH] Input: gpio_keys: Fix suspend/resume press event lost
Rebased on linux_omap/master.
During suspend/resume the key press can be lost if time of resume
sequence is significant.
If press event cannot be remembered then the driver can read the
current button state only in time of interrupt handling. But in some
cases when time between IRQ and IRQ handler is significant we can
read incorrect state. As a particular case, when device is in suspend
we press wakupable key and up it back in a jiffy, the interrupt
handler read the state of up but the interrupt source is press indeed.
As a result, in a OS like android, we resume then suspend right away
because the key state is not changed.
This patch add to gpio_keys framework opportunity to recover lost of
press key event at resuming. The variable key_pressed from
gpio_button_data structure is not used for gpio keys, it is only used
for gpio irq keys, so it is logically used to remember press lost
while resuming.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/input/keyboard/gpio_keys.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/input/keyboard/gpio_keys.c
b/drivers/input/keyboard/gpio_keys.c
index b29ca65..33ac8c5 100644
--- a/drivers/input/keyboard/gpio_keys.c
+++ b/drivers/input/keyboard/gpio_keys.c
@@ -45,6 +45,7 @@ struct gpio_button_data {
struct gpio_keys_drvdata {
const struct gpio_keys_platform_data *pdata;
struct input_dev *input;
+ int suspended;
struct mutex disable_lock;
struct gpio_button_data data[0];
};
@@ -326,14 +327,40 @@ static void gpio_keys_gpio_report_event(struct
gpio_button_data *bdata)
{
const struct gpio_keys_button *button = bdata-button;
struct input_dev *input = bdata-input;
+ struct gpio_keys_drvdata *ddata = input_get_drvdata(input);
unsigned int type = button-type ?: EV_KEY;
int state = (gpio_get_value_cansleep(button-gpio) ? 1 : 0) ^
button-active_low;
+ /*
+* Don't generate input event while resuming,
+* it will be generated at gpio_keys_resume function
+ */
+ if (ddata-suspended) {
+ /*
+* missed press event while resuming so set
+* key_pressed flag to generate press and up events
+* while gpio_keys_resume function.
+*/
+ if (button-wakeup state == 0)
+ bdata-key_pressed = 1;
+ return;
+ }
+
if (type == EV_ABS) {
if (state)
input_event(input, type, button-code, button-value);
} else {
- input_event(input, type, button-code, !!state);
+ /*
+* missed press key, so generate press event then up event
+*/
+ if (bdata-key_pressed) {
+ input_event(bdata-input, EV_KEY, button-code, 1);
+ input_sync(bdata-input);
+ input_event(bdata-input, EV_KEY, button-code, 0);
+ bdata-key_pressed = 0;
+ } else {
+ input_event(input, type, button-code, !!state);
+ }
}
input_sync(input);
}
@@ -822,6 +849,7 @@ static int gpio_keys_suspend(struct device *dev)
mutex_unlock(input-mutex);
}
+ ddata-suspended = 1;
return 0;
}
@@ -832,6 +860,7 @@ static int gpio_keys_resume(struct device *dev)
int error = 0;
int i;
+ ddata-suspended = 0;
if (device_may_wakeup(dev)) {
for (i = 0; i ddata-pdata-nbuttons; i++) {
struct gpio_button_data *bdata = ddata-data[i];
--
1.7.9.5
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[RFC PATCH] Input: gpio_keys: Fix suspend/resume press event lost
During suspend/resume the key press can be lost if time of resume
sequence is significant.
If press event cannot be remembered then the driver can read the
current button state only in time of interrupt handling. But in some
cases when time between IRQ and IRQ handler is significant we can
read incorrect state. As a particular case, when device is in suspend
we press wakupable key and up it back in a jiffy, the interrupt
handler read the state of up but the interrupt source is press indeed.
As a result, in a OS like android, we resume then suspend right away
because the key state is not changed.
This patch add to gpio_keys framework opportunity to recover lost of
press key event at resuming. The variable key_pressed from
gpio_button_data structure is not used for gpio keys, it is only used
for gpio irq keys, so it is logically used to remember press lost
while resuming.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/input/keyboard/gpio_keys.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/input/keyboard/gpio_keys.c
b/drivers/input/keyboard/gpio_keys.c
index 62bfce4..aa49aef 100644
--- a/drivers/input/keyboard/gpio_keys.c
+++ b/drivers/input/keyboard/gpio_keys.c
@@ -46,6 +46,7 @@ struct gpio_keys_drvdata {
struct input_dev *input;
struct mutex disable_lock;
unsigned int n_buttons;
+ int suspended;
int (*enable)(struct device *dev);
void (*disable)(struct device *dev);
struct gpio_button_data data[0];
@@ -328,14 +329,40 @@ static void gpio_keys_gpio_report_event(struct
gpio_button_data *bdata)
{
const struct gpio_keys_button *button = bdata-button;
struct input_dev *input = bdata-input;
+ struct gpio_keys_drvdata *ddata = input_get_drvdata(input);
unsigned int type = button-type ?: EV_KEY;
int state = (gpio_get_value_cansleep(button-gpio) ? 1 : 0) ^
button-active_low;
+ /*
+* Don't generate input event while resuming,
+* it will be generated at gpio_keys_resume function
+ */
+ if (ddata-suspended) {
+ /*
+* missed press event while resuming so set
+* key_pressed flag to generate press and up events
+* while gpio_keys_resume function.
+*/
+ if (button-wakeup state == 0)
+ bdata-key_pressed = 1;
+ return;
+ }
+
if (type == EV_ABS) {
if (state)
input_event(input, type, button-code, button-value);
} else {
- input_event(input, type, button-code, !!state);
+ /*
+* missed press key, so generate press event then up event
+*/
+ if (bdata-key_pressed) {
+ input_event(bdata-input, EV_KEY, button-code, 1);
+ input_sync(bdata-input);
+ input_event(bdata-input, EV_KEY, button-code, 0);
+ bdata-key_pressed = 0;
+ } else {
+ input_event(input, type, button-code, !!state);
+ }
}
input_sync(input);
}
@@ -792,6 +819,7 @@ static int gpio_keys_suspend(struct device *dev)
}
}
+ ddata-suspended = 1;
return 0;
}
@@ -800,6 +828,7 @@ static int gpio_keys_resume(struct device *dev)
struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev);
int i;
+ ddata-suspended = 0;
for (i = 0; i ddata-n_buttons; i++) {
struct gpio_button_data *bdata = ddata-data[i];
if (bdata-button-wakeup device_may_wakeup(dev))
--
1.7.9.5
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[PATCH 1/2] ARM: OMAP3: PRCM: Fix incorrect read of reset sources
The flag mask are incorrect, so fix it.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/mach-omap2/prcm.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 0f51e03..dc45156 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -48,9 +48,10 @@ void __iomem *prcm_mpu_base;
u32 omap_prcm_get_reset_sources(void)
{
- /* XXX This presumably needs modification for 34XX */
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ if (cpu_is_omap24xx())
return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) 0x7f;
+ if (cpu_is_omap34xx())
+ return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) 0x7ff;
if (cpu_is_omap44xx())
return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) 0x7f;
--
1.7.9.5
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[PATCH 2/2] ARM: OMAP4: PRCM: Fix incorrect read of reset sources
The address of PRM_RSTST register and flag mask are incorrect, so fix it. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/mach-omap2/prcm.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index dc45156..02f27f2 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -53,8 +53,8 @@ u32 omap_prcm_get_reset_sources(void) if (cpu_is_omap34xx()) return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) 0x7ff; if (cpu_is_omap44xx()) - return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) 0x7f; - + return omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + OMAP4_PRM_RSTST_OFFSET) 0x7ff; return 0; } EXPORT_SYMBOL(omap_prcm_get_reset_sources); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: OMAP4: PRM: Correct PRM_RSTST and PRM_RSTTIME registers shifts
According to TRMs the assigned shifts are wrong, so correct them. --- arch/arm/mach-omap2/prm44xx.h |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 22b0979..8ee1fbd 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -62,8 +62,8 @@ /* OMAP4 specific register offsets */ #define OMAP4_RM_RSTCTRL 0x -#define OMAP4_RM_RSTTIME 0x0004 -#define OMAP4_RM_RSTST 0x0008 +#define OMAP4_RM_RSTST 0x0004 +#define OMAP4_RM_RSTTIME 0x0008 #define OMAP4_PM_PWSTCTRL 0x #define OMAP4_PM_PWSTST0x0004 -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: OMAP4: PRM: Correct PRM_RSTST and PRM_RSTTIME registers shifts
According to TRMs the assigned shifts are wrong, so correct them. --- arch/arm/mach-omap2/prm44xx.h |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 22b0979..8ee1fbd 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -62,8 +62,8 @@ /* OMAP4 specific register offsets */ #define OMAP4_RM_RSTCTRL 0x -#define OMAP4_RM_RSTTIME 0x0004 -#define OMAP4_RM_RSTST 0x0008 +#define OMAP4_RM_RSTST 0x0004 +#define OMAP4_RM_RSTTIME 0x0008 #define OMAP4_PM_PWSTCTRL 0x #define OMAP4_PM_PWSTST0x0004 -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: OMAP4: PRM: Correct wrong instance usage for reading reset sources
To read reset sources registers we have to use PRM_DEVICE_INST --- arch/arm/mach-omap2/prm44xx.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 7498bc7..0b61b8d 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -333,7 +333,7 @@ static u32 omap44xx_prm_read_reset_sources(void) u32 r = 0; u32 v; - v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, + v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, OMAP4_RM_RSTST); p = omap44xx_prm_reset_src_map; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: OMAP4: PRM: Correct reset source map
In the map for reset sources register we use defines intended for
using with PRM_RSTCTRL register. So fix it.
---
arch/arm/mach-omap2/prm44xx.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 7498bc7..e335216 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -56,9 +56,9 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
* enumeration)
*/
static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
- { OMAP4430_RST_GLOBAL_WARM_SW_SHIFT,
+ { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
- { OMAP4430_RST_GLOBAL_COLD_SW_SHIFT,
+ { OMAP4430_GLOBAL_COLD_RST_SHIFT,
OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
{ OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
--
1.7.9.5
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[PATCH] ARM: OMAP4: PRM: Correct reset source map
In the map for reset sources register we use defines intended for
using with PRM_RSTCTRL register. So fix it.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/mach-omap2/prm44xx.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 7498bc7..e335216 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -56,9 +56,9 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
* enumeration)
*/
static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
- { OMAP4430_RST_GLOBAL_WARM_SW_SHIFT,
+ { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
- { OMAP4430_RST_GLOBAL_COLD_SW_SHIFT,
+ { OMAP4430_GLOBAL_COLD_RST_SHIFT,
OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
{ OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
--
1.7.9.5
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[PATCH] ARM: OMAP4: PRM: Correct wrong instance usage for reading reset sources
To read reset sources registers we have to use PRM_DEVICE_INST Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/mach-omap2/prm44xx.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 7498bc7..0b61b8d 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -333,7 +333,7 @@ static u32 omap44xx_prm_read_reset_sources(void) u32 r = 0; u32 v; - v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, + v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, OMAP4_RM_RSTST); p = omap44xx_prm_reset_src_map; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: OMAP4: PRM: fix RSTTIME and RSTST offsets
From: Nishanth Menon n...@ti.com RSTTIME is offset 0x8 and RSTST is offset 0x04 for OMAP4430 and OMAP4460. Signed-off-by: Nishanth Menon n...@ti.com [ivan.khoronz...@ti.com: ported from k3.4] Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- arch/arm/mach-omap2/prm44xx.h |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 22b0979..8ee1fbd 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -62,8 +62,8 @@ /* OMAP4 specific register offsets */ #define OMAP4_RM_RSTCTRL 0x -#define OMAP4_RM_RSTTIME 0x0004 -#define OMAP4_RM_RSTST 0x0008 +#define OMAP4_RM_RSTST 0x0004 +#define OMAP4_RM_RSTTIME 0x0008 #define OMAP4_PM_PWSTCTRL 0x #define OMAP4_PM_PWSTST0x0004 -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 3/6] watchdog: davinci: add GET_TIMELEFT option support
Currently, the davinci watchdog can be read while counting,
so we can add ability to report the remaining time before
the system will reboot.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
---
drivers/watchdog/davinci_wdt.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 4c3f417..d342fc2 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -116,6 +116,31 @@ static int davinci_wdt_ping(struct watchdog_device *wdd)
return 0;
}
+static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
+{
+ u64 timer_counter;
+ unsigned long freq;
+ u32 val;
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
+
+ /* if timeout has occured then return 0 */
+ val = ioread32(davinci_wdt-base + WDTCR);
+ if (val WDFLAG)
+ return 0;
+
+ freq = clk_get_rate(davinci_wdt-clk);
+
+ if (!freq)
+ return 0;
+
+ timer_counter = ioread32(davinci_wdt-base + TIM12);
+ timer_counter |= ((u64)ioread32(davinci_wdt-base + TIM34) 32);
+
+ do_div(timer_counter, freq);
+
+ return wdd-timeout - timer_counter;
+}
+
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
.identity = DaVinci Watchdog,
@@ -126,6 +151,7 @@ static const struct watchdog_ops davinci_wdt_ops = {
.start = davinci_wdt_start,
.stop = davinci_wdt_ping,
.ping = davinci_wdt_ping,
+ .get_timeleft = davinci_wdt_get_timeleft,
};
static int davinci_wdt_probe(struct platform_device *pdev)
--
1.7.9.5
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[PATCH v3 5/6] watchdog: davinci: reuse driver for keystone arch
The keystone arch uses the same IP watchdog, so add ti,keystone-wdt
compatible and correct identity.
The Keystone arch is using clocks in DT and source clock for watchdog
has to be specified, so add this to binding.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
---
.../devicetree/bindings/watchdog/davinci-wdt.txt | 12 ++--
drivers/watchdog/Kconfig |4 ++--
drivers/watchdog/davinci_wdt.c |2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index e450134..4d89317 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -1,11 +1,18 @@
-DaVinci Watchdog Timer (WDT) Controller
+Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
Required properties:
-- compatible : Should be ti,davinci-wdt
+- compatible : Should be ti,davinci-wdt or ti,keystone-wdt
- reg : Should contain WDT registers location and length
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
+- clocks : the clock feeding the watchdog timer.
+ Needed if platform uses clocks.
+ See clock-bindings.txt
+
+Documentation:
+Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
+Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Examples:
@@ -13,4 +20,5 @@ wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
timeout-sec = 30;
+ clocks = clkwdtimer0;
};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index eb8c89d..01f3f81 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -270,12 +270,12 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
- depends on ARCH_DAVINCI
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
select WATCHDOG_CORE
select WATCHDOG_NOWAYOUT
help
Say Y here if to include support for the watchdog timer
- in the DaVinci DM644x/DM646x processors.
+ in the DaVinci DM644x/DM646x or Keystone processors.
To compile this driver as a module, choose M here: the
module will be called davinci_wdt.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index d342fc2..9128c74 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -143,7 +143,7 @@ static unsigned int davinci_wdt_get_timeleft(struct
watchdog_device *wdd)
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
- .identity = DaVinci Watchdog,
+ .identity = DaVinci/Keystone Watchdog,
};
static const struct watchdog_ops davinci_wdt_ops = {
--
1.7.9.5
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[PATCH v3 4/6] watchdog: davinci: add timeout-sec property
Since Davinci WDT has been switched to use WDT core, it became able
to support timeout-sec property, so add it to it's binding description.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
---
.../devicetree/bindings/watchdog/davinci-wdt.txt |4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index 75558cc..e450134 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -4,9 +4,13 @@ Required properties:
- compatible : Should be ti,davinci-wdt
- reg : Should contain WDT registers location and length
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
Examples:
wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
+ timeout-sec = 30;
};
--
1.7.9.5
--
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[PATCH v3 2/6] watchdog: davinci: use davinci_wdt_device structure to hold device data
Some SoCs, like Keystone 2, can support more than one WDT and each
watchdog device has to use it's own base address, clock source,
watchdog device, so add new davinci_wdt_device structure to hold
device data.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter roeck li...@roeck-us.net
---
drivers/watchdog/davinci_wdt.c | 74 ++--
1 file changed, 48 insertions(+), 26 deletions(-)
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 2a94dde..4c3f417 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -56,51 +56,63 @@
#define WDKEY_SEQ1 (0xda7e 16)
static int heartbeat;
-static void __iomem*wdt_base;
-struct clk *wdt_clk;
-static struct watchdog_device wdt_wdd;
+
+/*
+ * struct to hold data for each WDT device
+ * @base - base io address of WD device
+ * @clk - source clock of WDT
+ * @wdd - hold watchdog device as is in WDT core
+ */
+struct davinci_wdt_device {
+ void __iomem*base;
+ struct clk *clk;
+ struct watchdog_device wdd;
+};
static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
unsigned long wdt_freq;
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
- wdt_freq = clk_get_rate(wdt_clk);
+ wdt_freq = clk_get_rate(davinci_wdt-clk);
/* disable, internal clock source */
- iowrite32(0, wdt_base + TCR);
+ iowrite32(0, davinci_wdt-base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
- iowrite32(0, wdt_base + TGCR);
+ iowrite32(0, davinci_wdt-base + TGCR);
tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
- iowrite32(tgcr, wdt_base + TGCR);
+ iowrite32(tgcr, davinci_wdt-base + TGCR);
/* clear counter regs */
- iowrite32(0, wdt_base + TIM12);
- iowrite32(0, wdt_base + TIM34);
+ iowrite32(0, davinci_wdt-base + TIM12);
+ iowrite32(0, davinci_wdt-base + TIM34);
/* set timeout period */
timer_margin = (((u64)wdd-timeout * wdt_freq) 0x);
- iowrite32(timer_margin, wdt_base + PRD12);
+ iowrite32(timer_margin, davinci_wdt-base + PRD12);
timer_margin = (((u64)wdd-timeout * wdt_freq) 32);
- iowrite32(timer_margin, wdt_base + PRD34);
+ iowrite32(timer_margin, davinci_wdt-base + PRD34);
/* enable run continuously */
- iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
+ iowrite32(ENAMODE12_PERIODIC, davinci_wdt-base + TCR);
/* Once the WDT is in pre-active state write to
* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
* write protected (except for the WDKEY field)
*/
/* put watchdog in pre-active state */
- iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt-base + WDTCR);
/* put watchdog in active state */
- iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt-base + WDTCR);
return 0;
}
static int davinci_wdt_ping(struct watchdog_device *wdd)
{
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
+
/* put watchdog in service state */
- iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ0, davinci_wdt-base + WDTCR);
/* put watchdog in active state */
- iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ1, davinci_wdt-base + WDTCR);
return 0;
}
@@ -122,14 +134,21 @@ static int davinci_wdt_probe(struct platform_device *pdev)
struct device *dev = pdev-dev;
struct resource *wdt_mem;
struct watchdog_device *wdd;
+ struct davinci_wdt_device *davinci_wdt;
+
+ davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
+ if (!davinci_wdt)
+ return -ENOMEM;
- wdt_clk = devm_clk_get(dev, NULL);
- if (WARN_ON(IS_ERR(wdt_clk)))
- return PTR_ERR(wdt_clk);
+ davinci_wdt-clk = devm_clk_get(dev, NULL);
+ if (WARN_ON(IS_ERR(davinci_wdt-clk)))
+ return PTR_ERR(davinci_wdt-clk);
- clk_prepare_enable(wdt_clk);
+ clk_prepare_enable(davinci_wdt-clk);
- wdd = wdt_wdd;
+ platform_set_drvdata(pdev, davinci_wdt);
+
+ wdd = davinci_wdt-wdd;
wdd-info = davinci_wdt_info;
wdd-ops= davinci_wdt_ops;
wdd-min_timeout= 1;
@@ -140,12 +159,13 @@ static int davinci_wdt_probe(struct platform_device *pdev)
dev_info(dev, heartbeat %d sec\n, wdd-timeout);
+ watchdog_set_drvdata(wdd, davinci_wdt);
watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
wdt_mem
[PATCH v3 0/6] Update Davinci watchdog driver
These patches are intended to update Davinci watchdog to use WDT core and reuse driver for keystone arch, because Keystone uses the similar IP like Davinci. See Documentation: Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf Also: - improved to support GET_TIMELEFT option. - added clocks and timeout-sec properties to DT. Based on git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git keystone/master v2..v3: - watchdog: davinci: change driver to use WDT core removed ti,keystone-wdt compatible from driver renamed wdt device names for mach-davinci from watchdog to davinci-wdt - watchdog: davinci: reuse driver for keystone arch moved clocks property under Optional properties improved decsription of clocks property - arm: dts: keystone: add watchdog entry replaced ti,keystone-wdt compatible on ti,keystone-wdt,ti,davinci-wdt Ivan Khoronzhuk (6): watchdog: davinci: change driver to use WDT core watchdog: davinci: use davinci_wdt_device structure to hold device data watchdog: davinci: add GET_TIMELEFT option support watchdog: davinci: add timeout-sec property watchdog: davinci: reuse driver for keystone arch arm: dts: keystone: add watchdog entry .../devicetree/bindings/watchdog/davinci-wdt.txt | 16 +- arch/arm/boot/dts/keystone.dtsi|6 + arch/arm/mach-davinci/da8xx-dt.c |2 +- arch/arm/mach-davinci/devices-da8xx.c |4 +- arch/arm/mach-davinci/devices.c|2 +- drivers/watchdog/Kconfig |6 +- drivers/watchdog/davinci_wdt.c | 225 +--- 7 files changed, 126 insertions(+), 135 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 1/6] watchdog: davinci: change driver to use WDT core
To reduce code duplicate and increase code readability use WDT core
code to handle WDT interface.
Remove io_lock as the WDT core uses mutex to lock each wdt device.
Remove wdt_state as the WDT core tracks state with its own variable.
The watchdog_init_timeout() can read timeout value from timeout-sec
property if the passed value is out of bounds. The heartbeat is
initialized in next way. If heartbeat is not set thought module
parameter, try to read it's value from WDT node timeout-sec property.
If node has no one, use default value.
The heartbeat is hold in wdd-timeout by WDT core, so use it in
order to set timeout period.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
---
arch/arm/mach-davinci/da8xx-dt.c |2 +-
arch/arm/mach-davinci/devices-da8xx.c |4 +-
arch/arm/mach-davinci/devices.c |2 +-
drivers/watchdog/Kconfig |2 +
drivers/watchdog/davinci_wdt.c| 151 -
5 files changed, 43 insertions(+), 118 deletions(-)
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index d2bc574..ed19287 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -32,7 +32,7 @@ static void __init da8xx_init_irq(void)
static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA(ti,davinci-i2c, 0x01c22000, i2c_davinci.1, NULL),
- OF_DEV_AUXDATA(ti,davinci-wdt, 0x01c21000, watchdog, NULL),
+ OF_DEV_AUXDATA(ti,davinci-wdt, 0x01c21000, davinci-wdt, NULL),
OF_DEV_AUXDATA(ti,da830-mmc, 0x01c4, da830-mmc.0, NULL),
OF_DEV_AUXDATA(ti,da850-ehrpwm, 0x01f0, ehrpwm, NULL),
OF_DEV_AUXDATA(ti,da850-ehrpwm, 0x01f02000, ehrpwm, NULL),
diff --git a/arch/arm/mach-davinci/devices-da8xx.c
b/arch/arm/mach-davinci/devices-da8xx.c
index c46eccb..f9ba74b 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -389,7 +389,7 @@ static struct resource da8xx_watchdog_resources[] = {
};
static struct platform_device da8xx_wdt_device = {
- .name = watchdog,
+ .name = davinci-wdt,
.id = -1,
.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
.resource = da8xx_watchdog_resources,
@@ -399,7 +399,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd)
{
struct device *dev;
- dev = bus_find_device_by_name(platform_bus_type, NULL, watchdog);
+ dev = bus_find_device_by_name(platform_bus_type, NULL, davinci-wdt);
if (!dev) {
pr_err(%s: failed to find watchdog device\n, __func__);
return;
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 3996e98..5cf9a02 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -302,7 +302,7 @@ static struct resource wdt_resources[] = {
};
struct platform_device davinci_wdt_device = {
- .name = watchdog,
+ .name = davinci-wdt,
.id = -1,
.num_resources = ARRAY_SIZE(wdt_resources),
.resource = wdt_resources,
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 5be6e91..eb8c89d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -271,6 +271,8 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
depends on ARCH_DAVINCI
+ select WATCHDOG_CORE
+ select WATCHDOG_NOWAYOUT
help
Say Y here if to include support for the watchdog timer
in the DaVinci DM644x/DM646x processors.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index dd625cc..2a94dde 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -3,7 +3,7 @@
*
* Watchdog driver for DaVinci DM644x/DM646x processors
*
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2013 Texas Instruments.
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
@@ -15,18 +15,12 @@
#include linux/moduleparam.h
#include linux/types.h
#include linux/kernel.h
-#include linux/fs.h
-#include linux/miscdevice.h
#include linux/watchdog.h
#include linux/init.h
-#include linux/bitops.h
#include linux/platform_device.h
-#include linux/spinlock.h
-#include linux/uaccess.h
#include linux/io.h
#include linux/device.h
#include linux/clk.h
-#include linux/slab.h
#include linux/err.h
#define MODULE_NAME DAVINCI-WDT:
@@ -61,31 +55,12 @@
#define WDKEY_SEQ0 (0xa5c6 16)
#define WDKEY_SEQ1 (0xda7e 16)
-static int heartbeat = DEFAULT_HEARTBEAT;
-
-static DEFINE_SPINLOCK(io_lock);
-static unsigned long wdt_status;
-#define WDT_IN_USE0
-#define
[PATCH v3 5/6] watchdog: davinci: reuse driver for keystone arch
The keystone arch uses the same IP watchdog, so add ti,keystone-wdt
compatible and correct identity.
The Keystone arch is using clocks in DT and source clock for watchdog
has to be specified, so add this to binding.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
---
.../devicetree/bindings/watchdog/davinci-wdt.txt | 12 ++--
drivers/watchdog/Kconfig |4 ++--
drivers/watchdog/davinci_wdt.c |2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index e450134..4d89317 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -1,11 +1,18 @@
-DaVinci Watchdog Timer (WDT) Controller
+Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
Required properties:
-- compatible : Should be ti,davinci-wdt
+- compatible : Should be ti,davinci-wdt or ti,keystone-wdt
- reg : Should contain WDT registers location and length
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
+- clocks : the clock feeding the watchdog timer.
+ Needed if platform uses clocks.
+ See clock-bindings.txt
+
+Documentation:
+Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
+Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Examples:
@@ -13,4 +20,5 @@ wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
timeout-sec = 30;
+ clocks = clkwdtimer0;
};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index eb8c89d..01f3f81 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -270,12 +270,12 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
- depends on ARCH_DAVINCI
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
select WATCHDOG_CORE
select WATCHDOG_NOWAYOUT
help
Say Y here if to include support for the watchdog timer
- in the DaVinci DM644x/DM646x processors.
+ in the DaVinci DM644x/DM646x or Keystone processors.
To compile this driver as a module, choose M here: the
module will be called davinci_wdt.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index d342fc2..9128c74 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -143,7 +143,7 @@ static unsigned int davinci_wdt_get_timeleft(struct
watchdog_device *wdd)
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
- .identity = DaVinci Watchdog,
+ .identity = DaVinci/Keystone Watchdog,
};
static const struct watchdog_ops davinci_wdt_ops = {
--
1.7.9.5
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[PATCH v3 6/6] arm: dts: keystone: add watchdog entry
Add watchdog entry to keystone device tree.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Guenter Roeck li...@roeck-us.net
---
arch/arm/boot/dts/keystone.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index f6d6d9e..54a8ff7 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -181,5 +181,11 @@
interrupts = GIC_SPI 300 IRQ_TYPE_EDGE_RISING;
clocks = clkspi;
};
+
+ wdt: wdt@022f0080 {
+ compatible = ti,keystone-wdt,ti,davinci-wdt;
+ reg = 0x022f0080 0x80;
+ clocks = clkwdtimer0;
+ };
};
};
--
1.7.9.5
--
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[PATCH] ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemif
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for another platform like Keystone.
The Keysone platform is going to use TI AEMIF driver.
If TI AEMIF is used we don't need to set timings and bus width.
It is done by AEMIF driver.
To get rid of davinci-nand driver dependency on aemif platform code
we moved aemif code to davinci platform.
The platform AEMIF code (aemif.c) has to be removed once Davinci
will be converted to DT and use ti-aemif.c driver.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/mach-davinci/aemif.c | 73 ++-
arch/arm/mach-davinci/board-da830-evm.c |3 +
arch/arm/mach-davinci/board-da850-evm.c |3 +
arch/arm/mach-davinci/board-dm355-evm.c |5 ++
arch/arm/mach-davinci/board-dm355-leopard.c |5 ++
arch/arm/mach-davinci/board-dm365-evm.c |4 ++
arch/arm/mach-davinci/board-dm644x-evm.c|5 ++
arch/arm/mach-davinci/board-dm646x-evm.c|3 +
arch/arm/mach-davinci/board-mityomapl138.c |3 +
arch/arm/mach-davinci/board-neuros-osd2.c |9 ++-
arch/arm/mach-davinci/devices-tnetv107x.c |3 +
drivers/mtd/nand/davinci_nand.c | 23 ---
include/linux/platform_data/mtd-davinci-aemif.h |5 +-
13 files changed, 116 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index f091a90..51b14c6 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -16,6 +16,7 @@
#include linux/time.h
#include linux/platform_data/mtd-davinci-aemif.h
+#include linux/platform_data/mtd-davinci.h
/* Timing value configuration */
@@ -43,6 +44,17 @@
WSTROBE(WSTROBE_MAX) | \
WSETUP(WSETUP_MAX))
+static inline unsigned int davinci_aemif_readl(void __iomem *base, int offset)
+{
+ return readl_relaxed(base + offset);
+}
+
+static inline void davinci_aemif_writel(void __iomem *base,
+ int offset, unsigned long value)
+{
+ writel_relaxed(value, base + offset);
+}
+
/*
* aemif_calc_rate - calculate timing data.
* @wanted: The cycle time needed in nanoseconds.
@@ -86,7 +98,7 @@ static int aemif_calc_rate(int wanted, unsigned long clk, int
max)
*
* Returns 0 on success, else negative errno.
*/
-int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+static int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
void __iomem *base, unsigned cs)
{
unsigned set, val;
@@ -130,4 +142,61 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing
*t,
return 0;
}
-EXPORT_SYMBOL(davinci_aemif_setup_timing);
+
+/**
+ * davinci_aemif_setup - setup AEMIF interface by davinci_nand_pdata
+ * @pdev - link to platform device to setup settings for
+ *
+ * This function does not use any locking while programming the AEMIF
+ * because it is expected that there is only one user of a given
+ * chip-select.
+ *
+ * Returns 0 on success, else negative errno.
+ */
+int davinci_aemif_setup(struct platform_device *pdev)
+{
+ struct davinci_nand_pdata *pdata = dev_get_platdata(pdev-dev);
+ uint32_t val;
+ struct resource *res;
+ void __iomem *base;
+ int ret = 0;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res) {
+ dev_err(pdev-dev, cannot get IORESOURCE_MEM\n);
+ return -ENOMEM;
+ }
+
+ base = ioremap(res-start, resource_size(res));
+ if (!base) {
+ dev_err(pdev-dev, ioremap failed for resource %pR\n, res);
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ /*
+* Setup Async configuration register in case we did not boot
+* from NAND and so bootloader did not bother to set it up.
+*/
+ val = davinci_aemif_readl(base, A1CR_OFFSET + pdev-id * 4);
+ /*
+* Extended Wait is not valid and Select Strobe mode is not
+* used
+*/
+ val = ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
+ if (pdata-options NAND_BUSWIDTH_16)
+ val |= 0x1;
+
+ davinci_aemif_writel(base, A1CR_OFFSET + pdev-id * 4, val);
+
+ if (pdata-timing)
+ ret = davinci_aemif_setup_timing(pdata-timing, base, pdev-id);
+
+ if (ret 0)
+ dev_dbg(pdev-dev, NAND timing values setup fail\n);
+
+err:
+ iounmap(base);
+ return ret;
+}
+EXPORT_SYMBOL(davinci_aemif_setup);
diff --git a/arch/arm/mach-davinci/board-da830-evm.c
b/arch/arm/mach-davinci/board-da830-evm.c
index d1f45af..5623131 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -419,6 +419,9 @@ static inline void
[PATCH v4 1/5] watchdog: davinci: change driver to use WDT core
To reduce code duplicate and increase code readability use WDT core
code to handle WDT interface.
Remove io_lock as the WDT core uses mutex to lock each wdt device.
Remove wdt_state as the WDT core tracks state with its own variable.
The watchdog_init_timeout() can read timeout value from timeout-sec
property if the passed value is out of bounds. The heartbeat is
initialized in next way. If heartbeat is not set thought module
parameter, try to read it's value from WDT node timeout-sec property.
If node has no one, use default value.
The heartbeat is hold in wdd-timeout by WDT core, so use it in
order to set timeout period.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/watchdog/Kconfig |2 +
drivers/watchdog/davinci_wdt.c | 147 ++--
2 files changed, 37 insertions(+), 112 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 5be6e91..eb8c89d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -271,6 +271,8 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
depends on ARCH_DAVINCI
+ select WATCHDOG_CORE
+ select WATCHDOG_NOWAYOUT
help
Say Y here if to include support for the watchdog timer
in the DaVinci DM644x/DM646x processors.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index dd625cc..9595e70 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -3,7 +3,7 @@
*
* Watchdog driver for DaVinci DM644x/DM646x processors
*
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2013 Texas Instruments.
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
@@ -15,18 +15,12 @@
#include linux/moduleparam.h
#include linux/types.h
#include linux/kernel.h
-#include linux/fs.h
-#include linux/miscdevice.h
#include linux/watchdog.h
#include linux/init.h
-#include linux/bitops.h
#include linux/platform_device.h
-#include linux/spinlock.h
-#include linux/uaccess.h
#include linux/io.h
#include linux/device.h
#include linux/clk.h
-#include linux/slab.h
#include linux/err.h
#define MODULE_NAME DAVINCI-WDT:
@@ -61,31 +55,12 @@
#define WDKEY_SEQ0 (0xa5c6 16)
#define WDKEY_SEQ1 (0xda7e 16)
-static int heartbeat = DEFAULT_HEARTBEAT;
-
-static DEFINE_SPINLOCK(io_lock);
-static unsigned long wdt_status;
-#define WDT_IN_USE0
-#define WDT_OK_TO_CLOSE 1
-#define WDT_REGION_INITED 2
-#define WDT_DEVICE_INITED 3
-
+static int heartbeat;
static void __iomem*wdt_base;
struct clk *wdt_clk;
+static struct watchdog_device wdt_wdd;
-static void wdt_service(void)
-{
- spin_lock(io_lock);
-
- /* put watchdog in service state */
- iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
- /* put watchdog in active state */
- iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
-
- spin_unlock(io_lock);
-}
-
-static void wdt_enable(void)
+static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
@@ -93,8 +68,6 @@ static void wdt_enable(void)
wdt_freq = clk_get_rate(wdt_clk);
- spin_lock(io_lock);
-
/* disable, internal clock source */
iowrite32(0, wdt_base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
@@ -105,9 +78,9 @@ static void wdt_enable(void)
iowrite32(0, wdt_base + TIM12);
iowrite32(0, wdt_base + TIM34);
/* set timeout period */
- timer_margin = (((u64)heartbeat * wdt_freq) 0x);
+ timer_margin = (((u64)wdd-timeout * wdt_freq) 0x);
iowrite32(timer_margin, wdt_base + PRD12);
- timer_margin = (((u64)heartbeat * wdt_freq) 32);
+ timer_margin = (((u64)wdd-timeout * wdt_freq) 32);
iowrite32(timer_margin, wdt_base + PRD34);
/* enable run continuously */
iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
@@ -119,84 +92,28 @@ static void wdt_enable(void)
iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
/* put watchdog in active state */
iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
-
- spin_unlock(io_lock);
-}
-
-static int davinci_wdt_open(struct inode *inode, struct file *file)
-{
- if (test_and_set_bit(WDT_IN_USE, wdt_status))
- return -EBUSY;
-
- wdt_enable();
-
- return nonseekable_open(inode, file);
+ return 0;
}
-static ssize_t
-davinci_wdt_write(struct file *file, const char *data, size_t len,
- loff_t *ppos)
+static int davinci_wdt_ping(struct watchdog_device *wdd)
{
- if (len)
- wdt_service();
-
- return len;
+ /* put watchdog in service state */
+ iowrite32(WDKEY_SEQ0
[PATCH v4 5/5] watchdog: davinci: reuse driver for keystone arch
The keystone arch uses the same IP watchdog, so add ti,keystone-wdt
compatible and correct identity.
The Keystone arch is using clocks in DT and source clock for watchdog
has to be specified, so add this to binding.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/watchdog/davinci-wdt.txt | 12 ++--
drivers/watchdog/Kconfig |4 ++--
drivers/watchdog/davinci_wdt.c |2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index e450134..e60b9a1 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -1,11 +1,18 @@
-DaVinci Watchdog Timer (WDT) Controller
+Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
Required properties:
-- compatible : Should be ti,davinci-wdt
+- compatible : Should be ti,davinci-wdt, ti,keystone-wdt
- reg : Should contain WDT registers location and length
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
+- clocks : the clock feeding the watchdog timer.
+ Needed if platform uses clocks.
+ See clock-bindings.txt
+
+Documentation:
+Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
+Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Examples:
@@ -13,4 +20,5 @@ wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
timeout-sec = 30;
+ clocks = clkwdtimer0;
};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index eb8c89d..01f3f81 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -270,12 +270,12 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
- depends on ARCH_DAVINCI
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
select WATCHDOG_CORE
select WATCHDOG_NOWAYOUT
help
Say Y here if to include support for the watchdog timer
- in the DaVinci DM644x/DM646x processors.
+ in the DaVinci DM644x/DM646x or Keystone processors.
To compile this driver as a module, choose M here: the
module will be called davinci_wdt.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 0eb2189..884f696 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -143,7 +143,7 @@ static unsigned int davinci_wdt_get_timeleft(struct
watchdog_device *wdd)
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
- .identity = DaVinci Watchdog,
+ .identity = DaVinci/Keystone Watchdog,
};
static const struct watchdog_ops davinci_wdt_ops = {
--
1.7.9.5
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[PATCH v4 2/5] watchdog: davinci: use davinci_wdt_device structure to hold device data
Some SoCs, like Keystone 2, can support more than one WDT and each
watchdog device has to use it's own base address, clock source,
watchdog device, so add new davinci_wdt_device structure to hold
device data.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/watchdog/davinci_wdt.c | 74 ++--
1 file changed, 48 insertions(+), 26 deletions(-)
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 9595e70..2d46c43 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -56,51 +56,63 @@
#define WDKEY_SEQ1 (0xda7e 16)
static int heartbeat;
-static void __iomem*wdt_base;
-struct clk *wdt_clk;
-static struct watchdog_device wdt_wdd;
+
+/*
+ * struct to hold data for each WDT device
+ * @base - base io address of WD device
+ * @clk - source clock of WDT
+ * @wdd - hold watchdog device as is in WDT core
+ */
+struct davinci_wdt_device {
+ void __iomem*base;
+ struct clk *clk;
+ struct watchdog_device wdd;
+};
static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
unsigned long wdt_freq;
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
- wdt_freq = clk_get_rate(wdt_clk);
+ wdt_freq = clk_get_rate(davinci_wdt-clk);
/* disable, internal clock source */
- iowrite32(0, wdt_base + TCR);
+ iowrite32(0, davinci_wdt-base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
- iowrite32(0, wdt_base + TGCR);
+ iowrite32(0, davinci_wdt-base + TGCR);
tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
- iowrite32(tgcr, wdt_base + TGCR);
+ iowrite32(tgcr, davinci_wdt-base + TGCR);
/* clear counter regs */
- iowrite32(0, wdt_base + TIM12);
- iowrite32(0, wdt_base + TIM34);
+ iowrite32(0, davinci_wdt-base + TIM12);
+ iowrite32(0, davinci_wdt-base + TIM34);
/* set timeout period */
timer_margin = (((u64)wdd-timeout * wdt_freq) 0x);
- iowrite32(timer_margin, wdt_base + PRD12);
+ iowrite32(timer_margin, davinci_wdt-base + PRD12);
timer_margin = (((u64)wdd-timeout * wdt_freq) 32);
- iowrite32(timer_margin, wdt_base + PRD34);
+ iowrite32(timer_margin, davinci_wdt-base + PRD34);
/* enable run continuously */
- iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
+ iowrite32(ENAMODE12_PERIODIC, davinci_wdt-base + TCR);
/* Once the WDT is in pre-active state write to
* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
* write protected (except for the WDKEY field)
*/
/* put watchdog in pre-active state */
- iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt-base + WDTCR);
/* put watchdog in active state */
- iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt-base + WDTCR);
return 0;
}
static int davinci_wdt_ping(struct watchdog_device *wdd)
{
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
+
/* put watchdog in service state */
- iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ0, davinci_wdt-base + WDTCR);
/* put watchdog in active state */
- iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ1, davinci_wdt-base + WDTCR);
return 0;
}
@@ -122,14 +134,21 @@ static int davinci_wdt_probe(struct platform_device *pdev)
struct device *dev = pdev-dev;
struct resource *wdt_mem;
struct watchdog_device *wdd;
+ struct davinci_wdt_device *davinci_wdt;
+
+ davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
+ if (!davinci_wdt)
+ return -ENOMEM;
- wdt_clk = devm_clk_get(dev, NULL);
- if (WARN_ON(IS_ERR(wdt_clk)))
- return PTR_ERR(wdt_clk);
+ davinci_wdt-clk = devm_clk_get(dev, NULL);
+ if (WARN_ON(IS_ERR(davinci_wdt-clk)))
+ return PTR_ERR(davinci_wdt-clk);
- clk_prepare_enable(wdt_clk);
+ clk_prepare_enable(davinci_wdt-clk);
- wdd = wdt_wdd;
+ platform_set_drvdata(pdev, davinci_wdt);
+
+ wdd = davinci_wdt-wdd;
wdd-info = davinci_wdt_info;
wdd-ops= davinci_wdt_ops;
wdd-min_timeout= 1;
@@ -140,12 +159,13 @@ static int davinci_wdt_probe(struct platform_device *pdev)
dev_info(dev, heartbeat %d sec\n, wdd-timeout);
+ watchdog_set_drvdata(wdd, davinci_wdt);
watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
wdt_mem
[PATCH v4 3/5] watchdog: davinci: add GET_TIMELEFT option support
Currently, the davinci watchdog can be read while counting,
so we can add ability to report the remaining time before
the system will reboot.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/watchdog/davinci_wdt.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 2d46c43..0eb2189 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -116,6 +116,31 @@ static int davinci_wdt_ping(struct watchdog_device *wdd)
return 0;
}
+static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
+{
+ u64 timer_counter;
+ unsigned long freq;
+ u32 val;
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
+
+ /* if timeout has occured then return 0 */
+ val = ioread32(davinci_wdt-base + WDTCR);
+ if (val WDFLAG)
+ return 0;
+
+ freq = clk_get_rate(davinci_wdt-clk);
+
+ if (!freq)
+ return 0;
+
+ timer_counter = ioread32(davinci_wdt-base + TIM12);
+ timer_counter |= ((u64)ioread32(davinci_wdt-base + TIM34) 32);
+
+ do_div(timer_counter, freq);
+
+ return wdd-timeout - timer_counter;
+}
+
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
.identity = DaVinci Watchdog,
@@ -126,6 +151,7 @@ static const struct watchdog_ops davinci_wdt_ops = {
.start = davinci_wdt_start,
.stop = davinci_wdt_ping,
.ping = davinci_wdt_ping,
+ .get_timeleft = davinci_wdt_get_timeleft,
};
static int davinci_wdt_probe(struct platform_device *pdev)
--
1.7.9.5
--
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[PATCH v4 4/5] watchdog: davinci: add timeout-sec property
Since Davinci WDT has been switched to use WDT core, it became able
to support timeout-sec property, so add it to it's binding description.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/watchdog/davinci-wdt.txt |4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index 75558cc..e450134 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -4,9 +4,13 @@ Required properties:
- compatible : Should be ti,davinci-wdt
- reg : Should contain WDT registers location and length
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
Examples:
wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
+ timeout-sec = 30;
};
--
1.7.9.5
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 0/5] Update Davinci watchdog driver
These patches are intended to update Davinci watchdog to use WDT core and reuse driver for keystone arch, because Keystone uses the similar IP like Davinci. See Documentation: Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf Also: - improved to support GET_TIMELEFT option. - added clocks and timeout-sec properties to DT. Based on git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git keystone/master v3..v4: - watchdog: davinci: change driver to use WDT core reverted rename of platform driver to davinci-wdt as it causes a regression on Davinci platforms. - arm: dts: keystone: add watchdog entry The patch will be sent separately after series is ready. v2..v3: - watchdog: davinci: change driver to use WDT core removed ti,keystone-wdt compatible from driver renamed wdt device names for mach-davinci from watchdog to davinci-wdt - watchdog: davinci: reuse driver for keystone arch moved clocks property under Optional properties improved description of clocks property - arm: dts: keystone: add watchdog entry replaced ti,keystone-wdt compatible on ti,keystone-wdt,ti,davinci-wdt v1..v2: - watchdog: davinci: change driver to use WDT core corrected 2011 - 2006-2013 removed useless function comment corrected initialization of heartbeat switched on CONFIG_WATCHDOG_NOWAYOUT option - watchdog: davinci: use davinci_wdt_device structure to hold device data substituted wdd to watchdog device in commit message - watchdog: davinci: add GET_TIMELEFT option support corrected comment (is - has) removed redundant error message clock freq is not set - watchdog: davinci: add GET_STATUS option support dropped - watchdog: davinci: add timeout-sec property use consistent formatting - watchdog: davinci: reuse driver for keystone arch use consistent formatting - watchdog: davinci: add clocks property merged with above patch Ivan Khoronzhuk (5): watchdog: davinci: change driver to use WDT core watchdog: davinci: use davinci_wdt_device structure to hold device data watchdog: davinci: add GET_TIMELEFT option support watchdog: davinci: add timeout-sec property watchdog: davinci: reuse driver for keystone arch .../devicetree/bindings/watchdog/davinci-wdt.txt | 16 +- drivers/watchdog/Kconfig |6 +- drivers/watchdog/davinci_wdt.c | 221 +--- 3 files changed, 114 insertions(+), 129 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] watchdog: davinci: rename platform driver to davinci-wdt
As we switch to use the watchdog core which permits more than one
active watchdog in the system, rename platform driver to
davinci-wdt to be identifiable.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
based on:
https://lkml.org/lkml/2013/11/27/164
CC:
Sekhar Nori nsek...@ti.com
Guenter Roeck li...@roeck-us.net
arch/arm/mach-davinci/da830.c |2 +-
arch/arm/mach-davinci/da850.c |2 +-
arch/arm/mach-davinci/da8xx-dt.c |2 +-
arch/arm/mach-davinci/devices-da8xx.c |4 ++--
arch/arm/mach-davinci/devices.c |2 +-
arch/arm/mach-davinci/dm355.c |2 +-
arch/arm/mach-davinci/dm365.c |2 +-
arch/arm/mach-davinci/dm644x.c|2 +-
arch/arm/mach-davinci/dm646x.c|2 +-
drivers/watchdog/davinci_wdt.c|4 ++--
10 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 0813b51..82c6013 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -385,7 +385,7 @@ static struct clk_lookup da830_clks[] = {
CLK(NULL, pll0_sysclk7, pll0_sysclk7),
CLK(i2c_davinci.1,NULL, i2c0_clk),
CLK(NULL, timer0, timerp64_0_clk),
- CLK(watchdog, NULL, timerp64_1_clk),
+ CLK(davinci-wdt, NULL, timerp64_1_clk),
CLK(NULL, arm_rom, arm_rom_clk),
CLK(NULL, scr0_ss, scr0_ss_clk),
CLK(NULL, scr1_ss, scr1_ss_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 352984e..ccb2f58 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -443,7 +443,7 @@ static struct clk_lookup da850_clks[] = {
CLK(NULL, pll1_sysclk3, pll1_sysclk3),
CLK(i2c_davinci.1,NULL, i2c0_clk),
CLK(NULL, timer0, timerp64_0_clk),
- CLK(watchdog, NULL, timerp64_1_clk),
+ CLK(davinci-wdt, NULL, timerp64_1_clk),
CLK(NULL, arm_rom, arm_rom_clk),
CLK(NULL, tpcc0,tpcc0_clk),
CLK(NULL, tptc0,tptc0_clk),
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index d2bc574..ed19287 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -32,7 +32,7 @@ static void __init da8xx_init_irq(void)
static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA(ti,davinci-i2c, 0x01c22000, i2c_davinci.1, NULL),
- OF_DEV_AUXDATA(ti,davinci-wdt, 0x01c21000, watchdog, NULL),
+ OF_DEV_AUXDATA(ti,davinci-wdt, 0x01c21000, davinci-wdt, NULL),
OF_DEV_AUXDATA(ti,da830-mmc, 0x01c4, da830-mmc.0, NULL),
OF_DEV_AUXDATA(ti,da850-ehrpwm, 0x01f0, ehrpwm, NULL),
OF_DEV_AUXDATA(ti,da850-ehrpwm, 0x01f02000, ehrpwm, NULL),
diff --git a/arch/arm/mach-davinci/devices-da8xx.c
b/arch/arm/mach-davinci/devices-da8xx.c
index c46eccb..f9ba74b 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -389,7 +389,7 @@ static struct resource da8xx_watchdog_resources[] = {
};
static struct platform_device da8xx_wdt_device = {
- .name = watchdog,
+ .name = davinci-wdt,
.id = -1,
.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
.resource = da8xx_watchdog_resources,
@@ -399,7 +399,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd)
{
struct device *dev;
- dev = bus_find_device_by_name(platform_bus_type, NULL, watchdog);
+ dev = bus_find_device_by_name(platform_bus_type, NULL, davinci-wdt);
if (!dev) {
pr_err(%s: failed to find watchdog device\n, __func__);
return;
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 3996e98..5cf9a02 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -302,7 +302,7 @@ static struct resource wdt_resources[] = {
};
struct platform_device davinci_wdt_device = {
- .name = watchdog,
+ .name = davinci-wdt,
.id = -1,
.num_resources = ARRAY_SIZE(wdt_resources),
.resource = wdt_resources,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index ef9ff1f..4bb8132 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -375,7 +375,7 @@ static struct clk_lookup dm355_clks[] = {
CLK(NULL, pwm3, pwm3_clk),
CLK(NULL, timer0, timer0_clk),
CLK(NULL, timer1, timer1_clk),
- CLK(watchdog, NULL, timer2_clk),
+ CLK(davinci-wdt, NULL, timer2_clk),
CLK(NULL, timer3, timer3_clk),
CLK(NULL, rto
[PATCH v2] ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemif
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for another platform like Keystone.
The Keysone platform is going to use TI AEMIF driver.
If TI AEMIF is used we don't need to set timings and bus width.
It is done by AEMIF driver.
To get rid of davinci-nand driver dependency on aemif platform code
we moved aemif code to davinci platform.
The platform AEMIF code (aemif.c) has to be removed once Davinci
will be converted to DT and use ti-aemif.c driver.
The long device name davinci_ntosd2_nandflash_device was renamed
to ntosd2_nandflash as requested by Sekhar Nori, because after
adding changes the line is so broken that its almost unreadable.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
v2..v1:
- enabled AEMIF clock
- removed EXPORT_SYMBOL(davinci_aemif_setup)
- renamed ugly name davinci_ntosd2_nandflash_device
CC:
Sekhar Nori nsek...@ti.com
arch/arm/mach-davinci/aemif.c | 89 ++-
arch/arm/mach-davinci/board-da830-evm.c |3 +
arch/arm/mach-davinci/board-da850-evm.c |3 +
arch/arm/mach-davinci/board-dm355-evm.c |5 ++
arch/arm/mach-davinci/board-dm355-leopard.c |5 ++
arch/arm/mach-davinci/board-dm365-evm.c |4 +
arch/arm/mach-davinci/board-dm644x-evm.c|5 ++
arch/arm/mach-davinci/board-dm646x-evm.c|3 +
arch/arm/mach-davinci/board-mityomapl138.c |3 +
arch/arm/mach-davinci/board-neuros-osd2.c | 13 +++-
arch/arm/mach-davinci/devices-tnetv107x.c |3 +
drivers/mtd/nand/davinci_nand.c | 23 --
include/linux/platform_data/mtd-davinci-aemif.h |5 +-
13 files changed, 133 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index f091a90..64dccfc 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -16,6 +16,7 @@
#include linux/time.h
#include linux/platform_data/mtd-davinci-aemif.h
+#include linux/platform_data/mtd-davinci.h
/* Timing value configuration */
@@ -43,6 +44,17 @@
WSTROBE(WSTROBE_MAX) | \
WSETUP(WSETUP_MAX))
+static inline unsigned int davinci_aemif_readl(void __iomem *base, int offset)
+{
+ return readl_relaxed(base + offset);
+}
+
+static inline void davinci_aemif_writel(void __iomem *base,
+ int offset, unsigned long value)
+{
+ writel_relaxed(value, base + offset);
+}
+
/*
* aemif_calc_rate - calculate timing data.
* @wanted: The cycle time needed in nanoseconds.
@@ -86,7 +98,7 @@ static int aemif_calc_rate(int wanted, unsigned long clk, int
max)
*
* Returns 0 on success, else negative errno.
*/
-int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+static int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
void __iomem *base, unsigned cs)
{
unsigned set, val;
@@ -130,4 +142,77 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing
*t,
return 0;
}
-EXPORT_SYMBOL(davinci_aemif_setup_timing);
+
+/**
+ * davinci_aemif_setup - setup AEMIF interface by davinci_nand_pdata
+ * @pdev - link to platform device to setup settings for
+ *
+ * This function does not use any locking while programming the AEMIF
+ * because it is expected that there is only one user of a given
+ * chip-select.
+ *
+ * Returns 0 on success, else negative errno.
+ */
+int davinci_aemif_setup(struct platform_device *pdev)
+{
+ struct davinci_nand_pdata *pdata = dev_get_platdata(pdev-dev);
+ uint32_t val;
+ struct resource *res;
+ void __iomem *base;
+ struct clk* clk;
+ int ret = 0;
+
+ clk = clk_get(pdev-dev, aemif);
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_dbg(pdev-dev, unable to get AEMIF clock, err %d\n, ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(clk);
+ if (ret 0) {
+ dev_dbg(pdev-dev, unable to enable AEMIF clock, err %d\n,
+ ret);
+ return ret;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res) {
+ dev_err(pdev-dev, cannot get IORESOURCE_MEM\n);
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ base = ioremap(res-start, resource_size(res));
+ if (!base) {
+ dev_err(pdev-dev, ioremap failed for resource %pR\n, res);
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ /*
+* Setup Async configuration register in case we did not boot
+* from NAND and so bootloader did not bother to set it up.
+*/
+ val = davinci_aemif_readl(base, A1CR_OFFSET + pdev-id * 4);
+ /*
+* Extended Wait
[PATCH 1/6] watchdog: davinci: change driver to use WDT core
To reduce code duplicate and increase code readability use WDT core
code to handle WDT interface.
Remove io_lock as the WDT core uses mutex to lock each wdt device.
Remove wdt_state as the WDT core track state with its own variable.
The watchdog_init_timeout() can read timeout value from timeout-sec
property if the passed value is out of bounds. The heartbeat is
initialized in next way. If heartbeat is not set thought module
parameter, try to read it's value from WDT node timeout-sec property.
If node has no one, use default value.
The heartbeat is hold in wdd-timeout by WDT core, so use it in
order to set timeout period.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
drivers/watchdog/Kconfig |2 +
drivers/watchdog/davinci_wdt.c | 152 ++--
2 files changed, 39 insertions(+), 115 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d1d53f3..d7db13d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -271,6 +271,8 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
depends on ARCH_DAVINCI
+ select WATCHDOG_CORE
+ select WATCHDOG_NOWAYOUT
help
Say Y here if to include support for the watchdog timer
in the DaVinci DM644x/DM646x processors.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index bead774..cb9e8c5 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -3,7 +3,7 @@
*
* Watchdog driver for DaVinci DM644x/DM646x processors
*
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2013 Texas Instruments.
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
@@ -15,18 +15,12 @@
#include linux/moduleparam.h
#include linux/types.h
#include linux/kernel.h
-#include linux/fs.h
-#include linux/miscdevice.h
#include linux/watchdog.h
#include linux/init.h
-#include linux/bitops.h
#include linux/platform_device.h
-#include linux/spinlock.h
-#include linux/uaccess.h
#include linux/io.h
#include linux/device.h
#include linux/clk.h
-#include linux/slab.h
#include linux/err.h
#define MODULE_NAME DAVINCI-WDT:
@@ -61,31 +55,12 @@
#define WDKEY_SEQ0 (0xa5c6 16)
#define WDKEY_SEQ1 (0xda7e 16)
-static int heartbeat = DEFAULT_HEARTBEAT;
-
-static DEFINE_SPINLOCK(io_lock);
-static unsigned long wdt_status;
-#define WDT_IN_USE0
-#define WDT_OK_TO_CLOSE 1
-#define WDT_REGION_INITED 2
-#define WDT_DEVICE_INITED 3
-
+static int heartbeat;
static void __iomem*wdt_base;
struct clk *wdt_clk;
+static struct watchdog_device wdt_wdd;
-static void wdt_service(void)
-{
- spin_lock(io_lock);
-
- /* put watchdog in service state */
- iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
- /* put watchdog in active state */
- iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
-
- spin_unlock(io_lock);
-}
-
-static void wdt_enable(void)
+static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
@@ -93,8 +68,6 @@ static void wdt_enable(void)
wdt_freq = clk_get_rate(wdt_clk);
- spin_lock(io_lock);
-
/* disable, internal clock source */
iowrite32(0, wdt_base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
@@ -105,9 +78,9 @@ static void wdt_enable(void)
iowrite32(0, wdt_base + TIM12);
iowrite32(0, wdt_base + TIM34);
/* set timeout period */
- timer_margin = (((u64)heartbeat * wdt_freq) 0x);
+ timer_margin = (((u64)wdd-timeout * wdt_freq) 0x);
iowrite32(timer_margin, wdt_base + PRD12);
- timer_margin = (((u64)heartbeat * wdt_freq) 32);
+ timer_margin = (((u64)wdd-timeout * wdt_freq) 32);
iowrite32(timer_margin, wdt_base + PRD34);
/* enable run continuously */
iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
@@ -119,84 +92,28 @@ static void wdt_enable(void)
iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
/* put watchdog in active state */
iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
-
- spin_unlock(io_lock);
-}
-
-static int davinci_wdt_open(struct inode *inode, struct file *file)
-{
- if (test_and_set_bit(WDT_IN_USE, wdt_status))
- return -EBUSY;
-
- wdt_enable();
-
- return nonseekable_open(inode, file);
+ return 0;
}
-static ssize_t
-davinci_wdt_write(struct file *file, const char *data, size_t len,
- loff_t *ppos)
+static int davinci_wdt_ping(struct watchdog_device *wdd)
{
- if (len)
- wdt_service();
-
- return len;
+ /* put watchdog in service state */
+ iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
+ /* put watchdog
[PATCH v2 0/6] Update Davinci watchdog driver
These patches are intended to update Davinci watchdog to use WDT core and reuse driver for keystone arch, because Keystone uses the similar IP like Davinci. See Documentation: Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf Also: - improved to support GET_TIMELEFT option. - added clocks and timeout-sec properties to DT. Based on git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git keystone/master v1..v2: - watchdog: davinci: change driver to use WDT core corrected 2011 - 2006-2013 removed useless function comment corrected initialization of heartbeat switched on CONFIG_WATCHDOG_NOWAYOUT option - watchdog: davinci: use davinci_wdt_device structure to hold device data substituted wdd to watchdog device in commit message - watchdog: davinci: add GET_TIMELEFT option support corrected comment (is - has) removed redundant error message clock freq is not set - watchdog: davinci: add GET_STATUS option support dropped - watchdog: davinci: add timeout-sec property use consistent formatting - watchdog: davinci: reuse driver for keystone arch use consistent formatting - watchdog: davinci: add clocks property merged with above patch Ivan Khoronzhuk (6): watchdog: davinci: change driver to use WDT core watchdog: davinci: use davinci_wdt_device structure to hold device data watchdog: davinci: add GET_TIMELEFT option support watchdog: davinci: add timeout-sec property watchdog: davinci: reuse driver for keystone arch arm: dts: keystone: add watchdog entry .../devicetree/bindings/watchdog/davinci-wdt.txt | 15 +- arch/arm/boot/dts/keystone.dts |6 + drivers/watchdog/Kconfig |6 +- drivers/watchdog/davinci_wdt.c | 227 +--- 4 files changed, 122 insertions(+), 132 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/6] watchdog: davinci: add GET_TIMELEFT option support
Currently, the davinci watchdog can be read while counting,
so we can add ability to report the remaining time before
the system will reboot.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
drivers/watchdog/davinci_wdt.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index b353df5..55deaf8 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -116,6 +116,31 @@ static int davinci_wdt_ping(struct watchdog_device *wdd)
return 0;
}
+static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
+{
+ u64 timer_counter;
+ unsigned long freq;
+ u32 val;
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
+
+ /* if timeout has occured then return 0 */
+ val = ioread32(davinci_wdt-base + WDTCR);
+ if (val WDFLAG)
+ return 0;
+
+ freq = clk_get_rate(davinci_wdt-clk);
+
+ if (!freq)
+ return 0;
+
+ timer_counter = ioread32(davinci_wdt-base + TIM12);
+ timer_counter |= ((u64)ioread32(davinci_wdt-base + TIM34) 32);
+
+ do_div(timer_counter, freq);
+
+ return wdd-timeout - timer_counter;
+}
+
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
.identity = DaVinci Watchdog,
@@ -126,6 +151,7 @@ static const struct watchdog_ops davinci_wdt_ops = {
.start = davinci_wdt_start,
.stop = davinci_wdt_ping,
.ping = davinci_wdt_ping,
+ .get_timeleft = davinci_wdt_get_timeleft,
};
static int davinci_wdt_probe(struct platform_device *pdev)
--
1.7.9.5
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[PATCH 4/6] watchdog: davinci: add timeout-sec property
Since Davinci WDT has been switched to use WDT core, it became able
to support timeout-sec property, so add it to it's binding description.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/watchdog/davinci-wdt.txt |4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index 75558cc..e450134 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -4,9 +4,13 @@ Required properties:
- compatible : Should be ti,davinci-wdt
- reg : Should contain WDT registers location and length
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
Examples:
wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
+ timeout-sec = 30;
};
--
1.7.9.5
--
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[PATCH 6/6] arm: dts: keystone: add watchdog entry
Add watchdog entry to keystone device tree.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Guenter Roeck li...@roeck-us.net
---
arch/arm/boot/dts/keystone.dts |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
index 100bdf5..a6e5f91 100644
--- a/arch/arm/boot/dts/keystone.dts
+++ b/arch/arm/boot/dts/keystone.dts
@@ -179,5 +179,11 @@
interrupts = GIC_SPI 300 IRQ_TYPE_EDGE_RISING;
clocks = clkspi;
};
+
+ wdt: wdt@022f0080 {
+ compatible = ti,keystone-wdt;
+ reg = 0x022f0080 0x80;
+ clocks = clkwdtimer0;
+ };
};
};
--
1.7.9.5
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[PATCH 5/6] watchdog: davinci: reuse driver for keystone arch
The keystone arch use the same IP watchdog, so add ti,keystone-wdt
compatible and correct identity.
The Keystone arch is using clocks in DT and source clock for watchdog
has to be specified, so add this to binding.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/watchdog/davinci-wdt.txt | 11 +--
drivers/watchdog/Kconfig |4 ++--
drivers/watchdog/davinci_wdt.c |3 ++-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index e450134..0f1aa99 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -1,16 +1,23 @@
-DaVinci Watchdog Timer (WDT) Controller
+Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
Required properties:
-- compatible : Should be ti,davinci-wdt
+- compatible : Should be ti,davinci-wdt or ti,keystone-wdt
- reg : Should contain WDT registers location and length
+- clocks : phandle reference to the controller clock.
+ Required only for Keystone arch. See clock-bindings.txt
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
+Documentation:
+Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
+Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
+
Examples:
wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
timeout-sec = 30;
+ clocks = clkwdtimer0;
};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d7db13d..addfc2c 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -270,12 +270,12 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
- depends on ARCH_DAVINCI
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
select WATCHDOG_CORE
select WATCHDOG_NOWAYOUT
help
Say Y here if to include support for the watchdog timer
- in the DaVinci DM644x/DM646x processors.
+ in the DaVinci DM644x/DM646x or Keystone processors.
To compile this driver as a module, choose M here: the
module will be called davinci_wdt.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 55deaf8..a6d365a 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -143,7 +143,7 @@ static unsigned int davinci_wdt_get_timeleft(struct
watchdog_device *wdd)
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
- .identity = DaVinci Watchdog,
+ .identity = DaVinci/Keystone Watchdog,
};
static const struct watchdog_ops davinci_wdt_ops = {
@@ -212,6 +212,7 @@ static int davinci_wdt_remove(struct platform_device *pdev)
static const struct of_device_id davinci_wdt_of_match[] = {
{ .compatible = ti,davinci-wdt, },
+ { .compatible = ti,keystone-wdt, },
{},
};
MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
--
1.7.9.5
--
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[PATCH 2/6] watchdog: davinci: use davinci_wdt_device structure to hold device data
Some SoCs, like Keystone 2, can support more than one WDT and each
watchdog device has to use it's own base address, clock source,
watchdog device, so add new davinci_wdt_device structure to hold
device data.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter roeck li...@roeck-us.net
---
drivers/watchdog/davinci_wdt.c | 74 ++--
1 file changed, 48 insertions(+), 26 deletions(-)
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index cb9e8c5..b353df5 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -56,51 +56,63 @@
#define WDKEY_SEQ1 (0xda7e 16)
static int heartbeat;
-static void __iomem*wdt_base;
-struct clk *wdt_clk;
-static struct watchdog_device wdt_wdd;
+
+/*
+ * struct to hold data for each WDT device
+ * @base - base io address of WD device
+ * @clk - source clock of WDT
+ * @wdd - hold watchdog device as is in WDT core
+ */
+struct davinci_wdt_device {
+ void __iomem*base;
+ struct clk *clk;
+ struct watchdog_device wdd;
+};
static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
unsigned long wdt_freq;
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
- wdt_freq = clk_get_rate(wdt_clk);
+ wdt_freq = clk_get_rate(davinci_wdt-clk);
/* disable, internal clock source */
- iowrite32(0, wdt_base + TCR);
+ iowrite32(0, davinci_wdt-base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
- iowrite32(0, wdt_base + TGCR);
+ iowrite32(0, davinci_wdt-base + TGCR);
tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
- iowrite32(tgcr, wdt_base + TGCR);
+ iowrite32(tgcr, davinci_wdt-base + TGCR);
/* clear counter regs */
- iowrite32(0, wdt_base + TIM12);
- iowrite32(0, wdt_base + TIM34);
+ iowrite32(0, davinci_wdt-base + TIM12);
+ iowrite32(0, davinci_wdt-base + TIM34);
/* set timeout period */
timer_margin = (((u64)wdd-timeout * wdt_freq) 0x);
- iowrite32(timer_margin, wdt_base + PRD12);
+ iowrite32(timer_margin, davinci_wdt-base + PRD12);
timer_margin = (((u64)wdd-timeout * wdt_freq) 32);
- iowrite32(timer_margin, wdt_base + PRD34);
+ iowrite32(timer_margin, davinci_wdt-base + PRD34);
/* enable run continuously */
- iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
+ iowrite32(ENAMODE12_PERIODIC, davinci_wdt-base + TCR);
/* Once the WDT is in pre-active state write to
* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
* write protected (except for the WDKEY field)
*/
/* put watchdog in pre-active state */
- iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt-base + WDTCR);
/* put watchdog in active state */
- iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt-base + WDTCR);
return 0;
}
static int davinci_wdt_ping(struct watchdog_device *wdd)
{
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
+
/* put watchdog in service state */
- iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ0, davinci_wdt-base + WDTCR);
/* put watchdog in active state */
- iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ1, davinci_wdt-base + WDTCR);
return 0;
}
@@ -122,14 +134,21 @@ static int davinci_wdt_probe(struct platform_device *pdev)
struct device *dev = pdev-dev;
struct resource *wdt_mem;
struct watchdog_device *wdd;
+ struct davinci_wdt_device *davinci_wdt;
+
+ davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
+ if (!davinci_wdt)
+ return -ENOMEM;
- wdt_clk = devm_clk_get(dev, NULL);
- if (WARN_ON(IS_ERR(wdt_clk)))
- return PTR_ERR(wdt_clk);
+ davinci_wdt-clk = devm_clk_get(dev, NULL);
+ if (WARN_ON(IS_ERR(davinci_wdt-clk)))
+ return PTR_ERR(davinci_wdt-clk);
- clk_prepare_enable(wdt_clk);
+ clk_prepare_enable(davinci_wdt-clk);
- wdd = wdt_wdd;
+ platform_set_drvdata(pdev, davinci_wdt);
+
+ wdd = davinci_wdt-wdd;
wdd-info = davinci_wdt_info;
wdd-ops= davinci_wdt_ops;
wdd-min_timeout= 1;
@@ -140,12 +159,13 @@ static int davinci_wdt_probe(struct platform_device *pdev)
dev_info(dev, heartbeat %d sec\n, wdd-timeout);
+ watchdog_set_drvdata(wdd, davinci_wdt);
watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
wdt_mem
[PATCH 3/7] mtd: nand: davinci: check required ti,davinci-chipselect property
The property ti,davinci-chipselect is required. So we have to check if it is set. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/mtd/nand/davinci_nand.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index ddcd7c8..9a96ac7 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -545,6 +545,9 @@ static struct davinci_nand_pdata if (!of_property_read_u32(pdev-dev.of_node, ti,davinci-chipselect, prop)) pdev-id = prop; + else + return ERR_PTR(-EINVAL); + if (!of_property_read_u32(pdev-dev.of_node, ti,davinci-mask-ale, prop)) pdata-mask_ale = prop; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 5/7] mtd: nand: davinci: move bindings under mtd
Move bindings under mtd. Do this in order to make davinci-nand
driver usable by keystone architecture.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/arm/davinci/nand.txt | 46
.../devicetree/bindings/mtd/davinci-nand.txt | 46
2 files changed, 46 insertions(+), 46 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/davinci/nand.txt
create mode 100644 Documentation/devicetree/bindings/mtd/davinci-nand.txt
diff --git a/Documentation/devicetree/bindings/arm/davinci/nand.txt
b/Documentation/devicetree/bindings/arm/davinci/nand.txt
deleted file mode 100644
index 3545ea7..000
--- a/Documentation/devicetree/bindings/arm/davinci/nand.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Texas Instruments Davinci NAND
-
-This file provides information, what the device node for the
-davinci nand interface contain.
-
-Required properties:
-- compatible: ti,davinci-nand;
-- reg : contain 2 offset/length values:
-- offset and length for the access window
-- offset and length for accessing the aemif control registers
-- ti,davinci-chipselect: Indicates on the davinci_nand driver which
- chipselect is used for accessing the nand.
-
-Recommended properties :
-- ti,davinci-mask-ale: mask for ale
-- ti,davinci-mask-cle: mask for cle
-- ti,davinci-mask-chipsel: mask for chipselect
-- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
- - none
- - soft
- - hw
-- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
-- ti,davinci-nand-buswidth: buswidth 8 or 16
-- ti,davinci-nand-use-bbt: use flash based bad block table support.
-
-nand device bindings may contain additional sub-nodes describing
-partitions of the address space. See partition.txt for more detail.
-
-Example(da850 EVM ):
-nand_cs3@6200 {
- compatible = ti,davinci-nand;
- reg = 0x6200 0x807ff
- 0x6800 0x8000;
- ti,davinci-chipselect = 1;
- ti,davinci-mask-ale = 0;
- ti,davinci-mask-cle = 0;
- ti,davinci-mask-chipsel = 0;
- ti,davinci-ecc-mode = hw;
- ti,davinci-ecc-bits = 4;
- ti,davinci-nand-use-bbt;
-
- partition@18 {
- label = ubifs;
- reg = 0x18 0x7e8;
- };
-};
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
new file mode 100644
index 000..3545ea7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
@@ -0,0 +1,46 @@
+* Texas Instruments Davinci NAND
+
+This file provides information, what the device node for the
+davinci nand interface contain.
+
+Required properties:
+- compatible: ti,davinci-nand;
+- reg : contain 2 offset/length values:
+- offset and length for the access window
+- offset and length for accessing the aemif control registers
+- ti,davinci-chipselect: Indicates on the davinci_nand driver which
+ chipselect is used for accessing the nand.
+
+Recommended properties :
+- ti,davinci-mask-ale: mask for ale
+- ti,davinci-mask-cle: mask for cle
+- ti,davinci-mask-chipsel: mask for chipselect
+- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
+ - none
+ - soft
+ - hw
+- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
+- ti,davinci-nand-buswidth: buswidth 8 or 16
+- ti,davinci-nand-use-bbt: use flash based bad block table support.
+
+nand device bindings may contain additional sub-nodes describing
+partitions of the address space. See partition.txt for more detail.
+
+Example(da850 EVM ):
+nand_cs3@6200 {
+ compatible = ti,davinci-nand;
+ reg = 0x6200 0x807ff
+ 0x6800 0x8000;
+ ti,davinci-chipselect = 1;
+ ti,davinci-mask-ale = 0;
+ ti,davinci-mask-cle = 0;
+ ti,davinci-mask-chipsel = 0;
+ ti,davinci-ecc-mode = hw;
+ ti,davinci-ecc-bits = 4;
+ ti,davinci-nand-use-bbt;
+
+ partition@18 {
+ label = ubifs;
+ reg = 0x18 0x7e8;
+ };
+};
--
1.7.9.5
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[PATCH 1/7] mtd: nand: davinci: fix driver registration
When kernel is booted using DT, there is no guarantee that Davinci
NAND device has been created already at the time when driver init
function is executed. Therefore, platform_driver_probe() can't be used
because this may result the Davinci NAND driver will never be probed.
The driver probing has to be made with core mechanism.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
drivers/mtd/nand/davinci_nand.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index b77a01e..d87213f 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -877,6 +877,7 @@ static int __exit nand_davinci_remove(struct
platform_device *pdev)
}
static struct platform_driver nand_davinci_driver = {
+ .probe = nand_davinci_probe,
.remove = __exit_p(nand_davinci_remove),
.driver = {
.name = davinci_nand,
@@ -886,7 +887,7 @@ static struct platform_driver nand_davinci_driver = {
};
MODULE_ALIAS(platform:davinci_nand);
-module_platform_driver_probe(nand_davinci_driver, nand_davinci_probe);
+module_platform_driver(nand_davinci_driver);
MODULE_LICENSE(GPL);
MODULE_AUTHOR(Texas Instruments);
--
1.7.9.5
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[PATCH 2/7] mtd: nand: davinci: return ENOMEM if memory allocation is failed
In case when memory allocation is failed the driver should return ENOMEM instead of ENODEV. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/mtd/nand/davinci_nand.c |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d87213f..ddcd7c8 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -541,7 +541,7 @@ static struct davinci_nand_pdata GFP_KERNEL); pdev-dev.platform_data = pdata; if (!pdata) - return NULL; + return ERR_PTR(-ENOMEM); if (!of_property_read_u32(pdev-dev.of_node, ti,davinci-chipselect, prop)) pdev-id = prop; @@ -598,6 +598,9 @@ static int __init nand_davinci_probe(struct platform_device *pdev) nand_ecc_modes_tecc_mode; pdata = nand_davinci_get_pdata(pdev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + /* insist on board-specific configuration */ if (!pdata) return -ENODEV; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 6/7] mtd: nand: davinci: extend description of bindings
Extend bindings for davinci_nand driver to be more clear.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/mtd/davinci-nand.txt | 77 ++--
1 file changed, 54 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
index 3545ea7..d2a3fc0 100644
--- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
@@ -1,36 +1,67 @@
-* Texas Instruments Davinci NAND
+Device tree bindings for Texas instruments Davinci NAND controller
-This file provides information, what the device node for the
-davinci nand interface contain.
+This file provides information, what the device node for the davinci NAND
+interface contains.
+
+Documentation:
+Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
Required properties:
-- compatible: ti,davinci-nand;
-- reg : contain 2 offset/length values:
-- offset and length for the access window
-- offset and length for accessing the aemif control registers
-- ti,davinci-chipselect: Indicates on the davinci_nand driver which
- chipselect is used for accessing the nand.
+
+- compatible: ti,davinci-nand
+
+- reg: Contains 2 offset/length values:
+ - offset and length for the access window.
+ - offset and length for accessing the AEMIF
+ control registers.
+
+- ti,davinci-chipselect: number of chipselect. Indicates on the
+ davinci_nand driver which chipselect is used
+ for accessing the nand.
+ Can be in the range [0-3].
Recommended properties :
-- ti,davinci-mask-ale: mask for ale
-- ti,davinci-mask-cle: mask for cle
-- ti,davinci-mask-chipsel: mask for chipselect
-- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
- - none
- - soft
- - hw
-- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
-- ti,davinci-nand-buswidth: buswidth 8 or 16
-- ti,davinci-nand-use-bbt: use flash based bad block table support.
-
-nand device bindings may contain additional sub-nodes describing
-partitions of the address space. See partition.txt for more detail.
+
+- ti,davinci-mask-ale: mask for ALE. Needed for executing address
+ phase. These offset will be added to the base
+ address for the chip select space the NAND Flash
+ device is connected to.
+ If not set equal to 0x08.
+
+- ti,davinci-mask-cle: mask for CLE. Needed for executing command
+ phase. These offset will be added to the base
+ address for the chip select space the NAND Flash
+ device is connected to.
+ If not set equal to 0x10.
+
+- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
+ addresses for given chipselect.
+
+- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
+ valid values for davinci driver:
+ - none
+ - soft
+ - hw
+
+- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
+
+- ti,davinci-nand-buswidth:buswidth 8 or 16.
+
+- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
+ identifier is saved in OOB area.
+
+Nand device bindings may contain additional sub-nodes describing partitions of
+the address space. See partition.txt for more detail. The NAND Flash timing
+values must be programmed in the chip select’s node of AEMIF
+memory-controller (see Documentation/devicetree/bindings/memory-controllers/
+davinci-aemif.txt).
Example(da850 EVM ):
+
nand_cs3@6200 {
compatible = ti,davinci-nand;
reg = 0x6200 0x807ff
- 0x6800 0x8000;
+ 0x6800 0x8000;
ti,davinci-chipselect = 1;
ti,davinci-mask-ale = 0;
ti,davinci-mask-cle = 0;
--
1.7.9.5
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[PATCH 7/7] mtd: nand: davinci: adjust DT properties to MTD generic
The properties davinci-ecc-mode, davinci-nand-use-bbt, davinci-nand-buswidth
are MTD generic. Correct names for them are: nand-ecc-mode, nand-on-flash-bbt,
nand-bus-width accordingly. So rename them in dts and documentation.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/mtd/davinci-nand.txt | 25
drivers/mtd/nand/davinci_nand.c| 11 ++---
2 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
index d2a3fc0..befaa5b 100644
--- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
@@ -37,7 +37,7 @@ Recommended properties :
- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
addresses for given chipselect.
-- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
+- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
valid values for davinci driver:
- none
- soft
@@ -45,10 +45,25 @@ Recommended properties :
- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
-- ti,davinci-nand-buswidth:buswidth 8 or 16.
+- nand-bus-width: buswidth 8 or 16. If not present 8.
+
+- nand-on-flash-bbt: use flash based bad block table support. OOB
+ identifier is saved in OOB area. If not present
+ false.
+
+Deprecated properties:
+
+- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
+ valid values for davinci driver:
+ - none
+ - soft
+ - hw
+
+- ti,davinci-nand-buswidth:buswidth 8 or 16. If not present 8.
- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
- identifier is saved in OOB area.
+ identifier is saved in OOB area. If not present
+ false.
Nand device bindings may contain additional sub-nodes describing partitions of
the address space. See partition.txt for more detail. The NAND Flash timing
@@ -66,9 +81,9 @@ nand_cs3@6200 {
ti,davinci-mask-ale = 0;
ti,davinci-mask-cle = 0;
ti,davinci-mask-chipsel = 0;
- ti,davinci-ecc-mode = hw;
+ nand-ecc-mode = hw;
ti,davinci-ecc-bits = 4;
- ti,davinci-nand-use-bbt;
+ nand-on-flash-bbt;
partition@18 {
label = ubifs;
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index c0be223..f7b21b8 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -534,7 +534,6 @@ static struct davinci_nand_pdata
struct davinci_nand_pdata *pdata;
const char *mode;
u32 prop;
- int len;
pdata = devm_kzalloc(pdev-dev,
sizeof(struct davinci_nand_pdata),
@@ -558,6 +557,8 @@ static struct davinci_nand_pdata
ti,davinci-mask-chipsel, prop))
pdata-mask_chipsel = prop;
if (!of_property_read_string(pdev-dev.of_node,
+ nand-ecc-mode, mode) ||
+ !of_property_read_string(pdev-dev.of_node,
ti,davinci-ecc-mode, mode)) {
if (!strncmp(none, mode, 4))
pdata-ecc_mode = NAND_ECC_NONE;
@@ -570,11 +571,15 @@ static struct davinci_nand_pdata
ti,davinci-ecc-bits, prop))
pdata-ecc_bits = prop;
if (!of_property_read_u32(pdev-dev.of_node,
+ nand-bus-width, prop) ||
+ !of_property_read_u32(pdev-dev.of_node,
ti,davinci-nand-buswidth, prop))
if (prop == 16)
pdata-options |= NAND_BUSWIDTH_16;
- if (of_find_property(pdev-dev.of_node,
- ti,davinci-nand-use-bbt, len))
+ if (of_property_read_bool(pdev-dev.of_node,
+ nand-on-flash-bbt) ||
+ of_property_read_bool(pdev-dev.of_node,
+ ti,davinci-nand-use-bbt))
pdata-bbt_options = NAND_BBT_USE_FLASH;
}
--
1.7.9.5
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[PATCH 4/7] mtd: nand: davinci: simplify error handling
There is not needed to use a lot of names for err handling.
It complicates code support and reading.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
drivers/mtd/nand/davinci_nand.c | 46 +++
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 9a96ac7..c0be223 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -615,8 +615,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
info = devm_kzalloc(pdev-dev, sizeof(*info), GFP_KERNEL);
if (!info) {
dev_err(pdev-dev, unable to allocate memory\n);
- ret = -ENOMEM;
- goto err_nomem;
+ return -ENOMEM;
}
platform_set_drvdata(pdev, info);
@@ -625,20 +624,16 @@ static int __init nand_davinci_probe(struct
platform_device *pdev)
res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res1 || !res2) {
dev_err(pdev-dev, resource missing\n);
- ret = -EINVAL;
- goto err_nomem;
+ return -EINVAL;
}
vaddr = devm_ioremap_resource(pdev-dev, res1);
- if (IS_ERR(vaddr)) {
- ret = PTR_ERR(vaddr);
- goto err_ioremap;
- }
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
base = devm_ioremap_resource(pdev-dev, res2);
- if (IS_ERR(base)) {
- ret = PTR_ERR(base);
- goto err_ioremap;
- }
+ if (IS_ERR(base))
+ return PTR_ERR(base);
info-dev = pdev-dev;
info-base = base;
@@ -705,7 +700,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
spin_unlock_irq(davinci_nand_lock);
if (ret == -EBUSY)
- goto err_ecc;
+ return ret;
info-chip.ecc.calculate = nand_davinci_calculate_4bit;
info-chip.ecc.correct = nand_davinci_correct_4bit;
@@ -721,8 +716,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
info-chip.ecc.strength = pdata-ecc_bits;
break;
default:
- ret = -EINVAL;
- goto err_ecc;
+ return -EINVAL;
}
info-chip.ecc.mode = ecc_mode;
@@ -730,7 +724,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
if (IS_ERR(info-clk)) {
ret = PTR_ERR(info-clk);
dev_dbg(pdev-dev, unable to get AEMIF clock, err %d\n, ret);
- goto err_clk;
+ return ret;
}
ret = clk_prepare_enable(info-clk);
@@ -759,7 +753,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
info-core_chipsel);
if (ret 0) {
dev_dbg(pdev-dev, NAND timing values setup fail\n);
- goto err_timing;
+ goto err;
}
spin_lock_irq(davinci_nand_lock);
@@ -775,7 +769,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
ret = nand_scan_ident(info-mtd, pdata-mask_chipsel ? 2 : 1, NULL);
if (ret 0) {
dev_dbg(pdev-dev, no NAND chip(s) found\n);
- goto err_scan;
+ goto err;
}
/* Update ECC layout if needed ... for 1-bit HW ECC, the default
@@ -789,7 +783,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
if (!chunks || info-mtd.oobsize 16) {
dev_dbg(pdev-dev, too small\n);
ret = -EINVAL;
- goto err_scan;
+ goto err;
}
/* For small page chips, preserve the manufacturer's
@@ -820,7 +814,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
dev_warn(pdev-dev, no 4-bit ECC support yet
for 4KiB-page NAND\n);
ret = -EIO;
- goto err_scan;
+ goto err;
syndrome_done:
info-chip.ecc.layout = info-ecclayout;
@@ -828,7 +822,7 @@ syndrome_done:
ret = nand_scan_tail(info-mtd);
if (ret 0)
- goto err_scan;
+ goto err;
if (pdata-parts)
ret = mtd_device_parse_register(info-mtd, NULL, NULL,
@@ -841,7 +835,7 @@ syndrome_done:
NULL, 0);
}
if (ret 0)
- goto err_scan;
+ goto err;
val = davinci_nand_readl(info, NRCSR_OFFSET);
dev_info(pdev-dev, controller rev. %d.%d\n,
@@ -849,8
[PATCH 0/7] Davinci nand driver fixes and updates
This series contains fixes and updates of Davinci nand driver, in order to prepare it to be reused for Keystone platform. V1: https://lkml.org/lkml/2013/11/11/352 Ivan Khoronzhuk (7): mtd: nand: davinci: fix driver registration mtd: nand: davinci: return ENOMEM if memory allocation is failed mtd: nand: davinci: check required ti,davinci-chipselect property mtd: nand: davinci: simplify error handling mtd: nand: davinci: move bindings under mtd mtd: nand: davinci: extend description of bindings mtd: nand: davinci: adjust DT properties to MTD generic .../devicetree/bindings/arm/davinci/nand.txt | 46 -- .../devicetree/bindings/mtd/davinci-nand.txt | 92 drivers/mtd/nand/davinci_nand.c| 68 +++ 3 files changed, 126 insertions(+), 80 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/davinci/nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/davinci-nand.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/2] Introduce AEMIF driver for Davinci/Keystone archs
These patches introduce Async External Memory Interface (EMIF16/AEMIF) controller driver for Davinci/Keystone archs. V1: https://lkml.org/lkml/2013/11/11/352 Ivan Khoronzhuk (2): memory: ti-aemif: introduce AEMIF driver memory: ti-aemif: add bindings for AEMIF driver .../bindings/memory-controllers/ti-aemif.txt | 198 ++ drivers/memory/Kconfig | 11 + drivers/memory/Makefile|1 + drivers/memory/ti-aemif.c | 415 4 files changed, 625 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt create mode 100644 drivers/memory/ti-aemif.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/2] memory: ti-aemif: add bindings for AEMIF driver
Add bindings for AEMIF controller drivers/memory/ti-aemif.c Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- .../bindings/memory-controllers/ti-aemif.txt | 198 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt new file mode 100644 index 000..be0c0cb --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt @@ -0,0 +1,198 @@ +* Device tree bindings for Texas instruments AEMIF controller + +Th Async External Memory Interface (EMIF16/AEMIF) controller is intended to +provide a glue-less interface to a variety of asynchronous memory devices like +ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories +can be accessed at any given time via four chip selects with 64M byte access +per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM +and Mobile SDR are not supported. + +Documentation: +Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf +OMAP-L138 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf +Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf + +Required properties: + +- compatible: ti,davinci-aemif + ti,keystone-aemif + ti,omap-L138-aemif + +- #address-cells: Must be 2. The first cell is the memory partition + number. The 0 partition is for chip selects. And the + second cell is the offset into the partition, for the 0 + partition it corresponds to chip select offset. + +- #size-cells: Must be set to 1. + +- reg: contains offset/length value for AEMIF control registers + space. + +- ranges: Must be set up to reflect the memory layout for 4 + chipselects and for AEMIF control range. + +- clocks: phandle reference to the controller clock. Required only + if clock tree data present in device tree. + See clock-bindings.txt + +- clock-names: clock name. It has to be aemif. Required only if clock + tree data present in device tree, in another case don't + use it. + See clock-bindings.txt + +- clock-ranges:Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + See clock-bindings.txt + + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt). +There might be board specific devices like FPGAs. + +Required child cs node properties: + +- compatible: ti,aemif-cs + +- #address-cells: Must be 2. The first cell is the memory partition + number. The 0 partition is for chip selects. And the + second cell is the offset into the partition, for the 0 + partition it corresponds to chip select offset. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +- clock-ranges:Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + +Optional child cs node properties: + + +- ti,bus-width:width of the asynchronous device's data bus + 8 or 16 if not preset 8 + +- ti,cs-ss:enable/disable select strobe mode + In select strobe mode chip select behaves as + the strobe and is active only during the strobe + period. If present then enable. + +- ti,cs-ew:enable/disable extended wait mode + if set, the controller monitors the EMIFWAIT pin + mapped to that chip select to determine if the + device wants to extend the strobe period. If + present then enable. + +- ti,cs-ta:minimum turn around time, ns + Time between the end of one asynchronous memory + access and the start of another asynchronous + memory access. This delay is not incurred + between a read followed by read or a write + followed by a write to same chip select. + +- ti,cs-rsetup:read
[PATCH 1/2] memory: ti-aemif: introduce AEMIF driver
Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via four chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 For more informations see documentation: Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf OMAP-L138 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/memory/Kconfig| 11 ++ drivers/memory/Makefile |1 + drivers/memory/ti-aemif.c | 415 + 3 files changed, 427 insertions(+) create mode 100644 drivers/memory/ti-aemif.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 29a11db..cc0e3c8 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -7,6 +7,17 @@ menuconfig MEMORY if MEMORY +config TI_AEMIF + bool Texas Instruments AEMIF driver + depends on (ARCH_DAVINCI || ARCH_KEYSTONE) OF + help + This driver is for the AEMIF module available in Texas Instruments + SoCs. AEMIF stands for Asynchronous External Memory Interface and + is intended to provide a glue-less interface to a variety of + asynchronuous memory devices like ASRAM, NOR and NAND memory. A total + of 256M bytes of any of these memories can be accessed at a given + time via four chip selects with 64M byte access per chip select. + config TI_EMIF tristate Texas Instruments EMIF driver depends on ARCH_OMAP2PLUS diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 969d923..d4e150c 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -5,6 +5,7 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c new file mode 100644 index 000..a4b479a --- /dev/null +++ b/drivers/memory/ti-aemif.c @@ -0,0 +1,415 @@ +/* + * TI AEMIF driver + * + * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/ + * Copyright (C) Heiko Schocher h...@denx.de + * Copyright (C) Ivan Khoronzhuk ivan.khoronz...@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/err.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_platform.h +#include linux/platform_device.h + +#define TA_SHIFT 2 +#define RHOLD_SHIFT4 +#define RSTROBE_SHIFT 7 +#define RSETUP_SHIFT 13 +#define WHOLD_SHIFT17 +#define WSTROBE_SHIFT 20 +#define WSETUP_SHIFT 26 +#define EW_SHIFT 30 +#define SS_SHIFT 31 + +#define TA(x) ((x) TA_SHIFT) +#define RHOLD(x) ((x) RHOLD_SHIFT) +#define RSTROBE(x) ((x) RSTROBE_SHIFT) +#define RSETUP(x) ((x) RSETUP_SHIFT) +#define WHOLD(x) ((x) WHOLD_SHIFT) +#define WSTROBE(x) ((x) WSTROBE_SHIFT) +#define WSETUP(x) ((x) WSETUP_SHIFT) +#define EW(x) ((x) EW_SHIFT) +#define SS(x) ((x) SS_SHIFT) + +#define ASIZE_MAX 0x1 +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX0x3f +#define WSETUP_MAX 0xf +#define EW_MAX 0x1 +#define SS_MAX 0x1 +#define NUM_CS 4 + +#define TA_VAL(x) (((x) TA(TA_MAX)) TA_SHIFT) +#define RHOLD_VAL(x) (((x) RHOLD(RHOLD_MAX)) RHOLD_SHIFT) +#define RSTROBE_VAL(x) (((x) RSTROBE(RSTROBE_MAX)) RSTROBE_SHIFT) +#define RSETUP_VAL(x) (((x) RSETUP(RSETUP_MAX)) RSETUP_SHIFT) +#define WHOLD_VAL(x) (((x) WHOLD(WHOLD_MAX)) WHOLD_SHIFT) +#define WSTROBE_VAL(x) (((x) WSTROBE(WSTROBE_MAX)) WSTROBE_SHIFT) +#define WSETUP_VAL(x) (((x) WSETUP(WSETUP_MAX)) WSETUP_SHIFT) +#define EW_VAL(x) (((x) EW(EW_MAX)) EW_SHIFT) +#define SS_VAL(x) (((x) SS(SS_MAX)) SS_SHIFT) + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASKBIT(30) +#define ACR_SS_MASKBIT(31) +#define ASIZE_16BIT1 + +#define CONFIG_MASK(TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX
[PATCH 3/3] mtd: nand: davinci: don't request AEMIF address range
The TI AEMIF driver registers are used to setup timings for each chip
select. The same registers range is used to setup NAND settings.
The AEMIF and NAND drivers not use the same registers in this range.
In case with TI AEMIF driver, the memory address range is requested
already by AEMIF, so we cannot request it twice, just ioremap.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
drivers/mtd/nand/davinci_nand.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index e904364..aa30708 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -638,9 +638,11 @@ static int __init nand_davinci_probe(struct
platform_device *pdev)
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
- base = devm_ioremap_resource(pdev-dev, res2);
- if (IS_ERR(base))
- return PTR_ERR(base);
+ base = devm_ioremap(pdev-dev, res2-start, resource_size(res2));
+ if (!base) {
+ dev_err(pdev-dev, ioremap failed for resource %pR\n, res2);
+ return -EADDRNOTAVAIL;
+ }
info-dev = pdev-dev;
info-base = base;
--
1.7.9.5
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[PATCH 0/3] Reuse davinci-nand driver for Keystone arch
This series contains updates of Davinci nand driver, in order to be reused for Keystone platform. Depends on: - Davinci nand driver fixes and updates: https://lkml.org/lkml/2013/11/20/271 - Introduce AEMIF driver for Davinci/Keystone archs: http://lkml.org/lkml/2013/11/11/352 V1: https://lkml.org/lkml/2013/11/11/352 Ivan Khoronzhuk (3): mtd: nand: davinci: reuse driver for Keystone arch mtd: nand: davinci: don't set timings if AEMIF is used mtd: nand: davinci: don't request AEMIF address range .../devicetree/bindings/mtd/davinci-nand.txt |8 +-- drivers/mtd/nand/Kconfig |6 +-- drivers/mtd/nand/davinci_nand.c| 57 +--- 3 files changed, 45 insertions(+), 26 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/3] mtd: nand: davinci: don't set timings if AEMIF is used
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for Keystone only.
The Keysone platform is going to use TI AEMIF driver.
If TI AEMIF is used we don't need to set timings and bus width.
It is done by AEMIF driver (drivers/memory/ti-aemfi.c).
The timings code has to be removed together with Davinci aemif
platform code (aemif.c), once Davinci will be converted to DT and use
ti-aemif.c driver.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/mtd/nand/davinci_nand.c | 48 +--
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 8459720..e904364 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -605,6 +605,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
int ret;
uint32_tval;
nand_ecc_modes_tecc_mode;
+ bool aemif = IS_ENABLED(CONFIG_TI_AEMIF);
pdata = nand_davinci_get_pdata(pdev);
if (IS_ERR(pdata))
@@ -741,25 +742,38 @@ static int __init nand_davinci_probe(struct
platform_device *pdev)
}
/*
-* Setup Async configuration register in case we did not boot from
-* NAND and so bootloader did not bother to set it up.
+* TODO:
+* This is temp solution to support Davinci platform and it has to be
+* removed once Davinci will be updated to use ti-aemif.c driver.
*/
- val = davinci_nand_readl(info, A1CR_OFFSET + info-core_chipsel * 4);
-
- /* Extended Wait is not valid and Select Strobe mode is not used */
- val = ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
- if (info-chip.options NAND_BUSWIDTH_16)
- val |= 0x1;
-
- davinci_nand_writel(info, A1CR_OFFSET + info-core_chipsel * 4, val);
+ if (!aemif) {
+ /*
+* Setup Async configuration register in case we did not boot
+* from NAND and so bootloader did not bother to set it up.
+*/
+ val = davinci_nand_readl(info, A1CR_OFFSET +
+info-core_chipsel * 4);
- ret = 0;
- if (info-timing)
- ret = davinci_aemif_setup_timing(info-timing, info-base,
- info-core_chipsel);
- if (ret 0) {
- dev_dbg(pdev-dev, NAND timing values setup fail\n);
- goto err;
+ /*
+* Extended Wait is not valid and Select Strobe mode is not
+* used
+*/
+ val = ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
+ if (info-chip.options NAND_BUSWIDTH_16)
+ val |= 0x1;
+
+ davinci_nand_writel(info, A1CR_OFFSET +
+ info-core_chipsel * 4, val);
+
+ ret = 0;
+ if (info-timing)
+ ret = davinci_aemif_setup_timing(info-timing,
+info-base,
+info-core_chipsel);
+ if (ret 0) {
+ dev_dbg(pdev-dev, NAND timing values setup fail\n);
+ goto err;
+ }
}
spin_lock_irq(davinci_nand_lock);
--
1.7.9.5
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[PATCH 1/3] mtd: nand: davinci: reuse driver for Keystone arch
The Keystone arch has compatible nand device, so reuse it.
In case with Keystone it depends on TI_AEMIF because AEMIF
driver is responsible to set timings.
See http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/mtd/davinci-nand.txt |8 +---
drivers/mtd/nand/Kconfig |6 +++---
drivers/mtd/nand/davinci_nand.c|1 +
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
index befaa5b..cfb18ab 100644
--- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
@@ -1,14 +1,16 @@
-Device tree bindings for Texas instruments Davinci NAND controller
+Device tree bindings for Texas instruments Davinci/Keystone NAND controller
-This file provides information, what the device node for the davinci NAND
-interface contains.
+This file provides information, what the device node for the davinci/keystone
+NAND interface contains.
Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
+Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
Required properties:
- compatible: ti,davinci-nand
+ ti,keystone-nand
- reg: Contains 2 offset/length values:
- offset and length for the access window.
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index d885298..8bf69c7 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -492,11 +492,11 @@ config MTD_NAND_SH_FLCTL
for NAND Flash using FLCTL.
config MTD_NAND_DAVINCI
-tristate Support NAND on DaVinci SoC
-depends on ARCH_DAVINCI
+tristate Support NAND on DaVinci/Keystone SoC
+depends on ARCH_DAVINCI || (ARCH_KEYSTONE TI_AEMIF)
help
Enable the driver for NAND flash chips on Texas Instruments
- DaVinci processors.
+ DaVinci/Keystone processors.
config MTD_NAND_TXX9NDFMC
tristate NAND Flash support for TXx9 SoC
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index f7b21b8..8459720 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -523,6 +523,7 @@ static struct nand_ecclayout hwecc4_2048 __initconst = {
#if defined(CONFIG_OF)
static const struct of_device_id davinci_nand_of_match[] = {
{.compatible = ti,davinci-nand, },
+ {.compatible = ti,keystone-nand, },
{},
};
MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
--
1.7.9.5
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[PATCH v2 0/2] Introduce AEMIF driver for Davinci/Keystone archs
These patches introduce Async External Memory Interface (EMIF16/AEMIF) controller driver for Davinci/Keystone archs. v1..v2: - added ti.cs-chipselect property instead to represent chipselect number in cs node name. Ivan Khoronzhuk (2): memory: ti-aemif: introduce AEMIF driver memory: ti-aemif: add bindings for AEMIF driver .../bindings/memory-controllers/ti-aemif.txt | 201 ++ drivers/memory/Kconfig | 11 + drivers/memory/Makefile|1 + drivers/memory/ti-aemif.c | 415 4 files changed, 628 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt create mode 100644 drivers/memory/ti-aemif.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/2] memory: ti-aemif: introduce AEMIF driver
Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via four chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 For more informations see documentation: Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf OMAP-L138 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/memory/Kconfig| 11 ++ drivers/memory/Makefile |1 + drivers/memory/ti-aemif.c | 415 + 3 files changed, 427 insertions(+) create mode 100644 drivers/memory/ti-aemif.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 29a11db..cc0e3c8 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -7,6 +7,17 @@ menuconfig MEMORY if MEMORY +config TI_AEMIF + bool Texas Instruments AEMIF driver + depends on (ARCH_DAVINCI || ARCH_KEYSTONE) OF + help + This driver is for the AEMIF module available in Texas Instruments + SoCs. AEMIF stands for Asynchronous External Memory Interface and + is intended to provide a glue-less interface to a variety of + asynchronuous memory devices like ASRAM, NOR and NAND memory. A total + of 256M bytes of any of these memories can be accessed at a given + time via four chip selects with 64M byte access per chip select. + config TI_EMIF tristate Texas Instruments EMIF driver depends on ARCH_OMAP2PLUS diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 969d923..d4e150c 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -5,6 +5,7 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c new file mode 100644 index 000..44cd700 --- /dev/null +++ b/drivers/memory/ti-aemif.c @@ -0,0 +1,415 @@ +/* + * TI AEMIF driver + * + * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/ + * Copyright (C) Heiko Schocher h...@denx.de + * Copyright (C) Ivan Khoronzhuk ivan.khoronz...@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/err.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_platform.h +#include linux/platform_device.h + +#define TA_SHIFT 2 +#define RHOLD_SHIFT4 +#define RSTROBE_SHIFT 7 +#define RSETUP_SHIFT 13 +#define WHOLD_SHIFT17 +#define WSTROBE_SHIFT 20 +#define WSETUP_SHIFT 26 +#define EW_SHIFT 30 +#define SS_SHIFT 31 + +#define TA(x) ((x) TA_SHIFT) +#define RHOLD(x) ((x) RHOLD_SHIFT) +#define RSTROBE(x) ((x) RSTROBE_SHIFT) +#define RSETUP(x) ((x) RSETUP_SHIFT) +#define WHOLD(x) ((x) WHOLD_SHIFT) +#define WSTROBE(x) ((x) WSTROBE_SHIFT) +#define WSETUP(x) ((x) WSETUP_SHIFT) +#define EW(x) ((x) EW_SHIFT) +#define SS(x) ((x) SS_SHIFT) + +#define ASIZE_MAX 0x1 +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX0x3f +#define WSETUP_MAX 0xf +#define EW_MAX 0x1 +#define SS_MAX 0x1 +#define NUM_CS 4 + +#define TA_VAL(x) (((x) TA(TA_MAX)) TA_SHIFT) +#define RHOLD_VAL(x) (((x) RHOLD(RHOLD_MAX)) RHOLD_SHIFT) +#define RSTROBE_VAL(x) (((x) RSTROBE(RSTROBE_MAX)) RSTROBE_SHIFT) +#define RSETUP_VAL(x) (((x) RSETUP(RSETUP_MAX)) RSETUP_SHIFT) +#define WHOLD_VAL(x) (((x) WHOLD(WHOLD_MAX)) WHOLD_SHIFT) +#define WSTROBE_VAL(x) (((x) WSTROBE(WSTROBE_MAX)) WSTROBE_SHIFT) +#define WSETUP_VAL(x) (((x) WSETUP(WSETUP_MAX)) WSETUP_SHIFT) +#define EW_VAL(x) (((x) EW(EW_MAX)) EW_SHIFT) +#define SS_VAL(x) (((x) SS(SS_MAX)) SS_SHIFT) + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASKBIT(30) +#define ACR_SS_MASKBIT(31) +#define ASIZE_16BIT1 + +#define CONFIG_MASK(TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX
[PATCH v2 2/2] memory: ti-aemif: add bindings for AEMIF driver
Add bindings for AEMIF controller drivers/memory/ti-aemif.c Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- .../bindings/memory-controllers/ti-aemif.txt | 201 1 file changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt new file mode 100644 index 000..7fc7efe --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt @@ -0,0 +1,201 @@ +* Device tree bindings for Texas instruments AEMIF controller + +Th Async External Memory Interface (EMIF16/AEMIF) controller is intended to +provide a glue-less interface to a variety of asynchronous memory devices like +ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories +can be accessed at any given time via four chip selects with 64M byte access +per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM +and Mobile SDR are not supported. + +Documentation: +Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf +OMAP-L138 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf +Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf + +Required properties: + +- compatible: ti,davinci-aemif + ti,keystone-aemif + ti,omap-L138-aemif + +- #address-cells: Must be 2. The first cell is the memory partition + number. The 0 partition is for chip selects. And the + second cell is the offset into the partition, for the 0 + partition it corresponds to chip select offset. + +- #size-cells: Must be set to 1. + +- reg: contains offset/length value for AEMIF control registers + space. + +- ranges: Must be set up to reflect the memory layout for 4 + chipselects and for AEMIF control range. + +- clocks: phandle reference to the controller clock. Required only + if clock tree data present in device tree. + See clock-bindings.txt + +- clock-names: clock name. It has to be aemif. Required only if clock + tree data present in device tree, in another case don't + use it. + See clock-bindings.txt + +- clock-ranges:Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + See clock-bindings.txt + + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt). +There might be board specific devices like FPGAs. + +Required child cs node properties: + +- compatible: ti,aemif-cs + +- #address-cells: Must be 2. The first cell is the memory partition + number. The 0 partition is for chip selects. And the + second cell is the offset into the partition, for the 0 + partition it corresponds to chip select offset. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +- clock-ranges:Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + +- ti,cs-chipselect:number of chipselect. Indicates on the aemif driver + which chipselect is used for accessing the memory. For + compatibles ti,davinci-aemif and ti,keystone-aemif + it can be in range [0-3]. For compatible + ti,omap-L138-aemif range is [2-5]. + +Optional child cs node properties: + +- ti,bus-width:width of the asynchronous device's data bus + 8 or 16 if not preset 8 + +- ti,cs-ss:enable/disable select strobe mode + In select strobe mode chip select behaves as + the strobe and is active only during the strobe + period. If present then enable. + +- ti,cs-ew:enable/disable extended wait mode + if set, the controller monitors the EMIFWAIT pin + mapped to that chip select to determine if the + device wants to extend the strobe period. If + present then enable. + +- ti,cs-ta:minimum turn around time, ns + Time between the end of one
[PATCH v2 01/10] mtd: nand: davinci: fix driver registration
When kernel is booted using DT, there is no guarantee that Davinci
NAND device has been created already at the time when driver init
function is executed. Therefore, platform_driver_probe() can't be used
because this may result the Davinci NAND driver will never be probed.
The driver probing has to be made with core mechanism.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
---
drivers/mtd/nand/davinci_nand.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index b77a01e..d87213f 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -877,6 +877,7 @@ static int __exit nand_davinci_remove(struct
platform_device *pdev)
}
static struct platform_driver nand_davinci_driver = {
+ .probe = nand_davinci_probe,
.remove = __exit_p(nand_davinci_remove),
.driver = {
.name = davinci_nand,
@@ -886,7 +887,7 @@ static struct platform_driver nand_davinci_driver = {
};
MODULE_ALIAS(platform:davinci_nand);
-module_platform_driver_probe(nand_davinci_driver, nand_davinci_probe);
+module_platform_driver(nand_davinci_driver);
MODULE_LICENSE(GPL);
MODULE_AUTHOR(Texas Instruments);
--
1.7.9.5
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[PATCH v2 00/10] Reuse davinci-nand driver for Keystone arch
This series contains fixes and updates of Davinci nand driver in order to reuse it for Keystone platform. The series is combination of two following series: - Davinci nand driver fixes and updates: https://lkml.org/lkml/2013/11/20/271 - Reuse davinci-nand driver for Keystone arch https://lkml.org/lkml/2013/11/20/315 Ivan Khoronzhuk (10): mtd: nand: davinci: fix driver registration mtd: nand: davinci: return ENOMEM if memory allocation is failed mtd: nand: davinci: check required ti,davinci-chipselect property mtd: nand: davinci: simplify error handling mtd: nand: davinci: move bindings under mtd mtd: nand: davinci: extend description of bindings mtd: nand: davinci: adjust DT properties to MTD generic mtd: nand: davinci: reuse driver for Keystone arch mtd: nand: davinci: don't set timings if AEMIF is used mtd: nand: davinci: don't request AEMIF address range .../devicetree/bindings/arm/davinci/nand.txt | 46 .../devicetree/bindings/mtd/davinci-nand.txt | 94 drivers/mtd/nand/Kconfig |6 +- drivers/mtd/nand/davinci_nand.c| 117 +++- 4 files changed, 164 insertions(+), 99 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/davinci/nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/davinci-nand.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 0/5] Update Davinci watchdog driver
These patches are intended to update Davinci watchdog to use WDT core and reuse driver for keystone arch, because Keystone uses the similar IP like Davinci. See Documentation: Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf Also: - improved to support GET_TIMELEFT option. - added clocks and timeout-sec properties to DT. Based on git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git keystone/master v4..v5: - watchdog: davinci: change driver to use WDT core switched off CONFIG_WATCHDOG_NOWAYOUT option v3..v4: - watchdog: davinci: change driver to use WDT core reverted rename of platform driver to davinci-wdt as it causes a regression on Davinci platforms. - arm: dts: keystone: add watchdog entry The patch will be sent separately after series is ready. v2..v3: - watchdog: davinci: change driver to use WDT core removed ti,keystone-wdt compatible from driver renamed wdt device names for mach-davinci from watchdog to davinci-wdt - watchdog: davinci: reuse driver for keystone arch moved clocks property under Optional properties improved description of clocks property - arm: dts: keystone: add watchdog entry replaced ti,keystone-wdt compatible on ti,keystone-wdt,ti,davinci-wdt v1..v2: - watchdog: davinci: change driver to use WDT core corrected 2011 - 2006-2013 removed useless function comment corrected initialization of heartbeat switched on CONFIG_WATCHDOG_NOWAYOUT option - watchdog: davinci: use davinci_wdt_device structure to hold device data substituted wdd to watchdog device in commit message - watchdog: davinci: add GET_TIMELEFT option support corrected comment (is - has) removed redundant error message clock freq is not set - watchdog: davinci: add GET_STATUS option support dropped - watchdog: davinci: add timeout-sec property use consistent formatting - watchdog: davinci: reuse driver for keystone arch use consistent formatting - watchdog: davinci: add clocks property merged with above patch Ivan Khoronzhuk (5): watchdog: davinci: change driver to use WDT core watchdog: davinci: use davinci_wdt_device structure to hold device data watchdog: davinci: add GET_TIMELEFT option support watchdog: davinci: add timeout-sec property watchdog: davinci: reuse driver for keystone arch .../devicetree/bindings/watchdog/davinci-wdt.txt | 16 +- drivers/watchdog/Kconfig |5 +- drivers/watchdog/davinci_wdt.c | 221 +--- 3 files changed, 113 insertions(+), 129 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 2/5] watchdog: davinci: use davinci_wdt_device structure to hold device data
Some SoCs, like Keystone 2, can support more than one WDT and each
watchdog device has to use it's own base address, clock source,
watchdog device, so add new davinci_wdt_device structure to hold
device data.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/watchdog/davinci_wdt.c | 74 ++--
1 file changed, 48 insertions(+), 26 deletions(-)
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 3701f06..b6b82d1d 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -56,51 +56,63 @@
#define WDKEY_SEQ1 (0xda7e 16)
static int heartbeat;
-static void __iomem*wdt_base;
-struct clk *wdt_clk;
-static struct watchdog_device wdt_wdd;
+
+/*
+ * struct to hold data for each WDT device
+ * @base - base io address of WD device
+ * @clk - source clock of WDT
+ * @wdd - hold watchdog device as is in WDT core
+ */
+struct davinci_wdt_device {
+ void __iomem*base;
+ struct clk *clk;
+ struct watchdog_device wdd;
+};
static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
unsigned long wdt_freq;
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
- wdt_freq = clk_get_rate(wdt_clk);
+ wdt_freq = clk_get_rate(davinci_wdt-clk);
/* disable, internal clock source */
- iowrite32(0, wdt_base + TCR);
+ iowrite32(0, davinci_wdt-base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
- iowrite32(0, wdt_base + TGCR);
+ iowrite32(0, davinci_wdt-base + TGCR);
tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
- iowrite32(tgcr, wdt_base + TGCR);
+ iowrite32(tgcr, davinci_wdt-base + TGCR);
/* clear counter regs */
- iowrite32(0, wdt_base + TIM12);
- iowrite32(0, wdt_base + TIM34);
+ iowrite32(0, davinci_wdt-base + TIM12);
+ iowrite32(0, davinci_wdt-base + TIM34);
/* set timeout period */
timer_margin = (((u64)wdd-timeout * wdt_freq) 0x);
- iowrite32(timer_margin, wdt_base + PRD12);
+ iowrite32(timer_margin, davinci_wdt-base + PRD12);
timer_margin = (((u64)wdd-timeout * wdt_freq) 32);
- iowrite32(timer_margin, wdt_base + PRD34);
+ iowrite32(timer_margin, davinci_wdt-base + PRD34);
/* enable run continuously */
- iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
+ iowrite32(ENAMODE12_PERIODIC, davinci_wdt-base + TCR);
/* Once the WDT is in pre-active state write to
* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
* write protected (except for the WDKEY field)
*/
/* put watchdog in pre-active state */
- iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt-base + WDTCR);
/* put watchdog in active state */
- iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt-base + WDTCR);
return 0;
}
static int davinci_wdt_ping(struct watchdog_device *wdd)
{
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
+
/* put watchdog in service state */
- iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ0, davinci_wdt-base + WDTCR);
/* put watchdog in active state */
- iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
+ iowrite32(WDKEY_SEQ1, davinci_wdt-base + WDTCR);
return 0;
}
@@ -122,14 +134,21 @@ static int davinci_wdt_probe(struct platform_device *pdev)
struct device *dev = pdev-dev;
struct resource *wdt_mem;
struct watchdog_device *wdd;
+ struct davinci_wdt_device *davinci_wdt;
+
+ davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
+ if (!davinci_wdt)
+ return -ENOMEM;
- wdt_clk = devm_clk_get(dev, NULL);
- if (WARN_ON(IS_ERR(wdt_clk)))
- return PTR_ERR(wdt_clk);
+ davinci_wdt-clk = devm_clk_get(dev, NULL);
+ if (WARN_ON(IS_ERR(davinci_wdt-clk)))
+ return PTR_ERR(davinci_wdt-clk);
- clk_prepare_enable(wdt_clk);
+ clk_prepare_enable(davinci_wdt-clk);
- wdd = wdt_wdd;
+ platform_set_drvdata(pdev, davinci_wdt);
+
+ wdd = davinci_wdt-wdd;
wdd-info = davinci_wdt_info;
wdd-ops= davinci_wdt_ops;
wdd-min_timeout= 1;
@@ -140,12 +159,13 @@ static int davinci_wdt_probe(struct platform_device *pdev)
dev_info(dev, heartbeat %d sec\n, wdd-timeout);
+ watchdog_set_drvdata(wdd, davinci_wdt);
watchdog_set_nowayout(wdd, 1);
wdt_mem = platform_get_resource(pdev
[PATCH v5 5/5] watchdog: davinci: reuse driver for keystone arch
The keystone arch uses the same IP watchdog, so add ti,keystone-wdt
compatible and correct identity.
The Keystone arch is using clocks in DT and source clock for watchdog
has to be specified, so add this to binding.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/watchdog/davinci-wdt.txt | 12 ++--
drivers/watchdog/Kconfig |4 ++--
drivers/watchdog/davinci_wdt.c |2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index e450134..e60b9a1 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -1,11 +1,18 @@
-DaVinci Watchdog Timer (WDT) Controller
+Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
Required properties:
-- compatible : Should be ti,davinci-wdt
+- compatible : Should be ti,davinci-wdt, ti,keystone-wdt
- reg : Should contain WDT registers location and length
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
+- clocks : the clock feeding the watchdog timer.
+ Needed if platform uses clocks.
+ See clock-bindings.txt
+
+Documentation:
+Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
+Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Examples:
@@ -13,4 +20,5 @@ wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
timeout-sec = 30;
+ clocks = clkwdtimer0;
};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 3ca69c8..2958e09 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -270,11 +270,11 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
- depends on ARCH_DAVINCI
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
select WATCHDOG_CORE
help
Say Y here if to include support for the watchdog timer
- in the DaVinci DM644x/DM646x processors.
+ in the DaVinci DM644x/DM646x or Keystone processors.
To compile this driver as a module, choose M here: the
module will be called davinci_wdt.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index cd6ff9d..f3774eb 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -143,7 +143,7 @@ static unsigned int davinci_wdt_get_timeleft(struct
watchdog_device *wdd)
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
- .identity = DaVinci Watchdog,
+ .identity = DaVinci/Keystone Watchdog,
};
static const struct watchdog_ops davinci_wdt_ops = {
--
1.7.9.5
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[PATCH v5 1/5] watchdog: davinci: change driver to use WDT core
To reduce code duplicate and increase code readability use WDT core
code to handle WDT interface.
Remove io_lock as the WDT core uses mutex to lock each wdt device.
Remove wdt_state as the WDT core tracks state with its own variable.
The watchdog_init_timeout() can read timeout value from timeout-sec
property if the passed value is out of bounds. The heartbeat is
initialized in next way. If heartbeat is not set thought module
parameter, try to read it's value from WDT node timeout-sec property.
If node has no one, use default value.
The heartbeat is hold in wdd-timeout by WDT core, so use it in
order to set timeout period.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/watchdog/Kconfig |1 +
drivers/watchdog/davinci_wdt.c | 147 ++--
2 files changed, 36 insertions(+), 112 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 5be6e91..3ca69c8 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -271,6 +271,7 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
depends on ARCH_DAVINCI
+ select WATCHDOG_CORE
help
Say Y here if to include support for the watchdog timer
in the DaVinci DM644x/DM646x processors.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index dd625cc..3701f06 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -3,7 +3,7 @@
*
* Watchdog driver for DaVinci DM644x/DM646x processors
*
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2013 Texas Instruments.
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
@@ -15,18 +15,12 @@
#include linux/moduleparam.h
#include linux/types.h
#include linux/kernel.h
-#include linux/fs.h
-#include linux/miscdevice.h
#include linux/watchdog.h
#include linux/init.h
-#include linux/bitops.h
#include linux/platform_device.h
-#include linux/spinlock.h
-#include linux/uaccess.h
#include linux/io.h
#include linux/device.h
#include linux/clk.h
-#include linux/slab.h
#include linux/err.h
#define MODULE_NAME DAVINCI-WDT:
@@ -61,31 +55,12 @@
#define WDKEY_SEQ0 (0xa5c6 16)
#define WDKEY_SEQ1 (0xda7e 16)
-static int heartbeat = DEFAULT_HEARTBEAT;
-
-static DEFINE_SPINLOCK(io_lock);
-static unsigned long wdt_status;
-#define WDT_IN_USE0
-#define WDT_OK_TO_CLOSE 1
-#define WDT_REGION_INITED 2
-#define WDT_DEVICE_INITED 3
-
+static int heartbeat;
static void __iomem*wdt_base;
struct clk *wdt_clk;
+static struct watchdog_device wdt_wdd;
-static void wdt_service(void)
-{
- spin_lock(io_lock);
-
- /* put watchdog in service state */
- iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
- /* put watchdog in active state */
- iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
-
- spin_unlock(io_lock);
-}
-
-static void wdt_enable(void)
+static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
@@ -93,8 +68,6 @@ static void wdt_enable(void)
wdt_freq = clk_get_rate(wdt_clk);
- spin_lock(io_lock);
-
/* disable, internal clock source */
iowrite32(0, wdt_base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
@@ -105,9 +78,9 @@ static void wdt_enable(void)
iowrite32(0, wdt_base + TIM12);
iowrite32(0, wdt_base + TIM34);
/* set timeout period */
- timer_margin = (((u64)heartbeat * wdt_freq) 0x);
+ timer_margin = (((u64)wdd-timeout * wdt_freq) 0x);
iowrite32(timer_margin, wdt_base + PRD12);
- timer_margin = (((u64)heartbeat * wdt_freq) 32);
+ timer_margin = (((u64)wdd-timeout * wdt_freq) 32);
iowrite32(timer_margin, wdt_base + PRD34);
/* enable run continuously */
iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
@@ -119,84 +92,28 @@ static void wdt_enable(void)
iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
/* put watchdog in active state */
iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
-
- spin_unlock(io_lock);
-}
-
-static int davinci_wdt_open(struct inode *inode, struct file *file)
-{
- if (test_and_set_bit(WDT_IN_USE, wdt_status))
- return -EBUSY;
-
- wdt_enable();
-
- return nonseekable_open(inode, file);
+ return 0;
}
-static ssize_t
-davinci_wdt_write(struct file *file, const char *data, size_t len,
- loff_t *ppos)
+static int davinci_wdt_ping(struct watchdog_device *wdd)
{
- if (len)
- wdt_service();
-
- return len;
+ /* put watchdog in service state */
+ iowrite32(WDKEY_SEQ0, wdt_base + WDTCR
[PATCH v5 4/5] watchdog: davinci: add timeout-sec property
Since Davinci WDT has been switched to use WDT core, it became able
to support timeout-sec property, so add it to it's binding description.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/watchdog/davinci-wdt.txt |4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
index 75558cc..e450134 100644
--- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
@@ -4,9 +4,13 @@ Required properties:
- compatible : Should be ti,davinci-wdt
- reg : Should contain WDT registers location and length
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
Examples:
wdt: wdt@232 {
compatible = ti,davinci-wdt;
reg = 0x0232 0x80;
+ timeout-sec = 30;
};
--
1.7.9.5
--
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[PATCH v5 3/5] watchdog: davinci: add GET_TIMELEFT option support
Currently, the davinci watchdog can be read while counting,
so we can add ability to report the remaining time before
the system will reboot.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/watchdog/davinci_wdt.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index b6b82d1d..cd6ff9d 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -116,6 +116,31 @@ static int davinci_wdt_ping(struct watchdog_device *wdd)
return 0;
}
+static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
+{
+ u64 timer_counter;
+ unsigned long freq;
+ u32 val;
+ struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
+
+ /* if timeout has occured then return 0 */
+ val = ioread32(davinci_wdt-base + WDTCR);
+ if (val WDFLAG)
+ return 0;
+
+ freq = clk_get_rate(davinci_wdt-clk);
+
+ if (!freq)
+ return 0;
+
+ timer_counter = ioread32(davinci_wdt-base + TIM12);
+ timer_counter |= ((u64)ioread32(davinci_wdt-base + TIM34) 32);
+
+ do_div(timer_counter, freq);
+
+ return wdd-timeout - timer_counter;
+}
+
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
.identity = DaVinci Watchdog,
@@ -126,6 +151,7 @@ static const struct watchdog_ops davinci_wdt_ops = {
.start = davinci_wdt_start,
.stop = davinci_wdt_ping,
.ping = davinci_wdt_ping,
+ .get_timeleft = davinci_wdt_get_timeleft,
};
static int davinci_wdt_probe(struct platform_device *pdev)
--
1.7.9.5
--
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[PATCH v6 1/5] watchdog: davinci: change driver to use WDT core
To reduce code duplicate and increase code readability use WDT core
code to handle WDT interface.
Remove io_lock as the WDT core uses mutex to lock each wdt device.
Remove wdt_state as the WDT core tracks state with its own variable.
The watchdog_init_timeout() can read timeout value from timeout-sec
property if the passed value is out of bounds. The heartbeat is
initialized in next way. If heartbeat is not set thought module
parameter, try to read it's value from WDT node timeout-sec property.
If node has no one, use default value.
The heartbeat is hold in wdd-timeout by WDT core, so use it in
order to set timeout period.
Davinci WDT can't be stopped and once it's expired - it can be
rearmed only after hardware reset, that's why nowayout feature
is enforced.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/watchdog/Kconfig |1 +
drivers/watchdog/davinci_wdt.c | 147 ++--
2 files changed, 36 insertions(+), 112 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 5be6e91..3ca69c8 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -271,6 +271,7 @@ config IOP_WATCHDOG
config DAVINCI_WATCHDOG
tristate DaVinci watchdog
depends on ARCH_DAVINCI
+ select WATCHDOG_CORE
help
Say Y here if to include support for the watchdog timer
in the DaVinci DM644x/DM646x processors.
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index dd625cc..3701f06 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -3,7 +3,7 @@
*
* Watchdog driver for DaVinci DM644x/DM646x processors
*
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2013 Texas Instruments.
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
@@ -15,18 +15,12 @@
#include linux/moduleparam.h
#include linux/types.h
#include linux/kernel.h
-#include linux/fs.h
-#include linux/miscdevice.h
#include linux/watchdog.h
#include linux/init.h
-#include linux/bitops.h
#include linux/platform_device.h
-#include linux/spinlock.h
-#include linux/uaccess.h
#include linux/io.h
#include linux/device.h
#include linux/clk.h
-#include linux/slab.h
#include linux/err.h
#define MODULE_NAME DAVINCI-WDT:
@@ -61,31 +55,12 @@
#define WDKEY_SEQ0 (0xa5c6 16)
#define WDKEY_SEQ1 (0xda7e 16)
-static int heartbeat = DEFAULT_HEARTBEAT;
-
-static DEFINE_SPINLOCK(io_lock);
-static unsigned long wdt_status;
-#define WDT_IN_USE0
-#define WDT_OK_TO_CLOSE 1
-#define WDT_REGION_INITED 2
-#define WDT_DEVICE_INITED 3
-
+static int heartbeat;
static void __iomem*wdt_base;
struct clk *wdt_clk;
+static struct watchdog_device wdt_wdd;
-static void wdt_service(void)
-{
- spin_lock(io_lock);
-
- /* put watchdog in service state */
- iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
- /* put watchdog in active state */
- iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
-
- spin_unlock(io_lock);
-}
-
-static void wdt_enable(void)
+static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
@@ -93,8 +68,6 @@ static void wdt_enable(void)
wdt_freq = clk_get_rate(wdt_clk);
- spin_lock(io_lock);
-
/* disable, internal clock source */
iowrite32(0, wdt_base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
@@ -105,9 +78,9 @@ static void wdt_enable(void)
iowrite32(0, wdt_base + TIM12);
iowrite32(0, wdt_base + TIM34);
/* set timeout period */
- timer_margin = (((u64)heartbeat * wdt_freq) 0x);
+ timer_margin = (((u64)wdd-timeout * wdt_freq) 0x);
iowrite32(timer_margin, wdt_base + PRD12);
- timer_margin = (((u64)heartbeat * wdt_freq) 32);
+ timer_margin = (((u64)wdd-timeout * wdt_freq) 32);
iowrite32(timer_margin, wdt_base + PRD34);
/* enable run continuously */
iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
@@ -119,84 +92,28 @@ static void wdt_enable(void)
iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
/* put watchdog in active state */
iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
-
- spin_unlock(io_lock);
-}
-
-static int davinci_wdt_open(struct inode *inode, struct file *file)
-{
- if (test_and_set_bit(WDT_IN_USE, wdt_status))
- return -EBUSY;
-
- wdt_enable();
-
- return nonseekable_open(inode, file);
+ return 0;
}
-static ssize_t
-davinci_wdt_write(struct file *file, const char *data, size_t len,
- loff_t *ppos)
+static int davinci_wdt_ping(struct watchdog_device *wdd)
{
- if (len
[PATCH v3 6/9] mtd: nand: davinci: extend description of bindings
Extend bindings for davinci_nand driver to be more clear.
This is clarification only, without semantic changes.
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
Reviewed-by: Taras Kondratiuk ta...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/mtd/davinci-nand.txt | 77 ++--
1 file changed, 54 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
index 3545ea7..d2a3fc0 100644
--- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
@@ -1,36 +1,67 @@
-* Texas Instruments Davinci NAND
+Device tree bindings for Texas instruments Davinci NAND controller
-This file provides information, what the device node for the
-davinci nand interface contain.
+This file provides information, what the device node for the davinci NAND
+interface contains.
+
+Documentation:
+Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
Required properties:
-- compatible: ti,davinci-nand;
-- reg : contain 2 offset/length values:
-- offset and length for the access window
-- offset and length for accessing the aemif control registers
-- ti,davinci-chipselect: Indicates on the davinci_nand driver which
- chipselect is used for accessing the nand.
+
+- compatible: ti,davinci-nand
+
+- reg: Contains 2 offset/length values:
+ - offset and length for the access window.
+ - offset and length for accessing the AEMIF
+ control registers.
+
+- ti,davinci-chipselect: number of chipselect. Indicates on the
+ davinci_nand driver which chipselect is used
+ for accessing the nand.
+ Can be in the range [0-3].
Recommended properties :
-- ti,davinci-mask-ale: mask for ale
-- ti,davinci-mask-cle: mask for cle
-- ti,davinci-mask-chipsel: mask for chipselect
-- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
- - none
- - soft
- - hw
-- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
-- ti,davinci-nand-buswidth: buswidth 8 or 16
-- ti,davinci-nand-use-bbt: use flash based bad block table support.
-
-nand device bindings may contain additional sub-nodes describing
-partitions of the address space. See partition.txt for more detail.
+
+- ti,davinci-mask-ale: mask for ALE. Needed for executing address
+ phase. These offset will be added to the base
+ address for the chip select space the NAND Flash
+ device is connected to.
+ If not set equal to 0x08.
+
+- ti,davinci-mask-cle: mask for CLE. Needed for executing command
+ phase. These offset will be added to the base
+ address for the chip select space the NAND Flash
+ device is connected to.
+ If not set equal to 0x10.
+
+- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
+ addresses for given chipselect.
+
+- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
+ valid values for davinci driver:
+ - none
+ - soft
+ - hw
+
+- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
+
+- ti,davinci-nand-buswidth:buswidth 8 or 16.
+
+- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
+ identifier is saved in OOB area.
+
+Nand device bindings may contain additional sub-nodes describing partitions of
+the address space. See partition.txt for more detail. The NAND Flash timing
+values must be programmed in the chip select’s node of AEMIF
+memory-controller (see Documentation/devicetree/bindings/memory-controllers/
+davinci-aemif.txt).
Example(da850 EVM ):
+
nand_cs3@6200 {
compatible = ti,davinci-nand;
reg = 0x6200 0x807ff
- 0x6800 0x8000;
+ 0x6800 0x8000;
ti,davinci-chipselect = 1;
ti,davinci-mask-ale = 0;
ti,davinci-mask-cle = 0;
--
1.7.9.5
--
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[PATCH v3 1/9] mtd: nand: davinci: fix driver registration
When kernel is booted using DT, there is no guarantee that Davinci
NAND device has been created already at the time when driver init
function is executed. Therefore, platform_driver_probe() can't be used
because this may result the Davinci NAND driver will never be probed.
The driver probing has to be made with core mechanism.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
Reviewed-by: Taras Kondratiuk ta...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/mtd/nand/davinci_nand.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index b77a01e..d87213f 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -877,6 +877,7 @@ static int __exit nand_davinci_remove(struct
platform_device *pdev)
}
static struct platform_driver nand_davinci_driver = {
+ .probe = nand_davinci_probe,
.remove = __exit_p(nand_davinci_remove),
.driver = {
.name = davinci_nand,
@@ -886,7 +887,7 @@ static struct platform_driver nand_davinci_driver = {
};
MODULE_ALIAS(platform:davinci_nand);
-module_platform_driver_probe(nand_davinci_driver, nand_davinci_probe);
+module_platform_driver(nand_davinci_driver);
MODULE_LICENSE(GPL);
MODULE_AUTHOR(Texas Instruments);
--
1.7.9.5
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[PATCH v3 7/9] mtd: nand: davinci: adjust DT properties to MTD generic
The properties davinci-ecc-mode, davinci-nand-use-bbt, davinci-nand-buswidth
are MTD generic. Correct names for them are: nand-ecc-mode, nand-on-flash-bbt,
nand-bus-width accordingly. So rename them in dts and documentation.
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
Reviewed-by: Taras Kondratiuk ta...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../devicetree/bindings/mtd/davinci-nand.txt | 25
drivers/mtd/nand/davinci_nand.c| 11 ++---
2 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
index d2a3fc0..befaa5b 100644
--- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
@@ -37,7 +37,7 @@ Recommended properties :
- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
addresses for given chipselect.
-- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
+- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
valid values for davinci driver:
- none
- soft
@@ -45,10 +45,25 @@ Recommended properties :
- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
-- ti,davinci-nand-buswidth:buswidth 8 or 16.
+- nand-bus-width: buswidth 8 or 16. If not present 8.
+
+- nand-on-flash-bbt: use flash based bad block table support. OOB
+ identifier is saved in OOB area. If not present
+ false.
+
+Deprecated properties:
+
+- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
+ valid values for davinci driver:
+ - none
+ - soft
+ - hw
+
+- ti,davinci-nand-buswidth:buswidth 8 or 16. If not present 8.
- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
- identifier is saved in OOB area.
+ identifier is saved in OOB area. If not present
+ false.
Nand device bindings may contain additional sub-nodes describing partitions of
the address space. See partition.txt for more detail. The NAND Flash timing
@@ -66,9 +81,9 @@ nand_cs3@6200 {
ti,davinci-mask-ale = 0;
ti,davinci-mask-cle = 0;
ti,davinci-mask-chipsel = 0;
- ti,davinci-ecc-mode = hw;
+ nand-ecc-mode = hw;
ti,davinci-ecc-bits = 4;
- ti,davinci-nand-use-bbt;
+ nand-on-flash-bbt;
partition@18 {
label = ubifs;
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index c0be223..f7b21b8 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -534,7 +534,6 @@ static struct davinci_nand_pdata
struct davinci_nand_pdata *pdata;
const char *mode;
u32 prop;
- int len;
pdata = devm_kzalloc(pdev-dev,
sizeof(struct davinci_nand_pdata),
@@ -558,6 +557,8 @@ static struct davinci_nand_pdata
ti,davinci-mask-chipsel, prop))
pdata-mask_chipsel = prop;
if (!of_property_read_string(pdev-dev.of_node,
+ nand-ecc-mode, mode) ||
+ !of_property_read_string(pdev-dev.of_node,
ti,davinci-ecc-mode, mode)) {
if (!strncmp(none, mode, 4))
pdata-ecc_mode = NAND_ECC_NONE;
@@ -570,11 +571,15 @@ static struct davinci_nand_pdata
ti,davinci-ecc-bits, prop))
pdata-ecc_bits = prop;
if (!of_property_read_u32(pdev-dev.of_node,
+ nand-bus-width, prop) ||
+ !of_property_read_u32(pdev-dev.of_node,
ti,davinci-nand-buswidth, prop))
if (prop == 16)
pdata-options |= NAND_BUSWIDTH_16;
- if (of_find_property(pdev-dev.of_node,
- ti,davinci-nand-use-bbt, len))
+ if (of_property_read_bool(pdev-dev.of_node,
+ nand-on-flash-bbt) ||
+ of_property_read_bool(pdev-dev.of_node,
+ ti,davinci-nand-use-bbt))
pdata-bbt_options = NAND_BBT_USE_FLASH;
}
--
1.7.9.5
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[PATCH v3 9/9] mtd: nand: davinci: don't request AEMIF address range
The TI AEMIF driver registers are used to setup timings for each chip
select. The same registers range is used to setup NAND settings.
The AEMIF and NAND drivers not use the same registers in this range.
In case with TI AEMIF driver, the memory address range is requested
already by AEMIF, so we cannot request it twice, just ioremap.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
Reviewed-by: Taras Kondratiuk ta...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/mtd/nand/davinci_nand.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index f7b21b8..0cd4dbc 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -636,9 +636,11 @@ static int __init nand_davinci_probe(struct
platform_device *pdev)
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
- base = devm_ioremap_resource(pdev-dev, res2);
- if (IS_ERR(base))
- return PTR_ERR(base);
+ base = devm_ioremap(pdev-dev, res2-start, resource_size(res2));
+ if (!base) {
+ dev_err(pdev-dev, ioremap failed for resource %pR\n, res2);
+ return -EADDRNOTAVAIL;
+ }
info-dev = pdev-dev;
info-base = base;
--
1.7.9.5
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[PATCH v3 5/9] mtd: nand: davinci: move bindings under mtd
Move bindings under mtd. Do this in order to make davinci-nand
driver usable by keystone architecture.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
Reviewed-by: Taras Kondratiuk ta...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../{arm/davinci/nand.txt = mtd/davinci-nand.txt} |0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{arm/davinci/nand.txt =
mtd/davinci-nand.txt} (100%)
diff --git a/Documentation/devicetree/bindings/arm/davinci/nand.txt
b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/davinci/nand.txt
rename to Documentation/devicetree/bindings/mtd/davinci-nand.txt
--
1.7.9.5
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[PATCH v3 4/9] mtd: nand: davinci: simplify error handling
There is not needed to use a lot of names for err handling.
It complicates code support and reading.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
Reviewed-by: Taras Kondratiuk ta...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/mtd/nand/davinci_nand.c | 46 +++
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 9a96ac7..c0be223 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -615,8 +615,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
info = devm_kzalloc(pdev-dev, sizeof(*info), GFP_KERNEL);
if (!info) {
dev_err(pdev-dev, unable to allocate memory\n);
- ret = -ENOMEM;
- goto err_nomem;
+ return -ENOMEM;
}
platform_set_drvdata(pdev, info);
@@ -625,20 +624,16 @@ static int __init nand_davinci_probe(struct
platform_device *pdev)
res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res1 || !res2) {
dev_err(pdev-dev, resource missing\n);
- ret = -EINVAL;
- goto err_nomem;
+ return -EINVAL;
}
vaddr = devm_ioremap_resource(pdev-dev, res1);
- if (IS_ERR(vaddr)) {
- ret = PTR_ERR(vaddr);
- goto err_ioremap;
- }
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
base = devm_ioremap_resource(pdev-dev, res2);
- if (IS_ERR(base)) {
- ret = PTR_ERR(base);
- goto err_ioremap;
- }
+ if (IS_ERR(base))
+ return PTR_ERR(base);
info-dev = pdev-dev;
info-base = base;
@@ -705,7 +700,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
spin_unlock_irq(davinci_nand_lock);
if (ret == -EBUSY)
- goto err_ecc;
+ return ret;
info-chip.ecc.calculate = nand_davinci_calculate_4bit;
info-chip.ecc.correct = nand_davinci_correct_4bit;
@@ -721,8 +716,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
info-chip.ecc.strength = pdata-ecc_bits;
break;
default:
- ret = -EINVAL;
- goto err_ecc;
+ return -EINVAL;
}
info-chip.ecc.mode = ecc_mode;
@@ -730,7 +724,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
if (IS_ERR(info-clk)) {
ret = PTR_ERR(info-clk);
dev_dbg(pdev-dev, unable to get AEMIF clock, err %d\n, ret);
- goto err_clk;
+ return ret;
}
ret = clk_prepare_enable(info-clk);
@@ -759,7 +753,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
info-core_chipsel);
if (ret 0) {
dev_dbg(pdev-dev, NAND timing values setup fail\n);
- goto err_timing;
+ goto err;
}
spin_lock_irq(davinci_nand_lock);
@@ -775,7 +769,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
ret = nand_scan_ident(info-mtd, pdata-mask_chipsel ? 2 : 1, NULL);
if (ret 0) {
dev_dbg(pdev-dev, no NAND chip(s) found\n);
- goto err_scan;
+ goto err;
}
/* Update ECC layout if needed ... for 1-bit HW ECC, the default
@@ -789,7 +783,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
if (!chunks || info-mtd.oobsize 16) {
dev_dbg(pdev-dev, too small\n);
ret = -EINVAL;
- goto err_scan;
+ goto err;
}
/* For small page chips, preserve the manufacturer's
@@ -820,7 +814,7 @@ static int __init nand_davinci_probe(struct platform_device
*pdev)
dev_warn(pdev-dev, no 4-bit ECC support yet
for 4KiB-page NAND\n);
ret = -EIO;
- goto err_scan;
+ goto err;
syndrome_done:
info-chip.ecc.layout = info-ecclayout;
@@ -828,7 +822,7 @@ syndrome_done:
ret = nand_scan_tail(info-mtd);
if (ret 0)
- goto err_scan;
+ goto err;
if (pdata-parts)
ret = mtd_device_parse_register(info-mtd, NULL, NULL,
@@ -841,7 +835,7 @@ syndrome_done:
NULL, 0);
}
if (ret 0)
- goto err_scan;
+ goto err;
val
[PATCH v3 0/9] Reuse davinci-nand driver for Keystone arch
This series contains fixes and updates of Davinci nand driver in order to reuse it for Keystone platform. v2..v3: - mtd: nand: davinci: don't set timings if AEMIF is used dropped, it would be replaced by alone patch ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemif v1..v2 The series is combination of two following series: - Davinci nand driver fixes and updates: https://lkml.org/lkml/2013/11/20/271 - Reuse davinci-nand driver for Keystone arch https://lkml.org/lkml/2013/11/20/315 - mtd: nand: davinci: extend description of bindings clarified changeset description - mtd: nand: davinci: reuse driver for Keystone arch removed ti,keystone-nand compatible from driver Ivan Khoronzhuk (9): mtd: nand: davinci: fix driver registration mtd: nand: davinci: return ENOMEM if memory allocation is failed mtd: nand: davinci: check required ti,davinci-chipselect property mtd: nand: davinci: simplify error handling mtd: nand: davinci: move bindings under mtd mtd: nand: davinci: extend description of bindings mtd: nand: davinci: adjust DT properties to MTD generic mtd: nand: davinci: reuse driver for Keystone arch mtd: nand: davinci: don't request AEMIF address range .../devicetree/bindings/arm/davinci/nand.txt | 46 -- .../devicetree/bindings/mtd/davinci-nand.txt | 94 drivers/mtd/nand/Kconfig |6 +- drivers/mtd/nand/davinci_nand.c| 70 --- 4 files changed, 133 insertions(+), 83 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/davinci/nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/davinci-nand.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 2/9] mtd: nand: davinci: return ENOMEM if memory allocation is failed
In case when memory allocation is failed the driver should return ENOMEM instead of ENODEV. Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com Reviewed-by: Taras Kondratiuk ta...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/mtd/nand/davinci_nand.c |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d87213f..ddcd7c8 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -541,7 +541,7 @@ static struct davinci_nand_pdata GFP_KERNEL); pdev-dev.platform_data = pdata; if (!pdata) - return NULL; + return ERR_PTR(-ENOMEM); if (!of_property_read_u32(pdev-dev.of_node, ti,davinci-chipselect, prop)) pdev-id = prop; @@ -598,6 +598,9 @@ static int __init nand_davinci_probe(struct platform_device *pdev) nand_ecc_modes_tecc_mode; pdata = nand_davinci_get_pdata(pdev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + /* insist on board-specific configuration */ if (!pdata) return -ENODEV; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 3/9] mtd: nand: davinci: check required ti,davinci-chipselect property
The property ti,davinci-chipselect is required. So we have to check if it is set. Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com Reviewed-by: Taras Kondratiuk ta...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/mtd/nand/davinci_nand.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index ddcd7c8..9a96ac7 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -545,6 +545,9 @@ static struct davinci_nand_pdata if (!of_property_read_u32(pdev-dev.of_node, ti,davinci-chipselect, prop)) pdev-id = prop; + else + return ERR_PTR(-EINVAL); + if (!of_property_read_u32(pdev-dev.of_node, ti,davinci-mask-ale, prop)) pdata-mask_ale = prop; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 8/9] mtd: nand: davinci: reuse driver for Keystone arch
The Keystone arch has compatible nand device, so reuse it. In case with Keystone it depends on TI_AEMIF because AEMIF driver is responsible to set timings. See http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com Reviewed-by: Taras Kondratiuk ta...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- .../devicetree/bindings/mtd/davinci-nand.txt |8 +--- drivers/mtd/nand/Kconfig |6 +++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Documentation/devicetree/bindings/mtd/davinci-nand.txt index befaa5b..cfb18ab 100644 --- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt +++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt @@ -1,14 +1,16 @@ -Device tree bindings for Texas instruments Davinci NAND controller +Device tree bindings for Texas instruments Davinci/Keystone NAND controller -This file provides information, what the device node for the davinci NAND -interface contains. +This file provides information, what the device node for the davinci/keystone +NAND interface contains. Documentation: Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf +Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf Required properties: - compatible: ti,davinci-nand + ti,keystone-nand - reg: Contains 2 offset/length values: - offset and length for the access window. diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 93ae6a6..35f3ea3 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -464,11 +464,11 @@ config MTD_NAND_SH_FLCTL for NAND Flash using FLCTL. config MTD_NAND_DAVINCI -tristate Support NAND on DaVinci SoC -depends on ARCH_DAVINCI +tristate Support NAND on DaVinci/Keystone SoC +depends on ARCH_DAVINCI || (ARCH_KEYSTONE TI_AEMIF) help Enable the driver for NAND flash chips on Texas Instruments - DaVinci processors. + DaVinci/Keystone processors. config MTD_NAND_TXX9NDFMC tristate NAND Flash support for TXx9 SoC -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3] ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemif
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for another platform like Keystone.
The Keysone platform is going to use TI AEMIF driver.
If TI AEMIF is used we don't need to set timings and bus width.
It is done by AEMIF driver.
To get rid of davinci-nand driver dependency on aemif platform code
we moved aemif code to davinci platform.
The platform AEMIF code (aemif.c) has to be removed once Davinci
will be converted to DT and use ti-aemif.c driver.
Signed-off-by: Sekhar Nori nsek...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
v3..v2:
- rebased on following patch series:
[PATCH v3 0/9] Reuse davinci-nand driver for Keystone arch
http://www.spinics.net/lists/arm-kernel/msg291723.html
- removed AEMIF setup from next boards:
arch/arm/mach-davinci/board-dm355-evm.c
arch/arm/mach-davinci/board-dm355-leopard.c
arch/arm/mach-davinci/board-dm365-evm.c
arch/arm/mach-davinci/board-neuros-osd2.c
arch/arm/mach-davinci/devices-tnetv107x.c
- removed repeated clk_get() from davinci_aemif_setup_timing()
v2..v1:
- enabled AEMIF clock
- removed EXPORT_SYMBOL(davinci_aemif_setup)
- renamed ugly name davinci_ntosd2_nandflash_device
CC:
Sekhar Nori nsek...@ti.com
arch/arm/mach-davinci/aemif.c | 106 ---
arch/arm/mach-davinci/board-da830-evm.c |3 +
arch/arm/mach-davinci/board-da850-evm.c |3 +
arch/arm/mach-davinci/board-dm644x-evm.c|5 ++
arch/arm/mach-davinci/board-dm646x-evm.c|3 +
arch/arm/mach-davinci/board-mityomapl138.c |3 +
drivers/mtd/nand/davinci_nand.c | 22 -
include/linux/platform_data/mtd-davinci-aemif.h |5 +-
8 files changed, 115 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index f091a90..7adfb7e 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -16,6 +16,7 @@
#include linux/time.h
#include linux/platform_data/mtd-davinci-aemif.h
+#include linux/platform_data/mtd-davinci.h
/* Timing value configuration */
@@ -43,6 +44,17 @@
WSTROBE(WSTROBE_MAX) | \
WSETUP(WSETUP_MAX))
+static inline unsigned int davinci_aemif_readl(void __iomem *base, int offset)
+{
+ return readl_relaxed(base + offset);
+}
+
+static inline void davinci_aemif_writel(void __iomem *base,
+ int offset, unsigned long value)
+{
+ writel_relaxed(value, base + offset);
+}
+
/*
* aemif_calc_rate - calculate timing data.
* @wanted: The cycle time needed in nanoseconds.
@@ -76,6 +88,7 @@ static int aemif_calc_rate(int wanted, unsigned long clk, int
max)
* @t: timing values to be progammed
* @base: The virtual base address of the AEMIF interface
* @cs: chip-select to program the timing values for
+ * @clkrate: the AEMIF clkrate
*
* This function programs the given timing values (in real clock) into the
* AEMIF registers taking the AEMIF clock into account.
@@ -86,24 +99,17 @@ static int aemif_calc_rate(int wanted, unsigned long clk,
int max)
*
* Returns 0 on success, else negative errno.
*/
-int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
- void __iomem *base, unsigned cs)
+static int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+ void __iomem *base, unsigned cs,
+ unsigned long clkrate)
{
unsigned set, val;
int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
unsigned offset = A1CR_OFFSET + cs * 4;
- struct clk *aemif_clk;
- unsigned long clkrate;
if (!t)
return 0; /* Nothing to do */
- aemif_clk = clk_get(NULL, aemif);
- if (IS_ERR(aemif_clk))
- return PTR_ERR(aemif_clk);
-
- clkrate = clk_get_rate(aemif_clk);
-
clkrate /= 1000;/* turn clock into kHz for ease of use */
ta = aemif_calc_rate(t-ta, clkrate, TA_MAX);
@@ -130,4 +136,82 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing
*t,
return 0;
}
-EXPORT_SYMBOL(davinci_aemif_setup_timing);
+
+/**
+ * davinci_aemif_setup - setup AEMIF interface by davinci_nand_pdata
+ * @pdev - link to platform device to setup settings for
+ *
+ * This function does not use any locking while programming the AEMIF
+ * because it is expected that there is only one user of a given
+ * chip-select.
+ *
+ * Returns 0 on success, else negative errno.
+ */
+int davinci_aemif_setup(struct platform_device *pdev)
+{
+ struct davinci_nand_pdata *pdata = dev_get_platdata(pdev-dev);
+ uint32_t val;
+ unsigned long clkrate;
+ struct resource *res
[PATCH] ARM: dts: keystone: Fix domain register range for clkfftc1
The domain register range for clkfftc1 has to be 0x0235004c
instead of 0x023504c0.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/boot/dts/k2hk-clocks.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi
b/arch/arm/boot/dts/k2hk-clocks.dtsi
index 8855b1f..96e6536 100644
--- a/arch/arm/boot/dts/k2hk-clocks.dtsi
+++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
@@ -209,7 +209,7 @@ clocks {
compatible = ti,keystone,psc-clock;
clocks = chipclk13;
clock-output-names = fftc-1;
- reg = 0x02350074 0xb00, 0x023504c0 0x400;
+ reg = 0x02350074 0xb00, 0x0235004c 0x400;
reg-names = control, domain;
domain-id = 19;
};
--
1.8.3.2
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[PATCH] ARM: dts: keystone: Fix control register range for clktsip
The control register range for clktsio interferes with clkaemifspi clock.
And it causes issues for NAND/AEMIF. So fix it.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
Only comment is corrected.
arch/arm/boot/dts/k2hk-clocks.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi
b/arch/arm/boot/dts/k2hk-clocks.dtsi
index a71aa29..8855b1f 100644
--- a/arch/arm/boot/dts/k2hk-clocks.dtsi
+++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
@@ -59,7 +59,7 @@ clocks {
compatible = ti,keystone,psc-clock;
clocks = chipclk16;
clock-output-names = tsip;
- reg = 0x0235000c 0xb00, 0x0235 0x400;
+ reg = 0x0235 0xb00, 0x0235 0x400;
reg-names = control, domain;
domain-id = 0;
};
--
1.8.3.2
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[PATCH v6 1/2] memory: ti-aemif: introduce AEMIF driver
Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Signed-off-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/memory/Kconfig| 11 ++ drivers/memory/Makefile | 1 + drivers/memory/ti-aemif.c | 427 ++ 3 files changed, 439 insertions(+) create mode 100644 drivers/memory/ti-aemif.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 29a11db..7bc3982 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -7,6 +7,17 @@ menuconfig MEMORY if MEMORY +config TI_AEMIF + tristate Texas Instruments AEMIF driver + depends on (ARCH_DAVINCI || ARCH_KEYSTONE) OF + help + This driver is for the AEMIF module available in Texas Instruments + SoCs. AEMIF stands for Asynchronous External Memory Interface and + is intended to provide a glue-less interface to a variety of + asynchronuous memory devices like ASRAM, NOR and NAND memory. A total + of 256M bytes of any of these memories can be accessed at a given + time via four chip selects with 64M byte access per chip select. + config TI_EMIF tristate Texas Instruments EMIF driver depends on ARCH_OMAP2PLUS diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 969d923..d4e150c 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -5,6 +5,7 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c new file mode 100644 index 000..d3df760 --- /dev/null +++ b/drivers/memory/ti-aemif.c @@ -0,0 +1,427 @@ +/* + * TI AEMIF driver + * + * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/ + * + * Authors: + * Murali Karicheri m-kariche...@ti.com + * Ivan Khoronzhuk ivan.khoronz...@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/err.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_platform.h +#include linux/platform_device.h + +#define TA_SHIFT 2 +#define RHOLD_SHIFT4 +#define RSTROBE_SHIFT 7 +#define RSETUP_SHIFT 13 +#define WHOLD_SHIFT17 +#define WSTROBE_SHIFT 20 +#define WSETUP_SHIFT 26 +#define EW_SHIFT 30 +#define SS_SHIFT 31 + +#define TA(x) ((x) TA_SHIFT) +#define RHOLD(x) ((x) RHOLD_SHIFT) +#define RSTROBE(x) ((x) RSTROBE_SHIFT) +#define RSETUP(x) ((x) RSETUP_SHIFT) +#define WHOLD(x) ((x) WHOLD_SHIFT) +#define WSTROBE(x) ((x) WSTROBE_SHIFT) +#define WSETUP(x) ((x) WSETUP_SHIFT) +#define EW(x) ((x) EW_SHIFT) +#define SS(x) ((x) SS_SHIFT) + +#define ASIZE_MAX 0x1 +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX0x3f +#define WSETUP_MAX 0xf +#define EW_MAX 0x1 +#define SS_MAX 0x1 +#define NUM_CS 4 + +#define TA_VAL(x) (((x) TA(TA_MAX)) TA_SHIFT) +#define RHOLD_VAL(x) (((x) RHOLD(RHOLD_MAX)) RHOLD_SHIFT) +#define RSTROBE_VAL(x) (((x) RSTROBE(RSTROBE_MAX)) RSTROBE_SHIFT) +#define RSETUP_VAL(x) (((x) RSETUP(RSETUP_MAX)) RSETUP_SHIFT) +#define WHOLD_VAL(x) (((x) WHOLD(WHOLD_MAX)) WHOLD_SHIFT) +#define WSTROBE_VAL(x) (((x) WSTROBE(WSTROBE_MAX)) WSTROBE_SHIFT) +#define WSETUP_VAL(x) (((x) WSETUP(WSETUP_MAX)) WSETUP_SHIFT) +#define EW_VAL(x) (((x) EW(EW_MAX)) EW_SHIFT) +#define SS_VAL(x) (((x) SS(SS_MAX)) SS_SHIFT) + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASKBIT(30) +#define ACR_SS_MASKBIT(31) +#define ASIZE_16BIT1 + +#define CONFIG_MASK(TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE
[PATCH v6 2/2] memory: ti-aemif: add bindings for AEMIF driver
Add bindings for TI Async External Memory Interface (AEMIF) controller. The Async External Memory Interface (EMIF16/AEMIF) controller is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed via 4 chip selects with 64M byte access per chip select. We are not encoding CS number in reg property, it's memory partition number. The CS number is encoded for Davinci NAND node using standalone property ti,davinci-chipselect and we need to provide two memory ranges to it, as result we can't encode CS number in reg for AEMIF child devices (NAND/NOR/etc), as it will break bindings compatibility. In this patch, NAND node is used just as an example of child node. Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- .../bindings/memory-controllers/ti-aemif.txt | 210 + 1 file changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt new file mode 100644 index 000..9592717 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt @@ -0,0 +1,210 @@ +* Device tree bindings for Texas instruments AEMIF controller + +The Async External Memory Interface (EMIF16/AEMIF) controller is intended to +provide a glue-less interface to a variety of asynchronous memory devices like +ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories +can be accessed at any given time via four chip selects with 64M byte access +per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM +and Mobile SDR are not supported. + +Documentation: +Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf +Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf + +Required properties: + +- compatible: ti,davinci-aemif + ti,keystone-aemif + ti,da850-aemif + +- reg: contains offset/length value for AEMIF control registers + space. + +- #address-cells: Must be 2. The partition number has to be encoded in the + first address cell and it may accept values 0..N-1 + (N - total number of partitions). It's recommended to + assign N-1 number for the control partition. The second + cell is the offset into the partition. + +- #size-cells: Must be set to 1. + +- ranges: Contains memory regions. There are two types of + ranges/partitions: + - CS-specific partition/range. If continuous, must be + set up to reflect the memory layout for 4 chipselects, + if not then additional range/partition can be added and + child device can select the proper one. + - control partition which is common for all CS + interfaces. + +- clocks: the clock feeding the controller clock. Required only + if clock tree data present in device tree. + See clock-bindings.txt + +- clock-names: clock name. It has to be aemif. Required only if clock + tree data present in device tree, in another case don't + use it. + See clock-bindings.txt + +- clock-ranges:Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + See clock-bindings.txt + + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt). +There might be board specific devices like FPGAs. + +Required child cs node properties: + +- #address-cells: Must be 2. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +- clock-ranges:Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + +- ti,cs-chipselect:number of chipselect. Indicates on the aemif driver + which chipselect is used for accessing the memory. For + compatibles ti,davinci-aemif and ti,keystone-aemif + it can be in range [0-3]. For compatible + ti,da850-aemif range is [2-5
[PATCH v6 0/2] Introduce AEMIF driver for Davinci/Keystone archs
These patches introduce Async External Memory Interface (EMIF16/AEMIF) controller driver for Davinci/Keystone archs. For more informations see documentation: Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf OMAP-L138 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf Based on v3.14-rc4 v5..v6: - memory: ti-aemif: introduce AEMIF driver - memory: ti-aemif: add bindings for AEMIF driver changed opaque names for cs node properties v4..v5: - memory: ti-aemif: introduce AEMIF driver deleted DRV_NAME in favour of KBUILD_MODNAME deleted redundant err message in case of memory allocation some cosmetic changes v3..v4: rebased on latest of linux-keystone.git keystone/master v2..v3 (https://lkml.org/lkml/2013/12/11/148): - memory: ti-aemif: introduce AEMIF driver changed to work with multiple AEMIF controllers corrected copyright to authors in header changed compatible ti,omap-L138-aemif to ti,da850-aeimf used NULL in clk_get() instead of aemif name driver can be build as loadable module treat all child nodes as cs nodes, it makes code simpler - memory: ti-aemif: add bindings for AEMIF driver deleted direct link driver/memory/ti-aemif.c clarified description of controller ranges property changed compatible ti,omap-L138-aemif to ti,da850-aeimf added cs number information in commit log removed compatible property from cs node, it makes code simpler v1..v2 (https://lkml.org/lkml/2013/11/21/170): - memory: ti-aemif: introduce AEMIF driver - memory: ti-aemif: add bindings for AEMIF driver added ti.cs-chipselect property instead of representing chipselect number in cs node name. Ivan Khoronzhuk (2): memory: ti-aemif: introduce AEMIF driver memory: ti-aemif: add bindings for AEMIF driver .../bindings/memory-controllers/ti-aemif.txt | 210 ++ drivers/memory/Kconfig | 11 + drivers/memory/Makefile| 1 + drivers/memory/ti-aemif.c | 427 + 4 files changed, 649 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt create mode 100644 drivers/memory/ti-aemif.c -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: linux-next: manual merge of the clk tree with the keystone tree
On 02/26/2014 09:15 AM, Stephen Rothwell wrote:
Hi Mike,
Today's linux-next merge of the clk tree got a conflict in
arch/arm/boot/dts/keystone-clocks.dtsi between commit 0cfc9ccec2a8 (ARM:
dts: keystone: preparatory patch to support K2L and K2E SOCs) from the
keystone tree and commit 565bbdcd3b91 (ARM: keystone: dts: fix clkvcp3
control register address) from the clk tree.
I fixed it up (by adding the following merge fix patch) and can carry the
fix as necessary (no action is required).
From: Stephen Rothwell s...@canb.auug.org.au
Date: Wed, 26 Feb 2014 18:12:55 +1100
Subject: [PATCH] ARM: keystone: dts: fix for code movement
Signed-off-by: Stephen Rothwell s...@canb.auug.org.au
---
arch/arm/boot/dts/k2hk-clocks.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi
b/arch/arm/boot/dts/k2hk-clocks.dtsi
index 4eed84feb761..a71aa2996321 100644
--- a/arch/arm/boot/dts/k2hk-clocks.dtsi
+++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
@@ -339,7 +339,7 @@ clocks {
compatible = ti,keystone,psc-clock;
clocks = chipclk13;
clock-output-names = vcp-3;
- reg = 0x0235000a8 0xb00, 0x02350060 0x400;
+ reg = 0x023500a8 0xb00, 0x02350060 0x400;
reg-names = control, domain;
domain-id = 24;
};
The patch ARM: dts: keystone: preparatory patch to support K2L and K2E
SOCs
is from [PATCH 0/4] ARM: dts: keystone: Add support for K2H and K2E
SOCs/EVMs
series (http://www.spinics.net/lists/arm-kernel/msg310946.html).
As I understand, this series splits keystone clock tree into tree boards.
As result clock clkvcp3 (for wich reg is corrected) is moved to the
following two dts:
k2hk-clocks.dtsi
k2l-clocks.dtsi
So probably you should apply this change to k2l-clocks.dtsi too.
--
Regards,
Ivan Khoronzhuk
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[PATCH 5/5] ARM: keystone: enable reset driver support
Enable reset driver support in order to have opportunity to reboot SoC by watchdog and by software. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- CC: Russell King li...@arm.linux.org.uk CC: Santosh Shilimkar santosh.shilim...@ti.com arch/arm/configs/keystone_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index 4582e16..3f9c688 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig @@ -130,6 +130,9 @@ CONFIG_SPI=y CONFIG_SPI_DAVINCI=y CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_KEYSTONE=y CONFIG_WATCHDOG=y CONFIG_USB=y CONFIG_USB_DEBUG=y -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/5] Power: reset: keystone-reset: introduce keystone reset driver
The keystone SoC can be rebooted in several ways. By external reset
pin, by soft and by watchdogs. To allow keystone SoC reset if
watchdog is triggered we have to enable it in reset mux configuration
register regarding of watchdog configuration. Also we need to set
soft/hard reset we are going to use.
So add keystone reset driver to handle all this stuff.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
CC: Dmitry Eremin-Solenikov dbarysh...@gmail.com
CC: David Woodhouse dw...@infradead.org
CC: Grant Likely grant.lik...@linaro.org
CC: Rob Herring robh...@kernel.org
drivers/power/reset/Kconfig | 7 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/keystone-reset.c | 171 +++
3 files changed, 179 insertions(+)
create mode 100644 drivers/power/reset/keystone-reset.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 6d452a7..9082a72 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -57,3 +57,10 @@ config POWER_RESET_XGENE
depends on POWER_RESET
help
Reboot support for the APM SoC X-Gene Eval boards.
+
+config POWER_RESET_KEYSTONE
+ bool Keystone reset driver
+ depends on ARCH_KEYSTONE
+ help
+ Reboot support for the KEYSTONE SoCs.
+
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index a5b4a77..802a420 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
obj-$(CONFIG_POWER_RESET_XGENE) += xgene-reboot.o
+obj-$(CONFIG_POWER_RESET_KEYSTONE) += keystone-reset.o
diff --git a/drivers/power/reset/keystone-reset.c
b/drivers/power/reset/keystone-reset.c
new file mode 100644
index 000..73f6e7a
--- /dev/null
+++ b/drivers/power/reset/keystone-reset.c
@@ -0,0 +1,171 @@
+/*
+ * TI keystone reboot driver
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated. http://www.ti.com/
+ *
+ * Author: Ivan Khoronzhuk ivan.khoronz...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/io.h
+#include linux/reboot.h
+#include linux/module.h
+#include linux/of_address.h
+#include linux/of_platform.h
+#include asm/system_misc.h
+
+#define RSCTRL_KEY_MASK0x
+#define RSCTRL_KEY 0x5a69
+#define RSCTRL_RESET BIT(16)
+
+#define RSCFG_RSTYPE_SOFT 0x300f
+#define RSCFG_RSTYPE_HARD 0x0
+
+#define RSTYPE_RG 0x0
+#define RSCTRL_RG 0x4
+#define RSCFG_RG 0x8
+#define RSISO_RG 0xc
+
+#define RSMUX_OMODE_MASK 0xe
+#define RSMUX_OMODE_RESET_SOC 0xa
+#define RSMUX_OMODE_RESET_OFF 0x0
+#define RSMUX_LOCK_MASK0x1
+#define RSMUX_LOCK_SET 0x1
+
+#define WDT_MUX_NUMBER 0x4
+
+static void __iomem *rspll_base;
+
+/**
+ * rsctrl_enable_rspll_write - enable access to RSCTRL, RSCFG
+ * To be able to access to RSCTRL, RSCFG registers
+ * we has to write a key before
+ */
+static void rsctrl_enable_rspll_write(void)
+{
+ void __iomem *rstctrl_rg;
+ u32 val;
+
+ rstctrl_rg = rspll_base + RSCTRL_RG;
+ val = readl(rstctrl_rg);
+ val = RSCTRL_KEY_MASK;
+ val |= RSCTRL_KEY;
+ writel(val, rstctrl_rg);
+}
+
+static void rsctrl_restart(enum reboot_mode mode, const char *cmd)
+{
+ u32 val;
+ void __iomem *rstctrl;
+
+ /* enable write access to RSTCTRL */
+ rsctrl_enable_rspll_write();
+
+ /* reset the SOC */
+ rstctrl = rspll_base + RSCTRL_RG;
+ val = readl(rstctrl);
+ val = ~RSCTRL_RESET;
+ writel(val, rstctrl);
+}
+
+static struct of_device_id rsctrl_of_match[] = {
+ {.compatible = ti,keystone-reset, },
+ {},
+};
+
+static int rsctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = pdev-dev;
+ struct device_node *np = dev-of_node;
+ void __iomem *rsmux_base;
+ void __iomem *rg;
+ struct resource *res;
+ u32 val;
+ int ret;
+ int i;
+
+ if (!np)
+ return -ENODEV;
+
+ i = of_property_match_string(np, reg-names, pllregs);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ rspll_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(rspll_base))
+ return PTR_ERR(rspll_base);
+
+ i = of_property_match_string(np, reg-names, muxregs);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ rsmux_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(rsmux_base
[PATCH 3/5] ARM: keystone: remove redundant reset stuff
Remove reset stuff in flavour of using keystone reset driver:
driver/power/reset/keystone-reset.c
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
CC: Santosh Shilimkar santosh.shilim...@ti.com
CC: Russell King li...@arm.linux.org.uk
arch/arm/mach-keystone/keystone.c | 35 ---
1 file changed, 35 deletions(-)
diff --git a/arch/arm/mach-keystone/keystone.c
b/arch/arm/mach-keystone/keystone.c
index 6e6bb7d..4d46e30 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -23,24 +23,8 @@
#include keystone.h
-#define PLL_RESET_WRITE_KEY_MASK 0x
-#define PLL_RESET_WRITE_KEY0x5a69
-#define PLL_RESET BIT(16)
-
-static void __iomem *keystone_rstctrl;
-
static void __init keystone_init(void)
{
- struct device_node *node;
-
- node = of_find_compatible_node(NULL, NULL, ti,keystone-reset);
- if (WARN_ON(!node))
- pr_warn(ti,keystone-reset node undefined\n);
-
- keystone_rstctrl = of_iomap(node, 0);
- if (WARN_ON(!keystone_rstctrl))
- pr_warn(ti,keystone-reset iomap error\n);
-
keystone_pm_runtime_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
@@ -50,24 +34,6 @@ static const char *keystone_match[] __initconst = {
NULL,
};
-void keystone_restart(enum reboot_mode mode, const char *cmd)
-{
- u32 val;
-
- BUG_ON(!keystone_rstctrl);
-
- /* Enable write access to RSTCTRL */
- val = readl(keystone_rstctrl);
- val = PLL_RESET_WRITE_KEY_MASK;
- val |= PLL_RESET_WRITE_KEY;
- writel(val, keystone_rstctrl);
-
- /* Reset the SOC */
- val = readl(keystone_rstctrl);
- val = ~PLL_RESET;
- writel(val, keystone_rstctrl);
-}
-
DT_MACHINE_START(KEYSTONE, Keystone)
#if defined(CONFIG_ZONE_DMA) defined(CONFIG_ARM_LPAE)
.dma_zone_size = SZ_2G,
@@ -75,5 +41,4 @@ DT_MACHINE_START(KEYSTONE, Keystone)
.smp= smp_ops(keystone_smp_ops),
.init_machine = keystone_init,
.dt_compat = keystone_match,
- .restart= keystone_restart,
MACHINE_END
--
1.8.3.2
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[PATCH 0/5] Introduce keystone reset driver
These patches introduce keystone reset driver. The keystone SoC can be rebooted in several ways. By external reset pin, by soft and by watchdogs. This driver allows software reset or reset by one of the watchdogs. Also added opportunity to set soft/hard reset type. Based on v3.14-rc4 CC: Dmitry Eremin-Solenikov dbarysh...@gmail.com CC: David Woodhouse dw...@infradead.org CC: Grant Likely grant.lik...@linaro.org CC: Rob Herring robh...@kernel.org CC: Pawel Moll pawel.m...@arm.com CC: Mark Rutland mark.rutl...@arm.com CC: Ian Campbell ijc+devicet...@hellion.org.uk CC: Kumar Gala ga...@codeaurora.org CC: Rob Landley r...@landley.net CC: Santosh Shilimkar santosh.shilim...@ti.com CC: Russell King li...@arm.linux.org.uk Ivan Khoronzhuk (5): Power: reset: keystone-reset: introduce keystone reset driver Power: reset: add bindings for keystone reset driver ARM: keystone: remove redundant reset stuff ARM: dts: keystone: update reset node to work with reset driver ARM: keystone: enable reset driver support .../bindings/power/reset/keystone-reset.txt| 59 +++ arch/arm/boot/dts/keystone.dtsi| 4 +- arch/arm/configs/keystone_defconfig| 3 + arch/arm/mach-keystone/keystone.c | 35 - drivers/power/reset/Kconfig| 7 + drivers/power/reset/Makefile | 1 + drivers/power/reset/keystone-reset.c | 171 + 7 files changed, 244 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/reset/keystone-reset.txt create mode 100644 drivers/power/reset/keystone-reset.c -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/5] Power: reset: add bindings for keystone reset driver
This node is intended to allow SoC reset in case of software reset
or appropriate watchdogs.
The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event input is connected to the Reset Mux
block. The Reset Mux block can be configured to cause reset or not.
Additionally soft or hard reset can be configured.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
CC: Rob Herring robh...@kernel.org
CC: Pawel Moll pawel.m...@arm.com
CC: Mark Rutland mark.rutl...@arm.com
CC: Ian Campbell ijc+devicet...@hellion.org.uk
CC: Kumar Gala ga...@codeaurora.org
CC: Rob Landley r...@landley.net
.../bindings/power/reset/keystone-reset.txt| 59 ++
1 file changed, 59 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/keystone-reset.txt
diff --git a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt
b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt
new file mode 100644
index 000..5ad5883
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt
@@ -0,0 +1,59 @@
+* Device tree bindings for Texas Instruments keystone reset
+
+This node is intended to allow SoC reset in case of software reset
+of selected watchdogs.
+
+The Keystone SoCs can contain up to 4 watchdog timers to reset
+SoC. Each watchdog timer event input is connected to the Reset Mux
+block. The Reset Mux block can be configured to cause reset or not.
+
+Additionally soft or hard reset can be configured.
+
+Required properties:
+
+- compatible: ti,keystone-reset
+
+- reg: Contains offset/length value for mux registers.
+
+ reg = 0x23100e4 0x10,
+ 0x2620328 0x10;
+
+-reg-names:Contains two ranges pllregs and muxregs.
+ pllregs - PLL reset control regs: RSTYPE, RSCTRL,
+ RSCFG, RSISO.
+ muxregs - mux block registers for all watchdogs.
+
+Optional properties:
+
+- ti,soft-reset: Boolean option indicating soft reset.
+ By default hard reset is used.
+
+- ti,wdt_list: WDT list that can cause SoC reset.
+ The list in format: 0, 2;
+ Begins from 0 to 3, as keystone can contain up
+ to 4 SoC reset watchdogs.
+
+Example 1:
+Setup keystone reset so that in case software reset or
+WDT1 is triggered it issues hard reset for SoC.
+
+rstctrl: reset-controller {
+ compatible = ti,keystone-reset;
+ reg = 0x23100e4 0x10,
+ 0x2620328 0x10;
+ reg-names = pllregs, muxregs;
+ ti,wdt_list = 0;
+};
+
+Example 2:
+Setup keystone reset so that in case of software reset or
+WDT1 or WDT3 is triggered it issues soft reset for SoC.
+
+rstctrl: reset-controller {
+ compatible = ti,keystone-reset;
+ reg = 0x23100e4 0x10,
+ 0x2620328 0x10;
+ reg-names = pllregs, muxregs;
+ ti,wdt_list = 0, 2;
+ ti,soft-reset;
+};
--
1.8.3.2
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[PATCH 4/5] ARM: dts: keystone: update reset node to work with reset driver
The reset controller registers are part of the PLL Controller MMRs.
According to TRM there are the following registers:
RSTYPE, RSCTRL, RSCFG and RSISO. Currently declared only one of them,
but that is not enough to correctly setup reset properties, so add
whole range of pll registers - pllregs.
Also add range for reset multiplex registers for SoC on the device.
These registers are located in Bootcfg memory space and needed
to setup behaviour after appropriate watchdog is triggered.
Add ti,wdt_list option to declare what watchdog are used to reboot
the SoC.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
CC: Rob Herring robh...@kernel.org
CC: Pawel Moll pawel.m...@arm.com
CC: Mark Rutland mark.rutl...@arm.com
CC: Ian Campbell ijc+devicet...@hellion.org.uk
CC: Kumar Gala ga...@codeaurora.org
CC: Russell King li...@arm.linux.org.uk
arch/arm/boot/dts/keystone.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 3a83ffe..7092208 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -99,7 +99,9 @@
rstctrl: reset-controller {
compatible = ti,keystone-reset;
- reg = 0x023100e8 4; /* pll reset control reg */
+ reg = 0x23100e4 0x10, 0x2620328 0x10;
+ reg-names = pllregs, muxregs;
+ ti,wdt_list = 0;
};
/include/ keystone-clocks.dtsi
--
1.8.3.2
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Re: [PATCH v4 1/2] memory: ti-aemif: introduce AEMIF driver
On 02/18/2014 10:30 PM, Greg KH wrote: On Wed, Feb 05, 2014 at 09:46:13PM +0200, Ivan Khoronzhuk wrote: Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Signed-off-by: [initial author] Murali Karicheri m-kariche...@ti.com What's this [] stuff? If Murali wrote this, that name needs to be in a From: line in the patch to properly attribute it, and drop the [] here. Ok, I'll delete [] stuff. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/memory/Kconfig| 11 ++ drivers/memory/Makefile | 1 + drivers/memory/ti-aemif.c | 429 ++ 3 files changed, 441 insertions(+) create mode 100644 drivers/memory/ti-aemif.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 29a11db..7bc3982 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -7,6 +7,17 @@ menuconfig MEMORY if MEMORY +config TI_AEMIF + tristate Texas Instruments AEMIF driver + depends on (ARCH_DAVINCI || ARCH_KEYSTONE) OF + help + This driver is for the AEMIF module available in Texas Instruments + SoCs. AEMIF stands for Asynchronous External Memory Interface and + is intended to provide a glue-less interface to a variety of + asynchronuous memory devices like ASRAM, NOR and NAND memory. A total + of 256M bytes of any of these memories can be accessed at a given + time via four chip selects with 64M byte access per chip select. + config TI_EMIF tristate Texas Instruments EMIF driver depends on ARCH_OMAP2PLUS diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 969d923..d4e150c 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -5,6 +5,7 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o obj-$(CONFIG_MVEBU_DEVBUS)+= mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c new file mode 100644 index 000..8d15d87 --- /dev/null +++ b/drivers/memory/ti-aemif.c @@ -0,0 +1,429 @@ +/* + * TI AEMIF driver + * + * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/ + * + * Authors: + * Murali Karicheri m-kariche...@ti.com + * Ivan Khoronzhuk ivan.khoronz...@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/err.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_platform.h +#include linux/platform_device.h + +#define TA_SHIFT 2 +#define RHOLD_SHIFT4 +#define RSTROBE_SHIFT 7 +#define RSETUP_SHIFT 13 +#define WHOLD_SHIFT17 +#define WSTROBE_SHIFT 20 +#define WSETUP_SHIFT 26 +#define EW_SHIFT 30 +#define SS_SHIFT 31 + +#define TA(x) ((x) TA_SHIFT) +#define RHOLD(x) ((x) RHOLD_SHIFT) +#define RSTROBE(x) ((x) RSTROBE_SHIFT) +#define RSETUP(x) ((x) RSETUP_SHIFT) +#define WHOLD(x) ((x) WHOLD_SHIFT) +#define WSTROBE(x) ((x) WSTROBE_SHIFT) +#define WSETUP(x) ((x) WSETUP_SHIFT) +#define EW(x) ((x) EW_SHIFT) +#define SS(x) ((x) SS_SHIFT) + +#define ASIZE_MAX 0x1 +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX0x3f +#define WSETUP_MAX 0xf +#define EW_MAX 0x1 +#define SS_MAX 0x1 +#define NUM_CS 4 + +#define TA_VAL(x) (((x) TA(TA_MAX)) TA_SHIFT) +#define RHOLD_VAL(x) (((x) RHOLD(RHOLD_MAX)) RHOLD_SHIFT) +#define RSTROBE_VAL(x) (((x) RSTROBE(RSTROBE_MAX)) RSTROBE_SHIFT) +#define RSETUP_VAL(x) (((x) RSETUP(RSETUP_MAX)) RSETUP_SHIFT) +#define WHOLD_VAL(x) (((x) WHOLD(WHOLD_MAX)) WHOLD_SHIFT) +#define WSTROBE_VAL(x) (((x) WSTROBE(WSTROBE_MAX)) WSTROBE_SHIFT) +#define WSETUP_VAL(x) (((x) WSETUP(WSETUP_MAX)) WSETUP_SHIFT) +#define EW_VAL(x) (((x) EW(EW_MAX)) EW_SHIFT) +#define SS_VAL(x) (((x) SS(SS_MAX)) SS_SHIFT) + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASKBIT(30) +#define ACR_SS_MASKBIT(31) +#define
[PATCH v5 2/2] memory: ti-aemif: add bindings for AEMIF driver
Add bindings for TI Async External Memory Interface (AEMIF) controller. The Async External Memory Interface (EMIF16/AEMIF) controller is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed via 4 chip selects with 64M byte access per chip select. We are not encoding CS number in reg property, it's memory partition number. The CS number is encoded for Davinci NAND node using standalone property ti,davinci-chipselect and we need to provide two memory ranges to it, as result we can't encode CS number in reg for AEMIF child devices (NAND/NOR/etc), as it will break bindings compatibility. In this patch, NAND node is used just as an example of child node. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- .../bindings/memory-controllers/ti-aemif.txt | 210 + 1 file changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt new file mode 100644 index 000..48f82e4 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt @@ -0,0 +1,210 @@ +* Device tree bindings for Texas instruments AEMIF controller + +The Async External Memory Interface (EMIF16/AEMIF) controller is intended to +provide a glue-less interface to a variety of asynchronous memory devices like +ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories +can be accessed at any given time via four chip selects with 64M byte access +per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM +and Mobile SDR are not supported. + +Documentation: +Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf +Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf + +Required properties: + +- compatible: ti,davinci-aemif + ti,keystone-aemif + ti,da850-aemif + +- reg: contains offset/length value for AEMIF control registers + space. + +- #address-cells: Must be 2. The partition number has to be encoded in the + first address cell and it may accept values 0..N-1 + (N - total number of partitions). It's recommended to + assign N-1 number for the control partition. The second + cell is the offset into the partition. + +- #size-cells: Must be set to 1. + +- ranges: Contains memory regions. There are two types of + ranges/partitions: + - CS-specific partition/range. If continuous, must be + set up to reflect the memory layout for 4 chipselects, + if not then additional range/partition can be added and + child device can select the proper one. + - control partition which is common for all CS + interfaces. + +- clocks: the clock feeding the controller clock. Required only + if clock tree data present in device tree. + See clock-bindings.txt + +- clock-names: clock name. It has to be aemif. Required only if clock + tree data present in device tree, in another case don't + use it. + See clock-bindings.txt + +- clock-ranges:Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + See clock-bindings.txt + + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt). +There might be board specific devices like FPGAs. + +Required child cs node properties: + +- #address-cells: Must be 2. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +- clock-ranges:Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + +- ti,cs-chipselect:number of chipselect. Indicates on the aemif driver + which chipselect is used for accessing the memory. For + compatibles ti,davinci-aemif and ti,keystone-aemif + it can be in range [0-3]. For compatible + ti,da850-aemif range is [2-5]. + +Optional child cs node properties: + +- ti,bus
[PATCH v5 0/2] Introduce AEMIF driver for Davinci/Keystone archs
These patches introduce Async External Memory Interface (EMIF16/AEMIF) controller driver for Davinci/Keystone archs. For more informations see documentation: Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf OMAP-L138 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf Based on v3.14-rc3. v4..v5: - memory: ti-aemif: introduce AEMIF driver deleted DRV_NAME in favour of KBUILD_MODNAME deleted redundant err message in case of memory allocation some cosmetic changes v3..v4: rebased on latest of linux-keystone.git keystone/master v2..v3 (https://lkml.org/lkml/2013/12/11/148): - memory: ti-aemif: introduce AEMIF driver changed to work with multiple AEMIF controllers corrected copyright to authors in header changed compatible ti,omap-L138-aemif to ti,da850-aeimf used NULL in clk_get() instead of aemif name driver can be build as loadable module treat all child nodes as cs nodes, it makes code simpler - memory: ti-aemif: add bindings for AEMIF driver deleted direct link driver/memory/ti-aemif.c clarified description of controller ranges property changed compatible ti,omap-L138-aemif to ti,da850-aeimf added cs number information in commit log removed compatible property from cs node, it makes code simpler v1..v2 (https://lkml.org/lkml/2013/11/21/170): - memory: ti-aemif: introduce AEMIF driver - memory: ti-aemif: add bindings for AEMIF driver added ti.cs-chipselect property instead of representing chipselect number in cs node name. Ivan Khoronzhuk (2): memory: ti-aemif: introduce AEMIF driver memory: ti-aemif: add bindings for AEMIF driver .../bindings/memory-controllers/ti-aemif.txt | 210 ++ drivers/memory/Kconfig | 11 + drivers/memory/Makefile| 1 + drivers/memory/ti-aemif.c | 427 + 4 files changed, 649 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt create mode 100644 drivers/memory/ti-aemif.c -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 1/2] memory: ti-aemif: introduce AEMIF driver
Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Signed-off-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- drivers/memory/Kconfig| 11 ++ drivers/memory/Makefile | 1 + drivers/memory/ti-aemif.c | 427 ++ 3 files changed, 439 insertions(+) create mode 100644 drivers/memory/ti-aemif.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 29a11db..7bc3982 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -7,6 +7,17 @@ menuconfig MEMORY if MEMORY +config TI_AEMIF + tristate Texas Instruments AEMIF driver + depends on (ARCH_DAVINCI || ARCH_KEYSTONE) OF + help + This driver is for the AEMIF module available in Texas Instruments + SoCs. AEMIF stands for Asynchronous External Memory Interface and + is intended to provide a glue-less interface to a variety of + asynchronuous memory devices like ASRAM, NOR and NAND memory. A total + of 256M bytes of any of these memories can be accessed at a given + time via four chip selects with 64M byte access per chip select. + config TI_EMIF tristate Texas Instruments EMIF driver depends on ARCH_OMAP2PLUS diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 969d923..d4e150c 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -5,6 +5,7 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c new file mode 100644 index 000..fcc25a1 --- /dev/null +++ b/drivers/memory/ti-aemif.c @@ -0,0 +1,427 @@ +/* + * TI AEMIF driver + * + * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/ + * + * Authors: + * Murali Karicheri m-kariche...@ti.com + * Ivan Khoronzhuk ivan.khoronz...@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/err.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_platform.h +#include linux/platform_device.h + +#define TA_SHIFT 2 +#define RHOLD_SHIFT4 +#define RSTROBE_SHIFT 7 +#define RSETUP_SHIFT 13 +#define WHOLD_SHIFT17 +#define WSTROBE_SHIFT 20 +#define WSETUP_SHIFT 26 +#define EW_SHIFT 30 +#define SS_SHIFT 31 + +#define TA(x) ((x) TA_SHIFT) +#define RHOLD(x) ((x) RHOLD_SHIFT) +#define RSTROBE(x) ((x) RSTROBE_SHIFT) +#define RSETUP(x) ((x) RSETUP_SHIFT) +#define WHOLD(x) ((x) WHOLD_SHIFT) +#define WSTROBE(x) ((x) WSTROBE_SHIFT) +#define WSETUP(x) ((x) WSETUP_SHIFT) +#define EW(x) ((x) EW_SHIFT) +#define SS(x) ((x) SS_SHIFT) + +#define ASIZE_MAX 0x1 +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX0x3f +#define WSETUP_MAX 0xf +#define EW_MAX 0x1 +#define SS_MAX 0x1 +#define NUM_CS 4 + +#define TA_VAL(x) (((x) TA(TA_MAX)) TA_SHIFT) +#define RHOLD_VAL(x) (((x) RHOLD(RHOLD_MAX)) RHOLD_SHIFT) +#define RSTROBE_VAL(x) (((x) RSTROBE(RSTROBE_MAX)) RSTROBE_SHIFT) +#define RSETUP_VAL(x) (((x) RSETUP(RSETUP_MAX)) RSETUP_SHIFT) +#define WHOLD_VAL(x) (((x) WHOLD(WHOLD_MAX)) WHOLD_SHIFT) +#define WSTROBE_VAL(x) (((x) WSTROBE(WSTROBE_MAX)) WSTROBE_SHIFT) +#define WSETUP_VAL(x) (((x) WSETUP(WSETUP_MAX)) WSETUP_SHIFT) +#define EW_VAL(x) (((x) EW(EW_MAX)) EW_SHIFT) +#define SS_VAL(x) (((x) SS(SS_MAX)) SS_SHIFT) + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASKBIT(30) +#define ACR_SS_MASKBIT(31) +#define ASIZE_16BIT1 + +#define CONFIG_MASK(TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE
Re: [PATCH v4 1/2] memory: ti-aemif: introduce AEMIF driver
On 02/19/2014 04:34 PM, Greg KH wrote:
On Wed, Feb 19, 2014 at 12:32:02PM +0200, Ivan Khoronzhuk wrote:
+ aemif-clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(aemif-clk)) {
+ dev_err(dev, cannot get clock 'aemif'\n);
+ return PTR_ERR(aemif-clk);
No freeing memory?
There is no need to free memory explicitly.
devm_kzalloc is used instead of kzalloc.
Yes, but where does the device on the error path get removed?
Why these functions are needed in that case...
As I see, memory allocated with these functions
are automatically freed on driver detach.
Additionally I've checked if resources are released after
AEMIF driver probe error.
And they're released completely in case of probe error.
:-\
--
Regards,
Ivan Khoronzhuk
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Re: [PATCH v5 2/2] memory: ti-aemif: add bindings for AEMIF driver
On 02/19/2014 08:11 PM, Mark Rutland wrote: On Wed, Feb 19, 2014 at 01:40:10PM +, Ivan Khoronzhuk wrote: Add bindings for TI Async External Memory Interface (AEMIF) controller. The Async External Memory Interface (EMIF16/AEMIF) controller is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed via 4 chip selects with 64M byte access per chip select. We are not encoding CS number in reg property, it's memory partition number. The CS number is encoded for Davinci NAND node using standalone property ti,davinci-chipselect and we need to provide two memory ranges to it, as result we can't encode CS number in reg for AEMIF child devices (NAND/NOR/etc), as it will break bindings compatibility. In this patch, NAND node is used just as an example of child node. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- .../bindings/memory-controllers/ti-aemif.txt | 210 + 1 file changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt [...] +- ranges: Contains memory regions. There are two types of + ranges/partitions: + - CS-specific partition/range. If continuous, must be + set up to reflect the memory layout for 4 chipselects, + if not then additional range/partition can be added and + child device can select the proper one. + - control partition which is common for all CS + interfaces. This really doesn't sound anything like the typical meaning of ranges on a bus. Why isn't this information encoded in reg properties on the child nodes? [...] Note that we do not introduce NAND device bindings here. The Davinci NAND bindings was introduced and accepted more then one year ago. And the CS number is encoded for Davinci NAND node using standalone property ti,davinci-chipselect and we need to provide two memory ranges to it, as result we can't encode CS number in reg for AEMIF child devices (NAND/NOR/etc), as it will break bindings compatibility. In this document, NAND node is used just as an example of child node. +- ti,cs-ss:enable/disable select strobe mode + In select strobe mode chip select behaves as + the strobe and is active only during the strobe + period. If present then enable. + +- ti,cs-ew:enable/disable extended wait mode + if set, the controller monitors the EMIFWAIT pin + mapped to that chip select to determine if the + device wants to extend the strobe period. If + present then enable. When would you have these two in the DT and when wouldn't you? Why can't the driver decide? These are properties of cs node, not the driver itself. The driver cannot know what child device you are going to attach to cs node , as result it cannot decide what settings you are using for particular cs node. These names are also opaque. We can clearly do better. I propose the following names?: ti,cs-ss -- ti,cs-select-strobe-mode ti,cs-ew -- ti,cs-extended-waite-mode Are you OK with it? + +- ti,cs-ta:minimum turn around time, ns + Time between the end of one asynchronous memory + access and the start of another asynchronous + memory access. This delay is not incurred + between a read followed by read or a write + followed by a write to same chip select. The name is opaque. How about ti,min-turnaround-time-ns ? I like without -ns suffix and with cs- prefix: ti,cs-ta -- ti,cs-min-turnaround-time Is it OK? + +- ti,cs-rsetup:read setup width, ns + Time between the beginning of a memory cycle + and the activation of read strobe. + Minimum value is 1 (0 treated as 1). + +- ti,cs-rstobe:read strobe width, ns + Time between the activation and deactivation of + the read strobe. + Minimum value is 1 (0 treated as 1). + +- ti,cs-rhold: read hold width, ns + Time between the deactivation of the read + strobe and the end of the cycle (which may be + either an address change or the deactivation of + the chip select signal. + Minimum value is 1 (0 treated as 1
Re: [PATCH v5 2/2] memory: ti-aemif: add bindings for AEMIF driver
On 02/20/2014 03:44 PM, Rob Herring wrote: On Thu, Feb 20, 2014 at 6:44 AM, Ivan Khoronzhuk ivan.khoronz...@ti.com wrote: On 02/19/2014 08:11 PM, Mark Rutland wrote: On Wed, Feb 19, 2014 at 01:40:10PM +, Ivan Khoronzhuk wrote: Add bindings for TI Async External Memory Interface (AEMIF) controller. The Async External Memory Interface (EMIF16/AEMIF) controller is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed via 4 chip selects with 64M byte access per chip select. We are not encoding CS number in reg property, it's memory partition number. The CS number is encoded for Davinci NAND node using standalone property ti,davinci-chipselect and we need to provide two memory ranges to it, as result we can't encode CS number in reg for AEMIF child devices (NAND/NOR/etc), as it will break bindings compatibility. In this patch, NAND node is used just as an example of child node. Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- .../bindings/memory-controllers/ti-aemif.txt | 210 + 1 file changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt [...] +- ranges: Contains memory regions. There are two types of + ranges/partitions: + - CS-specific partition/range. If continuous, must be + set up to reflect the memory layout for 4 chipselects, + if not then additional range/partition can be added and + child device can select the proper one. + - control partition which is common for all CS + interfaces. This really doesn't sound anything like the typical meaning of ranges on a bus. Why isn't this information encoded in reg properties on the child nodes? [...] Note that we do not introduce NAND device bindings here. The Davinci NAND bindings was introduced and accepted more then one year ago. And the CS number is encoded for Davinci NAND node using standalone property ti,davinci-chipselect and we need to provide two memory ranges to it, as result we can't encode CS number in reg for AEMIF child devices (NAND/NOR/etc), as it will break bindings compatibility. In this document, NAND node is used just as an example of child node. +- ti,cs-ss:enable/disable select strobe mode + In select strobe mode chip select behaves as + the strobe and is active only during the strobe + period. If present then enable. + +- ti,cs-ew:enable/disable extended wait mode + if set, the controller monitors the EMIFWAIT pin + mapped to that chip select to determine if the + device wants to extend the strobe period. If + present then enable. When would you have these two in the DT and when wouldn't you? Why can't the driver decide? These are properties of cs node, not the driver itself. The driver cannot know what child device you are going to attach to cs node , as result it cannot decide what settings you are using for particular cs node. These names are also opaque. We can clearly do better. I propose the following names?: ti,cs-ss -- ti,cs-select-strobe-mode ti,cs-ew -- ti,cs-extended-waite-mode Are you OK with it? + +- ti,cs-ta:minimum turn around time, ns + Time between the end of one asynchronous memory + access and the start of another asynchronous + memory access. This delay is not incurred + between a read followed by read or a write + followed by a write to same chip select. The name is opaque. How about ti,min-turnaround-time-ns ? I like without -ns suffix and with cs- prefix: ti,cs-ta -- ti,cs-min-turnaround-time Is it OK? + +- ti,cs-rsetup:read setup width, ns + Time between the beginning of a memory cycle + and the activation of read strobe. + Minimum value is 1 (0 treated as 1). + +- ti,cs-rstobe:read strobe width, ns + Time between the activation and deactivation of + the read strobe. + Minimum value is 1 (0 treated as 1). + +- ti,cs-rhold: read hold width, ns + Time between the deactivation of the read + strobe and the end of the cycle (which may be + either an address change or the deactivation
[PATCH v6 0/3] Introduce clocksource driver for Keystone platform
Add a broadcast timer64 based clockevent driver for keystone arch. This driver uses timer in 64-bit general purpose mode as clock event device. Documentation: http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf Based on git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git keystone/master v5..v6: added function to encapsulate __iowmb(). v4..v5: used __iowmb() insted of wmb() v3..v4: rebased on latest of linux-keystone.git keystone/master v2..v3: - clocksource: timer-keystone: introduce clocksource driver for changed u64 type to unsigned long for hz_period as more appropriate hz_period rounded up by DIV_ROUND_UP(rate, HZ) corrected comments v1..v2: - clocksource: timer-keystone: introduce clocksource driver for renamed timer on timer-keystone in keystone_timer_interrupt() evet pointer is passed via dev_id used __relaxed variants of writel/readl and added explicit barriers added keystone_timer_disable() for using in keystone_set_mode() keystone_timer_config() is not used for disabling the timer any more in case of an unsupported mode the keystone_timer_config() returns -1. used request_irq() instead of setup_irq() assigned irq for event_device in event_dev-irq calculated timer.hz_period for CLOCK_EVT_MODE_PERIODIC at init deleted spare call of keystone_timer_config() in keystone_timer_init() Ivan Khoronzhuk (3): clocksource: timer-keystone: introduce clocksource driver for Keystone clocksource: keystone: add bindings for keystone timer arm: dts: keystone: add keystone timer entry .../bindings/timer/ti,keystone-timer.txt | 29 +++ arch/arm/boot/dts/keystone-clocks.dtsi | 10 + arch/arm/boot/dts/keystone.dtsi| 7 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-keystone.c | 244 + 5 files changed, 291 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/ti,keystone-timer.txt create mode 100644 drivers/clocksource/timer-keystone.c -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 2/3] clocksource: keystone: add bindings for keystone timer
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.
It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.
Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Acked-by: Rob Herring r...@kernel.org
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
.../bindings/timer/ti,keystone-timer.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
new file mode 100644
index 000..5fbe361
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
@@ -0,0 +1,29 @@
+* Device tree bindings for Texas instruments Keystone timer
+
+This document provides bindings for the 64-bit timer in the KeyStone
+architecture devices. The timer can be configured as a general-purpose 64-bit
+timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
+timers, each half can operate in conjunction (chain mode) or independently
+(unchained mode) of each other.
+
+It is global timer is a free running up-counter and can generate interrupt
+when the counter reaches preset counter values.
+
+Documentation:
+http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
+
+Required properties:
+
+- compatible : should be ti,keystone-timer.
+- reg : specifies base physical address and count of the registers.
+- interrupts : interrupt generated by the timer.
+- clocks : the clock feeding the timer clock.
+
+Example:
+
+timer@22f {
+ compatible = ti,keystone-timer;
+ reg = 0x022f 0x80;
+ interrupts = GIC_SPI 110 IRQ_TYPE_EDGE_RISING;
+ clocks = clktimer15;
+};
--
1.8.3.2
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[PATCH v6 1/3] clocksource: timer-keystone: introduce clocksource driver for Keystone
Add broadcast clock-event device for the Keystone arch.
The timer can be configured as a general-purpose 64-bit timer,
dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or
independently (unchained mode) of each other.
Reviewed-by: Stephen Boyd sb...@codeaurora.org
Acked-by: Santosh shilimkar santosh.shilim...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keystone.c | 244 +++
2 files changed, 245 insertions(+)
create mode 100644 drivers/clocksource/timer-keystone.c
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index c7ca50a..4abe5aa 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o
+obj-$(CONFIG_ARCH_KEYSTONE)+= timer-keystone.o
diff --git a/drivers/clocksource/timer-keystone.c
b/drivers/clocksource/timer-keystone.c
new file mode 100644
index 000..86b08cd
--- /dev/null
+++ b/drivers/clocksource/timer-keystone.c
@@ -0,0 +1,244 @@
+/*
+ * Keystone broadcast clock-event
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *
+ * Author: Ivan Khoronzhuk ivan.khoronz...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include linux/clk.h
+#include linux/clockchips.h
+#include linux/clocksource.h
+#include linux/interrupt.h
+#include linux/of_address.h
+#include linux/of_irq.h
+
+#define TIMER_NAME timer-keystone
+
+/* Timer register offsets */
+#define TIM12 0x10
+#define TIM34 0x14
+#define PRD12 0x18
+#define PRD34 0x1c
+#define TCR0x20
+#define TGCR 0x24
+#define INTCTLSTAT 0x44
+
+/* Timer register bitfields */
+#define TCR_ENAMODE_MASK 0xC0
+#define TCR_ENAMODE_ONESHOT_MASK 0x40
+#define TCR_ENAMODE_PERIODIC_MASK 0x80
+
+#define TGCR_TIM_UNRESET_MASK 0x03
+#define INTCTLSTAT_ENINT_MASK 0x01
+
+/**
+ * struct keystone_timer: holds timer's data
+ * @base: timer memory base address
+ * @hz_period: cycles per HZ period
+ * @event_dev: event device based on timer
+ */
+static struct keystone_timer {
+ void __iomem *base;
+ unsigned long hz_period;
+ struct clock_event_device event_dev;
+} timer;
+
+static inline u32 keystone_timer_readl(unsigned long rg)
+{
+ return readl_relaxed(timer.base + rg);
+}
+
+static inline void keystone_timer_writel(u32 val, unsigned long rg)
+{
+ writel_relaxed(val, timer.base + rg);
+}
+
+/**
+ * keystone_timer_barrier: write memory barrier
+ * use explicit barrier to avoid using readl/writel non relaxed function
+ * variants, because in our case non relaxed variants hide the true places
+ * where barrier is needed.
+ */
+static inline void keystone_timer_barrier(void)
+{
+ __iowmb();
+}
+
+/**
+ * keystone_timer_config: configures timer to work in oneshot/periodic modes.
+ * @ mode: mode to configure
+ * @ period: cycles number to configure for
+ */
+static int keystone_timer_config(u64 period, enum clock_event_mode mode)
+{
+ u32 tcr;
+ u32 off;
+
+ tcr = keystone_timer_readl(TCR);
+ off = tcr ~(TCR_ENAMODE_MASK);
+
+ /* set enable mode */
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ tcr |= TCR_ENAMODE_ONESHOT_MASK;
+ break;
+ case CLOCK_EVT_MODE_PERIODIC:
+ tcr |= TCR_ENAMODE_PERIODIC_MASK;
+ break;
+ default:
+ return -1;
+ }
+
+ /* disable timer */
+ keystone_timer_writel(off, TCR);
+ /* here we have to be sure the timer has been disabled */
+ keystone_timer_barrier();
+
+ /* reset counter to zero, set new period */
+ keystone_timer_writel(0, TIM12);
+ keystone_timer_writel(0, TIM34);
+ keystone_timer_writel(period 0x, PRD12);
+ keystone_timer_writel(period 32, PRD34);
+
+ /*
+* enable timer
+* here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers
+* have been written.
+*/
+ keystone_timer_barrier();
+ keystone_timer_writel(tcr, TCR);
+ return 0;
+}
+
+static void keystone_timer_disable(void)
+{
+ u32 tcr;
+
+ tcr = keystone_timer_readl(TCR);
+
+ /* disable timer */
+ tcr = ~(TCR_ENAMODE_MASK);
+ keystone_timer_writel(tcr, TCR
[PATCH v6 3/3] arm: dts: keystone: add keystone timer entry
Add keystone timer entry to keystone device tree.
This 64-bit timer is used as backup clock event device.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/boot/dts/keystone-clocks.dtsi | 10 ++
arch/arm/boot/dts/keystone.dtsi| 7 +++
2 files changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi
b/arch/arm/boot/dts/keystone-clocks.dtsi
index 2363593..16d2aba 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -737,6 +737,16 @@ clocks {
domain-id = 0;
};
+ clktimer15: clktimer15 {
+ #clock-cells = 0;
+ compatible = ti,keystone,psc-clock;
+ clocks = clkmodrst0;
+ clock-output-names = timer15;
+ reg = 0x0235 0xb00, 0x0235 0x400;
+ reg-names = control, domain;
+ domain-id = 0;
+ };
+
clkuart0: clkuart0 {
#clock-cells = 0;
compatible = ti,keystone,psc-clock;
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index b420290..cac9841 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -208,5 +208,12 @@
usb-phy = usb_phy, usb_phy;
};
};
+
+ clock_event: timer@22f {
+ compatible = ti,keystone-timer;
+ reg = 0x022f 0x80;
+ interrupts = GIC_SPI 110 IRQ_TYPE_EDGE_RISING;
+ clocks = clktimer15;
+ };
};
};
--
1.8.3.2
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Re: [PATCH 15/28] Remove TI_AEMIF
On 02/11/2014 09:04 PM, Brian Norris wrote: + Ivan, others On Sun, Feb 09, 2014 at 09:54:02PM +0100, Paul Bolle wrote: On Sun, 2014-02-09 at 19:47 +0100, Richard Weinberger wrote: The symbol is an orphan, get rid of it. Signed-off-by: Richard Weinberger rich...@nod.at --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 90ff447..a195d57 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -465,7 +465,7 @@ config MTD_NAND_SH_FLCTL config MTD_NAND_DAVINCI tristate Support NAND on DaVinci/Keystone SoC -depends on ARCH_DAVINCI || (ARCH_KEYSTONE TI_AEMIF) +depends on ARCH_DAVINCI || ARCH_KEYSTONE help Enable the driver for NAND flash chips on Texas Instruments DaVinci/Keystone processors. What's strange about the current dependency is that the only aemif code I could find lives at arch/arm/mach-davinci/aemif.c. Is that reachable for code in arch/arm/mach-keystone? It looks like I merged this code before the supporting aemif driver [1] was merged. I think this is harmless, and so I plan to leave it as-is for now. Or if Ivan prefers, I can drop the Keystone dependency entirely until it is ready. https://lkml.org/lkml/2013/11/20/283 Brian It is harmless. For Keystone NAND depends on AEMIF. AEMIF is responsible to set timings. In case of Davinci the timings are set by arch/arm/mach-davinci/aemif.c. In case of Keystone the timings are going to be set by AEMIF driver. AEMIF is going to be merged I hope. That's plan. So you can leave it. -- Regards, Ivan Khoronzhuk -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/2] ARM: dts: keystone: disable subpage write for davinci nand device
Add the property davinci-no-subpage-write to disable sub page write in the
nand driver.
Signed-off-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/boot/dts/k2hk-evm.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index 1a1335b..624520f 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -118,6 +118,7 @@
nand-ecc-mode = hw;
ti,davinci-ecc-bits = 4;
nand-on-flash-bbt;
+ ti,davinci-no-subpage-write;
partition@0 {
label = u-boot;
--
1.8.3.2
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