Hi Ezequiel,
Sorry for delayed replies..
>From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com]
>Pekon,
>
>A few questions regarding this patch, despite the fact I'm not sure it will
>ever be included.
>
>On 20 Mar 01:04 PM, Pekon Gupta wrote:
>> +0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
>> gpmc_wait0.gpmc_wait0 */
>> +0x74 (MUX_MODE7 | PIN_OUTPUT_PULLUP)/*
>> gpmc_wpn.gpio0_30 */
>
>Is this output pin?
Yes, it's the "Write Protect (WP)" pin. And goes controller -> device.
>
>> +0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
>> gpmc_csn0.gpmc_csn0 */
>
>Again: is this output pin?
>
Yes, this is "Chip-select" and goes from controller -> device.
Though it should already have external pull-up resistor on board, to avoid
glitches due to noise, and avoid device getting confused when SoC
is not driving anything (like before pin-muxing).
>> +gpmc,wait-on-read = "true";
>> +gpmc,wait-on-write = "true";
>
>The devicetree binding says these wait properties are bool, so the above
>should be:
>
> gpmc,wait-on-read;
> gpmc,wait-on-write;
>
>But the problem is that there's no wait-pin defined, so this not enabled.
>
>Could you explain what should be the correct binding? This is very confusing
>for me.
>
I have fixed the above DT mapping in newer version of the patch [1].
Sorry, yes the wait-pin monitoring implementation is not cleanly done,
there is mix of platform_data and DT stuff. So in addition to updated DT patch
you need following patch to enable wait-pin monitoring in NAND driver.
http://www.spinics.net/lists/linux-omap/msg107253.html
with regards, pekon
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