Re: [PATCH] sh-sci: add R8A7743/5 support
On Fri, Sep 30, 2016 at 12:37:13AM +0300, Sergei Shtylyov wrote: > Renesas RZ/G SoC also have the SCIF, SCIFA, SCIFB, and HSCIF ports. > Document RZ/G1[ME] (also known as R8A774[35]) SoC bindings along with > the RZ/G family bindings. The driver itself also needs to recognize > the latter binding for the SCIF ports, so teach it... > > Signed-off-by: Sergei Shtylyov Acked-by: Simon Horman
[PATCH RFC v2 12/12] ARM: dts: sk-rzg1m: add Ether support
Define the SK-RZG1M board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov --- Changes in version 2: - new patch. arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts === --- renesas.orig/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -42,3 +42,16 @@ &scif0 { status = "okay"; }; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +};
[PATCH RFC v2 11/12] ARM: dts: sk-rzg1m: initial device tree
Add the initial device tree for the R8A7743 SoC based SK-RZG1M board. The board has one debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov --- arch/arm/boot/dts/Makefile |1 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 + 2 files changed, 45 insertions(+) Index: renesas/arch/arm/boot/dts/Makefile === --- renesas.orig/arch/arm/boot/dts/Makefile +++ renesas/arch/arm/boot/dts/Makefile @@ -654,6 +654,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7743-sk-rzg1m.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts === --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -0,0 +1,44 @@ +/* + * Device Tree Source for the SK-RZG1M board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743.dtsi" + +/ { + model = "SK-RZG1M"; + compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@4000 { + device_type = "memory"; + reg = <0 0x4000 0 0x4000>; + }; + + memory@2 { + device_type = "memory"; + reg = <2 0x 0 0x4000>; + }; +}; + +&extal_clk { + clock-frequency = <2000>; +}; + +&scif0 { + status = "okay"; +};
[PATCH RFC v2 10/12] DT: arm: shmobile: document SK-RZG1M board
Document the SK-RZG1M device tree bindings, listing it as a supported board. This allows to use checkpatch.pl to validate .dts files referring to the SK-RZG1M board. Signed-off-by: Sergei Shtylyov --- Changes in version 2: - new patch. Documentation/devicetree/bindings/arm/shmobile.txt |2 ++ 1 file changed, 2 insertions(+) Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt === --- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt +++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt @@ -75,5 +75,7 @@ Boards: compatible = "renesas,salvator-x", "renesas,r8a7796"; - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" + - SK-RZG1M (YR8A77430S000BE) +compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - Wheat compatible = "renesas,wheat", "renesas,r8a7792"
[PATCH RFC v2 9/12] ARM: dts: r8a7743: add IRQC support
Describe the IRQC interrupt controller in the R8A7743 device tree. Signed-off-by: Sergei Shtylyov --- Changes in version 2: - new patch. arch/arm/boot/dts/r8a7743.dtsi | 19 +++ 1 file changed, 19 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi === --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -72,6 +72,25 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller@e61c { + compatible = "renesas,irqc-r8a7743", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c 0 0x200>; + interrupts = , +, +, +, +, +, +, +, +, +; + clocks = <&mstp4_clks R8A7743_CLK_IRQC>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts =
[PATCH RFC v2 8/12] ARM: dts: r8a7743: add Ether support
Define the generic R8A7743 part of the Ether device node. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov --- Changes in version 2: - new patch. arch/arm/boot/dts/r8a7743.dtsi | 12 1 file changed, 12 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi === --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -415,6 +415,18 @@ status = "disabled"; }; + ether: ethernet@ee70 { + compatible = "renesas,ether-r8a7743"; + reg = <0 0xee70 0 0x400>; + interrupts = ; + clocks = <&mstp8_clks R8A7743_CLK_ETHER>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e615 { compatible = "renesas,r8a7743-cpg-clocks",
[PATCH RFC v2 7/12] ARM: dts: r8a7743: add [H]SCIF[AB] support
Describe [H]SCIF[AB] ports in the R8A7743 device tree. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov --- Changes in version 2: - used the new RZ/G family "compatible" prop values, reformatting where needed; - fixed the size cells of the SCIFB device nodes' "reg" properties; - changed the size cells of the "reg" properties to hexadecimal; - indented the SCIFA1 device node's closing brace correctly - adjusted the patch description, renamed the patch. arch/arm/boot/dts/r8a7743.dtsi | 261 + 1 file changed, 261 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi === --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -154,6 +154,267 @@ dma-channels = <15>; }; + scifa0: serial@e6c4 { + compatible = "renesas,scifa-r8a7743", +"renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c4 0 0x40>; + interrupts = ; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA0>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial@e6c5 { + compatible = "renesas,scifa-r8a7743", +"renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c5 0 0x40>; + interrupts = ; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA1>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial@e6c6 { + compatible = "renesas,scifa-r8a7743", +"renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c6 0 0x40>; + interrupts = ; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA2>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial@e6c7 { + compatible = "renesas,scifa-r8a7743", +"renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c7 0 0x40>; + interrupts = ; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA3>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7743", +"renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA4>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial@e6c8 { + compatible = "renesas,scifa-r8a7743", +"renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c8 0 0x40>; + interrupts = ; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA5>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; +
[PATCH RFC v2 6/12] ARM: dts: r8a7743: add SYS-DMAC support
Describe SYS-DMAC0/1 in the R8A7743 device tree. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - added Geert's tag. arch/arm/boot/dts/r8a7743.dtsi | 64 + 1 file changed, 64 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi === --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -90,6 +90,70 @@ #power-domain-cells = <1>; }; + dmac0: dma-controller@e670 { + compatible = "renesas,dmac-r8a7743", +"renesas,rcar-dmac"; + reg = <0 0xe670 0 0x2>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7743_CLK_SYS_DMAC0>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e672 { + compatible = "renesas,dmac-r8a7743", +"renesas,rcar-dmac"; + reg = <0 0xe672 0 0x2>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7743_CLK_SYS_DMAC1>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e615 { compatible = "renesas,r8a7743-cpg-clocks",
[PATCH RFC v2 5/12] ARM: dts: r8a7743: initial SoC device tree
The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, and the required clock descriptions. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov --- Changes in version 2: - added the IRQC and Ether clocks. arch/arm/boot/dts/r8a7743.dtsi | 235 + 1 file changed, 235 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi === --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -0,0 +1,235 @@ +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <15>; + clocks = <&cpg_clocks R8A7743_CLK_Z>; + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <15>; + power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , +, +, +; + }; + + sysc: system-controller@e618 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe618 0 0x0200>; + #power-domain-cells = <1>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e615 { + compatible = "renesas,r8a7743-cpg-clocks", +"renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe615 0 0x1000>; + clocks = <&extal_clk &usb_extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", +"lb", "qspi", "sdh", "sd0", "z", +"rcan"; + #power-domain-cells = <0>; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + zs_clk: zs { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + p_clk: p { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>;
[PATCH RFC v2 4/12] ARM: shmobile: r8a7743: basic SoC support
Add minimal support for the RZ/G1M (R8A7743) SoC. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - removed "select I2C" from the R8A7743 Kconfig entry; - documented the R8A7743 device tree binding; - added Geert's tag. Documentation/devicetree/bindings/arm/shmobile.txt |2 + arch/arm/mach-shmobile/Kconfig |4 ++ arch/arm/mach-shmobile/Makefile|1 arch/arm/mach-shmobile/setup-r8a7743.c | 34 + 4 files changed, 41 insertions(+) Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt === --- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt +++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt @@ -13,6 +13,8 @@ SoCs: compatible = "renesas,r8a73a4" - R-Mobile A1 (R8A77400) compatible = "renesas,r8a7740" + - RZ/G1M (R8A77430) +compatible = "renesas,r8a7743" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" - R-Car H1 (R8A77790) Index: renesas/arch/arm/mach-shmobile/Kconfig === --- renesas.orig/arch/arm/mach-shmobile/Kconfig +++ renesas/arch/arm/mach-shmobile/Kconfig @@ -68,6 +68,10 @@ config ARCH_R8A7740 select ARCH_RMOBILE select RENESAS_INTC_IRQPIN +config ARCH_R8A7743 + bool "RZ/G1M (R8A77430)" + select ARCH_RCAR_GEN2 + config ARCH_R8A7778 bool "R-Car M1A (R8A77781)" select ARCH_RCAR_GEN1 Index: renesas/arch/arm/mach-shmobile/Makefile === --- renesas.orig/arch/arm/mach-shmobile/Makefile +++ renesas/arch/arm/mach-shmobile/Makefile @@ -9,6 +9,7 @@ obj-y := timer.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o +obj-$(CONFIG_ARCH_R8A7743) += setup-r8a7743.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o Index: renesas/arch/arm/mach-shmobile/setup-r8a7743.c === --- /dev/null +++ renesas/arch/arm/mach-shmobile/setup-r8a7743.c @@ -0,0 +1,34 @@ +/* + * r8a7743 processor support + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include + +#include "common.h" +#include "rcar-gen2.h" + +static const char * const r8a7743_boards_compat_dt[] __initconst = { + "renesas,r8a7743", + NULL, +}; + +DT_MACHINE_START(R8A7743_DT, "Generic R8A7743 (Flattened Device Tree)") + .init_early = shmobile_init_delay, + .init_time = rcar_gen2_timer_init, + .init_late = shmobile_init_late, + .reserve= rcar_gen2_reserve, + .dt_compat = r8a7743_boards_compat_dt, +MACHINE_END
[PATCH RFC v2 3/12] soc: renesas: rcar-sysc: add R8A7743 support
Add support for RZ/G1M (R8A7743) SoC power areas to the R-Car SYSC driver. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - documented the R8A7743 SYSC device tree binding; - added "R-Car" to the patch description; - added Geert's tag. Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt |7 +- drivers/soc/renesas/Makefile |1 drivers/soc/renesas/r8a7743-sysc.c| 32 ++ drivers/soc/renesas/rcar-sysc.c |3 drivers/soc/renesas/rcar-sysc.h |1 5 files changed, 41 insertions(+), 3 deletions(-) Index: renesas/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt === --- renesas.orig/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ renesas/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -1,12 +1,13 @@ -DT bindings for the Renesas R-Car System Controller +DT bindings for the Renesas R-Car (RZ/G) System Controller == System Controller Node == -The R-Car System Controller provides power management for the CPU cores and -various coprocessors. +The R-Car (RZ/G) System Controller provides power management for the CPU cores +and various coprocessors. Required properties: - compatible: Must contain exactly one of the following: + - "renesas,r8a7743-sysc" (RZ/G1M) - "renesas,r8a7779-sysc" (R-Car H1) - "renesas,r8a7790-sysc" (R-Car H2) - "renesas,r8a7791-sysc" (R-Car M2-W) Index: renesas/drivers/soc/renesas/Makefile === --- renesas.orig/drivers/soc/renesas/Makefile +++ renesas/drivers/soc/renesas/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ARCH_R8A7743) += rcar-sysc.o r8a7743-sysc.o obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o obj-$(CONFIG_ARCH_R8A7791) += rcar-sysc.o r8a7791-sysc.o Index: renesas/drivers/soc/renesas/r8a7743-sysc.c === --- /dev/null +++ renesas/drivers/soc/renesas/r8a7743-sysc.c @@ -0,0 +1,32 @@ +/* + * Renesas RZ/G1M System Controller + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; of the License. + */ + +#include +#include + +#include + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a7743_areas[] __initconst = { + { "always-on", 0, 0, R8A7743_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca15-scu", 0x180, 0, R8A7743_PD_CA15_SCU, R8A7743_PD_ALWAYS_ON, + PD_SCU }, + { "ca15-cpu0", 0x40, 0, R8A7743_PD_CA15_CPU0, R8A7743_PD_CA15_SCU, + PD_CPU_NOCR }, + { "ca15-cpu1", 0x40, 1, R8A7743_PD_CA15_CPU1, R8A7743_PD_CA15_SCU, + PD_CPU_NOCR }, + { "sgx", 0xc0, 0, R8A7743_PD_SGX, R8A7743_PD_ALWAYS_ON }, +}; + +const struct rcar_sysc_info r8a7743_sysc_info __initconst = { + .areas = r8a7743_areas, + .num_areas = ARRAY_SIZE(r8a7743_areas), +}; Index: renesas/drivers/soc/renesas/rcar-sysc.c === --- renesas.orig/drivers/soc/renesas/rcar-sysc.c +++ renesas/drivers/soc/renesas/rcar-sysc.c @@ -275,6 +275,9 @@ finalize: } static const struct of_device_id rcar_sysc_matches[] = { +#ifdef CONFIG_ARCH_R8A7743 + { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info }, +#endif #ifdef CONFIG_ARCH_R8A7779 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info }, #endif Index: renesas/drivers/soc/renesas/rcar-sysc.h === --- renesas.orig/drivers/soc/renesas/rcar-sysc.h +++ renesas/drivers/soc/renesas/rcar-sysc.h @@ -50,6 +50,7 @@ struct rcar_sysc_info { unsigned int num_areas; }; +extern const struct rcar_sysc_info r8a7743_sysc_info; extern const struct rcar_sysc_info r8a7779_sysc_info; extern const struct rcar_sysc_info r8a7790_sysc_info; extern const struct rcar_sysc_info r8a7791_sysc_info;
[PATCH RFC v2 2/12] ARM: shmobile: r8a7743: add power domain index macros
Add macros usable by the device tree sources to reference R8A7743 SYSC power domains by index. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - added Geert's tag. include/dt-bindings/power/r8a7743-sysc.h | 25 + 1 file changed, 25 insertions(+) Index: renesas/include/dt-bindings/power/r8a7743-sysc.h === --- /dev/null +++ renesas/include/dt-bindings/power/r8a7743-sysc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7743_PD_CA15_CPU00 +#define R8A7743_PD_CA15_CPU11 +#define R8A7743_PD_CA15_SCU12 +#define R8A7743_PD_SGX 20 + +/* Always-on power area */ +#define R8A7743_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */
[PATCH RFC v2 1/12] ARM: shmobile: r8a7743: add clock index macros
Add macros usable by the device tree sources to reference the R8A7743 clocks by index. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov --- Changes in version 2: - fixed the file copyright. include/dt-bindings/clock/r8a7743-clock.h | 157 ++ 1 file changed, 157 insertions(+) Index: renesas/include/dt-bindings/clock/r8a7743-clock.h === --- /dev/null +++ renesas/include/dt-bindings/clock/r8a7743-clock.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7743_H__ +#define __DT_BINDINGS_CLOCK_R8A7743_H__ + +/* CPG */ +#define R8A7743_CLK_MAIN 0 +#define R8A7743_CLK_PLL0 1 +#define R8A7743_CLK_PLL1 2 +#define R8A7743_CLK_PLL3 3 +#define R8A7743_CLK_LB 4 +#define R8A7743_CLK_QSPI 5 +#define R8A7743_CLK_SDH6 +#define R8A7743_CLK_SD07 +#define R8A7743_CLK_Z 8 +#define R8A7743_CLK_RCAN 9 + +/* MSTP0 */ +#define R8A7743_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7743_CLK_VCP0 1 +#define R8A7743_CLK_VPC0 3 +#define R8A7743_CLK_TMU1 11 +#define R8A7743_CLK_3DG12 +#define R8A7743_CLK_2DDMAC 15 +#define R8A7743_CLK_FDP1_1 18 +#define R8A7743_CLK_FDP1_0 19 +#define R8A7743_CLK_TMU3 21 +#define R8A7743_CLK_TMU2 22 +#define R8A7743_CLK_CMT0 24 +#define R8A7743_CLK_TMU0 25 +#define R8A7743_CLK_VSP1_DU1 27 +#define R8A7743_CLK_VSP1_DU0 28 +#define R8A7743_CLK_VSP1_S 31 + +/* MSTP2 */ +#define R8A7743_CLK_SCIFA2 2 +#define R8A7743_CLK_SCIFA1 3 +#define R8A7743_CLK_SCIFA0 4 +#define R8A7743_CLK_MSIOF2 5 +#define R8A7743_CLK_SCIFB0 6 +#define R8A7743_CLK_SCIFB1 7 +#define R8A7743_CLK_MSIOF1 8 +#define R8A7743_CLK_SCIFB2 16 +#define R8A7743_CLK_SYS_DMAC1 18 +#define R8A7743_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7743_CLK_TPU0 4 +#define R8A7743_CLK_SDHI2 11 +#define R8A7743_CLK_SDHI1 12 +#define R8A7743_CLK_SDHI0 14 +#define R8A7743_CLK_MMCIF0 15 +#define R8A7743_CLK_IIC0 18 +#define R8A7743_CLK_PCIEC 19 +#define R8A7743_CLK_IIC1 23 +#define R8A7743_CLK_SSUSB 28 +#define R8A7743_CLK_CMT1 29 +#define R8A7743_CLK_USBDMAC0 30 +#define R8A7743_CLK_USBDMAC1 31 + +/* MSTP4 */ +#define R8A7743_CLK_IRQC 7 + +/* MSTP5 */ +#define R8A7743_CLK_AUDIO_DMAC11 +#define R8A7743_CLK_AUDIO_DMAC02 +#define R8A7743_CLK_THERMAL22 +#define R8A7743_CLK_PWM23 + +/* MSTP7 */ +#define R8A7743_CLK_EHCI 3 +#define R8A7743_CLK_HSUSB 4 +#define R8A7743_CLK_HSCIF2 13 +#define R8A7743_CLK_SCIF5 14 +#define R8A7743_CLK_SCIF4 15 +#define R8A7743_CLK_HSCIF1 16 +#define R8A7743_CLK_HSCIF0 17 +#define R8A7743_CLK_SCIF3 18 +#define R8A7743_CLK_SCIF2 19 +#define R8A7743_CLK_SCIF1 20 +#define R8A7743_CLK_SCIF0 21 +#define R8A7743_CLK_DU123 +#define R8A7743_CLK_DU024 +#define R8A7743_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7743_CLK_IPMMU_SGX 0 +#define R8A7743_CLK_VIN2 9 +#define R8A7743_CLK_VIN1 10 +#define R8A7743_CLK_VIN0 11 +#define R8A7743_CLK_ETHER 13 +#define R8A7743_CLK_SATA1 14 +#define R8A7743_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7743_CLK_GPIO7 4 +#define R8A7743_CLK_GPIO6 5 +#define R8A7743_CLK_GPIO5 7 +#define R8A7743_CLK_GPIO4 8 +#define R8A7743_CLK_GPIO3 9 +#define R8A7743_CLK_GPIO2 10 +#define R8A7743_CLK_GPIO1 11 +#define R8A7743_CLK_GPIO0 12 +#define R8A7743_CLK_RCAN1 15 +#define R8A7743_CLK_RCAN0 16 +#define R8A7743_CLK_QSPI_MOD 17 +#define R8A7743_CLK_I2C5 25 +#define R8A7743_CLK_IICDVFS26 +#define R8A7743_CLK_I2C4 27 +#define R8A7743_CLK_I2C3 28 +#define R8A7743_CLK_I2C2 29 +#define R8A7743_CLK_I2C1
[PATCH RFC v2 0/12] Add R8A7743/SK-RZG1M board support
Hello. Here's the set of 12 patches against Simon Horman's 'renesas.git' repo, 'renesas-devel-20160926-v4.8-rc8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. This version includes the Ether, so the board should boot with NFS root now. I tried to address all the comments to the version 1 (except the need to use the new CPG/MSSR drivers -- this one will be addressed RSN). The DMAC/SCIF/IRQC bindings patches posted recently are needed for scripts/checkpatch.pl to be happy. :-) [1/12] ARM: shmobile: r8a7743: add clock index macros [2/12] ARM: shmobile: r8a7743: add power domain index macros [3/12] soc: renesas: rcar-sysc: add R8A7743 support [4/12] ARM: shmobile: r8a7743: basic SoC support [5/12] ARM: dts: r8a7743: initial SoC device tree [6/12] ARM: dts: r8a7743: add SYS-DMAC support [7/12] ARM: dts: r8a7743: add [H]SCIF[AB] support [8/12] ARM: dts: r8a7743: add Ether support [9/12] ARM: dts: r8a7743: add IRQC support [10/12] DT: arm: shmobile: document SK-RZG1M board [11/12] ARM: dts: sk-rzg1m: initial device tree [12/12] ARM: dts: sk-rzg1m: add Ether support WBR, Sergei
[PATCH] sh-sci: add R8A7743/5 support
Renesas RZ/G SoC also have the SCIF, SCIFA, SCIFB, and HSCIF ports. Document RZ/G1[ME] (also known as R8A774[35]) SoC bindings along with the RZ/G family bindings. The driver itself also needs to recognize the latter binding for the SCIF ports, so teach it... Signed-off-by: Sergei Shtylyov --- This patch is against the 'tty-next' branch of GregKH's 'tty.git' repo. Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 12 ++ drivers/tty/serial/sh-sci.c |3 ++ 2 files changed, 15 insertions(+) Index: tty/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt === --- tty.orig/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ tty/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -9,6 +9,14 @@ Required properties: - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART. +- "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART. +- "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART. +- "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART. +- "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART. +- "renesas,scif-r8a7745" for R8A7745 (RZ/G1E) SCIF compatible UART. +- "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART. +- "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART. +- "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART. - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. @@ -38,11 +46,15 @@ Required properties: - "renesas,rcar-gen1-scif" for R-Car Gen1 SCIF compatible UART, - "renesas,rcar-gen2-scif" for R-Car Gen2 SCIF compatible UART, - "renesas,rcar-gen3-scif" for R-Car Gen3 SCIF compatible UART, +- "renesas,rzg-scif" for RZ/G SCIF compatible UART. - "renesas,rcar-gen2-scifa" for R-Car Gen2 SCIFA compatible UART, +- "renesas,rzg-scifa" for RZ/G SCIFA compatible UART. - "renesas,rcar-gen2-scifb" for R-Car Gen2 SCIFB compatible UART, +- "renesas,rzg-scifb" for RZ/G SCIFB compatible UART. - "renesas,rcar-gen1-hscif" for R-Car Gen1 HSCIF compatible UART, - "renesas,rcar-gen2-hscif" for R-Car Gen2 HSCIF compatible UART, - "renesas,rcar-gen3-hscif" for R-Car Gen3 HSCIF compatible UART, +- "renesas,rzg-hscif" for RZ/G HSCIF compatible UART. - "renesas,scif" for generic SCIF compatible UART. - "renesas,scifa" for generic SCIFA compatible UART. - "renesas,scifb" for generic SCIFB compatible UART. Index: tty/drivers/tty/serial/sh-sci.c === --- tty.orig/drivers/tty/serial/sh-sci.c +++ tty/drivers/tty/serial/sh-sci.c @@ -2950,6 +2950,9 @@ static const struct of_device_id of_sci_ }, { .compatible = "renesas,rcar-gen3-scif", .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), + }, { + .compatible = "renesas,rzg-scif", + .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), }, /* Generic types */ {
[PATCH] DT: irqchip: renesas-irqc: document R8A7743/5 support
Renesas RZ/G SoC have the R-Car gen2 compatible IRQC interrupt controllers. Document RZ/G1[ME] (also known as R8A774[35]) SoC bindings. Signed-off-by: Sergei Shtylyov --- The patch is against the 'tip.git' repo's 'irq/core' branch. Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) Index: tip/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt === --- tip.orig/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt +++ tip/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt @@ -1,10 +1,12 @@ -DT bindings for the R-Mobile/R-Car interrupt controller +DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller Required properties: - compatible: has to be "renesas,irqc-", "renesas,irqc" as fallback. Examples with soctypes are: - "renesas,irqc-r8a73a4" (R-Mobile APE6) +- "renesas,irqc-r8a7743" (RZ/G1M) +- "renesas,irqc-r8a7745" (RZ/G1E) - "renesas,irqc-r8a7790" (R-Car H2) - "renesas,irqc-r8a7791" (R-Car M2-W) - "renesas,irqc-r8a7792" (R-Car V2H)
[PATCH] dma-debug: fix ia64 build, use PHYS_PFN
kbuild test robot reports: lib/dma-debug.c: In function 'debug_dma_map_resource': >> lib/dma-debug.c:1541:16: error: implicit declaration of function >> '__phys_to_pfn' [-Werror=implicit-function-declaration] entry->pfn = __phys_to_pfn(addr); ^ ia64 does not provide __phys_to_pfn(), use the PHYS_PFN() alias. Fixes: 0e74b34dfc3318bf ("dma-debug: add support for resource mappings") Signed-off-by: Niklas Söderlund --- lib/dma-debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/dma-debug.c b/lib/dma-debug.c index 2ba086b..59e7586 100644 --- a/lib/dma-debug.c +++ b/lib/dma-debug.c @@ -1514,7 +1514,7 @@ void debug_dma_map_resource(struct device *dev, phys_addr_t addr, size_t size, entry->type = dma_debug_resource; entry->dev = dev; - entry->pfn = __phys_to_pfn(addr); + entry->pfn = PHYS_PFN(addr); entry->offset = offset_in_page(addr); entry->size = size; entry->dev_addr = dma_addr; -- 2.9.3
[PATCH/RFC] tty: serial_core: Move uart_console() check after console registration
The port->console flag is always false, as uart_console() is called before the serial console has been registered. Hence for a serial port used as the console, uart_tty_port_shutdown() will still be called when userspace closes the port, powering it down. This will lead to a system lock up when the serial console driver writes to the serial port's registers. To fix this, move the setting of port->console after the call to uart_configure_port(), which registers the serial console. Fixes: 761ed4a94582ab29 ("tty: serial_core: convert uart_close to use tty_port_close") Reported-by: Niklas Söderlund Reported-by: Takeshi Kihara Signed-off-by: Geert Uytterhoeven --- RFC because of the comment "If this port is a console, then the spinlock is already initialised", and the pre-existing code calling uart_console() before uart_configure_port(). Can be reproduced on Renesas boards: 1. With systemd: hangs during boot, 2. Without systemd: "telinit n" to switch to a runlevel that doesn't run a getty on ttySC0, and trigger kernel output. --- drivers/tty/serial/serial_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c index 6e4f63627479db8d..ce8899c13af3d97f 100644 --- a/drivers/tty/serial/serial_core.c +++ b/drivers/tty/serial/serial_core.c @@ -2746,8 +2746,6 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *uport) uport->cons = drv->cons; uport->minor = drv->tty_driver->minor_start + uport->line; - port->console = uart_console(uport); - /* * If this port is a console, then the spinlock is already * initialised. @@ -2761,6 +2759,8 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *uport) uart_configure_port(drv, state, uport); + port->console = uart_console(uport); + num_groups = 2; if (uport->attr_group) num_groups++; -- 1.9.1
Re: GEN2:Lager: Only 1 core works when turning off the SW8-PIN4
Hi Hiep, On Thu, Sep 29, 2016 at 1:03 PM, Hiep Cao Minh wrote: > I'd like to report the issue of the CPU operation. > We tested and found it on Lager board at linux-v4.8-rcx. > > The test procedure is the following: > > Confirmation command: > > # cat /proc/interrupts > CPU0 > 19: 2509 GIC-0 27 Level arch_timer > 21: 0 GIC-0 36 Level e605.gpio > 22: 0 GIC-0 37 Level e6051000.gpio > 23: 0 GIC-0 38 Level e6052000.gpio > 24: 0 GIC-0 39 Level e6053000.gpio > 25: 0 GIC-0 40 Level e6054000.gpio > 26: 0 GIC-0 41 Level e6055000.gpio > 27: 23 GIC-0 101 Level e61f.thermal > …” > > This issue appears when we changed the SW8-PIN4 of Lager board. > > SW8-PIN4: ON > > + At linux-v4.7: OK (4 cores work together normally). > + At linux-v4.8-rc2: OK (4 cores work together normally). > > SW8-PIN4: OFF > > + At linux-v4.7: -> OK(4 cores work together normally). > + At linux-v4.8-rc2: -> NG(Only 1 core works). And the kernel prints "Unable to boot CPU%u when MD21 is set", right? > We tried to find out the issued patch and we realize that it happens from > the following patch: > " 043248c Merge tag 'armsoc-dt' of > git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc" The issue you're seeing is due to a combination of commits 5f3bca0db8ac01a7 ("ARM: shmobile: apmu: Add APMU DT support via Enable method") and dc378795156d980c ("ARM: dts: r8a7790: Add APMU nodes"). When debug mode is enabled (SW8-4 = OFF), trying to boot secondary CPUs may lock up the system after a cold boot, depending of boot load version. Hence we explicitly prohibit that. BTW, this has been the case on Koelsch since commit 277efd30cfc72ec2 ("ARM: shmobile: Check r8a7791 MD21 at SMP boot"). Now, does series "[PATCH/RFT 0/4] ARM: shmobile: R-Car Gen2: Allow booting secondary CPU cores in debug mode" (included in all renesas-drivers releases during September) fix it for you? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Re: [PATCH 0/2] dma-mapping: fix ia64 and m32r build error and warnings
On 2016-09-29 17:40:04 +0530, Vinod Koul wrote: > On Thu, Sep 29, 2016 at 12:02:38PM +0200, Niklas Söderlund wrote: > > From: Niklas Söderlund > > > > Hi Vindo, > > :( I'm sorry, my hands sometimes moves faster then my head. > > > > > This small series fixes the build error and warnings for ia64 and m32r > > which kbuild test robot found and where introduced in the series > > '[PATCHv9 0/6] dmaengine: rcar-dmac: add iommu support for slave > > transfers'. > > Applied both Thanks. > > Thanks > -- > ~Vinod -- Regards, Niklas Söderlund
Re: [PATCH 0/2] dma-mapping: fix ia64 and m32r build error and warnings
On Thu, Sep 29, 2016 at 12:02:38PM +0200, Niklas Söderlund wrote: > From: Niklas Söderlund > > Hi Vindo, :( > > This small series fixes the build error and warnings for ia64 and m32r > which kbuild test robot found and where introduced in the series > '[PATCHv9 0/6] dmaengine: rcar-dmac: add iommu support for slave > transfers'. Applied both Thanks -- ~Vinod
[PATCH 2/2] dma-mapping: fix m32r build warning
From: Niklas Söderlund kbuild test robot reports: In file included from include/linux/skbuff.h:34:0, from include/linux/icmpv6.h:4, from include/linux/ipv6.h:75, from include/net/ipv6.h:16, from include/linux/sunrpc/clnt.h:27, from include/linux/nfs_fs.h:30, from fs/lockd/clntlock.c:13: include/linux/dma-mapping.h: In function 'dma_map_resource': >> include/linux/dma-mapping.h:274:16: warning: unused variable 'pfn' >> [-Wunused-variable] unsigned long pfn = __phys_to_pfn(phys_addr); ^~~ The pfn value is only used once in the call to pfn_valid(), remove the variable and calculate the pfn when it's needed. Note that the kbuild report is old and PHYS_PFN() is now used instead of __phys_to_pfn() to calculate the pfn. Signed-off-by: Niklas Söderlund --- include/linux/dma-mapping.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index ff7c87f..642cb4c 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -271,13 +271,12 @@ static inline dma_addr_t dma_map_resource(struct device *dev, unsigned long attrs) { struct dma_map_ops *ops = get_dma_ops(dev); - unsigned long pfn = PHYS_PFN(phys_addr); dma_addr_t addr; BUG_ON(!valid_dma_direction(dir)); /* Don't allow RAM to be mapped */ - BUG_ON(pfn_valid(pfn)); + BUG_ON(pfn_valid(PHYS_PFN(phys_addr))); addr = phys_addr; if (ops->map_resource) -- 2.9.3
[PATCH 1/2] dma-mapping: fix ia64 build, use PHYS_PFN
From: Niklas Söderlund kbuild test robot reports: In file included from include/linux/skbuff.h:34:0, from include/linux/tcp.h:21, from drivers/net/ethernet/amd/xgbe/xgbe-drv.c:119: include/linux/dma-mapping.h: In function 'dma_map_resource': >> include/linux/dma-mapping.h:274:22: error: implicit declaration of function >> '__phys_to_pfn' [-Werror=implicit-function-declaration] unsigned long pfn = __phys_to_pfn(phys_addr); ^ ia64 does not provide __phys_to_pfn(), use the PHYS_PFN() alias. Signed-off-by: Niklas Söderlund --- include/linux/dma-mapping.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 6e00c7f..ff7c87f 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -271,7 +271,7 @@ static inline dma_addr_t dma_map_resource(struct device *dev, unsigned long attrs) { struct dma_map_ops *ops = get_dma_ops(dev); - unsigned long pfn = __phys_to_pfn(phys_addr); + unsigned long pfn = PHYS_PFN(phys_addr); dma_addr_t addr; BUG_ON(!valid_dma_direction(dir)); -- 2.9.3
[PATCH 0/2] dma-mapping: fix ia64 and m32r build error and warnings
From: Niklas Söderlund Hi Vindo, This small series fixes the build error and warnings for ia64 and m32r which kbuild test robot found and where introduced in the series '[PATCHv9 0/6] dmaengine: rcar-dmac: add iommu support for slave transfers'. It is based ontop of: git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/slave-dma.git next The fixes are only compile tested for the ia64 and m32r architecture to show that the error and warnings are fixed. It is tested on ARM to prove that the intended functionality still works. Kbuild test robot found one more class of warnings for the patch series mentioned above for the balackfin arch. include/linux/dma-mapping.h: In function 'dma_map_resource': >> include/asm-generic/page.h:90:32: warning: comparison of unsigned expression >> >= 0 is always true [-Wtype-limits] #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && ((pfn) - ARCH_PFN_OFFSET) < max_mapnr) ^ These warnings are not addressed in this series since they are not new or unique to original patch. They come from how pfn_valid() is implemented in include/asm-generic/page.h, if ARCH_PFN_OFFSET is 0 the warning is triggered. On the kbuild blackfin build it is defined as '(0x0 >> 12)' so any invocation of pfn_valid() will trigger it. I tried to fix it but was unable to find a good solution. There is a MIPS specific fix for this in commit 95486e4 (MIPS: Fix flood of warnings about comparsion being always true.), but a similar fix for asm-generic seems to tricky for me to attempt since the macro needs to be turned into a static inline function and that might be harmful. I also toyed with the solution of '#if ARCH_PFN_OFFSET == 0' to provided an alternative pfn_valid() macro, but since ARCH_PFN_OFFSET is defined as an expression and not a constant that wont work. If you can think of another way I be happy to try that out and see if I can make it work. Niklas Söderlund (2): dma-mapping: fix ia64 build, use PHYS_PFN dma-mapping: fix m32r build warning include/linux/dma-mapping.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.9.3
Re: LVDS Support in R-Car E2(ALT) Board
On Thursday 29 Sep 2016 08:35:32 Geert Uytterhoeven wrote: > On Thu, Sep 29, 2016 at 6:14 AM, Jithin T Raj wrote: > > I have successfully applied the patch and build R-car M2 Kernel for > > Koelsch Board..now it support LVDS..Thank you all especially Geert and > > Laurent..now i tried the same source tree(v4.7.5) to build for R-Car > > Good to hear it works on Koelsch! > > > E2(ALT)Board to make LVDS up..but i am getting the following error > > during making .dtb file > > > > ubuntu@teltvm2468l:~/jithin_new/linux-4.7.5$ make -j4 r8a7794-alt.dtb > > > > DTC arch/arm/boot/dts/r8a7794-alt.dtb > > > > Error: arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi:39.1-16 Label or > > path lvds_connector not found FATAL ERROR: Syntax error parsing input > > tree > > make[1]: *** [arch/arm/boot/dts/r8a7794-alt.dtb] Error 1 > > make: *** [r8a7794-alt.dtb] Error 2 > > ubuntu@teltvm2468l:~/jithin_new/linux-4.7.5$ > > > > I have included the "#include "r8a77xx-aa104xd12-panel.dtsi" in > > r8a7794-alt.dts > > > > my source tree is v4.7.5 stable edition > > No one has added LVDS support for r8a7794/alt yet. The R8A7794 has no LVDS output. The Alt board uses an RGB to LVDS bridge, similar to the one used by the Marzen board. You can have a look at the Marzen DT to see how to implement that. -- Regards, Laurent Pinchart
Re: LVDS SUPPORT RCAR
Hello Jithin, On Wednesday 28 Sep 2016 09:22:46 Jithin T Raj wrote: > hi, >first of all thanks alot for the support you are giving..when i tried to > make .dtb file i am getting following error..I am using 3.10.31-ltsi 3.10.31 is very old. If you want community support I recommend upgrading to the mainline kernel. If you can't, you'll have to update your device tree (and possibly the DU driver) by backporting changes from mainline. > ubuntu@teltvm2468l:~/Jithin/Koelsch/kernel$ make -j4 r8a7791-koelsch.dtb > CC scripts/mod/devicetable-offsets.s > GEN scripts/mod/devicetable-offsets.h > HOSTCC scripts/mod/file2alias.o > HOSTLD scripts/mod/modpost > DTC arch/arm/boot/dts/r8a7791-koelsch.dtb > Error: arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi:41.4-5 label or path, > 'lvds_connector', not found FATAL ERROR: Syntax error parsing input tree > make[1]: *** [arch/arm/boot/dts/r8a7791-koelsch.dtb] Error 1 > make: *** [r8a7791-koelsch.dtb] Error 2 > > here i am attaching my r8a7791.dts file -- Regards, Laurent Pinchart
Re: [PATCH] DT: dma: rcar-dmac: document R8A7743/5 support
On Thu, Sep 29, 2016 at 12:25 AM, Sergei Shtylyov wrote: > Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers. > Document RZ/G1[ME] (also known as R8A774[35]) SoC bindings. > > Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds