[PATCH v2 2/2] arm64: dts: renesas: condor: add PCIe support
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
Changes in version 2:
- mentioned Vladimir's original work and added his signoff;
- refreshed the patch.
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 12
1 file changed, 12 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -223,6 +223,18 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
+_bus_clk {
+ clock-frequency = <1>;
+};
+
+_phy {
+ status = "okay";
+};
+
{
avb_pins: avb {
groups = "avb_mdio", "avb_rgmii";
[PATCH v2 1/2] arm64: dts: renesas: r8a77980: add PCIe support
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
Changes in version 2:
- merged in the PCIEC patch, renamed the patch, updated the description
accordingly;
- used R8A77980_PD_ALWAYS_ON in the "power-domains" props
- mentioned Vladimir's original work and added his signoff.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 49 ++
1 file changed, 49 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,13 @@
clock-frequency = <0>;
};
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -402,6 +409,16 @@
status = "disabled";
};
+ pcie_phy: pcie-phy@e65d {
+ compatible = "renesas,r8a77980-pcie-phy";
+ reg = <0 0xe65d 0 0x8000>;
+ #phy-cells = <0>;
+ clocks = < CPG_MOD 319>;
+ power-domains = < R8A77980_PD_ALWAYS_ON>;
+ resets = < 319>;
+ status = "disabled";
+ };
+
canfd: can@e66c {
compatible = "renesas,r8a77980-canfd",
"renesas,rcar-gen3-canfd";
@@ -653,6 +670,38 @@
resets = < 408>;
};
+ pciec: pcie@fe00 {
+ compatible = "renesas,pcie-r8a77980",
+"renesas,pcie-rcar-gen3";
+ reg = <0 0xfe00 0 0x8>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <
+ 0x0100 0 0x 0 0xfe10 0 0x010
+ 0x0200 0 0xfe20 0 0xfe20 0 0x020
+ 0x0200 0 0x3000 0 0x3000 0 0x800
+ 0x4200 0 0x3800 0 0x3800 0 0x800
+ >;
+ dma-ranges = <0x4200 0 0x4000 0 0x4000
+ 0 0x8000>;
+ interrupts = ,
+,
+;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 148
+IRQ_TYPE_LEVEL_HIGH>;
+ clocks = < CPG_MOD 319>, <_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = < R8A77980_PD_ALWAYS_ON>;
+ resets = < 319>;
+ phys = <_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
vspd0: vsp@fea2 {
compatible = "renesas,vsp2";
reg = <0 0xfea2 0 0x5000>;
[PATCH v2 0/2] Add R8A77980/Condor PCIe support
Hello! Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's 'renesas-devel-20180614v2-v4.17' tag. We're adding the R8A77980 PCIe related device nodes and then enable PCIe on the Condor board. These patches depend on the R8A77980 PCIe PHY driver support in order to work properly. Note that in case the PCIe PHY driver is not enabled, the kernel will BUG() due to I/O space page leak in the PCIe driver... [1/2] arm64: dts: renesas: r8a77980: add PCIe support [2/2] arm64: dts: renesas: condor: add PCIe support WBR, Sergei
Re: [PATCH V2 4/5] PCI: rcar: Support runtime PM, link state L1 handling
On Wed, Jun 13, 2018 at 12:25:59PM -0500, Bjorn Helgaas wrote:
> On Wed, Jun 13, 2018 at 04:52:52PM +0100, Lorenzo Pieralisi wrote:
> > On Wed, Jun 13, 2018 at 08:53:08AM -0500, Bjorn Helgaas wrote:
> > > On Wed, Jun 13, 2018 at 01:54:51AM +0200, Marek Vasut wrote:
> > > > On 06/11/2018 03:59 PM, Bjorn Helgaas wrote:
> > > > > On Sun, Jun 10, 2018 at 03:57:10PM +0200, Marek Vasut wrote:
> > > > >> On 11/17/2017 06:49 PM, Lorenzo Pieralisi wrote:
> > > > >>> On Fri, Nov 10, 2017 at 10:58:42PM +0100, Marek Vasut wrote:
> > > > From: Phil Edworthy
> > > >
> > > > Most PCIe host controllers support L0s and L1 power states via
> > > > ASPM.
> > > > The R-Car hardware only supports L0s, so when the system suspends
> > > > and
> > > > resumes we have to manually handle L1.
> > > > When the system suspends, cards can put themselves into L1 and
> > > > send a
> > > > >>>
> > > > >>> I assumed L1 entry has to be negotiated depending upon the PCIe
> > > > >>> hierarchy capabilities, I would appreciate if you can explain to
> > > > >>> me what's the root cause of the issue please.
> > > > >>
> > > > >> You should probably ignore the suspend/resume part altogether. The
> > > > >> issue
> > > > >> here is that the cards can enter L1 state, while the controller
> > > > >> won't do
> > > > >> that automatically, it can only detect that the link went into L1
> > > > >> state.
> > > > >> If that happens,the driver must manually put the controller to L1
> > > > >> state.
> > > > >> The controller can transition out of L1 state automatically though.
> > > > >
> > > > > From earlier discussion I thought the R-Car root port did not
> > > > > advertise L1 support.
> > > >
> > > > Which discussion ? This one or somewhere else ?
> > >
> > > https://lkml.kernel.org/r/hk2pr0601mb1393d917d343e6363484ca68f5...@hk2pr0601mb1393.apcprd06.prod.outlook.com
> > >
> > > Re-reading that, I think I see my misunderstanding. I was only
> > > considering L1 in the ASPM context. I didn't realize the L1
> > > implications of devices being in states other than D0.
> > >
> > > Obviously L1 support for ASPM is optional and advertised via Link
> > > Capabilities. But per PCIe r4.0, sec 5.2, L1 support is required for
> > > PCI-PM compatible power management, and is entered "whenever all
> > > Functions ... are programmed to a D-state other than D0."
> > >
> > > So I guess this means *every* device is supposed to support L1 when it
> > > is in a non-D0 power state. I think *this* is the case you're
> > > solving.
> > >
> > > A little more of this detail, e.g., that this issue has nothing to do
> > > with ASPM, it's probably an R-Car erratum that the RC can't transition
> > > from L1 to L0, etc., in the changelog would really help clear things
> > > up for me.
> >
> > I think that the issue is related to the L0->L1 transition upon system
> > suspend (ie the kernel must force the controller into L1 when all
> > devices are in a sleep state) and for this specific reason I still think
> > that checking for a PM_Enter_L1 DLLP reception and doing the L0->L1
> > transition within a config access is wrong and prone to error (what's
> > the rationale behind that ?), this ought to be done using PM methods in
> > the host controller driver.
>
> But doesn't the problem happen whenever the link goes to L1, for any
> reason? E.g., runtime power management might put an endpoint in D3
> even if we're not doing a whole system suspend. A user could even
> force the endpoint to D3 by writing to PCI_PM_CTRL with "setpci". If
> that's the case, I don't think the host controller PM methods will be
> enough to work around the issue.
By PM methods I included runtime PM (and related device dependencies)
but you are right there, I missed some use cases (which are not
necessarily the most common but we have to cope with them anyway).
> The comment in the patch ("If we are not in L1 link state and we have
> received PM_ENTER_L1 DLLP, transition to L1 link state") suggests that
> the R-Car host doesn't handle step 10 in PCIe r4.0, sec 5.3.2.1
> correctly, i.e., it doesn't complete the transition of the link to L1.
>
> Putting this workaround in the config accessor makes sense to me
> because in this situation the endpoint thinks it's in L1 and it won't
> receive TLPs for config accesses. Apparently forcing the RP to L1
> completes the L1 entry, and the RP correctly handles the "Exit from L1
> State" (sec 5.3.2.2) that's required when the RP needs to send a TLP
> to the endpoint.
Yep, see above, I do not like it but I do not see how we can solve it
in another way either.
> I think there's still a potential issue if the endpoint goes to a
> non-D0 state, the link is stuck in this transitional state (endpoint
> thinks it's L1, RP thinks it's L0), and the *endpoint* wants to exit
> L1, e.g., so it can send a PME message for a wakeup. I don't know
> what happens then.
That's for Marek to explain and the
Re: [PATCH v1 4/5] ARM: dts: Renesas R9A06G032 pinctrl node
Hello!
On 06/14/2018 02:00 PM, Michel Pollet wrote:
> This provides a pinctrl driver for the Renesas R9A06G032 SoC
>
> Signed-off-by: Michel Pollet
> ---
> arch/arm/boot/dts/r9a06g032.dtsi | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi
> b/arch/arm/boot/dts/r9a06g032.dtsi
> index 3e45375..fbad039 100644
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -88,6 +88,14 @@
> status = "disabled";
> };
>
> + pinctrl: pinctrl@40067000 {
"pin-controller@..." please, it's looking more generic.
> + compatible = "renesas,r9a06g032-pinctrl";
> + reg = <0x40067000 0x1000>, <0x5100 0x800>;
> + clocks = < R9A06G032_HCLK_PINCONFIG>;
> + clock-names = "bus";
> + status = "okay";
> + };
> +
> gic: gic@44101000 {
> compatible = "arm,cortex-a7-gic", "arm,gic-400";
> interrupt-controller;
MBR, Sergei
[GIT/RFC PULL LTSI-4.14] Renesas SoCs and Drivers to v4.17
Hi, ** This series is for informational purposes only! ** This series is comprised of backports to v4.14 of the following components from their standard as of v4.16 to that of v4.17: * at24 * cpg * dw-hdmi * gen3 * gpio-rcar * i2c-rcar * i2c-sh-mobile * ipmmu-vmsa * irq-renesas-irqc * m25p80 * mach-shmobile * pci-rcar-gen2 * pcie-rcar * phy-micrel * ravb * rcar-can * rcar-dmac * rcar-du * rcar-snd * rcar-thermal * rcar-vin * renesas-sdhi * renesas-soc-id * sata-rcar * sh-drivers * sh-eth * sh-flctl * sh-mmcif * sh-mobile-ceu-camera * sh-msiof * sh-pfc * sh-sci * smsc911x * sysc * usb3-peri * usbhs * vsp1 * watchdog * xhci-plat * xhci-rcar And limited backport of the following to provide dependencies for the above: * drm-tilcdc-compat * of-overlay This is intended as part of a dry-run for backporting components used by Renesas SoCs from v4.15, v4.16, v4.17 and beyond to v4.14. In posting this work I am not implying anything about decisions on the base of the LTSI release will be. There are 381 patches. This is based on similar backports of components to their standard as of v4.16, posted as "[GIT/RFC PULL LTSI-4.14] Renesas SoCs and Drivers to v4.16" and tagged as backport/v4.14.48/snapshot-to-v4.16-flattened. As this work is for informational purposes I do not expect these patches to be imported to quilt by Greg at this time. However, if you would like to do so and rebasing would help please feel free to ask me to do so. The following changes since commit 6485613bce7106b963ce9a9dd8b6d434c26b1bfd: tty: serial: sh-sci: Add default for number of ports for compile-testing (2018-06-14 10:31:17 +0200) are available in the git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-backport.git tags/backport/v4.14.48/snapshot-to-v4.17-flattened for you to fetch changes up to 3e69ed4311e31be8084d65159d65a6973616c18f: serial: sh-sci: Document r8a77470 bindings (2018-06-14 10:58:52 +0200) LTSI-v4.14 Preparation for Renesas SoCs (to v4.17) Base: * v4.14.48 * Similar backport of components for Renesas SoCs to v4.16 Backports of the following components to their standard as of v4.17: * at24 * cpg * dw-hdmi * gen3 * gpio-rcar * i2c-rcar * i2c-sh-mobile * ipmmu-vmsa * irq-renesas-irqc * m25p80 * mach-shmobile * pci-rcar-gen2 * pcie-rcar * phy-micrel * ravb * rcar-can * rcar-dmac * rcar-du * rcar-snd * rcar-thermal * rcar-vin * renesas-sdhi * renesas-soc-id * sata-rcar * sh-drivers * sh-eth * sh-flctl * sh-mmcif * sh-mobile-ceu-camera * sh-msiof * sh-pfc * sh-sci * smsc911x * sysc * usb3-peri * usbhs * vsp1 * watchdog * xhci-plat * xhci-rcar Limited backport of the following to provide dependencies for the above: * drm-tilcdc-compat * of-overlay Amit Kucheria (3): arm64: defconfig: Enable the APCS IPC driver on Qualcomm platforms arm64: defconfig: enable thermal sensor on QCOM platforms arm64: defconfig: enable more cpufreq governors Ard Biesheuvel (2): arm64: defconfig: add newly added accelerated crypto modules arm64: defconfig: add support for Socionext SynQuacer based platforms Arnd Bergmann (2): ASoC: rsnd: mark PM functions __maybe_unused media: renesas-ceu: mark PM functions as __maybe_unused Biju Das (9): dt-bindings: iommu: ipmmu-vmsa: Add device tree support for r8a774[35] ARM: dts: r8a7743: Add IPMMU DT nodes ARM: dts: r8a7745: Add IPMMU DT nodes ARM: dts: r8a7743: Add VSP support ARM: dts: r8a7745: Add VSP support dt-bindings: PCI: rcar: Add device tree support for r8a7743 dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC dt-bindings: rcar-dmac: Document r8a77470 support serial: sh-sci: Document r8a77470 bindings Colin Ian King (1): PCI: rcar-gen2: Remove duplicated bit-wise or of RCAR_PCI_INT_SIGRETABORT Davidlohr Bueso (1): irqchip/gic: Update supports_deactivate static key to modern api Dien Pham (4): arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices arm64: dts: renesas: r8a7796: Update OPPs to support CA53 dfs arm64: dts: renesas: r8a7795: Update OPPs to support CA53 dfs Dinh Nguyen (1): arm64: defconfig: enable stmmac ethernet to defconfig Fabrizio Castro (15): clk: renesas: r8a7743: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock ARM: dts: iwg20m: Enable cmt0 ARM: dts: iwg22m: Enable cmt0 ARM: shmobile: Add watchdog support ARM: shmobile: rcar-gen2: Add watchdog support dt-bindings: pwm: rcar: Document r8a774[35] PWM bindings dt-bindings: pwm: renesas-tpu: Document r8a774[35] support soc: renesas: rcar-rst:
[GIT/RFC PULL LTSI-4.14] Renesas SoCs and Drivers to v4.16
Hi, ** This series is for informational purposes only! ** This series is comprised of backports to v4.14 of the following components from their standard as of v4.15 to that of v4.16: * at24 * cpg * dw-hdmi * gen3 * gpio-rcar * i2c-rcar * i2c-sh-mobile * ipmmu-vmsa * irq-renesas-irqc * m25p80 * mach-shmobile * pci-rcar-gen2 * pcie-rcar * phy-micrel * ravb * rcar-can * rcar-dmac * rcar-du * rcar-snd * rcar-thermal * rcar-vin * renesas-sdhi * renesas-soc-id * sata-rcar * sh-drivers * sh-eth * sh-flctl * sh-mmcif * sh-mobile-ceu-camera * sh-msiof * sh-pfc * sh-sci * smsc911x * sysc * usb3-peri * usbhs * vsp1 * watchdog * xhci-plat * xhci-rcar This is intended as a dry-run for backporting components used by Renesas SoCs from v4.15, v4.16, v4.17 and beyond to v4.14. In posting this work I am not implying anything about decisions on the base of the LTSI release will be. There are 362 patches. This is based on similar backports of components to their standard as of v4.15, posted as "[GIT/RFC PULL LTSI-4.14] Renesas SoCs and Drivers to v4.15" and tagged as backport/v4.14.48/snapshot-to-v4.15-flattened. As this work is for informational purposes I do not expect these patches to be imported to quilt by Greg at this time. However, if you would like to do so and rebasing would help please feel free to ask me to do so. The following changes since commit 8f9df27e572ed5aec5e75ae3b81674649b9c0168: arm64: renesas: Add Renesas R8A77970 Kconfig support (2018-06-14 10:19:53 +0200) are available in the git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-backport.git tags/backport/v4.14.48/snapshot-to-v4.16-flattened for you to fetch changes up to 6485613bce7106b963ce9a9dd8b6d434c26b1bfd: tty: serial: sh-sci: Add default for number of ports for compile-testing (2018-06-14 10:31:17 +0200) LTSI-v4.14 Preparation for Renesas SoCs (to v4.16) Base: * v4.14.48 * Similar backport of components for Renesas SoCs to v4.15 Backports of the following components to their standard as of v4.16: * at24 * cpg * dw-hdmi * gen3 * gpio-rcar * i2c-rcar * i2c-sh-mobile * ipmmu-vmsa * irq-renesas-irqc * m25p80 * mach-shmobile * pci-rcar-gen2 * pcie-rcar * phy-micrel * ravb * rcar-can * rcar-dmac * rcar-du * rcar-snd * rcar-thermal * rcar-vin * renesas-sdhi * renesas-soc-id * sata-rcar * sh-drivers * sh-eth * sh-flctl * sh-mmcif * sh-mobile-ceu-camera * sh-msiof * sh-pfc * sh-sci * smsc911x * sysc * usb3-peri * usbhs * vsp1 * watchdog * xhci-plat * xhci-rcar ABE Hiroshige (1): clk: renesas: r8a7796: Add FDP clock Adam Wallis (1): usb: xhci: allow imod-interval to be configurable Alex Elder (3): arm64: defconfig: remove CONFIG_USB_EHCI_MSM arm64: defconfig: remove CONFIG_USB_MSM_OTG arm64: defconfig: remove CONFIG_USB_QCOM_8X16_PHY Amit Kucheria (1): arm64: defconfig: enable new trigger modes for leds Arnd Bergmann (1): mmc: tmio: hide unused tmio_mmc_clk_disable/tmio_mmc_clk_enable functions Bartosz Golaszewski (4): dt-bindings: at24: new optional property - wp-gpios dt-bindings: at24: consistently document the compatible property dt-bindings: at24: fix formatting and style dt-bindings: at24: extend the list of supported chips Biju Das (31): ARM: dts: r8a7745: Add HS-USB device node ARM: dts: r8a7745: Add USB-DMAC device nodes ARM: dts: r8a7745: Enable DMA for HSUSB ARM: dts: iwg22d-sodimm: Enable HS-USB ARM: dts: r8a7743: Add default PCIe bus clock ARM: dts: r8a7743: Add PCIe Controller device node ARM: dts: iwg20d-q7: Enable PCIe Controller ARM: shmobile: defconfig: Enable SGTL5000 audio codec ARM: dts: r8a7743: Add audio clocks ARM: dts: r8a7743: Add audio DMAC support ARM: dts: r8a7743: Add sound support ARM: dts: r8a7743: Add thermal device to DT ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec ARM: dts: iwg20d-q7-common: Sound PIO support ARM: dts: iwg20d-q7-common: Sound DMA support on DTS ARM: dts: iwg20d-q7-common: Sound DMA support via BUSIF on DTS ARM: dts: iwg20d-q7-common: Sound DMA support via SRC on DTS ARM: dts: iwg20d-q7-common: Sound DMA support via DVC on DTS ARM: dts: r8a7745: Add audio clocks ARM: dts: r8a7745: Add audio DMAC support ARM: dts: r8a7745: Add sound support ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio codec ARM: dts: iwg22d-sodimm: Sound PIO support ARM: dts: iwg22d-sodimm: Sound DMA support on DTS ARM: dts: iwg22d-sodimm: Sound DMA support via BUSIF on DTS ARM: dts: iwg22d-sodimm: Sound DMA support via SRC on DTS ARM: dts: iwg22d-sodimm: Sound DMA support via DVC on DTS ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core dt-bindings: thermal: rcar: Add device tree support
Re: [PATCH v2 2/2] arm64: dts: renesas: r8a7796 add missing SPDX identifier
On Thu, Jun 14, 2018 at 09:29:33AM +0200, Simon Horman wrote: > On Thu, Jun 14, 2018 at 10:56:07AM +0900, Wolfram Sang wrote: > > Due to a merge conflict, this got accidently dropped. Add it again. > > > > Signed-off-by: Wolfram Sang > > --- > > arch/arm64/boot/dts/renesas/r8a7796.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > > b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > > index 50a8475fa837..af8196281b06 100644 > > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > > @@ -1,3 +1,4 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > /* > > * Device Tree Source for the r8a7796 SoC > > * > > Thanks, I squashed this into the patch that I messed up. > The result is as follows. Looks good to me, thanks Simon! signature.asc Description: PGP signature
Re: [PATCH 3/3] ARM: shmobile: convert to SPDX identifier
On Thu, Jun 14, 2018 at 10:43:48AM +0900, Wolfram Sang wrote: > > > This does not apply cleanly on top of renesas-devel-20180608-v4.17. > > > > Please rebase. > > Sorry, seems I missed an update to renesas/devel :( Will rebase and > resend. Thanks Wolfram, much appreciated.
Re: [PATCH v2 1/2] ARM: shmobile: convert to SPDX identifier
On Thu, Jun 14, 2018 at 10:56:06AM +0900, Wolfram Sang wrote: > Signed-off-by: Wolfram Sang > Acked-by: Yoshihiro Shimoda > Acked-by: Kuninori Morimoto Thanks Wolfram, applied.
Re: [PATCH 1/3] arm64: dts: renesas: convert to SPDX identifiers
On Thu, Jun 14, 2018 at 10:42:30AM +0900, Wolfram Sang wrote: > Hi Simon, > > > I applied this by hand, resolving the conflict in r8a7796.dtsi. > > Thanks for doing this Simon. > > > The result is below. Wolfram, please check it. > > I am afraid there is something missing, though... > > > arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts| 5 + > > arch/arm64/boot/dts/renesas/r8a7796.dtsi | 4 > > arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 5 + > > See the broken pattern in the diffstat? > > > diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > > b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > > index 2a04635bc9ae..03319d008ba1 100644 > > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > > @@ -2,10 +2,6 @@ > > * Device Tree Source for the r8a7796 SoC > > * > > * Copyright (C) 2016-2017 Renesas Electronics Corp. > > - * > > - * This file is licensed under the terms of the GNU General Public License > > - * version 2. This program is licensed "as is" without any warranty of any > > - * kind, whether express or implied. > > */ > > The actual SPDX identifier like this > > > +// SPDX-License-Identifier: GPL-2.0 > > got accidently dropped. Thanks, should be fixed the next time I push.
Re: [PATCH v2 2/2] arm64: dts: renesas: r8a7796 add missing SPDX identifier
On Thu, Jun 14, 2018 at 10:56:07AM +0900, Wolfram Sang wrote: > Due to a merge conflict, this got accidently dropped. Add it again. > > Signed-off-by: Wolfram Sang > --- > arch/arm64/boot/dts/renesas/r8a7796.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > index 50a8475fa837..af8196281b06 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > @@ -1,3 +1,4 @@ > +// SPDX-License-Identifier: GPL-2.0 > /* > * Device Tree Source for the r8a7796 SoC > * Thanks, I squashed this into the patch that I messed up. The result is as follows. From: Wolfram Sang Subject: [PATCH] arm64: dts: renesas: convert to SPDX identifiers Signed-off-by: Wolfram Sang Acked-by: Yoshihiro Shimoda Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 5 + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts| 5 + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 + arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts | 5 + arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 5 + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 5 + arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts| 5 + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 + arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 5 + arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 5 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 5 + arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 5 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 5 + arch/arm64/boot/dts/renesas/salvator-common.dtsi | 5 + arch/arm64/boot/dts/renesas/salvator-x.dtsi| 5 + arch/arm64/boot/dts/renesas/salvator-xs.dtsi | 5 + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 5 + arch/arm64/boot/dts/renesas/ulcb.dtsi | 5 + 24 files changed, 24 insertions(+), 96 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts index 009cb1cb0dde..2f24dfc45617 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the H3ULCB Kingfisher board * * Copyright (C) 2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7795-es1-h3ulcb.dts" diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts index dd4f9b6a4254..598b98168559 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts index 3f46345a4644..6b5fa91f1d5d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x * * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index e19dcd6cb767..fde3e84626d7 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source
Re: [PATCH v3 2/2] arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support
On Wed, Jun 13, 2018 at 11:12:40PM +0300, Sergei Shtylyov wrote:
> Define the Condor/V3HSK board dependent parts of the DU and LVDS device
> nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
> Analog Devices ADV7511W HDMI transmitter...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov
> Signed-off-by: Sergei Shtylyov
>
> ---
> Changes in version 2:
> - added the V3HSK DT update, reworded the description, renamed the patch;
> - added a space between the HDMI node name and a brace.
>
> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 106 +
> arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 120
>
Laurent, could you review this?
> 2 files changed, 226 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> ===
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -45,6 +45,56 @@
> regulator-boot-on;
> regulator-always-on;
> };
> +
> + d1_8v: regulator-2 {
> + compatible = "regulator-fixed";
> + regulator-name = "D1.8V";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + hdmi-out {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> + };
> +
> + lvds-decoder {
> + compatible = "thine,thc63lvd1024";
> + vcc-supply = <_3v>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + thc63lvd1024_in: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + thc63lvd1024_out: endpoint {
> + remote-endpoint = <_in>;
> + };
> + };
> + };
> + };
> +
> + x1_clk: x1-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <14850>;
> + };
> };
>
> {
> @@ -74,6 +124,13 @@
> };
> };
>
> + {
> + clocks = < CPG_MOD 724>,
> + <_clk>;
> + clock-names = "du.0", "dclkin.0";
> + status = "okay";
> +};
> +
> _clk {
> clock-frequency = <1666>;
> };
> @@ -102,6 +159,55 @@
> gpio-controller;
> #gpio-cells = <2>;
> };
> +
> + hdmi@39 {
> + compatible = "adi,adv7511w";
> + reg = <0x39>;
> + interrupt-parent = <>;
> + interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
> + avdd-supply = <_8v>;
> + dvdd-supply = <_8v>;
> + pvdd-supply = <_8v>;
> + bgvdd-supply = <_8v>;
> + dvdd-3v-supply = <_3v>;
> +
> + adi,input-depth = <8>;
> + adi,input-colorspace = "rgb";
> + adi,input-clock = "1x";
> + adi,input-style = <1>;
> + adi,input-justification = "evenly";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + adv7511_in: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + adv7511_out: endpoint {
> + remote-endpoint = <_con>;
> + };
> + };
> + };
> + };
> +};
> +
> + {
> + status = "okay";
> +
> + ports {
> + port@1 {
> + lvds0_out: endpoint {
> + remote-endpoint = <_in>;
> + };
> + };
> + };
> };
>
> {
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
> ===
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
> @@ -27,6 +27,63 @@
> /* first 128MB is reserved for secure area. */
> reg =
Re: [PATCH v3 1/2] arm64: dts: renesas: r8a77980: add FCPVD/VSPD/DU/LVDS support
On Wed, Jun 13, 2018 at 11:11:27PM +0300, Sergei Shtylyov wrote: > Describe the interconnected FCPVD0, VSPD0, DU, and LVDS0 devices in the > R8A77980 device tree... > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov > Signed-off-by: Sergei Shtylyov > Reviewed-by: Laurent Pinchart > > --- > Changes in version 3: > - merged in the VSPD/DU/LVDS patches, renamed the patch, and updated the patch > description accordingly; > - fixed the VSPD0's "reg" property. Thanks Sergei, applied.
Re: [PATCH v2] arm64: dts: renesas: condor/v3hsk: specify Ethernet PHY IRQs
On Wed, Jun 13, 2018 at 07:44:02PM +0300, Sergei Shtylyov wrote: > On 06/13/2018 07:42 PM, Sergei Shtylyov wrote: > > > Specify Ethernet PHY IRQs in the Condor/V3HSK board device trees, now that > > we have the GPIO support (previously phylib had to resort to polling). > > > > Based on the original (and large) patch by Vladimir Barinov. > > > > Signed-off-by: Vladimir Barinov > > Signed-off-by: Sergei Shtylyov > > > > --- > >Forgot to add the the patch is against the 'renesas-devel-20180613-v4.17' > tag. > Thanks Sergei, applied.
