[PATCH] spi: sh-msiof: fix deferred probing
Since commit 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq")
platform_get_irq() can return -EPROBE_DEFER. However, the driver overrides
an error returned by that function with -ENOENT which breaks the deferred
probing. Propagate upstream an error code returned by platform_get_irq()
and remove the bogus "platform" from the error message, while at it...
Fixes: 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq")
Signed-off-by: Sergei Shtylyov
---
The patch is against the 'for-linus' branch of Mark Brown's 'spi.git' repo.
drivers/spi/spi-sh-msiof.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: spi/drivers/spi/spi-sh-msiof.c
===
--- spi.orig/drivers/spi/spi-sh-msiof.c
+++ spi/drivers/spi/spi-sh-msiof.c
@@ -1343,8 +1343,8 @@ static int sh_msiof_spi_probe(struct pla
i = platform_get_irq(pdev, 0);
if (i < 0) {
- dev_err(>dev, "cannot get platform IRQ\n");
- ret = -ENOENT;
+ dev_err(>dev, "cannot get IRQ\n");
+ ret = i;
goto err1;
}
Re: [PATCH] dt-bindings: PCI: rcar: Add device tree support for r8a7744
On Mon, Oct 08, 2018 at 09:34:45AM +0200, Simon Horman wrote: > On Thu, Oct 04, 2018 at 05:07:47PM +0100, Biju Das wrote: > > Add support for r8a7744. The Renesas RZ/G1N (R8A7744) PCIe controller > > is identical to the R-Car Gen2 family. > > > > Signed-off-by: Biju Das > > Reviewed-by: Chris Paterson > > Reviewed-by: Simon Horman Simon, Biju, I pulled the same binding for rcar2, I would pull this in the PCI tree too unless you object, please let me know. Thanks, Lorenzo
[PATCH/RFC/WIP] serial: sh-sci: Fixes for DMA fallback to PIO
Fallback to PIO never really worked due to various reasons (sh-sci
driver issues and dmaengine framework limitations).
There are three places where DMA submission can fall, and the driver
should fall back to PIO:
1. sci_submit_rx(),
2. sci_dma_rx_complete(),
3. work_fn_tx().
This RFC fixes some of them. Unfortunatey not all, but I didn't want to
withhold this from you for the weekend ;-)
A. Some callers of sci_submit_rx() hold the port spinlock, others
don't. When submission of receive DMA requests fails, the driver
will fall back to PIO, and obtain the port spinlock. If the lock
was already held, spinlock recursion is detected, causing a
deadlock: BUG: spinlock recursion on CPU#0.
Fix this by adding a flag parameter to sci_submit_rx() for the
caller to indicate the port spinlock is already held, so spinlock
recursion can be avoided.
Move the spin_lock_irqsave() up, so all DMA disable steps are
protected, which is safe as the recently introduced
dmaengine_terminate_async() can be called in atomic context.
After this, PIO fallback in sci_submit_rx() works on SCIFA (and
presumably SCIFB, which is very similar w.r.t. DMA).
B. When falling back to PIO, active_rx must be set to a different
value than cookie_rx[i], else sci_dma_rx_find_active() will
incorrectly find a match, leading to a NULL pointer dereference in
rx_timer_fn() later.
C. On (H)SCIF, sci_submit_rx() is called in the receive interrupt
handler. Hence if DMA submission fails, the interrupt handler
should handle reception using PIO.
After this, PIO fallback in sci_submit_rx() works on SCIF (and
presumably HSCIF, which is very similar w.r.t. DMA).
D. When falling back to PIO in sci_dma_rx_complete(), the cookies must
be invalidated, else rx_timer_fn() will trigger a NULL pointer
dereference.
Note that this change is not sufficient to make PIO fallback in
sci_dma_rx_complete() work: serial input is still dead.
To do:
- Fix case 2,
- Try case 3, and fix it, if needed.
All testing was done on r8a7791/koelsch using SCIF1 on debug serial 1,
and SCIFA3 on EXIO-B, by introducing random failures in DMA submission
code.
Not-Yet-Signed-off-by: Geert Uytterhoeven
---
Against tty/next + "serial: sh-sci: Fix receive on SCIFA/SCIFB variants
with DMA".
drivers/tty/serial/sh-sci.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 3aad48e64b9b71ff..9dc4309a600c9806 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1272,6 +1272,7 @@ static void sci_dma_rx_complete(void *arg)
struct dma_async_tx_descriptor *desc;
unsigned long flags;
int active, count = 0;
+ unsigned int i;
dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
s->active_rx);
@@ -1313,6 +1314,9 @@ static void sci_dma_rx_complete(void *arg)
dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
/* Switch to PIO */
spin_lock_irqsave(>lock, flags);
+ for (i = 0; i < 2; i++)
+ s->cookie_rx[i] = -EINVAL;
+ s->active_rx = 0;
s->chan_rx = NULL;
sci_start_rx(port);
spin_unlock_irqrestore(>lock, flags);
@@ -1331,7 +1335,7 @@ static void sci_tx_dma_release(struct sci_port *s)
dma_release_channel(chan);
}
-static void sci_submit_rx(struct sci_port *s)
+static int sci_submit_rx(struct sci_port *s, bool port_lock_held)
{
struct dma_chan *chan = s->chan_rx;
struct uart_port *port = >port;
@@ -1359,19 +1363,22 @@ static void sci_submit_rx(struct sci_port *s)
s->active_rx = s->cookie_rx[0];
dma_async_issue_pending(chan);
- return;
+ return 0;
fail:
+ if (!port_lock_held)
+ spin_lock_irqsave(>lock, flags);
if (i)
dmaengine_terminate_async(chan);
for (i = 0; i < 2; i++)
s->cookie_rx[i] = -EINVAL;
- s->active_rx = -EINVAL;
+ s->active_rx = 0;
/* Switch to PIO */
- spin_lock_irqsave(>lock, flags);
s->chan_rx = NULL;
sci_start_rx(port);
- spin_unlock_irqrestore(>lock, flags);
+ if (!port_lock_held)
+ spin_unlock_irqrestore(>lock, flags);
+ return -1;
}
static void work_fn_tx(struct work_struct *work)
@@ -1491,7 +1498,7 @@ static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
}
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
- sci_submit_rx(s);
+ sci_submit_rx(s, true);
/* Direct new serial port interrupts back to CPU */
scr = serial_port_in(port, SCSCR);
@@ -1617,7 +1624,7 @@ static void sci_request_dma(struct uart_port *port)
s->chan_rx_saved = s->chan_rx = chan;
if (port->type == PORT_SCIFA ||
Re: [PATCH v3 1/6] dt-bindings: mmc: renesas_sdhi: Add r8a77470 support
On Mon, 8 Oct 2018 09:51:47 +0100, Fabrizio Castro wrote: > The RZ/G1C (a.k.a. R8A77470) comes with three SDHI interfaces, > SDHI0 and SDHI2 are compatible with R-Car Gen2 SDHIs, and > SDHI1 is compatible with R-Car Gen3 SDHIs, as it comes with an > internal DMAC, therefore SDHI1 is fully compatible with driver > renesas_sdhi_internal_dmac driver. As a result, the compatible > strings for the R8A77470 SDHI interfaces are a little bit special. > Document SDHI support for the RZ/G1C SoC. > > Signed-off-by: Fabrizio Castro > Reviewed-by: Biju Das > Reviewed-by: Geert Uytterhoeven > > --- > v2->v3: > * Incorporated comments from Geert > > v1->v2: > * Added "renesas,sdhi-mmc-r8a77470" > * Using generic/fallback compatibilty only for SDHI[02] > * Reworked changelog > --- > Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring
Re: [PATCH v4 3/3] dt-bindings: mmc: tmio_mmc: Document Renesas R7S9210
On Fri, 12 Oct 2018 07:29:24 -0500, Chris Brandt wrote: > Document support for the RZ/A2 (R7S9210) SoC. > > Signed-off-by: Chris Brandt > Reviewed-by: Geert Uytterhoeven > --- > v2: > * Documented that R7S9210 has 2 clocks > --- > Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring
Re: [PATCH v2] arm64: dts: renesas: r8a77970: add thermal support
On 10/12/2018 02:21 PM, Simon Horman wrote: >>> Describe THS/CIVM in the R8A77970 device tree. >>> >>> Based on the original (and large) patches by Vladimir Barinov. >>> >>> Signed-off-by: Vladimir Barinov >>> Signed-off-by: Sergei Shtylyov >>> >>> --- >>> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon >>> Horman's 'renesas.git' repo. >>> >>> Changed in version 2: >>> - fix the "reg" prop in the thermal device node; >>> - fixed wrong plural in the patch description. >> >> Reviewed-by: Geert Uytterhoeven > > Thanks, applied for v4.21. Not seeing any updates -- forgot to push? MBR, Sergei
[PATCH] serial: sh-sci: do not warn if DMA transfers are not supported
Not all (H)SCIF devices support DMA, and failure to set it up is not
normally a cause for concern. This patch demotes the associated warning to
debug output.
Inspired by BSP patch "sci: sh-sci: Fix transfer sequence of unsupport DMA
transfer" (6beb1f98d3bd30) by Hiromitsu Yamasaki.
Signed-off-by: Ulrich Hecht
---
drivers/tty/serial/sh-sci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 426241d..ff6ba6d 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1516,7 +1516,7 @@ static struct dma_chan *sci_request_dma_chan(struct
uart_port *port,
chan = dma_request_slave_channel(port->dev,
dir == DMA_MEM_TO_DEV ? "tx" : "rx");
if (!chan) {
- dev_warn(port->dev, "dma_request_slave_channel failed\n");
+ dev_dbg(port->dev, "dma_request_slave_channel failed\n");
return NULL;
}
--
2.7.4
[PATCH v4 3/3] dt-bindings: mmc: tmio_mmc: Document Renesas R7S9210
Document support for the RZ/A2 (R7S9210) SoC. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v2: * Documented that R7S9210 has 2 clocks --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index d39d5e46f7d2..cdfbcce34b97 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -13,6 +13,7 @@ Required properties: - compatible: should contain one or more of the following: "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC + "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC @@ -54,7 +55,7 @@ Required properties: "core" and "cd". If the controller only has 1 clock, naming is not required. Devices which have more than 1 clock are listed below: - 2: R7S72100 + 2: R7S72100, R7S9210 Optional properties: - pinctrl-names: should be "default", "state_uhs" -- 2.16.1
[PATCH v4 2/3] mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but
with some minor differences.
Signed-off-by: Chris Brandt
---
v4:
* Fixed spelling in #define
v3:
* Removed extra space in Kconfig
* Removed unneeded parentheses
v2:
* Made comment clearer
---
drivers/mmc/host/Kconfig | 5 +++--
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 28 +--
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index cf984f0f0246..b69d5cd45d0f 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -636,13 +636,14 @@ config MMC_SDHI_SYS_DMAC
config MMC_SDHI_INTERNAL_DMAC
tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
- depends on ARM64 || COMPILE_TEST
+ depends on ARM64 || ARCH_R7S9210 || COMPILE_TEST
depends on MMC_SDHI
default MMC_SDHI if ARM64
help
This provides DMA support for SDHI SD/SDIO controllers
using on-chip bus mastering. This supports the controllers
- found in arm64 based SoCs.
+ found in arm64 based SoCs. This controller is also found in
+ RZ/A2 series SoCs.
config MMC_UNIPHIER
tristate "UniPhier SD/eMMC Host Controller support"
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index e5e5015ca680..065dc527291c 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -34,7 +34,7 @@
#define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
#define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */
#define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4))
-#define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */
+#define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */
/* DM_CM_DTRAN_CTRL */
#define DTRAN_CTRL_DM_STARTBIT(0)
@@ -73,6 +73,9 @@ static unsigned long global_flags;
#define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0
#define SDHI_INTERNAL_DMAC_RX_IN_USE 1
+/* RZ/A2 does not have the ADRR_MODE bit */
+#define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2
+
/* Definitions for sampling clocks */
static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
{
@@ -81,6 +84,21 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
},
};
+static const struct renesas_sdhi_of_data of_rza2_compatible = {
+ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
+ TMIO_MMC_HAVE_CBSY,
+ .tmio_ocr_mask = MMC_VDD_32_33,
+ .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ MMC_CAP_CMD23,
+ .bus_shift = 2,
+ .scc_offset = 0 - 0x1000,
+ .taps = rcar_gen3_scc_taps,
+ .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
+ /* DMAC can handle 0x blk count but only 1 segment */
+ .max_blk_count = 0x,
+ .max_segs = 1,
+};
+
static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
@@ -113,6 +131,7 @@ static const struct renesas_sdhi_of_data
of_rcar_gen3_compatible = {
};
static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
+ { .compatible = "renesas,sdhi-r7s9210", .data = _rza2_compatible, },
{ .compatible = "renesas,sdhi-r8a7795", .data =
_rcar_r8a7795_compatible, },
{ .compatible = "renesas,sdhi-r8a7796", .data =
_rcar_r8a7795_compatible, },
{ .compatible = "renesas,rcar-gen3-sdhi", .data =
_rcar_gen3_compatible, },
@@ -171,7 +190,10 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host
*host,
struct mmc_data *data)
{
struct scatterlist *sg = host->sg_ptr;
- u32 dtran_mode = DTRAN_MODE_BUS_WIDTH | DTRAN_MODE_ADDR_MODE;
+ u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
+
+ if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, _flags))
+ dtran_mode |= DTRAN_MODE_ADDR_MODE;
if (!dma_map_sg(>pdev->dev, sg, host->sg_len,
mmc_get_dma_dir(data)))
@@ -290,6 +312,8 @@ static const struct tmio_mmc_dma_ops
renesas_sdhi_internal_dmac_dma_ops = {
*/
static const struct soc_device_attribute gen3_soc_whitelist[] = {
/* specific ones */
+ { .soc_id = "r7s9210",
+ .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) },
{ .soc_id = "r8a7795", .revision = "ES1.*",
.data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
{ .soc_id = "r8a7796", .revision = "ES1.0",
--
2.16.1
[PATCH v4 0/3] mmc: tmio_mmc: Add support for RZ/A2
Basically the same HW block that was used in R-Car Gen 3 is used in RZ/A2 (with only a couple small differences). Not sure if you're going to like the Kconfig change or not. Chris Brandt (3): clk: renesas: r7s9210: Add SDHI clocks mmc: renesas_sdhi_internal_dmac: Add R7S9210 support dt-bindings: mmc: tmio_mmc: Document Renesas R7S9210 Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 3 ++- drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 drivers/mmc/host/Kconfig | 5 ++-- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 28 -- 4 files changed, 36 insertions(+), 5 deletions(-) -- 2.16.1
[PATCH v4 1/3] clk: renesas: r7s9210: Add SDHI clocks
Add SDHI clocks for RZ/A2
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 5135f13ec628..9056da15dc72 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -98,6 +98,11 @@ static const struct mssr_mod_clk r7s9210_mod_clks[]
__initconst = {
DEF_MOD_STB("spi2", 95,R7S9210_CLK_P1),
DEF_MOD_STB("spi1", 96,R7S9210_CLK_P1),
DEF_MOD_STB("spi0", 97,R7S9210_CLK_P1),
+
+ DEF_MOD_STB("sdhi11", 100,R7S9210_CLK_B),
+ DEF_MOD_STB("sdhi10", 101,R7S9210_CLK_B),
+ DEF_MOD_STB("sdhi01", 102,R7S9210_CLK_B),
+ DEF_MOD_STB("sdhi00", 103,R7S9210_CLK_B),
};
/* The clock dividers in the table vary based on DT and register settings */
--
2.16.1
Re: [PATCH v3 2/3] mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
> Even after you pointed that out...I had to stare real hard to see it. I
> guess the brain corrects what you see.
Yes. c57d3e7a9391 ("i2c-dev: Fix typo in ioctl name reference") fixed
something in 2015 which was around forever. I had to look twice at this
patch as well.
> I was getting information through someone that was not in the design
> team. So to be fair to the chip design guys, I want to avoid the word
> "broken". They took the bit out of the hardware manual, and since the
> HW was designed to work either way (and the default register setting
> is for fixed), I consider it an 'unsupported feature'.
>
> So, how about a compromise of:
>
> #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2
Perfect. Now we nailed it, I think.
> I don't think this applies to Gen3. This is just a RZ/A2 thing.
OK. Thanks for the heads up!
signature.asc
Description: PGP signature
RE: [PATCH v3 2/3] mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
Hi Wolfram, On Friday, October 12, 2018, Wolfram Sang wrote: > > +/* RZ/A2 does not have the ADRR_MODE bit */ > > +#define SDHI_INTERNAL_DMAC_ADRR_MODE_FIXED 2 > > First, there is a typo: s/ADRR/ADDR/g Thanks! Even after you pointed that out...I had to stare real hard to see it. I guess the brain corrects what you see. > Also, I think it would make the code much more comprehensible if this > macro was named SDHI_INTERNAL_DMAC_ADDR_MODE_BROKEN. Or maybe > SDHI_INTERNAL_DMAC_FIXED_ADDR_MODE_BROKEN. Currently, on first read I > thought this mode was fixed on this SoC and broken on all the others and > was confused. To be honest, I was not able to fully understand the issue in detail. I was getting information through someone that was not in the design team. So to be fair to the chip design guys, I want to avoid the word "broken". They took the bit out of the hardware manual, and since the HW was designed to work either way (and the default register setting is for fixed), I consider it an 'unsupported feature'. So, how about a compromise of: #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2 >From your other email: > > As you can imagine, it does have this bit. And it worked fine from me. > > But the chip guys said they found something not right with it, so they > > removed it from the v1.0 Hardware Manual. > > Do you happen to know if this applies for Gen3 SDHI as well? I don't think this applies to Gen3. This is just a RZ/A2 thing. With that said, there are some Gen3 HW bugs that are in RZ/A2 HW, like the QSPI read bug. Since the RZ/A2 has the exact same HW as Gen3, it has the same HW bug. Now that one is a "bug", and I don't mind calling that one broken. Chris
Re: [PATCH] dt-bindings: pwm: renesas-tpu: Document r8a7744 support
On Thu, Oct 04, 2018 at 05:21:34PM +0100, Biju Das wrote: > Document r8a7744 specific compatible strings. No driver change is > needed as the fallback compatible string "renesas,tpu" activates the > right code in the driver. > > Signed-off-by: Biju Das > Reviewed-by: Chris Paterson > --- > This patch is tested against next-20181004 > --- > Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt | 1 + > 1 file changed, 1 insertion(+) Applied, thanks. Thierry signature.asc Description: PGP signature
Re: [PATCH] dt-bindings: pwm: rcar: Add r8a7744 support
On Thu, Oct 04, 2018 at 05:17:19PM +0100, Biju Das wrote: > Document RZ/G1N (R8A7744) SoC bindings. > > Signed-off-by: Biju Das > Reviewed-by: Chris Paterson > --- > This patch is tested against next-20181004 > --- > Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 + > 1 file changed, 1 insertion(+) Applied, thanks. Thierry signature.asc Description: PGP signature
Re: [PATCH v2] arm64: dts: renesas: r8a77980: add thermal support
On Thu, Oct 11, 2018 at 09:30:02AM +0200, Niklas Söderlund wrote:
> Hi Geert,
>
> On 2018-10-11 09:02:22 +0200, Geert Uytterhoeven wrote:
> > Hi Niklas,
> >
> > On Thu, Oct 11, 2018 at 12:11 AM Niklas Söderlund
> > wrote:
> > > On 2018-10-10 22:18:11 +0300, Sergei Shtylyov wrote:
> > > > Describe THS/CIVM in the R8A77980 device trees.
> > > >
> > > > Signed-off-by: Sergei Shtylyov
> >
> > > > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > > > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > > > @@ -330,6 +330,19 @@
> > > > #power-domain-cells = <1>;
> > > > };
> > > >
> > > > + tsc: thermal@e6198000 {
> > > > + compatible = "renesas,r8a77980-thermal";
> > > > + reg = <0 0xe6198000 0 0x100>,
> > > > + <0 0xe61a 0 0x100>;
> > > > + interrupts = ,
> > > > + ,
> > > > + ;
> > > > + clocks = < CPG_MOD 522>;
> > > > + power-domains = < R8A77980_PD_ALWAYS_ON>;
> > > > + resets = < 522>;
> > > > + #thermal-sensor-cells = <1>;
> > >
> > > The status property is missing but as you told me in v1 it should not
> > > matter. I will leave it for Simon to decide if he wants it to keep it
> > > consistent with other SoC or if we should remove it from the other dtsi
> > > files. In any case with or without the status property.
> >
> > Forgot to review commit c79661eb5060e2bf ("arm64: dts: renesas: Remove
> > unneeded status from thermal nodes")? ;-)
>
> Not only that also reviewing using the context from v4.19-rc1 which of
> course is not correct for dtsi patches, thanks for enlightening me :-)
Thanks everyone, applied or v4.21.
Re: [PATCH] dt-bindings: pwm: renesas: pwm-rcar: document R8A779{7|8}0 bindings
On Mon, Oct 01, 2018 at 10:57:39PM +0300, Sergei Shtylyov wrote:
> Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas R-Car PWM
> bindings. R8A77970's hardware is a generic R-Car gen3 PWM, while R8A77980
> has an extra error injection register...
>
> Signed-off-by: Sergei Shtylyov
>
> ---
> This patch is against the 'for-next' branch of Thierry Reding's
> 'linux-pwm.git'
> repo.
>
> Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt |2 ++
> 1 file changed, 2 insertions(+)
Applied, thanks.
Thierry
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Re: [PATCH v2] arm64: dts: renesas: r8a77970: add thermal support
On Wed, Oct 10, 2018 at 09:12:54AM +0200, Geert Uytterhoeven wrote: > On Tue, Oct 9, 2018 at 9:50 PM Sergei Shtylyov > wrote: > > Describe THS/CIVM in the R8A77970 device tree. > > > > Based on the original (and large) patches by Vladimir Barinov. > > > > Signed-off-by: Vladimir Barinov > > Signed-off-by: Sergei Shtylyov > > > > --- > > This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon > > Horman's 'renesas.git' repo. > > > > Changed in version 2: > > - fix the "reg" prop in the thermal device node; > > - fixed wrong plural in the patch description. > > Reviewed-by: Geert Uytterhoeven Thanks, applied for v4.21.
Re: [PATCH] dt-bindings: pwm: renesas: tpu: document R8A779{7|8}0 bindings
On Sat, Sep 22, 2018 at 10:57:29PM +0300, Sergei Shtylyov wrote:
> Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas TPU bindings;
> the TPU hardware in those is the Renesas standard 4-channel timer pulse
> unit.
>
> Signed-off-by: Sergei Shtylyov
>
> ---
> This patch is against Linus' repo plus the bindings fix just reposted...
>
> Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt |4
> 1 file changed, 4 insertions(+)
Applied, thanks.
Thierry
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Re: [PATCH] arm64: dts: renesas: r8a77990: Add DMA properties to MSIOF nodes
On Wed, Oct 10, 2018 at 02:39:18PM +0200, Geert Uytterhoeven wrote: > On Tue, Oct 9, 2018 at 9:39 AM Yoshihiro Kaneko wrote: > > This patch adds DMA properties to the MSIOF device nodes of R8A77990 SoC. > > > > Signed-off-by: Yoshihiro Kaneko > > Reviewed-by: Geert Uytterhoeven > Tested-by: Geert Uytterhoeven > on Ebisu using a 25LC040 EEPROM > https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/tree/arch/arm64/boot/dts/renesas/r8a77990-ebisu-cn41-msiof0-25lc040.dtso?h=topic/renesas-overlays Thanks, applied for v4.21.
Re: [PATCH v2] dt-bindings: pwm: renesas: tpu: fix "compatible" prop description
On Sat, Sep 22, 2018 at 10:43:24PM +0300, Sergei Shtylyov wrote:
> The "compatible" property description contradicts even the example given:
> it only says that there must be a single value while the example has the
> fallback value too -- which makes much more sense. Moreover, the generic
> property value is misdocumented as being R-Car (and RZ/G1) specific...
>
> Fixes: 382457e562bb ("pwm: renesas-tpu: Add DT support")
> Fixes: 3ba111a01822 ("dt-bindings: pwm: renesas-tpu: Document r8a774[35]
> support")
> Signed-off-by: Sergei Shtylyov
>
> ---
> This patch is against Linus' repo -- the 'fixes' branch in Thierry Reding's
> 'linux-pwm.git' repo is very outdated...
>
> Changes in version 2:
> - fixed the wording of the fallback value description.
>
> Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt |5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Applied, thanks.
Thierry
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Re: [PATCH] ARM: dts: r8a77470: Add I2C[0123] support
On Wed, Oct 10, 2018 at 11:25:30AM +0200, Geert Uytterhoeven wrote: > On Mon, Oct 8, 2018 at 11:53 AM Fabrizio Castro > wrote: > > Add device tree nodes for the I2C[0123] controllers. Also, add > > the aliases node. > > > > Signed-off-by: Fabrizio Castro > > Reviewed-by: Biju Das > > Reviewed-by: Geert Uytterhoeven Thanks, applied for v4.21.
Re: [PATCH 2/3] mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
> As you can imagine, it does have this bit. And it worked fine from me. > But the chip guys said they found something not right with it, so they > removed it from the v1.0 Hardware Manual. Do you happen to know if this applies for Gen3 SDHI as well? signature.asc Description: PGP signature
Re: [PATCH v3 2/3] mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
Hi Chris, > +/* RZ/A2 does not have the ADRR_MODE bit */ > +#define SDHI_INTERNAL_DMAC_ADRR_MODE_FIXED 2 First, there is a typo: s/ADRR/ADDR/g Also, I think it would make the code much more comprehensible if this macro was named SDHI_INTERNAL_DMAC_ADDR_MODE_BROKEN. Or maybe SDHI_INTERNAL_DMAC_FIXED_ADDR_MODE_BROKEN. Currently, on first read I thought this mode was fixed on this SoC and broken on all the others and was confused. What do you think? Rest looks okay to me! Regards, Wolfram signature.asc Description: PGP signature
Re: [PATCH resend] pwm: renesas-tpu: convert to SPDX identifiers
On Wed, Sep 26, 2018 at 01:45:47AM +, Kuninori Morimoto wrote: > > From: Kuninori Morimoto > > This patch updates license to use SPDX-License-Identifier > instead of verbose license text. > > Signed-off-by: Kuninori Morimoto > Reviewed-by: Simon Horman > --- > Thierry > > 2weeks past, resend patch > > drivers/pwm/pwm-renesas-tpu.c | 10 +- > 1 file changed, 1 insertion(+), 9 deletions(-) Applied, thanks. Thierry signature.asc Description: PGP signature
Re: [PATCH resend] pwm: rcar: convert to SPDX identifiers
On Wed, Sep 26, 2018 at 01:45:17AM +, Kuninori Morimoto wrote: > > From: Kuninori Morimoto > > This patch updates license to use SPDX-License-Identifier > instead of verbose license text. > > Signed-off-by: Kuninori Morimoto > Reviewed-by: Simon Horman > --- > Thierry > > 2weeks past, resend patch There's usually no need to resend a patch, just ping me on the original. Applied, thanks. Thierry signature.asc Description: PGP signature
[PATCH] pinctrl: rzn1: Fix check for used MDIO bus
This fixes the check for unused mdio bus setting and the following static
checker warning:
drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select()
warn: always true condition '(ipctl->mdio_func[mdio] >= 0) => (0-u32max >= 0)'
Reported-by: Dan Carpenter
Signed-off-by: Phil Edworthy
---
drivers/pinctrl/pinctrl-rzn1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rzn1.c b/drivers/pinctrl/pinctrl-rzn1.c
index ce05e3a00be2..f688f3a29dfd 100644
--- a/drivers/pinctrl/pinctrl-rzn1.c
+++ b/drivers/pinctrl/pinctrl-rzn1.c
@@ -195,7 +195,7 @@ static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8
lock, u8 value)
static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio,
u32 func)
{
- if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
+ if (ipctl->mdio_func[mdio] != -1 && ipctl->mdio_func[mdio] != func)
dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio);
ipctl->mdio_func[mdio] = func;
--
2.17.1
RE: [PATCH] arm64: dts: renesas: add/enable USB2.0 peripheral for R-Car [DE]3
Hi Shimoda-San,
Thanks for the patch.
> -Original Message-
> From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Yoshihiro Shimoda
> Sent: 09 October 2018 11:45
> To: ho...@verge.net.au; magnus.d...@gmail.com
> Cc: linux-renesas-soc@vger.kernel.org; Yoshihiro Shimoda
>
> Subject: [PATCH] arm64: dts: renesas: add/enable USB2.0 peripheral for R-
> Car [DE]3
>
> arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 8 +
> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 45
> ++
> 4 files changed, 106 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> index 7278cd5..e3726307 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -357,6 +357,51 @@
> resets = < 407>;
> };
>
> +hsusb: usb@e659 {
> +compatible = "renesas,usbhs-r8a77990",
> + "renesas,rcar-gen3-usbhs";
> +reg = <0 0xe659 0 0x100>;
is it not 0x200?
Renesas_usbhs driver("drivers/usb/renesas_usbhs/common.c ") maps the address
up to 0x100 using "devm_ioremap_resource" function
where as the "drivers/usb/renesas_usbhs/rcar3" access addresses beyond 0x100
(for eg:- 0x102,0x180,0x184,0x188) using iowrite32/16 calls.
This issue is present in other R-Car Gen3 variant as well(for eg:- R-Car
H3/M3-W,. etc).
> +interrupts = ;
> +clocks = < CPG_MOD 704>, < CPG_MOD
> 703>;
> +dmas = <_dmac0 0>, <_dmac0 1>,
> + <_dmac1 0>, <_dmac1 1>;
> +dma-names = "ch0", "ch1", "ch2", "ch3";
> +renesas,buswait = <11>;
> +phys = <_phy0>;
> +phy-names = "usb";
> +power-domains = <
> R8A77990_PD_ALWAYS_ON>;
> +resets = < 704>, < 703>;
> +status = "disabled";
> +};
> +
> +usb_dmac0: dma-controller@e65a {
> +compatible = "renesas,r8a77990-usb-dmac",
> + "renesas,usb-dmac";
> +reg = <0 0xe65a 0 0x100>;
> +interrupts = + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> +interrupt-names = "ch0", "ch1";
> +clocks = < CPG_MOD 330>;
> +power-domains = <
> R8A77990_PD_ALWAYS_ON>;
> +resets = < 330>;
> +#dma-cells = <1>;
> +dma-channels = <2>;
> +};
> +
> +usb_dmac1: dma-controller@e65b {
> +compatible = "renesas,r8a77990-usb-dmac",
> + "renesas,usb-dmac";
> +reg = <0 0xe65b 0 0x100>;
> +interrupts = + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> +interrupt-names = "ch0", "ch1";
> +clocks = < CPG_MOD 331>;
> +power-domains = <
> R8A77990_PD_ALWAYS_ON>;
> +resets = < 331>;
> +#dma-cells = <1>;
> +dma-channels = <2>;
> +};
> +
> dmac0: dma-controller@e670 {
> compatible = "renesas,dmac-r8a77990",
> "renesas,rcar-dmac";
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> index 2405eaa..48bb1d7 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> @@ -179,6 +179,7 @@
> };
>
> {
> +dr_mode = "host";
> status = "okay";
> };
>
> @@ -186,6 +187,11 @@
> clock-frequency = <4800>;
> };
>
> + {
> +dr_mode = "host";
> +status = "okay";
> +};
> +
> {
> pinctrl-0 = <_pins>;
> pinctrl-names = "default";
> @@ -337,6 +343,7 @@
> };
>
> {
> +dr_mode = "host";
> status = "okay";
> };
>
> @@ -445,6 +452,7 @@
> pinctrl-0 = <_pins>;
> pinctrl-names = "default";
>
> +renesas,no-otg-pins;
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> index 214f495..186f477 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -344,6 +344,51 @@
> status = "disabled";
> };
>
> +hsusb: usb@e659 {
> +compatible = "renesas,usbhs-r8a77995",
> + "renesas,rcar-gen3-usbhs";
> +reg = <0 0xe659 0 0x100>;
Same as above.
> +interrupts = ;
> +clocks = < CPG_MOD 704>, < CPG_MOD
> 703>;
> +dmas = <_dmac0 0>, <_dmac0 1>,
> + <_dmac1 0>, <_dmac1 1>;
> +dma-names = "ch0", "ch1", "ch2", "ch3";
> +renesas,buswait = <11>;
> +phys = <_phy0>;
> +phy-names = "usb";
> +power-domains = <
> R8A77995_PD_ALWAYS_ON>;
> +resets = < 704>, < 703>;
> +status = "disabled";
> +};
> +
> +usb_dmac0: dma-controller@e65a {
> +compatible = "renesas,r8a77995-usb-dmac",
> + "renesas,usb-dmac";
> +reg = <0 0xe65a 0 0x100>;
> +interrupts = + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> +interrupt-names = "ch0", "ch1";
> +clocks = < CPG_MOD 330>;
> +power-domains = <
> R8A77995_PD_ALWAYS_ON>;
> +resets = < 330>;
> +#dma-cells = <1>;
> +dma-channels = <2>;
> +};
> +
> +usb_dmac1: dma-controller@e65b {
> +compatible = "renesas,r8a77995-usb-dmac",
> + "renesas,usb-dmac";
> +reg = <0 0xe65b 0 0x100>;
> +interrupts = + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> +interrupt-names = "ch0", "ch1";
> +clocks = < CPG_MOD 331>;
> +power-domains = <
> R8A77995_PD_ALWAYS_ON>;
> +resets = < 331>;
> +#dma-cells = <1>;
> +dma-channels = <2>;
> +};
> +
> canfd: can@e66c {
> compatible =
