On Tue, Oct 16, 2018 at 11:33:43AM +0100, Fabrizio Castro wrote:
> Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI pins
> capable of switching voltage, also add pin groups and functions
> for SDHI0 and SDHI1. Please note that with the RZ/G1C only 1
> bit of the POC Control Register is used to control each interface.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
> Reviewed-by: Geert Uytterhoeven
>
> ---
> v3->v4:
> * Fixed voltage control of GP0_11 and GP0_12
>
> v2->v3:
> * No change
>
> v1->v2:
> * Reworked implementation of r8a77470_pin_to_pocctrl as per Wolfram's
> and Geert's comments
> * Added SDHI0 and SDHI1 pins and IO voltage control
> * Added SDHI0 and SDHI1 pin groups and functions
> * Reworked changelog and title
> * Please note that there is some overlapping between mmc pin groups
> and sdhi1 pin groups
> ---
> drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 162
> +-
> 1 file changed, 160 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
> index 5e29b95..4359aeb 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
> @@ -10,14 +10,45 @@
> #include "sh_pfc.h"
>
> #define CPU_ALL_PORT(fn, sfx)
> \
> - PORT_GP_23(0, fn, sfx), \
> + PORT_GP_4(0, fn, sfx), \
> + PORT_GP_1(0, 4, fn, sfx), \
> + PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_1(0, 11, fn, sfx), \
> + PORT_GP_1(0, 12, fn, sfx), \
> + PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> PORT_GP_23(1, fn, sfx), \
> PORT_GP_32(2, fn, sfx), \
> PORT_GP_17(3, fn, sfx), \
> PORT_GP_1(3, 27, fn, sfx), \
> PORT_GP_1(3, 28, fn, sfx), \
> PORT_GP_1(3, 29, fn, sfx), \
> - PORT_GP_26(4, fn, sfx), \
> + PORT_GP_14(4, fn, sfx), \
> + PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
> + PORT_GP_1(4, 20, fn, sfx), \
> + PORT_GP_1(4, 21, fn, sfx), \
> + PORT_GP_1(4, 22, fn, sfx), \
> + PORT_GP_1(4, 23, fn, sfx), \
> + PORT_GP_1(4, 24, fn, sfx), \
> + PORT_GP_1(4, 25, fn, sfx), \
> PORT_GP_32(5, fn, sfx)
>
> enum {
> @@ -1865,6 +1896,81 @@ static const unsigned int scif_clk_b_pins[] = {
> static const unsigned int scif_clk_b_mux[] = {
> SCIF_CLK_B_MARK,
> };
> +/* - SDHI0
> -- */
> +static const unsigned int sdhi0_data1_pins[] = {
> + /* D0 */
> + RCAR_GP_PIN(0, 7),
> +};
> +static const unsigned int sdhi0_data1_mux[] = {
> + SD0_DAT0_MARK,
> +};
> +static const unsigned int sdhi0_data4_pins[] = {
> + /* D[0:3] */
> + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
> +