Re: [PATCH v3] PCI: hosts: mark pcie/pci (msi) irq cascade handler as IRQF_NO_THREAD

[Bjorn Helgaas]

Hi Grygorii,

On Thu, Dec 10, 2015 at 09:18:20PM +0200, Grygorii Strashko wrote:
> On -RT and if kernel is booting with "threadirqs" cmd line parameter
> pcie/pci (msi) irq cascade handlers (like dra7xx_pcie_msi_irq_handler())
> will be forced threaded and, as result, will generate warnings like:
> 
> WARNING: CPU: 1 PID: 82 at kernel/irq/handle.c:150 
> handle_irq_event_percpu+0x14c/0x174()
> irq 460 handler irq_default_primary_handler+0x0/0x14 enabled interrupts
> Backtrace:
>  (warn_slowpath_common) from [] (warn_slowpath_fmt+0x38/0x40)
>  (warn_slowpath_fmt) from [] (handle_irq_event_percpu+0x14c/0x174)
>  (handle_irq_event_percpu) from [] (handle_irq_event+0x84/0xb8)
>  (handle_irq_event) from [] (handle_simple_irq+0x90/0x118)
>  (handle_simple_irq) from [] (generic_handle_irq+0x30/0x44)
>  (generic_handle_irq) from [] 
> (dra7xx_pcie_msi_irq_handler+0x7c/0x8c)
>  (dra7xx_pcie_msi_irq_handler) from [] 
> (irq_forced_thread_fn+0x28/0x5c)
>  (irq_forced_thread_fn) from [] (irq_thread+0x128/0x204)
> 
> This happens because all of them invoke generic_handle_irq() from the
> requsted handler. generic_handle_irq grabs raw_locks and this needs to
> run in raw-irq context.
> 
> This issue was originally reproduced on TI dra7-evem, but, as was
> identified during dicussion [1], other PCI(e) hosts can also suffer
> from this issue. So let's fix all them at once and mark pcie/pci (msi)
> irq cascade handlers IRQF_NO_THREAD explicitly.
> 
> [1] https://lkml.org/lkml/2015/11/20/356
> 
> Cc: Kishon Vijay Abraham I <kis...@ti.com>
> Cc: Bjorn Helgaas <bhelg...@google.com>
> Cc: Jingoo Han <jingooh...@gmail.com>
> Cc: Kukjin Kim <kg...@kernel.org>
> Cc: Krzysztof Kozlowski <k.kozlow...@samsung.com>
> Cc: Richard Zhu <richard@freescale.com>
> Cc: Lucas Stach <l.st...@pengutronix.de>
> Cc: Thierry Reding <thierry.red...@gmail.com>
> Cc: Stephen Warren <swar...@wwwdotorg.org>
> Cc: Alexandre Courbot <gnu...@gmail.com>
> Cc: Simon Horman <ho...@verge.net.au>
> Cc: Pratyush Anand <pratyush.an...@gmail.com>
> Cc: Michal Simek <michal.si...@xilinx.com>
> Cc: "Sören Brinkmann" <soren.brinkm...@xilinx.com>
> Cc: Sebastian Andrzej Siewior <bige...@linutronix.de>
> Signed-off-by: Grygorii Strashko <grygorii.stras...@ti.com>
> ---
> Changes in v3:
>  - change applied to all affected pci(e) host drivers in drivers/pci/hosts.
>After some invsetigation I've decided to not touch arch code - it is not 
> easy
>to identify all places which need to be fixed. 
>if it's still required - i can send separate patches for 
>arch/mips/pci/msi-octeon.c and arch/sparc/kernel/pci_msi.c.
> Links
> v2: https://lkml.org/lkml/2015/11/20/356
> v1: https://lkml.org/lkml/2015/11/5/593
> ref: https://lkml.org/lkml/2015/11/3/660
> 
>  drivers/pci/host/pci-dra7xx.c | 13 -
>  drivers/pci/host/pci-exynos.c |  3 ++-
>  drivers/pci/host/pci-imx6.c   |  3 ++-
>  drivers/pci/host/pci-tegra.c  |  2 +-
>  drivers/pci/host/pcie-rcar.c  |  6 --
>  drivers/pci/host/pcie-spear13xx.c |  3 ++-
>  drivers/pci/host/pcie-xilinx.c|  3 ++-
>  7 files changed, 25 insertions(+), 8 deletions(-)

I applied this to pci/host for v4.5, thanks.  I added a stable tag.
I haven't seen any acks from the host driver guys, but I will still add
them if I see any in the next few days.

Bjorn

> diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
> index 8c36880..0415192 100644
> --- a/drivers/pci/host/pci-dra7xx.c
> +++ b/drivers/pci/host/pci-dra7xx.c
> @@ -301,8 +301,19 @@ static int __init dra7xx_add_pcie_port(struct 
> dra7xx_pcie *dra7xx,
>   return -EINVAL;
>   }
>  
> + /*
> +  * Mark dra7xx_pcie_msi IRQ as IRQF_NO_THREAD
> +  * On -RT and if kernel is booting with "threadirqs" cmd line parameter
> +  * the dra7xx_pcie_msi_irq_handler() will be forced threaded but,
> +  * in the same time, it's IRQ dispatcher and calls generic_handle_irq(),
> +  * which, in turn, will be resolved to handle_simple_irq() call.
> +  * The handle_simple_irq() expected to be called with IRQ disabled, as
> +  * result kernle will display warning:
> +  * "irq XXX handler YYY+0x0/0x14 enabled interrupts".
> +  */
>   ret = devm_request_irq(>dev, pp->irq,
> -dra7xx_pcie_msi_irq_handler, IRQF_SHARED,
> +dra7xx_pcie_msi_irq_handler,
> +IRQF_SHARED | IRQF_NO_THREAD,
>  "dra7-pcie-msi", pp);
>   if (ret) {
>   dev_err(>

Re: [PATCH] PCI: designware: bail out if host_init failed

[Bjorn Helgaas]

Hi Jisheng,

On Thu, Nov 12, 2015 at 09:48:45PM +0800, Jisheng Zhang wrote:
> There's no reason to continue the initialization such as configure
> register, scan root bus etc. if customized host_init() failed. This
> patch tries to check the host_init result, bail out if failed.

This patch changes the (*host_init) return type and adds "return 0" to
the host_init() implementations of ten different drivers, all to
support a possible error in one driver.

Is there any way to detect and handle the error in
ls1021_pcie_host_init() earlier, maybe by doing the syscon_regmap
lookup in ls_pcie_probe() instead of in the host_init() function?

That would be even better because you wouldn't have to touch any of
the other drivers, and you'd detect the error even earlier, before
we've done any of the designware setup.

Bjorn

> Signed-off-by: Jisheng Zhang 
> ---
>  drivers/pci/host/pci-dra7xx.c  |  4 +++-
>  drivers/pci/host/pci-exynos.c  |  4 +++-
>  drivers/pci/host/pci-imx6.c|  4 +++-
>  drivers/pci/host/pci-keystone.c|  4 +++-
>  drivers/pci/host/pci-layerscape.c  | 25 -
>  drivers/pci/host/pcie-designware.c |  7 +--
>  drivers/pci/host/pcie-designware.h |  2 +-
>  drivers/pci/host/pcie-spear13xx.c  |  4 +++-
>  8 files changed, 37 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
> index 8c36880..b3160a1 100644
> --- a/drivers/pci/host/pci-dra7xx.c
> +++ b/drivers/pci/host/pci-dra7xx.c
> @@ -149,7 +149,7 @@ static void dra7xx_pcie_enable_interrupts(struct 
> pcie_port *pp)
>  LEG_EP_INTERRUPTS);
>  }
>  
> -static void dra7xx_pcie_host_init(struct pcie_port *pp)
> +static int dra7xx_pcie_host_init(struct pcie_port *pp)
>  {
>   dw_pcie_setup_rc(pp);
>  
> @@ -162,6 +162,8 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
>   if (IS_ENABLED(CONFIG_PCI_MSI))
>   dw_pcie_msi_init(pp);
>   dra7xx_pcie_enable_interrupts(pp);
> +
> + return 0;
>  }
>  
>  static struct pcie_host_ops dra7xx_pcie_host_ops = {
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 01095e1..57f370b 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -481,10 +481,12 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
>   return 0;
>  }
>  
> -static void exynos_pcie_host_init(struct pcie_port *pp)
> +static int exynos_pcie_host_init(struct pcie_port *pp)
>  {
>   exynos_pcie_establish_link(pp);
>   exynos_pcie_enable_interrupts(pp);
> +
> + return 0;
>  }
>  
>  static struct pcie_host_ops exynos_pcie_host_ops = {
> diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
> index 22e8224..9a46680 100644
> --- a/drivers/pci/host/pci-imx6.c
> +++ b/drivers/pci/host/pci-imx6.c
> @@ -425,7 +425,7 @@ static int imx6_pcie_establish_link(struct pcie_port *pp)
>   return 0;
>  }
>  
> -static void imx6_pcie_host_init(struct pcie_port *pp)
> +static int imx6_pcie_host_init(struct pcie_port *pp)
>  {
>   imx6_pcie_assert_core_reset(pp);
>  
> @@ -439,6 +439,8 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
>  
>   if (IS_ENABLED(CONFIG_PCI_MSI))
>   dw_pcie_msi_init(pp);
> +
> + return 0;
>  }
>  
>  static void imx6_pcie_reset_phy(struct pcie_port *pp)
> diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
> index 0aa81bd..2604571 100644
> --- a/drivers/pci/host/pci-keystone.c
> +++ b/drivers/pci/host/pci-keystone.c
> @@ -250,7 +250,7 @@ static int keystone_pcie_fault(unsigned long addr, 
> unsigned int fsr,
>   return 0;
>  }
>  
> -static void __init ks_pcie_host_init(struct pcie_port *pp)
> +static int __init ks_pcie_host_init(struct pcie_port *pp)
>  {
>   struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
>   u32 val;
> @@ -277,6 +277,8 @@ static void __init ks_pcie_host_init(struct pcie_port *pp)
>*/
>   hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
>   "Asynchronous external abort");
> +
> + return 0;
>  }
>  
>  static struct pcie_host_ops keystone_pcie_host_ops = {
> diff --git a/drivers/pci/host/pci-layerscape.c 
> b/drivers/pci/host/pci-layerscape.c
> index 3923bed..a6e9070 100644
> --- a/drivers/pci/host/pci-layerscape.c
> +++ b/drivers/pci/host/pci-layerscape.c
> @@ -94,8 +94,9 @@ static int ls1021_pcie_link_up(struct pcie_port *pp)
>   return 1;
>  }
>  
> -static void ls1021_pcie_host_init(struct pcie_port *pp)
> +static int ls1021_pcie_host_init(struct pcie_port *pp)
>  {
> + int ret;
>   struct ls_pcie *pcie = to_ls_pcie(pp);
>   u32 val, index[2];
>  
> @@ -103,15 +104,14 @@ static void ls1021_pcie_host_init(struct pcie_port *pp)
>"fsl,pcie-scfg");
>   if (IS_ERR(pcie->scfg)) {
>   dev_err(pp->dev, "No syscfg phandle specified\n");
> -   

Re: [PATCH 0/8] i.MX6 PCIe binding change and MSI support

[Bjorn Helgaas]

On Tue, Jun 3, 2014 at 7:22 AM, Lucas Stach l.st...@pengutronix.de wrote:
 Hello Bjorn,

 Am Freitag, den 30.05.2014, 11:30 -0600 schrieb Bjorn Helgaas:
 On Mon, May 12, 2014 at 10:59:43AM +0200, Lucas Stach wrote:
  Hi Bjorn,
 
  just a friendly reminder. It would be nice if you could pull those in.
 
  Shawn already pulled the DT change and as it is a binding change this
  means PCIe on i.MX6 is broken in -next, as long as the remaining patches
  are missing.

 I applied these to pci/host-imx6 for v3.16.

 Sorry I didn't do this sooner; I get a lot of email and it's easy to
 overlook things.  I mostly work from patchwork
 (http://patchwork.ozlabs.org/project/linux-pci/list/?order=date), and I had
 dropped this series from there because there was enough discussion that I
 expected a re-post, so it wasn't on my radar screen anymore.

 Bjorn

  Am Dienstag, den 29.04.2014, 14:31 +0200 schrieb Lucas Stach:
   Hi Bjorn,
  
   Am Freitag, den 25.04.2014, 08:39 -0600 schrieb Bjorn Helgaas:
   [...]
PCI: designware: split Exynos and i.MX bindings

 It seems you missed this one patch. This isn't too urgent, as it is just
 the doc update, but it should still go into 3.16 along with the other
 changes. I would have expected that is ok for this to go through your
 tree.

Oops, sorry.  I had mentioned patches 4-8 earlier in the conversation,
so that's what I merged.

I added patch 2 to pci/host-imx6, and I'll ask Linus to pull it later
along with some other things I forgot.  Thanks for the reminder!

Bjorn
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Re: [PATCH 0/8] i.MX6 PCIe binding change and MSI support

[Bjorn Helgaas]

On Mon, May 12, 2014 at 10:59:43AM +0200, Lucas Stach wrote:
 Hi Bjorn,
 
 just a friendly reminder. It would be nice if you could pull those in.
 
 Shawn already pulled the DT change and as it is a binding change this
 means PCIe on i.MX6 is broken in -next, as long as the remaining patches
 are missing.

I applied these to pci/host-imx6 for v3.16.

Sorry I didn't do this sooner; I get a lot of email and it's easy to
overlook things.  I mostly work from patchwork
(http://patchwork.ozlabs.org/project/linux-pci/list/?order=date), and I had
dropped this series from there because there was enough discussion that I
expected a re-post, so it wasn't on my radar screen anymore.

Bjorn

 Am Dienstag, den 29.04.2014, 14:31 +0200 schrieb Lucas Stach:
  Hi Bjorn,
  
  Am Freitag, den 25.04.2014, 08:39 -0600 schrieb Bjorn Helgaas:
  [...]
   PCI: designware: split Exynos and i.MX bindings
   ARM: dts: imx6: update pcie to bring in line with new binding
   PCI: imx6: use new clock names
   PCI: imx6: drop old irq mapping
   PCI: imx6: rip out optional (and unused) irqs
   PCI: designware: make MSI isr shared irq aware
   PCI: imx6: add support for MSI
   
What's the status of all these?  I would normally apply patches 4-8 of 
this
series through my tree, given the appropriate acks, but I haven't seen
those yet.  And I'm not sure what dependencies there are between the
non-PCI patches and the PCI ones.
   
It's a complete binding change, so applying one part without the other
is going to horribly break things.
   
So I would at least want to see an ack for the binding change on the
i.MX side from Shawn and Richard. This will need some follow on patches,
as some boards adding PCIe using the old binding have cropped up in
linux-next, but I can do the patches on short notice if everyone agrees
to merge this patchset.
   
The designware part is pretty simple and doesn't change anything for
other users than i.MX. Though I would like to see an ack from Jingoo for
those.
   
I have some more stuff in the pipes regarding multiple MSI irqs, that
depend on this series and also the Keystone people are waiting for this
to be applied in order to consolidate the clock handling of the
designware core driver, so it would be nice to get this moving again.
   
   OK, just poke me again when you're ready for me to do something with 
   these.
   
  
  As both Richard and Jingoo gave their ack for the respective patches I
  think this is good to go in and I would expect all the PCI patches to go
  through your tree for 3.16.
  
  Shawn, if you are not okay with this change, please speak up now.
  Otherwise please pick the dts change for 3.16. I'll go over linux-next
  and prepare the patches to fix up the boards there.
  
 
 
 -- 
 Pengutronix e.K. | Lucas Stach |
 Industrial Linux Solutions   | http://www.pengutronix.de/  |
 
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Re: [PATCH 1/1] PCI: exynos: Fix section mismatch warning

[Bjorn Helgaas]

On Wed, May 28, 2014 at 03:18:45PM +0530, Sachin Kamat wrote:
 add_pcie_port is called from probe which is annotated with __init.
 add_pcie_port calls dw_pcie_host_init which is also annotated with
 __init. Thus it makes sense to annotate add_pcie_port with __init
 to avoid the following section mismatch warning:
 
 WARNING: drivers/pci/built-in.o(.text.unlikely+0xf8): Section mismatch in 
 reference from the function add_pcie_port() to the function 
 .init.text:dw_pcie_host_init()
The function add_pcie_port() references
the function __init dw_pcie_host_init().
This is often because add_pcie_port lacks a __init
annotation or the annotation of dw_pcie_host_init is wrong.
 
 Reported-by: kbuild test robot fengguang...@intel.com
 Signed-off-by: Sachin Kamat sachin.ka...@linaro.org

Applied with Jingoo's ack to pci/host-exynos for v3.16, thanks!

 ---
  drivers/pci/host/pci-exynos.c |3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)
 
 diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
 index 3de6bfbbe8e9..3c1ff89829ec 100644
 --- a/drivers/pci/host/pci-exynos.c
 +++ b/drivers/pci/host/pci-exynos.c
 @@ -511,7 +511,8 @@ static struct pcie_host_ops exynos_pcie_host_ops = {
   .host_init = exynos_pcie_host_init,
  };
  
 -static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
 +static int __init add_pcie_port(struct pcie_port *pp,
 + struct platform_device *pdev)
  {
   int ret;
  
 -- 
 1.7.9.5
 
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Re: [PATCH 0/8] i.MX6 PCIe binding change and MSI support

[Bjorn Helgaas]

On Fri, Apr 25, 2014 at 4:21 AM, Lucas Stach l.st...@pengutronix.de wrote:
 Am Donnerstag, den 24.04.2014, 11:58 -0600 schrieb Bjorn Helgaas:
 On Fri, Mar 28, 2014 at 05:52:51PM +0100, Lucas Stach wrote:
  While working on MSI support for the i.MX6 PCIe host driver
  it has been discovered that the binding for this host controller
  is broken in many ways (refer to the patch descriptions for more
  info) and was introduced without proper discussion about what
  should/should not be in the binding.
 
  This series fixes this and minimizes the difference of the
  i.MX6 binding to the common designware PCIe binding. I'm aware
  that this is a quite radical change, but I think it's justified
  to do this as long as there aren't many user of the old binding
  (most of the optional properties in the binding aren't even
  implemented).
 
  Looking forward to your feedback.
 
  Lucas Stach (8):
ARM: imx6q-clk: parent lvds_gate from lvds_sel
 This one is already applied.

PCI: designware: split Exynos and i.MX bindings
ARM: dts: imx6: update pcie to bring in line with new binding
PCI: imx6: use new clock names
PCI: imx6: drop old irq mapping
PCI: imx6: rip out optional (and unused) irqs
PCI: designware: make MSI isr shared irq aware
PCI: imx6: add support for MSI

 What's the status of all these?  I would normally apply patches 4-8 of this
 series through my tree, given the appropriate acks, but I haven't seen
 those yet.  And I'm not sure what dependencies there are between the
 non-PCI patches and the PCI ones.

 It's a complete binding change, so applying one part without the other
 is going to horribly break things.

 So I would at least want to see an ack for the binding change on the
 i.MX side from Shawn and Richard. This will need some follow on patches,
 as some boards adding PCIe using the old binding have cropped up in
 linux-next, but I can do the patches on short notice if everyone agrees
 to merge this patchset.

 The designware part is pretty simple and doesn't change anything for
 other users than i.MX. Though I would like to see an ack from Jingoo for
 those.

 I have some more stuff in the pipes regarding multiple MSI irqs, that
 depend on this series and also the Keystone people are waiting for this
 to be applied in order to consolidate the clock handling of the
 designware core driver, so it would be nice to get this moving again.

OK, just poke me again when you're ready for me to do something with these.

Bjorn
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Re: [PATCH 0/8] i.MX6 PCIe binding change and MSI support

[Bjorn Helgaas]

On Fri, Mar 28, 2014 at 05:52:51PM +0100, Lucas Stach wrote:
 While working on MSI support for the i.MX6 PCIe host driver
 it has been discovered that the binding for this host controller
 is broken in many ways (refer to the patch descriptions for more
 info) and was introduced without proper discussion about what
 should/should not be in the binding.
 
 This series fixes this and minimizes the difference of the
 i.MX6 binding to the common designware PCIe binding. I'm aware
 that this is a quite radical change, but I think it's justified
 to do this as long as there aren't many user of the old binding
 (most of the optional properties in the binding aren't even
 implemented).
 
 Looking forward to your feedback.
 
 Lucas Stach (8):
   ARM: imx6q-clk: parent lvds_gate from lvds_sel
   PCI: designware: split Exynos and i.MX bindings
   ARM: dts: imx6: update pcie to bring in line with new binding
   PCI: imx6: use new clock names
   PCI: imx6: drop old irq mapping
   PCI: imx6: rip out optional (and unused) irqs
   PCI: designware: make MSI isr shared irq aware
   PCI: imx6: add support for MSI

What's the status of all these?  I would normally apply patches 4-8 of this
series through my tree, given the appropriate acks, but I haven't seen
those yet.  And I'm not sure what dependencies there are between the
non-PCI patches and the PCI ones.

Bjorn
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Re: [PATCH v2 2/6] PCI: tegra: use new OF interrupt mapping when possible

[Bjorn Helgaas]

On Wed, Apr 16, 2014 at 10:20:45AM +0200, Lucas Stach wrote:
 Am Dienstag, den 15.04.2014, 12:30 -0600 schrieb Bjorn Helgaas:
  On Tue, Apr 15, 2014 at 12:07:34PM +0200, Lucas Stach wrote:
   Hi Bjorn,
   
   Am Freitag, den 04.04.2014, 10:55 -0600 schrieb Bjorn Helgaas:
On Wed, Mar 05, 2014 at 02:25:47PM +0100, Lucas Stach wrote:
 This is the recommended method of doing the IRQ
 mapping. For old devicetrees we fall back to the
 previous practice.
 
 Signed-off-by: Lucas Stach l.st...@pengutronix.de
 Acked-by: Arnd Bergmann a...@arndb.de

Applied with Stephen's Tested-by to my pending/host-tegra branch.  I'll
rebase and rename it after v3.15-rc1, and I think we can squeeze it into
v3.15 shortly after that.  Thanks.

   
   Are you still planning to push this into 3.15, or has this slipped to
   3.16?
  
  Yes, I'm hoping to put them in v3.15.  I assume these actually
  fix something, e.g., we need these changes to boot with new devicetrees, or
  something?
  
  The changelogs don't make it clear that these are fixes, and I want to heed
  Linus' guidance: Anyway, because -rc1 is already pretty darn big, I do
  *not* want to hear about 'sorry this missed the window, can I still sneak
  in'.  Fixes only.
  
  I should have applied these sooner to make the merge window; I apologize
  for that.  Anyway, if you outline what these fix, I'll update the
  changelogs in my tree.
  
 Actually they are a bit on the fence.
 
 The i.MX and thus the designware patch actually fixes wrong behavior,
 where all PCI legacy interrupts would be mapped to a single GIC
 interrupt, which would leave INT B,C,D nonfunctional on i.MX.
 
 The others only make DT interrupt mapping functional for all drivers, so
 they would be useful if you need to remap interrupts across bridges or
 something. But apparently nobody had the need to to this on platforms
 other than i.MX until now, so those patches only fix a theoretical
 issue.

It sounds like the others should fix real problems; it's just that nobody
has actually tested relevant configurations yet.  I think that's fair game,
so I updated the changelogs and put them in my for-linus branch for v3.15.

This includes the designware, rcar, and tegra patches.

Bjorn
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Re: [PATCH v2 2/6] PCI: tegra: use new OF interrupt mapping when possible

[Bjorn Helgaas]

On Tue, Apr 15, 2014 at 12:07:34PM +0200, Lucas Stach wrote:
 Hi Bjorn,
 
 Am Freitag, den 04.04.2014, 10:55 -0600 schrieb Bjorn Helgaas:
  On Wed, Mar 05, 2014 at 02:25:47PM +0100, Lucas Stach wrote:
   This is the recommended method of doing the IRQ
   mapping. For old devicetrees we fall back to the
   previous practice.
   
   Signed-off-by: Lucas Stach l.st...@pengutronix.de
   Acked-by: Arnd Bergmann a...@arndb.de
  
  Applied with Stephen's Tested-by to my pending/host-tegra branch.  I'll
  rebase and rename it after v3.15-rc1, and I think we can squeeze it into
  v3.15 shortly after that.  Thanks.
  
 
 Are you still planning to push this into 3.15, or has this slipped to
 3.16?

Yes, I'm hoping to put them in v3.15.  I assume these actually
fix something, e.g., we need these changes to boot with new devicetrees, or
something?

The changelogs don't make it clear that these are fixes, and I want to heed
Linus' guidance: Anyway, because -rc1 is already pretty darn big, I do
*not* want to hear about 'sorry this missed the window, can I still sneak
in'.  Fixes only.

I should have applied these sooner to make the merge window; I apologize
for that.  Anyway, if you outline what these fix, I'll update the
changelogs in my tree.

Bjorn
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Re: [PATCH v2 2/6] PCI: tegra: use new OF interrupt mapping when possible

[Bjorn Helgaas]

On Wed, Mar 05, 2014 at 02:25:47PM +0100, Lucas Stach wrote:
 This is the recommended method of doing the IRQ
 mapping. For old devicetrees we fall back to the
 previous practice.
 
 Signed-off-by: Lucas Stach l.st...@pengutronix.de
 Acked-by: Arnd Bergmann a...@arndb.de

Applied with Stephen's Tested-by to my pending/host-tegra branch.  I'll
rebase and rename it after v3.15-rc1, and I think we can squeeze it into
v3.15 shortly after that.  Thanks.

 ---
  drivers/pci/host/pci-tegra.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)
 
 diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
 index 330f7e3a32dd..083cf37ca047 100644
 --- a/drivers/pci/host/pci-tegra.c
 +++ b/drivers/pci/host/pci-tegra.c
 @@ -639,10 +639,15 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data 
 *sys)
  static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
  {
   struct tegra_pcie *pcie = sys_to_pcie(pdev-bus-sysdata);
 + int irq;
  
   tegra_cpuidle_pcie_irqs_in_use();
  
 - return pcie-irq;
 + irq = of_irq_parse_and_map_pci(pdev, slot, pin);
 + if (!irq)
 + irq = pcie-irq;
 +
 + return irq;
  }
  
  static void tegra_pcie_add_bus(struct pci_bus *bus)
 -- 
 1.9.0
 
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Re: [PATCH v2 6/6] PCI: designware: use new OF interrupt mapping when possible

[Bjorn Helgaas]

On Wed, Mar 05, 2014 at 11:42:19AM -0700, Jason Gunthorpe wrote:
 On Wed, Mar 05, 2014 at 02:25:51PM +0100, Lucas Stach wrote:
  -   return pp-irq;
  +   irq = of_irq_parse_and_map_pci(dev, slot, pin);
  +   if (!irq)
  +   irq = pp-irq;
 
 In light of the two bugs that Tim found, it might be wise to throw a
 'dev_warn(FW_BUG Missing DT interrupt mapping)' in the fall back
 path, so it doesn't continue to silently cover up errors on the OF/DT
 side..

This sounds like a reasonable thing to do, but I didn't see a response to
this comment.  Should I merge it as-is, or do you want to add the message?
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Re: [PATCH v2 6/6] PCI: designware: use new OF interrupt mapping when possible

[Bjorn Helgaas]

On Fri, Apr 04, 2014 at 11:03:41AM -0600, Bjorn Helgaas wrote:
 On Wed, Mar 05, 2014 at 11:42:19AM -0700, Jason Gunthorpe wrote:
  On Wed, Mar 05, 2014 at 02:25:51PM +0100, Lucas Stach wrote:
   - return pp-irq;
   + irq = of_irq_parse_and_map_pci(dev, slot, pin);
   + if (!irq)
   + irq = pp-irq;
  
  In light of the two bugs that Tim found, it might be wise to throw a
  'dev_warn(FW_BUG Missing DT interrupt mapping)' in the fall back
  path, so it doesn't continue to silently cover up errors on the OF/DT
  side..
 
 This sounds like a reasonable thing to do, but I didn't see a response to
 this comment.  Should I merge it as-is, or do you want to add the message?

Oh, and I suppose the same question applies to the other host drivers in
this series (tegra, rcar)?
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Re: [PATCH] MAINTAINERS: Add DesignWare, i.MX6, Armada, R-Car PCI host maintainers

[Bjorn Helgaas]

On Thu, Dec 12, 2013 at 12:00 AM, Shawn Guo shawn@linaro.org wrote:
 Hi Bjorn,

 On Wed, Dec 11, 2013 at 11:32:37AM -0700, Bjorn Helgaas wrote:
 +PCI DRIVER FOR IMX6
 +M:   Shawn Guo shawn@linaro.org

 Thanks for the nomination.  But I think a better person for this
 position would be Richard Zhu r65...@freescale.com (copied).  He knows
 the driver and controller much better than myself, and most importantly
 he is the driver owner for Freescale kernel and he has the contact to
 Freescale PCIe hardware people.

Richard, are you OK with being listed here?  Shawn, do you want to be
listed here in addition, if only to make sure you're copied on changes
to pci-imx6.c?
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[PATCH v2] MAINTAINERS: Add DesignWare, i.MX6, Armada, R-Car PCI host maintainers

[Bjorn Helgaas]

[+cc Thomas]

On Wed, Dec 11, 2013 at 11:32:37AM -0700, Bjorn Helgaas wrote:
 If this looks reasonable, I'll merge it via the PCI tree for v3.13.

OK, here's another try.  I'm not actually trying to nominate anybody; I
just tried to write down the list we came up with in an earlier discussion [1].

I'd like confirmation from the following people that they approve of being
listed here:

  Richard Zhu (IMX6)
  Thomas Petazzoni (MVEBU)
  Magnus Damm (R-CAR)

I think everybody else listed has already said they approve.

[1] 
http://lkml.kernel.org/r/CAErSpo5tN==4nsv2u3sube_l4vswn4p7tn+ltrc172qj1vh...@mail.gmail.com


MAINTAINERS: Add DesignWare, i.MX6, Armada, R-Car PCI host maintainers

From: Bjorn Helgaas bhelg...@google.com

Add entries for PCI host controller drivers in drivers/pci/host/.

Signed-off-by: Mohit Kumar mohit.ku...@st.com (DesignWare)
Signed-off-by: Pratyush Anand pratyush.an...@st.com   (DesignWare)
Signed-off-by: Bjorn Helgaas bhelg...@google.com
Acked-by: Simon Horman horms+rene...@verge.net.au (R-CAR)
Acked-by: Jason Cooper ja...@lakedaemon.net   (MVEBU)
Acked-by: Jingoo Han jg1@samsung.com
Acked-by: Thierry Reding tred...@nvidia.com
---
 MAINTAINERS |   34 ++
 1 file changed, 34 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8285ed4676b6..1c5dc36ec522 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6449,19 +6449,53 @@ F:  drivers/pci/
 F: include/linux/pci*
 F: arch/x86/pci/
 
+PCI DRIVER FOR IMX6
+M: Richard Zhu r65...@freescale.com
+M: Shawn Guo shawn@linaro.org
+L: linux-...@vger.kernel.org
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: drivers/pci/host/*imx6*
+
+PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
+M: Thomas Petazzoni thomas.petazz...@free-electrons.com
+M: Jason Cooper ja...@lakedaemon.net
+L: linux-...@vger.kernel.org
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: drivers/pci/host/*mvebu*
+
 PCI DRIVER FOR NVIDIA TEGRA
 M: Thierry Reding thierry.red...@gmail.com
 L: linux-te...@vger.kernel.org
+L: linux-...@vger.kernel.org
 S: Supported
 F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
 F: drivers/pci/host/pci-tegra.c
 
+PCI DRIVER FOR RENESAS R-CAR
+M: Simon Horman ho...@verge.net.au
+M: Magnus Damm magnus.d...@gmail.com
+L: linux-...@vger.kernel.org
+L: linux...@vger.kernel.org
+S: Maintained
+F: drivers/pci/host/*rcar*
+
 PCI DRIVER FOR SAMSUNG EXYNOS
 M: Jingoo Han jg1@samsung.com
 L: linux-...@vger.kernel.org
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
 S: Maintained
 F: drivers/pci/host/pci-exynos.c
 
+PCI DRIVER FOR SYNOPSIS DESIGNWARE
+M: Mohit Kumar mohit.ku...@st.com
+M: Jingoo Han jg1@samsung.com
+L: linux-...@vger.kernel.org
+S: Maintained
+F: drivers/pci/host/*designware*
+
 PCMCIA SUBSYSTEM
 P: Linux PCMCIA Team
 L: linux-pcm...@lists.infradead.org
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[PATCH] MAINTAINERS: Add DesignWare, i.MX6, Armada, R-Car PCI host maintainers

[Bjorn Helgaas]

If this looks reasonable, I'll merge it via the PCI tree for v3.13.

Bjorn


MAINTAINERS: Add DesignWare, i.MX6, Armada, R-Car PCI host maintainers

Add entries for PCI host controller drivers in drivers/pci/host/.

Signed-off-by: Bjorn Helgaas bhelg...@google.com
---
 MAINTAINERS |   31 +++
 1 file changed, 31 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8285ed4676b6..826c722d92ba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6449,16 +6449,47 @@ F:  drivers/pci/
 F: include/linux/pci*
 F: arch/x86/pci/
 
+PCI DRIVER FOR DESIGNWARE
+M: Jingoo Han jg1@samsung.com
+L: linux-...@vger.kernel.org
+S: Maintained
+F: drivers/pci/host/*designware*
+
+PCI DRIVER FOR IMX6
+M: Shawn Guo shawn@linaro.org
+L: linux-...@vger.kernel.org
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: drivers/pci/host/*imx6*
+
+PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
+M: Jason Cooper ja...@lakedaemon.net
+L: linux-...@vger.kernel.org
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: drivers/pci/host/*mvebu*
+
 PCI DRIVER FOR NVIDIA TEGRA
 M: Thierry Reding thierry.red...@gmail.com
 L: linux-te...@vger.kernel.org
+L: linux-...@vger.kernel.org
 S: Supported
 F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
 F: drivers/pci/host/pci-tegra.c
 
+PCI DRIVER FOR RENESAS R-CAR
+M: Simon Horman ho...@verge.net.au
+M: Magnus Damm magnus.d...@gmail.com
+L: linux-...@vger.kernel.org
+L: linux...@vger.kernel.org
+S: Maintained
+F: drivers/pci/host/*rcar*
+
 PCI DRIVER FOR SAMSUNG EXYNOS
 M: Jingoo Han jg1@samsung.com
 L: linux-...@vger.kernel.org
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
 S: Maintained
 F: drivers/pci/host/pci-exynos.c
 
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Re: [PATCH V2] PCI: designware: Add irq_create_mapping()

[Bjorn Helgaas]

On Wed, Oct 9, 2013 at 6:32 AM, Jingoo Han jg1@samsung.com wrote:
 From: Pratyush Anand pratyush.an...@st.com

 Without irq_create_mapping(), the correct irq number cannot be
 provided. In this case, it makes problems such as NULL deference.
 Thus, irq_create_mapping() should be added for MSI.

 Signed-off-by: Pratyush Anand pratyush.an...@st.com
 Suggested-by: Kishon Vijay Abraham I kis...@ti.com
 Signed-off-by: Jingoo Han jg1@samsung.com

Applied to my pci/host-exynos branch for v3.13, thanks!

Bjorn

 ---
 Tested on Exynos5440.

  drivers/pci/host/pcie-designware.c |   25 +
  drivers/pci/host/pcie-designware.h |2 +-
  2 files changed, 14 insertions(+), 13 deletions(-)

 diff --git a/drivers/pci/host/pcie-designware.c 
 b/drivers/pci/host/pcie-designware.c
 index 8963017..92d58fd 100644
 --- a/drivers/pci/host/pcie-designware.c
 +++ b/drivers/pci/host/pcie-designware.c
 @@ -157,7 +157,7 @@ static struct irq_chip dw_msi_irq_chip = {
  void dw_handle_msi_irq(struct pcie_port *pp)
  {
 unsigned long val;
 -   int i, pos;
 +   int i, pos, irq;

 for (i = 0; i  MAX_MSI_CTRLS; i++) {
 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
 @@ -165,8 +165,9 @@ void dw_handle_msi_irq(struct pcie_port *pp)
 if (val) {
 pos = 0;
 while ((pos = find_next_bit(val, 32, pos)) != 32) {
 -   generic_handle_irq(pp-msi_irq_start
 -   + (i * 32) + pos);
 +   irq = irq_find_mapping(pp-irq_domain,
 +   i * 32 + pos);
 +   generic_handle_irq(irq);
 pos++;
 }
 }
 @@ -237,9 +238,8 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, 
 int *pos)
 }
 }

 -   irq = (pp-msi_irq_start + pos0);
 -
 -   if ((irq + no_irqs)  (pp-msi_irq_start + MAX_MSI_IRQS-1))
 +   irq = irq_find_mapping(pp-irq_domain, pos0);
 +   if (!irq)
 goto no_valid_irq;

 i = 0;
 @@ -270,6 +270,7 @@ static void clear_irq(unsigned int irq)
 struct irq_desc *desc;
 struct msi_desc *msi;
 struct pcie_port *pp;
 +   struct irq_data *data = irq_get_irq_data(irq);

 /* get the port structure */
 desc = irq_to_desc(irq);
 @@ -280,7 +281,7 @@ static void clear_irq(unsigned int irq)
 return;
 }

 -   pos = irq - pp-msi_irq_start;
 +   pos = data-hwirq;

 irq_free_desc(irq);

 @@ -371,8 +372,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 struct of_pci_range range;
 struct of_pci_range_parser parser;
 u32 val;
 -
 -   struct irq_domain *irq_domain;
 +   int i;

 if (of_pci_range_parser_init(parser, np)) {
 dev_err(pp-dev, missing ranges property\n);
 @@ -441,15 +441,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 }

 if (IS_ENABLED(CONFIG_PCI_MSI)) {
 -   irq_domain = irq_domain_add_linear(pp-dev-of_node,
 +   pp-irq_domain = irq_domain_add_linear(pp-dev-of_node,
 MAX_MSI_IRQS, msi_domain_ops,
 dw_pcie_msi_chip);
 -   if (!irq_domain) {
 +   if (!pp-irq_domain) {
 dev_err(pp-dev, irq domain init failed\n);
 return -ENXIO;
 }

 -   pp-msi_irq_start = irq_find_mapping(irq_domain, 0);
 +   for (i = 0; i  MAX_MSI_IRQS; i++)
 +   irq_create_mapping(pp-irq_domain, i);
 }

 if (pp-ops-host_init)
 diff --git a/drivers/pci/host/pcie-designware.h 
 b/drivers/pci/host/pcie-designware.h
 index faccbbf..1bf9fc5 100644
 --- a/drivers/pci/host/pcie-designware.h
 +++ b/drivers/pci/host/pcie-designware.h
 @@ -47,7 +47,7 @@ struct pcie_port {
 u32 lanes;
 struct pcie_host_ops*ops;
 int msi_irq;
 -   int msi_irq_start;
 +   struct irq_domain   *irq_domain;
 unsigned long   msi_data;
 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
  };
 --
 1.7.10.4


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Re: [PATCH] PCI: exynos: missing clk_disable_unprepare() on error in exynos_pcie_probe()

[Bjorn Helgaas]

On Sun, Sep 29, 2013 at 10:29:11AM +0800, Wei Yongjun wrote:
 From: Wei Yongjun yongjun_...@trendmicro.com.cn
 
 Add the missing clk_disable_unprepare() before return
 from exynos_pcie_probe() in the error handling case.
 
 Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn

Applied with Jingoo's ack and Sylwester's subject line to
pci/host-exynos.  Thanks!

Bjorn

 ---
  drivers/pci/host/pci-exynos.c | 18 --
  1 file changed, 12 insertions(+), 6 deletions(-)
 
 diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
 index 94e096b..e25598a 100644
 --- a/drivers/pci/host/pci-exynos.c
 +++ b/drivers/pci/host/pci-exynos.c
 @@ -487,18 +487,24 @@ static int __init exynos_pcie_probe(struct 
 platform_device *pdev)
  
   elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   exynos_pcie-elbi_base = devm_ioremap_resource(pdev-dev, elbi_base);
 - if (IS_ERR(exynos_pcie-elbi_base))
 - return PTR_ERR(exynos_pcie-elbi_base);
 + if (IS_ERR(exynos_pcie-elbi_base)) {
 + ret = PTR_ERR(exynos_pcie-elbi_base);
 + goto fail_bus_clk;
 + }
  
   phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
   exynos_pcie-phy_base = devm_ioremap_resource(pdev-dev, phy_base);
 - if (IS_ERR(exynos_pcie-phy_base))
 - return PTR_ERR(exynos_pcie-phy_base);
 + if (IS_ERR(exynos_pcie-phy_base)) {
 + ret = PTR_ERR(exynos_pcie-phy_base);
 + goto fail_bus_clk;
 + }
  
   block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
   exynos_pcie-block_base = devm_ioremap_resource(pdev-dev, block_base);
 - if (IS_ERR(exynos_pcie-block_base))
 - return PTR_ERR(exynos_pcie-block_base);
 + if (IS_ERR(exynos_pcie-block_base)) {
 + ret = PTR_ERR(exynos_pcie-block_base);
 + goto fail_bus_clk;
 + }
  
   ret = add_pcie_port(pp, pdev);
   if (ret  0)
 
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Re: [PATCH] MAINTAINERS: add maintainer entry for Samsung Exynos PCIe driver

[Bjorn Helgaas]

On Thu, Sep 12, 2013 at 5:29 AM, Jingoo Han jg1@samsung.com wrote:
 Add myself as maintainer for Samsung Exynos PCIe driver.

 Signed-off-by: Jingoo Han jg1@samsung.com

Applied to my pci/host-exynos branch for v3.13.  Thanks!

 ---
  MAINTAINERS |6 ++
  1 file changed, 6 insertions(+)

 diff --git a/MAINTAINERS b/MAINTAINERS
 index 6d0dabe..f00c469 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
 @@ -6346,6 +6346,12 @@ S:   Supported
  F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
  F: drivers/pci/host/pci-tegra.c

 +PCI DRIVER FOR SAMSUNG EXYNOS
 +M: Jingoo Han jg1@samsung.com
 +L: linux-...@vger.kernel.org
 +S: Maintained
 +F: drivers/pci/host/pci-exynos.c
 +
  PCMCIA SUBSYSTEM
  P: Linux PCMCIA Team
  L: linux-pcm...@lists.infradead.org
 --
 1.7.10.4


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Re: [PATCH V3] PCI: exynos: add support for MSI

[Bjorn Helgaas]

On Fri, Sep 6, 2013 at 12:54 AM, Jingoo Han jg1@samsung.com wrote:
 This patch adds support for Message Signaled Interrupt in the
 Exynos PCIe diver using Synopsys designware PCIe core IP.

 Signed-off-by: Siva Reddy Kallam siva.kal...@samsung.com
 Signed-off-by: Srikanth T Shivanand ts.srika...@samsung.com
 Signed-off-by: Jingoo Han jg1@samsung.com
 Cc: Pratyush Anand pratyush.an...@st.com
 Cc: Mohit KUMAR mohit.ku...@st.com

Applied to my pci/host-exynos branch for v3.13.  Thanks!

Bjorn
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Re: [PATCH] PCI: exynos: turn off power of phy block when link failed

[Bjorn Helgaas]

On Fri, Sep 6, 2013 at 2:21 AM, Jingoo Han jg1@samsung.com wrote:
 When link failed, there is no need to turn on phy block. Also,
 turning on phy block is added, in order to turn on phy block
 regardless of the default value of phy registers.

 Signed-off-by: Jingoo Han jg1@samsung.com

Applied to my pci/host-exynos branch for v3.13.  Thanks!

Bjorn
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Re: [PATCH V3] PCI: exynos: add support for MSI

[Bjorn Helgaas]

On Wed, Sep 25, 2013 at 10:32 PM, Jingoo Han jg1@samsung.com wrote:
 On Friday, September 06, 2013 3:55 PM, Jingoo Han wrote:

 This patch adds support for Message Signaled Interrupt in the
 Exynos PCIe diver using Synopsys designware PCIe core IP.

 Signed-off-by: Siva Reddy Kallam siva.kal...@samsung.com
 Signed-off-by: Srikanth T Shivanand ts.srika...@samsung.com
 Signed-off-by: Jingoo Han jg1@samsung.com
 Cc: Pratyush Anand pratyush.an...@st.com
 Cc: Mohit KUMAR mohit.ku...@st.com

 Hi Bjorn Helgaas,

 There is no comment for last 3 weeks.
 Would you merge this patch to your tree?

I worked on merging your patches today, which is what prompted my
message about how to manage the exynos, mvebu, tegra, etc., host
drivers.  Assuming we come to a consensus about that, they should
appear in -next by the end of this week.

Bjorn
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Re: [PATCH V5] pci: exynos: split into two parts such as Synopsys part and Exynos part

[Bjorn Helgaas]

On Tue, Aug 6, 2013 at 10:13 PM, Jingoo Han jg1@samsung.com wrote:
 On Wednesday, July 31, 2013 5:14 PM, Jingoo Han jg1@samsung.com wrote:
 Exynos PCIe IP consists of Synopsys specific part and Exynos
 specific part. Only core block is a Synopsys designware part;
 other parts are Exynos specific.
 Also, the Synopsys designware part can be shared with other
 platforms; thus, it can be split two parts such as Synopsys
 designware part and Exynos specific part.

 Signed-off-by: Jingoo Han jg1@samsung.com
 Cc: Pratyush Anand pratyush.an...@st.com
 Cc: Mohit KUMAR mohit.ku...@st.com

 Hi Bjorn Helgaas,

 There is no comment for last 2 weeks.
 Will you accept this patch?

I don't have any problem with this, since it's really arch code.  Do
you want me to merge it, or do you have a standard path for merging
Exynos and/or Designware changes?

Bjorn

In case you need it:

Acked-by: Bjorn Helgaas bhelg...@google.com

 ---
 Changes since v4:
 - fixed section mismatch warnings
 - fixed sparse warnings

  .../devicetree/bindings/pci/designware-pcie.txt|3 +
  arch/arm/boot/dts/exynos5440.dtsi  |2 +
  drivers/pci/host/Makefile  |3 +-
  drivers/pci/host/pci-exynos.c  |  530 ++
  drivers/pci/host/pcie-designware.c | 1011 
 ++--
  drivers/pci/host/pcie-designware.h |   65 ++
  6 files changed, 874 insertions(+), 740 deletions(-)
  create mode 100644 drivers/pci/host/pci-exynos.c
  create mode 100644 drivers/pci/host/pcie-designware.h


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Re: [PATCH V10 1/4] pci: Add PCIe driver for Samsung Exynos

[Bjorn Helgaas]

On Fri, Jun 21, 2013 at 04:24:54PM +0900, Jingoo Han wrote:
 Exynos5440 has a PCIe controller which can be used as Root Complex.
 This driver supports a PCIe controller as Root Complex mode.
 
 Signed-off-by: Surendranath Gurivireddy Balla suren.re...@samsung.com
 Signed-off-by: Siva Reddy Kallam siva.kal...@samsung.com
 Signed-off-by: Jingoo Han jg1@samsung.com
 Acked-by: Arnd Bergmann a...@arndb.de

Acked-by: Bjorn Helgaas bhelg...@google.com

Please merge this through arm-soc as you discussed.

 ---
  .../devicetree/bindings/pci/designware-pcie.txt|   73 ++
  drivers/pci/host/Kconfig   |9 +
  drivers/pci/host/Makefile  |1 +
  drivers/pci/host/pcie-designware.c | 1057 
 
  4 files changed, 1140 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt
  create mode 100644 drivers/pci/host/pcie-designware.c
 
 diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt 
 b/Documentation/devicetree/bindings/pci/designware-pcie.txt
 new file mode 100644
 index 000..e2371f5
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
 @@ -0,0 +1,73 @@
 +* Synopsis Designware PCIe interface
 +
 +Required properties:
 +- compatible: should contain snps,dw-pcie to identify the
 + core, plus an identifier for the specific instance, such
 + as samsung,exynos5440-pcie.
 +- reg: base addresses and lengths of the pcie controller,
 + the phy controller, additional register for the phy controller.
 +- interrupts: interrupt values for level interrupt,
 + pulse interrupt, special interrupt.
 +- clocks: from common clock binding: handle to pci clock.
 +- clock-names: from common clock binding: should be pcie and pcie_bus.
 +- #address-cells: set to 3
 +- #size-cells: set to 2
 +- device_type: set to pci
 +- ranges: ranges for the PCI memory and I/O regions
 +- #interrupt-cells: set to 1
 +- interrupt-map-mask and interrupt-map: standard PCI properties
 + to define the mapping of the PCIe interface to interrupt
 + numbers.
 +- reset-gpio: gpio pin number of power good signal
 +
 +Example:
 +
 +SoC specific DT Entry:
 +
 + pcie@29 {
 + compatible = samsung,exynos5440-pcie, snps,dw-pcie;
 + reg = 0x29 0x1000
 + 0x27 0x1000
 + 0x271000 0x40;
 + interrupts = 0 20 0, 0 21 0, 0 22 0;
 + clocks = clock 28, clock 27;
 + clock-names = pcie, pcie_bus;
 + #address-cells = 3;
 + #size-cells = 2;
 + device_type = pci;
 + ranges = 0x0800 0 0x4000 0x4000 0 0x1000   /* 
 configuration space */
 +   0x8100 0 0  0x40001000 0 0x0001   /* 
 downstream I/O */
 +   0x8200 0 0x40011000 0x40011000 0 0x1ffef000; /* 
 non-prefetchable memory */
 + #interrupt-cells = 1;
 + interrupt-map-mask = 0 0 0 0;
 + interrupt-map = 0x0 0 gic 53;
 + };
 +
 + pcie@2a {
 + compatible = samsung,exynos5440-pcie, snps,dw-pcie;
 + reg = 0x2a 0x1000
 + 0x272000 0x1000
 + 0x271040 0x40;
 + interrupts = 0 23 0, 0 24 0, 0 25 0;
 + clocks = clock 29, clock 27;
 + clock-names = pcie, pcie_bus;
 + #address-cells = 3;
 + #size-cells = 2;
 + device_type = pci;
 + ranges = 0x0800 0 0x6000 0x6000 0 0x1000   /* 
 configuration space */
 +   0x8100 0 0  0x60001000 0 0x0001   /* 
 downstream I/O */
 +   0x8200 0 0x60011000 0x60011000 0 0x1ffef000; /* 
 non-prefetchable memory */
 + #interrupt-cells = 1;
 + interrupt-map-mask = 0 0 0 0;
 + interrupt-map = 0x0 0 gic 56;
 + };
 +
 +Board specific DT Entry:
 +
 + pcie@29 {
 + reset-gpio = pin_ctrl 5 0;
 + };
 +
 + pcie@2a {
 + reset-gpio = pin_ctrl 22 0;
 + };
 diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
 index 1f1d67f..1184ff6 100644
 --- a/drivers/pci/host/Kconfig
 +++ b/drivers/pci/host/Kconfig
 @@ -5,4 +5,13 @@ config PCI_MVEBU
   bool Marvell EBU PCIe controller
   depends on ARCH_MVEBU || ARCH_KIRKWOOD
  
 +config PCIE_DW
 + bool
 +
 +config PCI_EXYNOS
 + bool Samsung Exynos PCIe controller
 + depends on SOC_EXYNOS5440
 + select PCIEPORTBUS
 + select PCIE_DW
 +
  endmenu
 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
 index 5ea2d8b..086d850 100644
 --- a/drivers/pci/host/Makefile
 +++ b/drivers/pci/host/Makefile
 @@ -1 +1,2 @@
  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
 +obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 diff --git a/drivers/pci/host/pcie-designware.c 
 b/drivers/pci