Change exynos-audss clock driver as per existing clock framework from
the existing module driver framework.
Signed-off-by: Tushar Behera
---
drivers/clk/samsung/clk-exynos-audss.c | 239
1 file changed, 87 insertions(+), 152 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index ebfc5da..49f4163 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,26 +19,25 @@
#include
+#include "clk.h"
+
enum exynos_audss_clk_type {
TYPE_EXYNOS4210,
TYPE_EXYNOS5250,
TYPE_EXYNOS5420,
};
-static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
-#define ASS_CLK_SRC 0x0
-#define ASS_CLK_DIV 0x4
-#define ASS_CLK_GATE 0x8
+#define ASS_CLK_SRC0x0
+#define ASS_CLK_DIV0x4
+#define ASS_CLK_GATE 0x8
#ifdef CONFIG_PM_SLEEP
static unsigned long reg_save[][2] = {
- {ASS_CLK_SRC, 0},
- {ASS_CLK_DIV, 0},
- {ASS_CLK_GATE, 0},
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
};
static int exynos_audss_clk_suspend(void)
@@ -65,21 +64,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
};
#endif /* CONFIG_PM_SLEEP */
-static const struct of_device_id exynos_audss_clk_of_match[] = {
- { .compatible = "samsung,exynos4210-audss-clock",
- .data = (void *)TYPE_EXYNOS4210, },
- { .compatible = "samsung,exynos5250-audss-clock",
- .data = (void *)TYPE_EXYNOS5250, },
- { .compatible = "samsung,exynos5420-audss-clock",
- .data = (void *)TYPE_EXYNOS5420, },
- {},
-};
-
-/* register exynos_audss clocks */
-static int exynos_audss_clk_probe(struct platform_device *pdev)
+static void __init exynos_audss_clk_init(struct device_node *np,
+ enum exynos_audss_clk_type variant)
{
- int i, ret = 0;
- struct resource *res;
+ int i;
struct clk *tmp;
const char *clk_name_ref[] = {
"pll_ref", "pll_in", "cdclk", "sclk_audio", "sclk_pcm_in" };
@@ -87,163 +75,110 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
"fin_pll", "fout_epll", "cdclk0", "sclk_audio0", "sclk_pcm0"};
const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
- const char *sclk_pcm_p = "sclk_pcm0";
- const struct of_device_id *match;
- enum exynos_audss_clk_type variant;
-
- match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
- if (!match)
- return -EINVAL;
- variant = (enum exynos_audss_clk_type)match->data;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- reg_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(reg_base)) {
- dev_err(&pdev->dev, "failed to map audss registers\n");
- return PTR_ERR(reg_base);
- }
- clk_table = devm_kzalloc(&pdev->dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
- GFP_KERNEL);
- if (!clk_table)
- return -ENOMEM;
-
- clk_data.clks = clk_table;
- if (variant == TYPE_EXYNOS5420)
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- else
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
+ char sclk_pcm_p[32];
+
+ struct samsung_mux_clock exynos_audss_mux_clks[] = {
+ MUX(EXYNOS_MOUT_AUDSS, "mout_audss", mout_audss_p,
+ ASS_CLK_SRC, 0, 1),
+ MUX(EXYNOS_MOUT_I2S, "mout_i2s", mout_i2s_p,
+ ASS_CLK_SRC, 2, 2),
+ };
+
+ struct samsung_div_clock exynos_audss_div_clks[] = {
+ DIV(EXYNOS_DOUT_SRP, "dout_srp", "mout_audss",
+ ASS_CLK_DIV, 0, 4),
+ DIV(EXYNOS_DOUT_AUD_BUS, "dout_aud_bus", "dout_srp",
+ ASS_CLK_DIV, 4, 4),
+ DIV(EXYNOS_DOUT_I2S, "dout_i2s", "mout_i2s", ASS_CLK_DIV, 8, 4),
+ };
+
+ struct samsung_gate_clock exynos_audss_gate_clks[] = {
+ GATE(EXYNOS_SRP_CLK, "srp_clk", "dout_srp",
+ ASS_CLK_GATE, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_I2S_BUS, "i2s_bus", "dout_aud_bus",
+ ASS_CLK_GATE, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_I2S, "sclk_i2s", "dout_i2s",
+ ASS_CLK_GATE, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_PCM_BUS, "pcm_bus", "sclk_pcm",
+ ASS_CLK_GATE, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_PCM, "sclk_pcm", sclk_pcm_p,
+ ASS_CLK_GATE, 5, CLK_SET_RATE_PARENT
