Mesa (master): i965: Handle nested uniform array indexing
Module: Mesa
Branch: master
Commit: 07c99b443cb7903adffb6b9e7648aa4b55fa421e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07c99b443cb7903adffb6b9e7648aa4b55fa421e
Author: Chris Forbes chr...@ijw.co.nz
Date: Tue Nov 18 21:15:06 2014 +1300
i965: Handle nested uniform array indexing
When converting a uniform array reference to a pull constant load, the
`reladdr` expression itself may have its own `reladdr`, arbitrarily
deeply. This arises from expressions like:
a[b[x]] where a, b are uniform arrays (or lowered const arrays),
and x is not a constant.
Just iterate the lowering to pull constants until we stop seeing these
nested. For most shaders, there will be only one pass through this loop.
Fixes the piglit test:
tests/spec/glsl-1.20/linker/double-indirect-1.shader_test
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Cc: 10.3 10.4 mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 66 +---
1 file changed, 37 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index af7ca0c..22a6fb9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3354,6 +3354,7 @@
vec4_visitor::move_uniform_array_access_to_pull_constants()
{
int pull_constant_loc[this-uniforms];
memset(pull_constant_loc, -1, sizeof(pull_constant_loc));
+ bool nested_reladdr;
/* Walk through and find array access of uniforms. Put a copy of that
* uniform in the pull constant buffer.
@@ -3361,44 +3362,51 @@
vec4_visitor::move_uniform_array_access_to_pull_constants()
* Note that we don't move constant-indexed accesses to arrays. No
* testing has been done of the performance impact of this choice.
*/
- foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
- for (int i = 0 ; i 3; i++) {
-if (inst-src[i].file != UNIFORM || !inst-src[i].reladdr)
- continue;
+ do {
+ nested_reladdr = false;
-int uniform = inst-src[i].reg;
+ foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
+ for (int i = 0 ; i 3; i++) {
+if (inst-src[i].file != UNIFORM || !inst-src[i].reladdr)
+ continue;
-/* If this array isn't already present in the pull constant buffer,
- * add it.
- */
-if (pull_constant_loc[uniform] == -1) {
- const gl_constant_value **values =
- stage_prog_data-param[uniform * 4];
+int uniform = inst-src[i].reg;
- pull_constant_loc[uniform] = stage_prog_data-nr_pull_params / 4;
+if (inst-src[i].reladdr-reladdr)
+ nested_reladdr = true; /* will need another pass */
- assert(uniform uniform_array_size);
- for (int j = 0; j uniform_size[uniform] * 4; j++) {
- stage_prog_data-pull_param[stage_prog_data-nr_pull_params++]
- = values[j];
- }
-}
+/* If this array isn't already present in the pull constant buffer,
+ * add it.
+ */
+if (pull_constant_loc[uniform] == -1) {
+ const gl_constant_value **values =
+ stage_prog_data-param[uniform * 4];
-/* Set up the annotation tracking for new generated instructions. */
-base_ir = inst-ir;
-current_annotation = inst-annotation;
+ pull_constant_loc[uniform] = stage_prog_data-nr_pull_params /
4;
-dst_reg temp = dst_reg(this, glsl_type::vec4_type);
+ assert(uniform uniform_array_size);
+ for (int j = 0; j uniform_size[uniform] * 4; j++) {
+
stage_prog_data-pull_param[stage_prog_data-nr_pull_params++]
+ = values[j];
+ }
+}
-emit_pull_constant_load(block, inst, temp, inst-src[i],
-pull_constant_loc[uniform]);
+/* Set up the annotation tracking for new generated instructions.
*/
+base_ir = inst-ir;
+current_annotation = inst-annotation;
-inst-src[i].file = temp.file;
-inst-src[i].reg = temp.reg;
-inst-src[i].reg_offset = temp.reg_offset;
-inst-src[i].reladdr = NULL;
+dst_reg temp = dst_reg(this, glsl_type::vec4_type);
+
+emit_pull_constant_load(block, inst, temp, inst-src[i],
+pull_constant_loc[uniform]);
+
+inst-src[i].file = temp.file;
+inst-src[i].reg = temp.reg;
+inst-src[i].reg_offset = temp.reg_offset;
+inst-src[i].reladdr = NULL;
+ }
}
- }
+ } while (nested_reladdr);
/* Now there are no accesses of the UNIFORM file with a reladdr, so
* no need to track them as larger-than-vec4 objects. This
Mesa (master): i965: Skip _mesa_load_state_parameters when there are zero parameters.
Module: Mesa
Branch: master
Commit: 2c44946c8a1efbafad5b3594b0345d496a0a26cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c44946c8a1efbafad5b3594b0345d496a0a26cf
Author: Kenneth Graunke kenn...@whitecape.org
Date: Thu Nov 13 22:50:03 2014 -0800
i965: Skip _mesa_load_state_parameters when there are zero parameters.
Saves a tiny bit of CPU overhead.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
Acked-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 10 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c| 12 ++--
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 1cc96cf..4e18c7d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -59,11 +59,6 @@ brw_upload_pull_constants(struct brw_context *brw,
int i;
uint32_t surf_index = prog_data-binding_table.pull_constants_start;
- /* Updates the ParamaterValues[i] pointers for all parameters of the
-* basic type of PROGRAM_STATE_VAR.
-*/
- _mesa_load_state_parameters(brw-ctx, prog-Parameters);
-
if (!prog_data-nr_pull_params) {
if (stage_state-surf_offset[surf_index]) {
stage_state-surf_offset[surf_index] = 0;
@@ -72,6 +67,11 @@ brw_upload_pull_constants(struct brw_context *brw,
return;
}
+ /* Updates the ParamaterValues[i] pointers for all parameters of the
+* basic type of PROGRAM_STATE_VAR.
+*/
+ _mesa_load_state_parameters(brw-ctx, prog-Parameters);
+
/* CACHE_NEW_*_PROG | _NEW_PROGRAM_CONSTANTS */
uint32_t size = prog_data-nr_pull_params * 4;
drm_intel_bo *const_bo = NULL;
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 2427407..1de3c26 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -58,15 +58,15 @@ gen6_upload_push_constants(struct brw_context *brw,
{
struct gl_context *ctx = brw-ctx;
- /* Updates the ParamaterValues[i] pointers for all parameters of the
-* basic type of PROGRAM_STATE_VAR.
-*/
- /* XXX: Should this happen somewhere before to get our state flag set? */
- _mesa_load_state_parameters(ctx, prog-Parameters);
-
if (prog_data-nr_params == 0) {
stage_state-push_const_size = 0;
} else {
+ /* Updates the ParamaterValues[i] pointers for all parameters of the
+ * basic type of PROGRAM_STATE_VAR.
+ */
+ /* XXX: Should this happen somewhere before to get our state flag set? */
+ _mesa_load_state_parameters(ctx, prog-Parameters);
+
gl_constant_value *param;
int i;
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Mesa (master): i965: Skip _mesa_load_state_parameters when there are zero parameters.
Module: Mesa
Branch: master
Commit: 5e37a2a4a8aa9776ac17de794786479af2da2723
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e37a2a4a8aa9776ac17de794786479af2da2723
Author: Kenneth Graunke kenn...@whitecape.org
Date: Thu Nov 13 22:50:03 2014 -0800
i965: Skip _mesa_load_state_parameters when there are zero parameters.
Saves a tiny bit of CPU overhead.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
Acked-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 10 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c| 12 ++--
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 1cc96cf..4e18c7d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -59,11 +59,6 @@ brw_upload_pull_constants(struct brw_context *brw,
int i;
uint32_t surf_index = prog_data-binding_table.pull_constants_start;
- /* Updates the ParamaterValues[i] pointers for all parameters of the
-* basic type of PROGRAM_STATE_VAR.
-*/
- _mesa_load_state_parameters(brw-ctx, prog-Parameters);
-
if (!prog_data-nr_pull_params) {
if (stage_state-surf_offset[surf_index]) {
stage_state-surf_offset[surf_index] = 0;
@@ -72,6 +67,11 @@ brw_upload_pull_constants(struct brw_context *brw,
return;
}
+ /* Updates the ParamaterValues[i] pointers for all parameters of the
+* basic type of PROGRAM_STATE_VAR.
+*/
+ _mesa_load_state_parameters(brw-ctx, prog-Parameters);
+
/* CACHE_NEW_*_PROG | _NEW_PROGRAM_CONSTANTS */
uint32_t size = prog_data-nr_pull_params * 4;
drm_intel_bo *const_bo = NULL;
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 2427407..1de3c26 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -58,15 +58,15 @@ gen6_upload_push_constants(struct brw_context *brw,
{
struct gl_context *ctx = brw-ctx;
- /* Updates the ParamaterValues[i] pointers for all parameters of the
-* basic type of PROGRAM_STATE_VAR.
-*/
- /* XXX: Should this happen somewhere before to get our state flag set? */
- _mesa_load_state_parameters(ctx, prog-Parameters);
-
if (prog_data-nr_params == 0) {
stage_state-push_const_size = 0;
} else {
+ /* Updates the ParamaterValues[i] pointers for all parameters of the
+ * basic type of PROGRAM_STATE_VAR.
+ */
+ /* XXX: Should this happen somewhere before to get our state flag set? */
+ _mesa_load_state_parameters(ctx, prog-Parameters);
+
gl_constant_value *param;
int i;
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Mesa (master): rtasm,translate: Re-enable SSE on Mingw64.
Module: Mesa Branch: master Commit: 56bf948e11dd43c671fa6731bb49b4b68f9fe025 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=56bf948e11dd43c671fa6731bb49b4b68f9fe025 Author: José Fonseca jfons...@vmware.com Date: Wed Nov 19 12:04:44 2014 + rtasm,translate: Re-enable SSE on Mingw64. This reverts f4dd0991719ef3e2606920c5100b372181c60899. The src/gallium/tests/unit/translate_test.c gives the same results on MinGW 64-bits as on Linux 64-bits. And since MinGW is often used for development/testing due to its convenience, it's better not to have this sort of differences relative to MSVC. Reviewed-by: Roland Scheidegger srol...@vmware.com --- src/gallium/auxiliary/rtasm/rtasm_x86sse.c |2 +- src/gallium/auxiliary/translate/translate_sse.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/rtasm/rtasm_x86sse.c b/src/gallium/auxiliary/rtasm/rtasm_x86sse.c index 24ff820..f963788 100644 --- a/src/gallium/auxiliary/rtasm/rtasm_x86sse.c +++ b/src/gallium/auxiliary/rtasm/rtasm_x86sse.c @@ -25,7 +25,7 @@ #include pipe/p_config.h #include util/u_cpu_detect.h -#if defined(PIPE_ARCH_X86) || (defined(PIPE_ARCH_X86_64) !defined(__MINGW32__)) +#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) #include pipe/p_compiler.h #include util/u_debug.h diff --git a/src/gallium/auxiliary/translate/translate_sse.c b/src/gallium/auxiliary/translate/translate_sse.c index c7c53b3..c7b6c36 100644 --- a/src/gallium/auxiliary/translate/translate_sse.c +++ b/src/gallium/auxiliary/translate/translate_sse.c @@ -35,7 +35,7 @@ #include translate.h -#if (defined(PIPE_ARCH_X86) || (defined(PIPE_ARCH_X86_64) !defined(__MINGW32__))) !defined(PIPE_SUBSYSTEM_EMBEDDED) +#if (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)) !defined(PIPE_SUBSYSTEM_EMBEDDED) #include rtasm/rtasm_cpu.h #include rtasm/rtasm_x86sse.h ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/disasm: Properly decode branch_ctrl (gen8+)
Module: Mesa
Branch: master
Commit: ca39c46c3be82be0a36316e5da32b558c4837aea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca39c46c3be82be0a36316e5da32b558c4837aea
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Tue Nov 18 12:20:10 2014 -0800
i965/disasm: Properly decode branch_ctrl (gen8+)
Add support for decoding the new branch control bit. I saw two things wrong with
the existing code.
1. It didn't bother trying to decode the bit.
- While we do not *intentionally* emit this bit today, I think it's interesting
to see if we somehow ended up with the bit set. It may also be useful in the
future.
2. It seemed to be the wrong bit.
- The docs are pretty poor wrt which bit this actually occupies. To me, it
/looks/ like it should be bit 28. I am not sure where Ken got 30 from. I
verified it should be 28 by looking at the simulator code.
I also added the most basic support for GOTO simply so we don't need to remember
to change the function in the future.
v2:
Move the branch_ctrl check out of the if gen = 6 check to make it more
readable. (Matt)
ENDIF doesn't have branch_ctrl (Matt + Ken)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965/brw_disasm.c | 22 +-
src/mesa/drivers/dri/i965/brw_inst.h|2 +-
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 53cd75e..ed94bcc 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -820,6 +820,7 @@ enum opcode {
BRW_OPCODE_MSAVE = 44, /** Pre-Gen6 */
BRW_OPCODE_MRESTORE = 45, /** Pre-Gen6 */
BRW_OPCODE_PUSH = 46, /** Pre-Gen6 */
+ BRW_OPCODE_GOTO = 46, /** Gen8+*/
BRW_OPCODE_POP =47, /** Pre-Gen6 */
BRW_OPCODE_WAIT = 48,
BRW_OPCODE_SEND = 49,
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 53ec767..b211a0f 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -131,6 +131,17 @@ has_uip(struct brw_context *brw, enum opcode opcode)
}
static bool
+has_branch_ctrl(struct brw_context *brw, enum opcode opcode)
+{
+ if (brw-gen 8)
+ return false;
+
+ return opcode == BRW_OPCODE_IF ||
+ opcode == BRW_OPCODE_ELSE ||
+ opcode == BRW_OPCODE_GOTO;
+}
+
+static bool
is_logic_instruction(unsigned opcode)
{
return opcode == BRW_OPCODE_AND ||
@@ -217,6 +228,11 @@ static const char *const accwr[2] = {
[1] = AccWrEnable
};
+static const char *const branch_ctrl[2] = {
+ [0] = ,
+ [1] = BranchCtrl
+};
+
static const char *const wectrl[2] = {
[0] = ,
[1] = WE_all
@@ -1544,9 +1560,13 @@ brw_disassemble_inst(FILE *file, struct brw_context
*brw, brw_inst *inst,
err |= control(file, compaction, cmpt_ctrl, is_compacted, space);
err |= control(file, thread control, thread_ctrl,
brw_inst_thread_control(brw, inst), space);
- if (brw-gen = 6)
+ if (has_branch_ctrl(brw, opcode)) {
+ err |= control(file, branch ctrl, branch_ctrl,
+brw_inst_branch_control(brw, inst), space);
+ } else if (brw-gen = 6) {
err |= control(file, acc write control, accwr,
brw_inst_acc_wr_control(brw, inst), space);
+ }
if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC)
err |= control(file, end of thread, end_of_thread,
brw_inst_eot(brw, inst), space);
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h
b/src/mesa/drivers/dri/i965/brw_inst.h
index c1ff10d..372aa2b 100644
--- a/src/mesa/drivers/dri/i965/brw_inst.h
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -169,9 +169,9 @@ FF(flag_reg_nr,
/* 8: */ 33, 33)
F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
F(saturate, 31, 31)
-FC(branch_control, 30, 30, brw-gen = 8)
F(debug_control,30, 30)
F(cmpt_control, 29, 29)
+FC(branch_control, 28, 28, brw-gen = 8)
F(acc_wr_control, 28, 28)
F(cond_modifier,27, 24)
FC(math_function, 27, 24, brw-gen = 6)
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Mesa (master): i915: Only use TEXCOORDTYPE_VECTOR with cube maps on gen2
Module: Mesa
Branch: master
Commit: 390799c496d363e7476afb0dbb8f28cbc6e20807
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=390799c496d363e7476afb0dbb8f28cbc6e20807
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Wed Jul 2 02:23:20 2014 +0300
i915: Only use TEXCOORDTYPE_VECTOR with cube maps on gen2
Check that the target is GL_TEXTURE_CUBE_MAP before emitting
TEXCOORDTYPE_VECTOR texture coordinates.
I'm not sure if the hardware would like CARTESIAN coordinates
with cube maps, and as I'm too lazy to find out just emit the
VECTOR coordinates for cube maps always. For other targets use
CARTESIAN or HOMOGENOUS depending on the number of texture
coordinates provided.
Fixes rendering of the electric background texture in chromium-bsu
main menu. We appear to be provided with three texture coordinates
there (I'm guessing due to the funky texture matrix rotation it does).
So the code would decide to use TEXCOORDTYPE_VECTOR instead of
TEXCOORDTYPE_CARTESIAN even though we're dealing with a 2D texure.
The results weren't what one might expect.
demos/cubemap still works, which hopefully indicates that this doesn't
break things.
Also tested with:
bin/glean -o -v -v -v -t +texCube --quick
bin/cubemap -auto
from piglit.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
src/mesa/drivers/dri/i915/i830_vtbl.c | 37 +
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 1471482..91da977 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -134,27 +134,28 @@ i830_render_start(struct intel_context *intel)
GLuint mcs = (i830-state.Tex[i][I830_TEXREG_MCS]
~TEXCOORDTYPE_MASK);
-switch (sz) {
-case 1:
-case 2:
- emit = EMIT_2F;
- sz = 2;
- mcs |= TEXCOORDTYPE_CARTESIAN;
- break;
-case 3:
+if (intel-ctx.Texture.Unit[i]._Current-Target ==
GL_TEXTURE_CUBE_MAP) {
emit = EMIT_3F;
sz = 3;
mcs |= TEXCOORDTYPE_VECTOR;
- break;
-case 4:
- emit = EMIT_3F_XYW;
- sz = 3;
- mcs |= TEXCOORDTYPE_HOMOGENEOUS;
- break;
-default:
- continue;
-};
-
+} else {
+ switch (sz) {
+ case 1:
+ case 2:
+ case 3:
+ emit = EMIT_2F;
+ sz = 2;
+ mcs |= TEXCOORDTYPE_CARTESIAN;
+ break;
+ case 4:
+ emit = EMIT_3F_XYW;
+ sz = 3;
+ mcs |= TEXCOORDTYPE_HOMOGENEOUS;
+ break;
+ default:
+ continue;
+ }
+}
EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
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Mesa (master): vc4: Update for new kernel ABI with async execution and waits.
Module: Mesa
Branch: master
Commit: 21577571b37e68edc0422fbf80932588a4614abc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21577571b37e68edc0422fbf80932588a4614abc
Author: Eric Anholt e...@anholt.net
Date: Wed Nov 19 17:39:04 2014 -0800
vc4: Update for new kernel ABI with async execution and waits.
Our submits now return immediately and you have to manually wait for
things to complete if you want to (like a normal driver).
---
src/gallium/drivers/vc4/Makefile.sources |1 +
src/gallium/drivers/vc4/vc4_bufmgr.c | 65 +-
src/gallium/drivers/vc4/vc4_bufmgr.h | 10 ++-
src/gallium/drivers/vc4/vc4_context.c| 10 +++
src/gallium/drivers/vc4/vc4_context.h|3 +
src/gallium/drivers/vc4/vc4_drm.h| 38 +++
src/gallium/drivers/vc4/vc4_fence.c | 108 ++
src/gallium/drivers/vc4/vc4_resource.c |5 +-
src/gallium/drivers/vc4/vc4_screen.h | 13
9 files changed, 250 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/vc4/Makefile.sources
b/src/gallium/drivers/vc4/Makefile.sources
index 2336565..6ec48ab 100644
--- a/src/gallium/drivers/vc4/Makefile.sources
+++ b/src/gallium/drivers/vc4/Makefile.sources
@@ -9,6 +9,7 @@ C_SOURCES := \
vc4_draw.c \
vc4_drm.h \
vc4_emit.c \
+ vc4_fence.c \
vc4_formats.c \
vc4_opt_algebraic.c \
vc4_opt_copy_propagation.c \
diff --git a/src/gallium/drivers/vc4/vc4_bufmgr.c
b/src/gallium/drivers/vc4/vc4_bufmgr.c
index 33592e8..3b73ac8 100644
--- a/src/gallium/drivers/vc4/vc4_bufmgr.c
+++ b/src/gallium/drivers/vc4/vc4_bufmgr.c
@@ -152,8 +152,57 @@ vc4_bo_flink(struct vc4_bo *bo, uint32_t *name)
return true;
}
+bool
+vc4_wait_seqno(struct vc4_screen *screen, uint64_t seqno, uint64_t timeout_ns)
+{
+#ifndef USE_VC4_SIMULATOR
+struct drm_vc4_wait_seqno wait;
+memset(wait, 0, sizeof(wait));
+wait.seqno = seqno;
+wait.timeout_ns = timeout_ns;
+
+int ret = drmIoctl(screen-fd, DRM_IOCTL_VC4_WAIT_SEQNO, wait);
+if (ret == -ETIME) {
+return false;
+} else if (ret != 0) {
+fprintf(stderr, wait failed\n);
+abort();
+} else {
+screen-finished_seqno = wait.seqno;
+return true;
+}
+#else
+return true;
+#endif
+}
+
+bool
+vc4_bo_wait(struct vc4_bo *bo, uint64_t timeout_ns)
+{
+#ifndef USE_VC4_SIMULATOR
+struct vc4_screen *screen = bo-screen;
+
+struct drm_vc4_wait_bo wait;
+memset(wait, 0, sizeof(wait));
+wait.handle = bo-handle;
+wait.timeout_ns = timeout_ns;
+
+int ret = drmIoctl(screen-fd, DRM_IOCTL_VC4_WAIT_BO, wait);
+if (ret == -ETIME) {
+return false;
+} else if (ret != 0) {
+fprintf(stderr, wait failed\n);
+abort();
+} else {
+return true;
+}
+#else
+return true;
+#endif
+}
+
void *
-vc4_bo_map(struct vc4_bo *bo)
+vc4_bo_map_unsynchronized(struct vc4_bo *bo)
{
int ret;
@@ -179,3 +228,17 @@ vc4_bo_map(struct vc4_bo *bo)
return bo-map;
}
+
+void *
+vc4_bo_map(struct vc4_bo *bo)
+{
+void *map = vc4_bo_map_unsynchronized(bo);
+
+bool ok = vc4_bo_wait(bo, PIPE_TIMEOUT_INFINITE);
+if (!ok) {
+fprintf(stderr, BO wait for map failed\n);
+abort();
+}
+
+return map;
+}
diff --git a/src/gallium/drivers/vc4/vc4_bufmgr.h
b/src/gallium/drivers/vc4/vc4_bufmgr.h
index 00ea149..4a1d4a4 100644
--- a/src/gallium/drivers/vc4/vc4_bufmgr.h
+++ b/src/gallium/drivers/vc4/vc4_bufmgr.h
@@ -78,9 +78,17 @@ vc4_bo_unreference(struct vc4_bo **bo)
*bo = NULL;
}
-
void *
vc4_bo_map(struct vc4_bo *bo);
+void *
+vc4_bo_map_unsynchronized(struct vc4_bo *bo);
+
+bool
+vc4_bo_wait(struct vc4_bo *bo, uint64_t timeout_ns);
+
+bool
+vc4_wait_seqno(struct vc4_screen *screen, uint64_t seqno, uint64_t timeout_ns);
+
#endif /* VC4_BUFMGR_H */
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index a6becaf..bb30c0e 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -322,6 +322,8 @@ vc4_flush(struct pipe_context *pctx)
}
}
+vc4-last_emit_seqno = submit.seqno;
+
vc4_reset_cl(vc4-bcl);
vc4_reset_cl(vc4-rcl);
vc4_reset_cl(vc4-shader_rec);
@@ -350,7 +352,15 @@ static void
vc4_pipe_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
unsigned flags)
{
+struct vc4_context *vc4 = vc4_context(pctx);
+
vc4_flush(pctx);
+
+if (fence) {
+struct vc4_fence *f = vc4_fence_create(vc4-screen,
+ vc4-last_emit_seqno);
+*fence = (struct
