Ryzen 9 4900H amdgpu firmware

2022-03-23 Thread Fredrik Engberg 
Hey, Im having a bit problem with my Ryzen 9 4900H. When I install the
amdgpu firmware, I only get a black screen after it loads the
firmware. Im running -current. Im wondering if anyone else has this
problem. This is the error I get. I will attach my dmesg also.

drm:pid0:psp_get_runtime_db_entry *WARNING* PSP runtime database doesn't exist
[drm] Unknown EDID CEA parser results
drm:pid0:gmc_v9_0_process_interrupt *ERROR* [mmhub0] no-retry page
fault (src_id:0 ring:158 vmid:0 pasid:0, for process  pid 0 thread
pid 0)
drm:pid0:gmc_v9_0_process_interrupt *ERROR*   in page starting at
address 0x00561000 from IH client 0x12 (VMC)
drm:pid0:gmc_v9_0_process_interrupt *ERROR*
VM_L2_PROTECTION_FAULT_STATUS:0x3B3C
drm:pid0:gmc_v9_0_process_interrupt *ERROR* Faulty UTCL2 client ID: VCNU (0x1d)
drm:pid0:gmc_v9_0_process_interrupt *ERROR* MORE_FAULTS: 0x0
drm:pid0:gmc_v9_0_process_interrupt *ERROR* WALKER_ERROR: 0x6
drm:pid0:gmc_v9_0_process_interrupt *ERROR* PERMISSION_FAULTS: 0x3
drm:pid0:gmc_v9_0_process_interrupt *ERROR* MAPPING_ERROR: 0x1
drm:pid0:gmc_v9_0_process_interrupt *ERROR* RW: 0x0
[drm] *ERROR* ring vcn_dec test failed (-60)
[drm] *ERROR* hw_init of IP block  failed -60
drm:pid0:amdgpu_device_init *ERROR* amdgpu_device_ip_init failed
drm:pid0:amdgpu_attachhook *ERROR* Fatal error during GPU init


OpenBSD 7.1-beta (GENERIC.MP) #429: Tue Mar 22 10:45:17 MDT 2022
dera...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 33703485440 (32142MB)
avail mem = 32664760320 (31151MB)
random: good seed from bootblocks
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.2 @ 0xcd01f000 (44 entries)
bios0: vendor American Megatrends Inc. version "5.16" date 10/13/2021
bios0: BESSTAR TECH LIMITED HM90
acpi0 at bios0: ACPI 6.0
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP SSDT IVRS FIDT MCFG HPET SSDT VFCT BGRT TPM2
SSDT CRAT CDIT SSDT SSDT SSDT SSDT WSMT APIC SSDT SSDT FPDT
acpi0: wakeup devices GPP0(S4) GPP1(S4) GPP2(S4) GPP3(S4) GPP4(S4)
GPP5(S4) GP17(S4) XHC0(S4) XHC1(S4) GP18(S4) GP19(S4) SIO1(S3)
acpitimer0 at acpi0: 3579545 Hz, 32 bits
acpimcfg0 at acpi0
acpimcfg0: addr 0xf000, bus 0-127
acpihpet0 at acpi0: 14318180 Hz
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: AMD Ryzen 9 4900H with Radeon Graphics, 3294.30 MHz, 17-60-01
cpu0: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu0: 32KB 64b/line 8-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
64b/line 8-way L2 cache
cpu0: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu0: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges
cpu0: apic clock running at 99MHz
cpu0: mwait min=64, max=64, C-substates=1.1, IBE
cpu1 at mainbus0: apid 1 (application processor)
cpu1: AMD Ryzen 9 4900H with Radeon Graphics, 3293.82 MHz, 17-60-01
cpu1: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu1: 32KB 64b/line 8-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
64b/line 8-way L2 cache
cpu1: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu1: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu1: smt 1, core 0, package 0
cpu2 at mainbus0: apid 2 (application processor)
cpu2: AMD Ryzen 9 4900H with Radeon Graphics, 3293.82 MHz, 17-60-01
cpu2: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu2: 32KB 64b/line 8-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
64b/line 8-way L2 cache
cpu2: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu2: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu2:

Re: AX201 Surface Pro 7

2021-03-05 Thread Fredrik Engberg 
Hey, 

I had no luck with the "Qu-b0-hr-b0-48" firmware. But I had to change to 
"Qu-c0-hr-b0-48" and that seems to work.  Here it is the changes I had to do to 
get it working. I might have done something wrong here so please point it out 
to me. 

Index: if_iwx.c
===
RCS file: /cvs/src/sys/dev/pci/if_iwx.c,v
retrieving revision 1.49
diff -u -p -u -p -r1.49 if_iwx.c
--- if_iwx.c17 Jan 2021 14:24:00 -  1.49
+++ if_iwx.c28 Feb 2021 07:18:44 -
@@ -7710,6 +7710,7 @@ static const struct pci_matchid iwx_devi
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_1 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_2 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_3 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_4,},
 };

 static const struct pci_matchid iwx_subsystem_id_ax201[] = {
@@ -7749,6 +7750,7 @@ iwx_match(struct device *parent, iwx_mat
return 1; /* match any device */
case PCI_PRODUCT_INTEL_WL_22500_2: /* AX201 */
case PCI_PRODUCT_INTEL_WL_22500_3: /* AX201 */
+   case PCI_PRODUCT_INTEL_WL_22500_4: /* AX201 */
for (i = 0; i < nitems(iwx_subsystem_id_ax201); i++) {
if (svid == iwx_subsystem_id_ax201[i].pm_vid &&
spid == iwx_subsystem_id_ax201[i].pm_pid)
@@ -7951,6 +7953,17 @@ iwx_attach(struct device *parent, struct
sc->sc_tx_with_siso_diversity = 0;
sc->sc_uhb_supported = 0;
break;
+   case PCI_PRODUCT_INTEL_WL_22500_4:
+   sc->sc_fwname = "iwx-Qu-c0-hr-b0-48";
+   sc->sc_device_family = IWX_DEVICE_FAMILY_22000;
+   sc->sc_fwdmasegsz = IWX_FWDMASEGSZ_8000;
+   sc->sc_integrated = 1;
+   sc->sc_ltr_delay = IWX_SOC_FLAGS_LTR_APPLY_DELAY_200;
+   sc->sc_low_latency_xtal = 0;
+   sc->sc_xtal_latency = 5000;
+   sc->sc_tx_with_siso_diversity = 0;
+   sc->sc_uhb_supported = 0;
+   break;
default:
printf("%s: unknown adapter type\n", DEVNAME(sc));
return;
Index: pcidevs
===
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1959
diff -u -p -u -p -r1.1959 pcidevs
--- pcidevs 27 Feb 2021 03:00:54 -  1.1959
+++ pcidevs 28 Feb 2021 07:18:44 -
@@ -5942,6 +5942,7 @@ product INTEL 500SERIES_LP_XHCI   0xa0ed  5
 product INTEL 500SERIES_LP_XDCI0xa0ee  500 Series xDCI
 product INTEL 500SERIES_LP_SRAM0xa0ef  500 Series Shared SRAM
 product INTEL WL_22500_3   0xa0f0  Wi-Fi 6 AX201
+product INTEL WL_22500_4   0x34f0  Killer Wi-Fi AX1650i (201NGW)
 product INTEL 500SERIES_LP_GSPI_3  0xa0fb  500 Series GSPI
 product INTEL 500SERIES_LP_ISH 0xa0fc  500 Series ISH
 product INTEL 500SERIES_LP_GSPI_4  0xa0fd  500 Series GSPI
Index: pcidevs.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.1953
diff -u -p -u -p -r1.1953 pcidevs.h
--- pcidevs.h   27 Feb 2021 03:01:25 -  1.1953
+++ pcidevs.h   28 Feb 2021 07:18:44 -
@@ -5947,6 +5947,7 @@
 #definePCI_PRODUCT_INTEL_500SERIES_LP_XDCI 0xa0ee  /* 500 
Series xDCI */
 #definePCI_PRODUCT_INTEL_500SERIES_LP_SRAM 0xa0ef  /* 500 
Series Shared SRAM */
 #definePCI_PRODUCT_INTEL_WL_22500_30xa0f0  /* Wi-Fi 6 
AX201 */
+#definePCI_PRODUCT_INTEL_WL_22500_40x34f0  /* Killer Wi-Fi 
6 AX16501i (201NGW) */
 #definePCI_PRODUCT_INTEL_500SERIES_LP_GSPI_3   0xa0fb  /* 500 
Series GSPI */
 #definePCI_PRODUCT_INTEL_500SERIES_LP_ISH  0xa0fc  /* 500 
Series ISH */
 #definePCI_PRODUCT_INTEL_500SERIES_LP_GSPI_4   0xa0fd  /* 500 
Series GSPI */
Index: pcidevs_data.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.1948
diff -u -p -u -p -r1.1948 pcidevs_data.h
--- pcidevs_data.h  27 Feb 2021 03:01:25 -  1.1948
+++ pcidevs_data.h  28 Feb 2021 07:18:45 -
@@ -21208,6 +21208,10 @@ static const struct pci_known_product pc
"500 Series Shared SRAM",
},
{
+   PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_4,
+   "Killer Wi-Fi 6 AX1650i (201NGW)",
+   },
+   {
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_3,
"Wi-Fi 6 AX201",
    },




On Fri, Feb 5, 2021 at 3:12 PM Stefan Sperling  wrote:
On Fri, Feb 05, 2021 at 11:38:24AM +0100, Fredrik Engberg wrote:
> Hey 
> 
> I got myself a Surface Pro 7 and thought it had a supported AX201 wifi chip 
> in it but after some looking around

Re: AX201 Surface Pro 7

2021-03-05 Thread Fredrik Engberg 
Hey, 

I had no luck with the "Qu-b0-hr-b0-48" firmware. But if I changed to 
"Qu-c0-hr-b0-48" and that seems to work.  Here it is the changes I had to do to 
get it working. I might have done something wrong here so please point it out 
to me. 

Index: if_iwx.c
===
RCS file: /cvs/src/sys/dev/pci/if_iwx.c,v
retrieving revision 1.49
diff -u -p -u -p -r1.49 if_iwx.c
--- if_iwx.c17 Jan 2021 14:24:00 -  1.49
+++ if_iwx.c28 Feb 2021 07:18:44 -
@@ -7710,6 +7710,7 @@ static const struct pci_matchid iwx_devi
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_1 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_2 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_3 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_4,},
 };

 static const struct pci_matchid iwx_subsystem_id_ax201[] = {
@@ -7749,6 +7750,7 @@ iwx_match(struct device *parent, iwx_mat
return 1; /* match any device */
case PCI_PRODUCT_INTEL_WL_22500_2: /* AX201 */
case PCI_PRODUCT_INTEL_WL_22500_3: /* AX201 */
+   case PCI_PRODUCT_INTEL_WL_22500_4: /* AX201 */
for (i = 0; i < nitems(iwx_subsystem_id_ax201); i++) {
if (svid == iwx_subsystem_id_ax201[i].pm_vid &&
spid == iwx_subsystem_id_ax201[i].pm_pid)
@@ -7951,6 +7953,17 @@ iwx_attach(struct device *parent, struct
sc->sc_tx_with_siso_diversity = 0;
sc->sc_uhb_supported = 0;
break;
+   case PCI_PRODUCT_INTEL_WL_22500_4:
+   sc->sc_fwname = "iwx-Qu-c0-hr-b0-48";
+   sc->sc_device_family = IWX_DEVICE_FAMILY_22000;
+   sc->sc_fwdmasegsz = IWX_FWDMASEGSZ_8000;
+   sc->sc_integrated = 1;
+   sc->sc_ltr_delay = IWX_SOC_FLAGS_LTR_APPLY_DELAY_200;
+   sc->sc_low_latency_xtal = 0;
+   sc->sc_xtal_latency = 5000;
+   sc->sc_tx_with_siso_diversity = 0;
+   sc->sc_uhb_supported = 0;
+   break;
default:
printf("%s: unknown adapter type\n", DEVNAME(sc));
return;
Index: pcidevs
===
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1959
diff -u -p -u -p -r1.1959 pcidevs
--- pcidevs 27 Feb 2021 03:00:54 -  1.1959
+++ pcidevs 28 Feb 2021 07:18:44 -
@@ -5942,6 +5942,7 @@ product INTEL 500SERIES_LP_XHCI   0xa0ed  5
 product INTEL 500SERIES_LP_XDCI0xa0ee  500 Series xDCI
 product INTEL 500SERIES_LP_SRAM0xa0ef  500 Series Shared SRAM
 product INTEL WL_22500_3   0xa0f0  Wi-Fi 6 AX201
+product INTEL WL_22500_4   0x34f0  Killer Wi-Fi AX1650i (201NGW)
 product INTEL 500SERIES_LP_GSPI_3  0xa0fb  500 Series GSPI
 product INTEL 500SERIES_LP_ISH 0xa0fc  500 Series ISH
 product INTEL 500SERIES_LP_GSPI_4  0xa0fd  500 Series GSPI
Index: pcidevs.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.1953
diff -u -p -u -p -r1.1953 pcidevs.h
--- pcidevs.h   27 Feb 2021 03:01:25 -  1.1953
+++ pcidevs.h   28 Feb 2021 07:18:44 -
@@ -5947,6 +5947,7 @@
 #definePCI_PRODUCT_INTEL_500SERIES_LP_XDCI 0xa0ee  /* 500 
Series xDCI */
 #definePCI_PRODUCT_INTEL_500SERIES_LP_SRAM 0xa0ef  /* 500 
Series Shared SRAM */
 #definePCI_PRODUCT_INTEL_WL_22500_30xa0f0  /* Wi-Fi 6 
AX201 */
+#definePCI_PRODUCT_INTEL_WL_22500_40x34f0  /* Killer Wi-Fi 
6 AX16501i (201NGW) */
 #definePCI_PRODUCT_INTEL_500SERIES_LP_GSPI_3   0xa0fb  /* 500 
Series GSPI */
 #definePCI_PRODUCT_INTEL_500SERIES_LP_ISH  0xa0fc  /* 500 
Series ISH */
 #definePCI_PRODUCT_INTEL_500SERIES_LP_GSPI_4   0xa0fd  /* 500 
Series GSPI */
Index: pcidevs_data.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.1948
diff -u -p -u -p -r1.1948 pcidevs_data.h
--- pcidevs_data.h  27 Feb 2021 03:01:25 -  1.1948
+++ pcidevs_data.h  28 Feb 2021 07:18:45 -
@@ -21208,6 +21208,10 @@ static const struct pci_known_product pc
"500 Series Shared SRAM",
},
{
+   PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_4,
+   "Killer Wi-Fi 6 AX1650i (201NGW)",
+   },
+   {
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_3,
"Wi-Fi 6 AX201",
    },




On Fri, Feb 5, 2021 at 3:12 PM Stefan Sperling  wrote:
On Fri, Feb 05, 2021 at 11:38:24AM +0100, Fredrik Engberg wrote:
> Hey 
> 
> I got myself a Surface Pro 7 and thought it had a supported AX201 wifi chip 
> in it but after some looking around

AX201 Surface Pro 7

2021-02-05 Thread Fredrik Engberg 
Hey 

I got myself a Surface Pro 7 and thought it had a supported AX201 wifi chip in 
it but after some looking around in the source I couldn’t find the device ID in 
there so I tried myself to add it to pcidevs and pcidevs.h. 
I also added the pci_products to if_iwx.c and pcidevs_data.h. I got it to show 
up in dmesg. But I get “iwx0: unsupported AX201 adapter". I think Im in a bit 
of deep water here and my knowledge is to low for it. Im wondering if someone 
else has gotten this AX1650 card to work? 

Here is pcidump from the machine: 

 0:20:3: Intel unknown
0x: Vendor ID: 8086, Product ID: 34f0
0x0004: Command: 0006, Status: 0010
0x0008: Class: 02 Network, Subclass: 80 Miscellaneous,
Interface: 00, Revision: 30
0x000c: BIST: 00, Header Type: 80, Latency Timer: 00,
Cache Line Size: 00
0x0010: BAR mem 64bit addr: 0x006002134000/0x4000
0x0018: BAR empty ()
0x001c: BAR empty ()
0x0020: BAR empty ()
0x0024: BAR empty ()
0x0028: Cardbus CIS: 
0x002c: Subsystem Vendor ID: 8086 Product ID: 0074
0x0030: Expansion ROM Base Address: 
0x0038: 
0x003c: Interrupt Pin: 01 Line: ff Min Gnt: 00 Max Lat: 00
0x00c8: Capability 0x01: Power Management
State: D0
0x00d0: Capability 0x05: Message Signalled Interrupts (MSI)
Enabled: no
0x0040: Capability 0x10: PCI Express
Max Payload Size: 128 / 128 bytes
Max Read Request Size: 128 bytes
0x0100: Enhanced Capability 0x18: Latency Tolerance Reporting
0x0164: Enhanced Capability 0x0b: Vendor-Specific
0x0080: Capability 0x11: Extended Message Signalled Interrupts (MSI-X)
Enabled: yes; table size 16 (BAR 0:8192)


//Fredrik Engberg